core/stdarch/crates/core_arch/src/x86_64/
avx512bw.rs

1use crate::core_arch::x86::*;
2
3/// Convert 64-bit mask a into an integer value, and store the result in dst.
4///
5/// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_cvtmask64_u64)
6#[inline]
7#[target_feature(enable = "avx512bw")]
8#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
9#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
10pub const fn _cvtmask64_u64(a: __mmask64) -> u64 {
11    a
12}
13
14/// Convert integer value a into an 64-bit mask, and store the result in k.
15///
16/// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_cvtu64_mask64)
17#[inline]
18#[target_feature(enable = "avx512bw")]
19#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
20#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
21pub const fn _cvtu64_mask64(a: u64) -> __mmask64 {
22    a
23}
24
25#[cfg(test)]
26mod tests {
27    use crate::core_arch::assert_eq_const as assert_eq;
28
29    use stdarch_test::simd_test;
30
31    use crate::core_arch::{x86::*, x86_64::*};
32
33    #[simd_test(enable = "avx512bw")]
34    const unsafe fn test_cvtmask64_u64() {
35        let a: __mmask64 = 0b11001100_00110011_01100110_10011001;
36        let r = _cvtmask64_u64(a);
37        let e: u64 = 0b11001100_00110011_01100110_10011001;
38        assert_eq!(r, e);
39    }
40
41    #[simd_test(enable = "avx512bw")]
42    const unsafe fn test_cvtu64_mask64() {
43        let a: u64 = 0b11001100_00110011_01100110_10011001;
44        let r = _cvtu64_mask64(a);
45        let e: __mmask64 = 0b11001100_00110011_01100110_10011001;
46        assert_eq!(r, e);
47    }
48}