1use crate::{
2 core_arch::{simd::*, x86::*, x86_64::*},
3 mem::transmute,
4};
5
6#[cfg(test)]
7use stdarch_test::assert_instr;
8
9#[inline]
13#[target_feature(enable = "avx512f")]
14#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15#[cfg_attr(test, assert_instr(vcvtsd2si))]
16pub fn _mm_cvtsd_i64(a: __m128d) -> i64 {
17 _mm_cvtsd_si64(a)
18}
19
20#[inline]
24#[target_feature(enable = "avx512f")]
25#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
26#[cfg_attr(test, assert_instr(vcvtss2si))]
27pub fn _mm_cvtss_i64(a: __m128) -> i64 {
28 _mm_cvtss_si64(a)
29}
30
31#[inline]
35#[target_feature(enable = "avx512f")]
36#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
37#[cfg_attr(test, assert_instr(vcvtss2usi))]
38pub fn _mm_cvtss_u64(a: __m128) -> u64 {
39 unsafe { vcvtss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
40}
41
42#[inline]
46#[target_feature(enable = "avx512f")]
47#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
48#[cfg_attr(test, assert_instr(vcvtsd2usi))]
49pub fn _mm_cvtsd_u64(a: __m128d) -> u64 {
50 unsafe { vcvtsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
51}
52
53#[inline]
57#[target_feature(enable = "avx512f")]
58#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
59#[cfg_attr(test, assert_instr(vcvtsi2ss))]
60#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
61pub const fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 {
62 unsafe {
63 let b = b as f32;
64 simd_insert!(a, 0, b)
65 }
66}
67
68#[inline]
72#[target_feature(enable = "avx512f")]
73#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
74#[cfg_attr(test, assert_instr(vcvtsi2sd))]
75#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
76pub const fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d {
77 unsafe {
78 let b = b as f64;
79 simd_insert!(a, 0, b)
80 }
81}
82
83#[inline]
87#[target_feature(enable = "avx512f")]
88#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
89#[cfg_attr(test, assert_instr(vcvtusi2ss))]
90#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
91pub const fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 {
92 unsafe {
93 let b = b as f32;
94 simd_insert!(a, 0, b)
95 }
96}
97
98#[inline]
102#[target_feature(enable = "avx512f")]
103#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
104#[cfg_attr(test, assert_instr(vcvtusi2sd))]
105#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
106pub const fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d {
107 unsafe {
108 let b = b as f64;
109 simd_insert!(a, 0, b)
110 }
111}
112
113#[inline]
117#[target_feature(enable = "avx512f")]
118#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
119#[cfg_attr(test, assert_instr(vcvttsd2si))]
120pub fn _mm_cvttsd_i64(a: __m128d) -> i64 {
121 unsafe { vcvttsd2si64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
122}
123
124#[inline]
128#[target_feature(enable = "avx512f")]
129#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
130#[cfg_attr(test, assert_instr(vcvttsd2usi))]
131pub fn _mm_cvttsd_u64(a: __m128d) -> u64 {
132 unsafe { vcvttsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
133}
134
135#[inline]
139#[target_feature(enable = "avx512f")]
140#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
141#[cfg_attr(test, assert_instr(vcvttss2si))]
142pub fn _mm_cvttss_i64(a: __m128) -> i64 {
143 unsafe { vcvttss2si64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
144}
145
146#[inline]
150#[target_feature(enable = "avx512f")]
151#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
152#[cfg_attr(test, assert_instr(vcvttss2usi))]
153pub fn _mm_cvttss_u64(a: __m128) -> u64 {
154 unsafe { vcvttss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
155}
156
157#[inline]
167#[target_feature(enable = "avx512f")]
168#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
169#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
170#[rustc_legacy_const_generics(2)]
171pub fn _mm_cvt_roundi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
172 unsafe {
173 static_assert_rounding!(ROUNDING);
174 let a = a.as_f64x2();
175 let r = vcvtsi2sd64(a, b, ROUNDING);
176 transmute(r)
177 }
178}
179
180#[inline]
190#[target_feature(enable = "avx512f")]
191#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
192#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
193#[rustc_legacy_const_generics(2)]
194pub fn _mm_cvt_roundsi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
195 unsafe {
196 static_assert_rounding!(ROUNDING);
197 let a = a.as_f64x2();
198 let r = vcvtsi2sd64(a, b, ROUNDING);
199 transmute(r)
200 }
201}
202
203#[inline]
213#[target_feature(enable = "avx512f")]
214#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
215#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
216#[rustc_legacy_const_generics(2)]
217pub fn _mm_cvt_roundi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
218 unsafe {
219 static_assert_rounding!(ROUNDING);
220 let a = a.as_f32x4();
221 let r = vcvtsi2ss64(a, b, ROUNDING);
222 transmute(r)
223 }
224}
225
226#[inline]
236#[target_feature(enable = "avx512f")]
237#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
238#[cfg_attr(test, assert_instr(vcvtusi2sd, ROUNDING = 8))]
239#[rustc_legacy_const_generics(2)]
240pub fn _mm_cvt_roundu64_sd<const ROUNDING: i32>(a: __m128d, b: u64) -> __m128d {
241 unsafe {
242 static_assert_rounding!(ROUNDING);
243 let a = a.as_f64x2();
244 let r = vcvtusi2sd64(a, b, ROUNDING);
245 transmute(r)
246 }
247}
248
249#[inline]
259#[target_feature(enable = "avx512f")]
260#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
261#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
262#[rustc_legacy_const_generics(2)]
263pub fn _mm_cvt_roundsi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
264 unsafe {
265 static_assert_rounding!(ROUNDING);
266 let a = a.as_f32x4();
267 let r = vcvtsi2ss64(a, b, ROUNDING);
268 transmute(r)
269 }
270}
271
272#[inline]
282#[target_feature(enable = "avx512f")]
283#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
284#[cfg_attr(test, assert_instr(vcvtusi2ss, ROUNDING = 8))]
285#[rustc_legacy_const_generics(2)]
286pub fn _mm_cvt_roundu64_ss<const ROUNDING: i32>(a: __m128, b: u64) -> __m128 {
287 unsafe {
288 static_assert_rounding!(ROUNDING);
289 let a = a.as_f32x4();
290 let r = vcvtusi2ss64(a, b, ROUNDING);
291 transmute(r)
292 }
293}
294
295#[inline]
305#[target_feature(enable = "avx512f")]
306#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
307#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
308#[rustc_legacy_const_generics(1)]
309pub fn _mm_cvt_roundsd_si64<const ROUNDING: i32>(a: __m128d) -> i64 {
310 unsafe {
311 static_assert_rounding!(ROUNDING);
312 let a = a.as_f64x2();
313 vcvtsd2si64(a, ROUNDING)
314 }
315}
316
317#[inline]
327#[target_feature(enable = "avx512f")]
328#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
329#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
330#[rustc_legacy_const_generics(1)]
331pub fn _mm_cvt_roundsd_i64<const ROUNDING: i32>(a: __m128d) -> i64 {
332 unsafe {
333 static_assert_rounding!(ROUNDING);
334 let a = a.as_f64x2();
335 vcvtsd2si64(a, ROUNDING)
336 }
337}
338
339#[inline]
349#[target_feature(enable = "avx512f")]
350#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
351#[cfg_attr(test, assert_instr(vcvtsd2usi, ROUNDING = 8))]
352#[rustc_legacy_const_generics(1)]
353pub fn _mm_cvt_roundsd_u64<const ROUNDING: i32>(a: __m128d) -> u64 {
354 unsafe {
355 static_assert_rounding!(ROUNDING);
356 let a = a.as_f64x2();
357 vcvtsd2usi64(a, ROUNDING)
358 }
359}
360
361#[inline]
371#[target_feature(enable = "avx512f")]
372#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
373#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
374#[rustc_legacy_const_generics(1)]
375pub fn _mm_cvt_roundss_si64<const ROUNDING: i32>(a: __m128) -> i64 {
376 unsafe {
377 static_assert_rounding!(ROUNDING);
378 let a = a.as_f32x4();
379 vcvtss2si64(a, ROUNDING)
380 }
381}
382
383#[inline]
393#[target_feature(enable = "avx512f")]
394#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
395#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
396#[rustc_legacy_const_generics(1)]
397pub fn _mm_cvt_roundss_i64<const ROUNDING: i32>(a: __m128) -> i64 {
398 unsafe {
399 static_assert_rounding!(ROUNDING);
400 let a = a.as_f32x4();
401 vcvtss2si64(a, ROUNDING)
402 }
403}
404
405#[inline]
415#[target_feature(enable = "avx512f")]
416#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
417#[cfg_attr(test, assert_instr(vcvtss2usi, ROUNDING = 8))]
418#[rustc_legacy_const_generics(1)]
419pub fn _mm_cvt_roundss_u64<const ROUNDING: i32>(a: __m128) -> u64 {
420 unsafe {
421 static_assert_rounding!(ROUNDING);
422 let a = a.as_f32x4();
423 vcvtss2usi64(a, ROUNDING)
424 }
425}
426
427#[inline]
432#[target_feature(enable = "avx512f")]
433#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
434#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
435#[rustc_legacy_const_generics(1)]
436pub fn _mm_cvtt_roundsd_si64<const SAE: i32>(a: __m128d) -> i64 {
437 unsafe {
438 static_assert_sae!(SAE);
439 let a = a.as_f64x2();
440 vcvttsd2si64(a, SAE)
441 }
442}
443
444#[inline]
449#[target_feature(enable = "avx512f")]
450#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
451#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
452#[rustc_legacy_const_generics(1)]
453pub fn _mm_cvtt_roundsd_i64<const SAE: i32>(a: __m128d) -> i64 {
454 unsafe {
455 static_assert_sae!(SAE);
456 let a = a.as_f64x2();
457 vcvttsd2si64(a, SAE)
458 }
459}
460
461#[inline]
466#[target_feature(enable = "avx512f")]
467#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
468#[cfg_attr(test, assert_instr(vcvttsd2usi, SAE = 8))]
469#[rustc_legacy_const_generics(1)]
470pub fn _mm_cvtt_roundsd_u64<const SAE: i32>(a: __m128d) -> u64 {
471 unsafe {
472 static_assert_sae!(SAE);
473 let a = a.as_f64x2();
474 vcvttsd2usi64(a, SAE)
475 }
476}
477
478#[inline]
483#[target_feature(enable = "avx512f")]
484#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
485#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
486#[rustc_legacy_const_generics(1)]
487pub fn _mm_cvtt_roundss_i64<const SAE: i32>(a: __m128) -> i64 {
488 unsafe {
489 static_assert_sae!(SAE);
490 let a = a.as_f32x4();
491 vcvttss2si64(a, SAE)
492 }
493}
494
495#[inline]
500#[target_feature(enable = "avx512f")]
501#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
502#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
503#[rustc_legacy_const_generics(1)]
504pub fn _mm_cvtt_roundss_si64<const SAE: i32>(a: __m128) -> i64 {
505 unsafe {
506 static_assert_sae!(SAE);
507 let a = a.as_f32x4();
508 vcvttss2si64(a, SAE)
509 }
510}
511
512#[inline]
517#[target_feature(enable = "avx512f")]
518#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
519#[cfg_attr(test, assert_instr(vcvttss2usi, SAE = 8))]
520#[rustc_legacy_const_generics(1)]
521pub fn _mm_cvtt_roundss_u64<const SAE: i32>(a: __m128) -> u64 {
522 unsafe {
523 static_assert_sae!(SAE);
524 let a = a.as_f32x4();
525 vcvttss2usi64(a, SAE)
526 }
527}
528
529#[allow(improper_ctypes)]
530unsafe extern "C" {
531 #[link_name = "llvm.x86.avx512.vcvtss2si64"]
532 fn vcvtss2si64(a: f32x4, rounding: i32) -> i64;
533 #[link_name = "llvm.x86.avx512.vcvtss2usi64"]
534 fn vcvtss2usi64(a: f32x4, rounding: i32) -> u64;
535 #[link_name = "llvm.x86.avx512.vcvtsd2si64"]
536 fn vcvtsd2si64(a: f64x2, rounding: i32) -> i64;
537 #[link_name = "llvm.x86.avx512.vcvtsd2usi64"]
538 fn vcvtsd2usi64(a: f64x2, rounding: i32) -> u64;
539
540 #[link_name = "llvm.x86.avx512.cvtsi2ss64"]
541 fn vcvtsi2ss64(a: f32x4, b: i64, rounding: i32) -> f32x4;
542 #[link_name = "llvm.x86.avx512.cvtsi2sd64"]
543 fn vcvtsi2sd64(a: f64x2, b: i64, rounding: i32) -> f64x2;
544 #[link_name = "llvm.x86.avx512.cvtusi642ss"]
545 fn vcvtusi2ss64(a: f32x4, b: u64, rounding: i32) -> f32x4;
546 #[link_name = "llvm.x86.avx512.cvtusi642sd"]
547 fn vcvtusi2sd64(a: f64x2, b: u64, rounding: i32) -> f64x2;
548
549 #[link_name = "llvm.x86.avx512.cvttss2si64"]
550 fn vcvttss2si64(a: f32x4, rounding: i32) -> i64;
551 #[link_name = "llvm.x86.avx512.cvttss2usi64"]
552 fn vcvttss2usi64(a: f32x4, rounding: i32) -> u64;
553 #[link_name = "llvm.x86.avx512.cvttsd2si64"]
554 fn vcvttsd2si64(a: f64x2, rounding: i32) -> i64;
555 #[link_name = "llvm.x86.avx512.cvttsd2usi64"]
556 fn vcvttsd2usi64(a: f64x2, rounding: i32) -> u64;
557}
558
559#[cfg(test)]
560mod tests {
561 use crate::core_arch::assert_eq_const as assert_eq;
562
563 use stdarch_test::simd_test;
564
565 use crate::core_arch::x86::*;
566 use crate::core_arch::x86_64::*;
567 use crate::hint::black_box;
568
569 #[simd_test(enable = "avx512f")]
570 const unsafe fn test_mm512_abs_epi64() {
571 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
572 let r = _mm512_abs_epi64(a);
573 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
574 assert_eq_m512i(r, e);
575 }
576
577 #[simd_test(enable = "avx512f")]
578 const unsafe fn test_mm512_mask_abs_epi64() {
579 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
580 let r = _mm512_mask_abs_epi64(a, 0, a);
581 assert_eq_m512i(r, a);
582 let r = _mm512_mask_abs_epi64(a, 0b11111111, a);
583 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
584 assert_eq_m512i(r, e);
585 }
586
587 #[simd_test(enable = "avx512f")]
588 const unsafe fn test_mm512_maskz_abs_epi64() {
589 let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
590 let r = _mm512_maskz_abs_epi64(0, a);
591 assert_eq_m512i(r, _mm512_setzero_si512());
592 let r = _mm512_maskz_abs_epi64(0b11111111, a);
593 let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
594 assert_eq_m512i(r, e);
595 }
596
597 #[simd_test(enable = "avx512f,avx512vl")]
598 const unsafe fn test_mm256_abs_epi64() {
599 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
600 let r = _mm256_abs_epi64(a);
601 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
602 assert_eq_m256i(r, e);
603 }
604
605 #[simd_test(enable = "avx512f,avx512vl")]
606 const unsafe fn test_mm256_mask_abs_epi64() {
607 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
608 let r = _mm256_mask_abs_epi64(a, 0, a);
609 assert_eq_m256i(r, a);
610 let r = _mm256_mask_abs_epi64(a, 0b00001111, a);
611 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
612 assert_eq_m256i(r, e);
613 }
614
615 #[simd_test(enable = "avx512f,avx512vl")]
616 const unsafe fn test_mm256_maskz_abs_epi64() {
617 let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
618 let r = _mm256_maskz_abs_epi64(0, a);
619 assert_eq_m256i(r, _mm256_setzero_si256());
620 let r = _mm256_maskz_abs_epi64(0b00001111, a);
621 let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
622 assert_eq_m256i(r, e);
623 }
624
625 #[simd_test(enable = "avx512f,avx512vl")]
626 const unsafe fn test_mm_abs_epi64() {
627 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
628 let r = _mm_abs_epi64(a);
629 let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
630 assert_eq_m128i(r, e);
631 let a = _mm_set_epi64x(100, -100);
632 let r = _mm_abs_epi64(a);
633 let e = _mm_set_epi64x(100, 100);
634 assert_eq_m128i(r, e);
635 }
636
637 #[simd_test(enable = "avx512f,avx512vl")]
638 const unsafe fn test_mm_mask_abs_epi64() {
639 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
640 let r = _mm_mask_abs_epi64(a, 0, a);
641 assert_eq_m128i(r, a);
642 let r = _mm_mask_abs_epi64(a, 0b00000011, a);
643 let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
644 assert_eq_m128i(r, e);
645 let a = _mm_set_epi64x(100, -100);
646 let r = _mm_mask_abs_epi64(a, 0b00000011, a);
647 let e = _mm_set_epi64x(100, 100);
648 assert_eq_m128i(r, e);
649 }
650
651 #[simd_test(enable = "avx512f,avx512vl")]
652 const unsafe fn test_mm_maskz_abs_epi64() {
653 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
654 let r = _mm_maskz_abs_epi64(0, a);
655 assert_eq_m128i(r, _mm_setzero_si128());
656 let r = _mm_maskz_abs_epi64(0b00000011, a);
657 let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
658 assert_eq_m128i(r, e);
659 let a = _mm_set_epi64x(100, -100);
660 let r = _mm_maskz_abs_epi64(0b00000011, a);
661 let e = _mm_set_epi64x(100, 100);
662 assert_eq_m128i(r, e);
663 }
664
665 #[simd_test(enable = "avx512f")]
666 const unsafe fn test_mm512_abs_pd() {
667 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
668 let r = _mm512_abs_pd(a);
669 let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MAX, 100., 100., 32.);
670 assert_eq_m512d(r, e);
671 }
672
673 #[simd_test(enable = "avx512f")]
674 const unsafe fn test_mm512_mask_abs_pd() {
675 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
676 let r = _mm512_mask_abs_pd(a, 0, a);
677 assert_eq_m512d(r, a);
678 let r = _mm512_mask_abs_pd(a, 0b00001111, a);
679 let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MIN, 100., -100., -32.);
680 assert_eq_m512d(r, e);
681 }
682
683 #[simd_test(enable = "avx512f")]
684 const unsafe fn test_mm512_mask_mov_epi64() {
685 let src = _mm512_set1_epi64(1);
686 let a = _mm512_set1_epi64(2);
687 let r = _mm512_mask_mov_epi64(src, 0, a);
688 assert_eq_m512i(r, src);
689 let r = _mm512_mask_mov_epi64(src, 0b11111111, a);
690 assert_eq_m512i(r, a);
691 }
692
693 #[simd_test(enable = "avx512f")]
694 const unsafe fn test_mm512_maskz_mov_epi64() {
695 let a = _mm512_set1_epi64(2);
696 let r = _mm512_maskz_mov_epi64(0, a);
697 assert_eq_m512i(r, _mm512_setzero_si512());
698 let r = _mm512_maskz_mov_epi64(0b11111111, a);
699 assert_eq_m512i(r, a);
700 }
701
702 #[simd_test(enable = "avx512f,avx512vl")]
703 const unsafe fn test_mm256_mask_mov_epi64() {
704 let src = _mm256_set1_epi64x(1);
705 let a = _mm256_set1_epi64x(2);
706 let r = _mm256_mask_mov_epi64(src, 0, a);
707 assert_eq_m256i(r, src);
708 let r = _mm256_mask_mov_epi64(src, 0b00001111, a);
709 assert_eq_m256i(r, a);
710 }
711
712 #[simd_test(enable = "avx512f,avx512vl")]
713 const unsafe fn test_mm256_maskz_mov_epi64() {
714 let a = _mm256_set1_epi64x(2);
715 let r = _mm256_maskz_mov_epi64(0, a);
716 assert_eq_m256i(r, _mm256_setzero_si256());
717 let r = _mm256_maskz_mov_epi64(0b00001111, a);
718 assert_eq_m256i(r, a);
719 }
720
721 #[simd_test(enable = "avx512f,avx512vl")]
722 const unsafe fn test_mm_mask_mov_epi64() {
723 let src = _mm_set1_epi64x(1);
724 let a = _mm_set1_epi64x(2);
725 let r = _mm_mask_mov_epi64(src, 0, a);
726 assert_eq_m128i(r, src);
727 let r = _mm_mask_mov_epi64(src, 0b00000011, a);
728 assert_eq_m128i(r, a);
729 }
730
731 #[simd_test(enable = "avx512f,avx512vl")]
732 const unsafe fn test_mm_maskz_mov_epi64() {
733 let a = _mm_set1_epi64x(2);
734 let r = _mm_maskz_mov_epi64(0, a);
735 assert_eq_m128i(r, _mm_setzero_si128());
736 let r = _mm_maskz_mov_epi64(0b00000011, a);
737 assert_eq_m128i(r, a);
738 }
739
740 #[simd_test(enable = "avx512f")]
741 const unsafe fn test_mm512_mask_mov_pd() {
742 let src = _mm512_set1_pd(1.);
743 let a = _mm512_set1_pd(2.);
744 let r = _mm512_mask_mov_pd(src, 0, a);
745 assert_eq_m512d(r, src);
746 let r = _mm512_mask_mov_pd(src, 0b11111111, a);
747 assert_eq_m512d(r, a);
748 }
749
750 #[simd_test(enable = "avx512f")]
751 const unsafe fn test_mm512_maskz_mov_pd() {
752 let a = _mm512_set1_pd(2.);
753 let r = _mm512_maskz_mov_pd(0, a);
754 assert_eq_m512d(r, _mm512_setzero_pd());
755 let r = _mm512_maskz_mov_pd(0b11111111, a);
756 assert_eq_m512d(r, a);
757 }
758
759 #[simd_test(enable = "avx512f,avx512vl")]
760 const unsafe fn test_mm256_mask_mov_pd() {
761 let src = _mm256_set1_pd(1.);
762 let a = _mm256_set1_pd(2.);
763 let r = _mm256_mask_mov_pd(src, 0, a);
764 assert_eq_m256d(r, src);
765 let r = _mm256_mask_mov_pd(src, 0b00001111, a);
766 assert_eq_m256d(r, a);
767 }
768
769 #[simd_test(enable = "avx512f,avx512vl")]
770 const unsafe fn test_mm256_maskz_mov_pd() {
771 let a = _mm256_set1_pd(2.);
772 let r = _mm256_maskz_mov_pd(0, a);
773 assert_eq_m256d(r, _mm256_setzero_pd());
774 let r = _mm256_maskz_mov_pd(0b00001111, a);
775 assert_eq_m256d(r, a);
776 }
777
778 #[simd_test(enable = "avx512f,avx512vl")]
779 const unsafe fn test_mm_mask_mov_pd() {
780 let src = _mm_set1_pd(1.);
781 let a = _mm_set1_pd(2.);
782 let r = _mm_mask_mov_pd(src, 0, a);
783 assert_eq_m128d(r, src);
784 let r = _mm_mask_mov_pd(src, 0b00000011, a);
785 assert_eq_m128d(r, a);
786 }
787
788 #[simd_test(enable = "avx512f,avx512vl")]
789 const unsafe fn test_mm_maskz_mov_pd() {
790 let a = _mm_set1_pd(2.);
791 let r = _mm_maskz_mov_pd(0, a);
792 assert_eq_m128d(r, _mm_setzero_pd());
793 let r = _mm_maskz_mov_pd(0b00000011, a);
794 assert_eq_m128d(r, a);
795 }
796
797 #[simd_test(enable = "avx512f")]
798 const unsafe fn test_mm512_add_epi64() {
799 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
800 let b = _mm512_set1_epi64(1);
801 let r = _mm512_add_epi64(a, b);
802 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN + 1, 101, -99, -31);
803 assert_eq_m512i(r, e);
804 }
805
806 #[simd_test(enable = "avx512f")]
807 const unsafe fn test_mm512_mask_add_epi64() {
808 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
809 let b = _mm512_set1_epi64(1);
810 let r = _mm512_mask_add_epi64(a, 0, a, b);
811 assert_eq_m512i(r, a);
812 let r = _mm512_mask_add_epi64(a, 0b00001111, a, b);
813 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN, 100, -100, -32);
814 assert_eq_m512i(r, e);
815 }
816
817 #[simd_test(enable = "avx512f")]
818 const unsafe fn test_mm512_maskz_add_epi64() {
819 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
820 let b = _mm512_set1_epi64(1);
821 let r = _mm512_maskz_add_epi64(0, a, b);
822 assert_eq_m512i(r, _mm512_setzero_si512());
823 let r = _mm512_maskz_add_epi64(0b00001111, a, b);
824 let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, 0, 0, 0, 0);
825 assert_eq_m512i(r, e);
826 }
827
828 #[simd_test(enable = "avx512f,avx512vl")]
829 const unsafe fn test_mm256_mask_add_epi64() {
830 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
831 let b = _mm256_set1_epi64x(1);
832 let r = _mm256_mask_add_epi64(a, 0, a, b);
833 assert_eq_m256i(r, a);
834 let r = _mm256_mask_add_epi64(a, 0b00001111, a, b);
835 let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
836 assert_eq_m256i(r, e);
837 }
838
839 #[simd_test(enable = "avx512f,avx512vl")]
840 const unsafe fn test_mm256_maskz_add_epi64() {
841 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
842 let b = _mm256_set1_epi64x(1);
843 let r = _mm256_maskz_add_epi64(0, a, b);
844 assert_eq_m256i(r, _mm256_setzero_si256());
845 let r = _mm256_maskz_add_epi64(0b00001111, a, b);
846 let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
847 assert_eq_m256i(r, e);
848 }
849
850 #[simd_test(enable = "avx512f,avx512vl")]
851 const unsafe fn test_mm_mask_add_epi64() {
852 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
853 let b = _mm_set1_epi64x(1);
854 let r = _mm_mask_add_epi64(a, 0, a, b);
855 assert_eq_m128i(r, a);
856 let r = _mm_mask_add_epi64(a, 0b00000011, a, b);
857 let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
858 assert_eq_m128i(r, e);
859 }
860
861 #[simd_test(enable = "avx512f,avx512vl")]
862 const unsafe fn test_mm_maskz_add_epi64() {
863 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
864 let b = _mm_set1_epi64x(1);
865 let r = _mm_maskz_add_epi64(0, a, b);
866 assert_eq_m128i(r, _mm_setzero_si128());
867 let r = _mm_maskz_add_epi64(0b00000011, a, b);
868 let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
869 assert_eq_m128i(r, e);
870 }
871
872 #[simd_test(enable = "avx512f")]
873 const unsafe fn test_mm512_add_pd() {
874 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
875 let b = _mm512_set1_pd(1.);
876 let r = _mm512_add_pd(a, b);
877 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN + 1., 101., -99., -31.);
878 assert_eq_m512d(r, e);
879 }
880
881 #[simd_test(enable = "avx512f")]
882 const unsafe fn test_mm512_mask_add_pd() {
883 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
884 let b = _mm512_set1_pd(1.);
885 let r = _mm512_mask_add_pd(a, 0, a, b);
886 assert_eq_m512d(r, a);
887 let r = _mm512_mask_add_pd(a, 0b00001111, a, b);
888 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN, 100., -100., -32.);
889 assert_eq_m512d(r, e);
890 }
891
892 #[simd_test(enable = "avx512f")]
893 const unsafe fn test_mm512_maskz_add_pd() {
894 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
895 let b = _mm512_set1_pd(1.);
896 let r = _mm512_maskz_add_pd(0, a, b);
897 assert_eq_m512d(r, _mm512_setzero_pd());
898 let r = _mm512_maskz_add_pd(0b00001111, a, b);
899 let e = _mm512_setr_pd(1., 2., 0., f64::MAX, 0., 0., 0., 0.);
900 assert_eq_m512d(r, e);
901 }
902
903 #[simd_test(enable = "avx512f,avx512vl")]
904 const unsafe fn test_mm256_mask_add_pd() {
905 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
906 let b = _mm256_set1_pd(1.);
907 let r = _mm256_mask_add_pd(a, 0, a, b);
908 assert_eq_m256d(r, a);
909 let r = _mm256_mask_add_pd(a, 0b00001111, a, b);
910 let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
911 assert_eq_m256d(r, e);
912 }
913
914 #[simd_test(enable = "avx512f,avx512vl")]
915 const unsafe fn test_mm256_maskz_add_pd() {
916 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
917 let b = _mm256_set1_pd(1.);
918 let r = _mm256_maskz_add_pd(0, a, b);
919 assert_eq_m256d(r, _mm256_setzero_pd());
920 let r = _mm256_maskz_add_pd(0b00001111, a, b);
921 let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
922 assert_eq_m256d(r, e);
923 }
924
925 #[simd_test(enable = "avx512f,avx512vl")]
926 const unsafe fn test_mm_mask_add_pd() {
927 let a = _mm_set_pd(f64::MAX, f64::MIN);
928 let b = _mm_set1_pd(1.);
929 let r = _mm_mask_add_pd(a, 0, a, b);
930 assert_eq_m128d(r, a);
931 let r = _mm_mask_add_pd(a, 0b00000011, a, b);
932 let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
933 assert_eq_m128d(r, e);
934 }
935
936 #[simd_test(enable = "avx512f,avx512vl")]
937 const unsafe fn test_mm_maskz_add_pd() {
938 let a = _mm_set_pd(f64::MAX, f64::MIN);
939 let b = _mm_set1_pd(1.);
940 let r = _mm_maskz_add_pd(0, a, b);
941 assert_eq_m128d(r, _mm_setzero_pd());
942 let r = _mm_maskz_add_pd(0b00000011, a, b);
943 let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
944 assert_eq_m128d(r, e);
945 }
946
947 #[simd_test(enable = "avx512f")]
948 const unsafe fn test_mm512_sub_epi64() {
949 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
950 let b = _mm512_set1_epi64(1);
951 let r = _mm512_sub_epi64(a, b);
952 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MAX, 99, -101, -33);
953 assert_eq_m512i(r, e);
954 }
955
956 #[simd_test(enable = "avx512f")]
957 const unsafe fn test_mm512_mask_sub_epi64() {
958 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
959 let b = _mm512_set1_epi64(1);
960 let r = _mm512_mask_sub_epi64(a, 0, a, b);
961 assert_eq_m512i(r, a);
962 let r = _mm512_mask_sub_epi64(a, 0b00001111, a, b);
963 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MIN, 100, -100, -32);
964 assert_eq_m512i(r, e);
965 }
966
967 #[simd_test(enable = "avx512f")]
968 const unsafe fn test_mm512_maskz_sub_epi64() {
969 let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
970 let b = _mm512_set1_epi64(1);
971 let r = _mm512_maskz_sub_epi64(0, a, b);
972 assert_eq_m512i(r, _mm512_setzero_si512());
973 let r = _mm512_maskz_sub_epi64(0b00001111, a, b);
974 let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, 0, 0, 0, 0);
975 assert_eq_m512i(r, e);
976 }
977
978 #[simd_test(enable = "avx512f,avx512vl")]
979 const unsafe fn test_mm256_mask_sub_epi64() {
980 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
981 let b = _mm256_set1_epi64x(1);
982 let r = _mm256_mask_sub_epi64(a, 0, a, b);
983 assert_eq_m256i(r, a);
984 let r = _mm256_mask_sub_epi64(a, 0b00001111, a, b);
985 let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
986 assert_eq_m256i(r, e);
987 }
988
989 #[simd_test(enable = "avx512f,avx512vl")]
990 const unsafe fn test_mm256_maskz_sub_epi64() {
991 let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
992 let b = _mm256_set1_epi64x(1);
993 let r = _mm256_maskz_sub_epi64(0, a, b);
994 assert_eq_m256i(r, _mm256_setzero_si256());
995 let r = _mm256_maskz_sub_epi64(0b00001111, a, b);
996 let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
997 assert_eq_m256i(r, e);
998 }
999
1000 #[simd_test(enable = "avx512f,avx512vl")]
1001 const unsafe fn test_mm_mask_sub_epi64() {
1002 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
1003 let b = _mm_set1_epi64x(1);
1004 let r = _mm_mask_sub_epi64(a, 0, a, b);
1005 assert_eq_m128i(r, a);
1006 let r = _mm_mask_sub_epi64(a, 0b00000011, a, b);
1007 let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
1008 assert_eq_m128i(r, e);
1009 }
1010
1011 #[simd_test(enable = "avx512f,avx512vl")]
1012 const unsafe fn test_mm_maskz_sub_epi64() {
1013 let a = _mm_set_epi64x(i64::MAX, i64::MIN);
1014 let b = _mm_set1_epi64x(1);
1015 let r = _mm_maskz_sub_epi64(0, a, b);
1016 assert_eq_m128i(r, _mm_setzero_si128());
1017 let r = _mm_maskz_sub_epi64(0b00000011, a, b);
1018 let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
1019 assert_eq_m128i(r, e);
1020 }
1021
1022 #[simd_test(enable = "avx512f")]
1023 const unsafe fn test_mm512_sub_pd() {
1024 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1025 let b = _mm512_set1_pd(1.);
1026 let r = _mm512_sub_pd(a, b);
1027 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 99., -101., -33.);
1028 assert_eq_m512d(r, e);
1029 }
1030
1031 #[simd_test(enable = "avx512f")]
1032 const unsafe fn test_mm512_mask_sub_pd() {
1033 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1034 let b = _mm512_set1_pd(1.);
1035 let r = _mm512_mask_sub_pd(a, 0, a, b);
1036 assert_eq_m512d(r, a);
1037 let r = _mm512_mask_sub_pd(a, 0b00001111, a, b);
1038 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 100., -100., -32.);
1039 assert_eq_m512d(r, e);
1040 }
1041
1042 #[simd_test(enable = "avx512f")]
1043 const unsafe fn test_mm512_maskz_sub_pd() {
1044 let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1045 let b = _mm512_set1_pd(1.);
1046 let r = _mm512_maskz_sub_pd(0, a, b);
1047 assert_eq_m512d(r, _mm512_setzero_pd());
1048 let r = _mm512_maskz_sub_pd(0b00001111, a, b);
1049 let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., 0., 0., 0., 0.);
1050 assert_eq_m512d(r, e);
1051 }
1052
1053 #[simd_test(enable = "avx512f,avx512vl")]
1054 const unsafe fn test_mm256_mask_sub_pd() {
1055 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1056 let b = _mm256_set1_pd(1.);
1057 let r = _mm256_mask_sub_pd(a, 0, a, b);
1058 assert_eq_m256d(r, a);
1059 let r = _mm256_mask_sub_pd(a, 0b00001111, a, b);
1060 let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1061 assert_eq_m256d(r, e);
1062 }
1063
1064 #[simd_test(enable = "avx512f,avx512vl")]
1065 const unsafe fn test_mm256_maskz_sub_pd() {
1066 let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1067 let b = _mm256_set1_pd(1.);
1068 let r = _mm256_maskz_sub_pd(0, a, b);
1069 assert_eq_m256d(r, _mm256_setzero_pd());
1070 let r = _mm256_maskz_sub_pd(0b00001111, a, b);
1071 let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1072 assert_eq_m256d(r, e);
1073 }
1074
1075 #[simd_test(enable = "avx512f,avx512vl")]
1076 const unsafe fn test_mm_mask_sub_pd() {
1077 let a = _mm_set_pd(f64::MAX, f64::MIN);
1078 let b = _mm_set1_pd(1.);
1079 let r = _mm_mask_sub_pd(a, 0, a, b);
1080 assert_eq_m128d(r, a);
1081 let r = _mm_mask_sub_pd(a, 0b00000011, a, b);
1082 let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1083 assert_eq_m128d(r, e);
1084 }
1085
1086 #[simd_test(enable = "avx512f,avx512vl")]
1087 const unsafe fn test_mm_maskz_sub_pd() {
1088 let a = _mm_set_pd(f64::MAX, f64::MIN);
1089 let b = _mm_set1_pd(1.);
1090 let r = _mm_maskz_sub_pd(0, a, b);
1091 assert_eq_m128d(r, _mm_setzero_pd());
1092 let r = _mm_maskz_sub_pd(0b00000011, a, b);
1093 let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1094 assert_eq_m128d(r, e);
1095 }
1096
1097 #[simd_test(enable = "avx512f")]
1098 const unsafe fn test_mm512_mul_epi32() {
1099 let a = _mm512_set1_epi32(1);
1100 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1101 let r = _mm512_mul_epi32(a, b);
1102 let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1103 assert_eq_m512i(r, e);
1104 }
1105
1106 #[simd_test(enable = "avx512f")]
1107 const unsafe fn test_mm512_mask_mul_epi32() {
1108 let a = _mm512_set1_epi32(1);
1109 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1110 let r = _mm512_mask_mul_epi32(a, 0, a, b);
1111 assert_eq_m512i(r, a);
1112 let r = _mm512_mask_mul_epi32(a, 0b00001111, a, b);
1113 #[rustfmt::skip]
1114 let e = _mm512_set_epi64(
1115 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1116 7, 5, 3, 1,
1117 );
1118 assert_eq_m512i(r, e);
1119 }
1120
1121 #[simd_test(enable = "avx512f")]
1122 const unsafe fn test_mm512_maskz_mul_epi32() {
1123 let a = _mm512_set1_epi32(1);
1124 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1125 let r = _mm512_maskz_mul_epi32(0, a, b);
1126 assert_eq_m512i(r, _mm512_setzero_si512());
1127 let r = _mm512_maskz_mul_epi32(0b00001111, a, b);
1128 let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1129 assert_eq_m512i(r, e);
1130 }
1131
1132 #[simd_test(enable = "avx512f,avx512vl")]
1133 const unsafe fn test_mm256_mask_mul_epi32() {
1134 let a = _mm256_set1_epi32(1);
1135 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1136 let r = _mm256_mask_mul_epi32(a, 0, a, b);
1137 assert_eq_m256i(r, a);
1138 let r = _mm256_mask_mul_epi32(a, 0b00001111, a, b);
1139 let e = _mm256_set_epi64x(2, 4, 6, 8);
1140 assert_eq_m256i(r, e);
1141 }
1142
1143 #[simd_test(enable = "avx512f,avx512vl")]
1144 const unsafe fn test_mm256_maskz_mul_epi32() {
1145 let a = _mm256_set1_epi32(1);
1146 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1147 let r = _mm256_maskz_mul_epi32(0, a, b);
1148 assert_eq_m256i(r, _mm256_setzero_si256());
1149 let r = _mm256_maskz_mul_epi32(0b00001111, a, b);
1150 let e = _mm256_set_epi64x(2, 4, 6, 8);
1151 assert_eq_m256i(r, e);
1152 }
1153
1154 #[simd_test(enable = "avx512f,avx512vl")]
1155 const unsafe fn test_mm_mask_mul_epi32() {
1156 let a = _mm_set1_epi32(1);
1157 let b = _mm_set_epi32(1, 2, 3, 4);
1158 let r = _mm_mask_mul_epi32(a, 0, a, b);
1159 assert_eq_m128i(r, a);
1160 let r = _mm_mask_mul_epi32(a, 0b00000011, a, b);
1161 let e = _mm_set_epi64x(2, 4);
1162 assert_eq_m128i(r, e);
1163 }
1164
1165 #[simd_test(enable = "avx512f,avx512vl")]
1166 const unsafe fn test_mm_maskz_mul_epi32() {
1167 let a = _mm_set1_epi32(1);
1168 let b = _mm_set_epi32(1, 2, 3, 4);
1169 let r = _mm_maskz_mul_epi32(0, a, b);
1170 assert_eq_m128i(r, _mm_setzero_si128());
1171 let r = _mm_maskz_mul_epi32(0b00000011, a, b);
1172 let e = _mm_set_epi64x(2, 4);
1173 assert_eq_m128i(r, e);
1174 }
1175
1176 #[simd_test(enable = "avx512f")]
1177 const unsafe fn test_mm512_mul_epu32() {
1178 let a = _mm512_set1_epi32(1);
1179 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1180 let r = _mm512_mul_epu32(a, b);
1181 let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1182 assert_eq_m512i(r, e);
1183 }
1184
1185 #[simd_test(enable = "avx512f")]
1186 const unsafe fn test_mm512_mask_mul_epu32() {
1187 let a = _mm512_set1_epi32(1);
1188 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1189 let r = _mm512_mask_mul_epu32(a, 0, a, b);
1190 assert_eq_m512i(r, a);
1191 let r = _mm512_mask_mul_epu32(a, 0b00001111, a, b);
1192 #[rustfmt::skip]
1193 let e = _mm512_set_epi64(
1194 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1195 7, 5, 3, 1,
1196 );
1197 assert_eq_m512i(r, e);
1198 }
1199
1200 #[simd_test(enable = "avx512f")]
1201 const unsafe fn test_mm512_maskz_mul_epu32() {
1202 let a = _mm512_set1_epi32(1);
1203 let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1204 let r = _mm512_maskz_mul_epu32(0, a, b);
1205 assert_eq_m512i(r, _mm512_setzero_si512());
1206 let r = _mm512_maskz_mul_epu32(0b00001111, a, b);
1207 let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1208 assert_eq_m512i(r, e);
1209 }
1210
1211 #[simd_test(enable = "avx512f,avx512vl")]
1212 const unsafe fn test_mm256_mask_mul_epu32() {
1213 let a = _mm256_set1_epi32(1);
1214 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1215 let r = _mm256_mask_mul_epu32(a, 0, a, b);
1216 assert_eq_m256i(r, a);
1217 let r = _mm256_mask_mul_epu32(a, 0b00001111, a, b);
1218 let e = _mm256_set_epi64x(2, 4, 6, 8);
1219 assert_eq_m256i(r, e);
1220 }
1221
1222 #[simd_test(enable = "avx512f,avx512vl")]
1223 const unsafe fn test_mm256_maskz_mul_epu32() {
1224 let a = _mm256_set1_epi32(1);
1225 let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1226 let r = _mm256_maskz_mul_epu32(0, a, b);
1227 assert_eq_m256i(r, _mm256_setzero_si256());
1228 let r = _mm256_maskz_mul_epu32(0b00001111, a, b);
1229 let e = _mm256_set_epi64x(2, 4, 6, 8);
1230 assert_eq_m256i(r, e);
1231 }
1232
1233 #[simd_test(enable = "avx512f,avx512vl")]
1234 const unsafe fn test_mm_mask_mul_epu32() {
1235 let a = _mm_set1_epi32(1);
1236 let b = _mm_set_epi32(1, 2, 3, 4);
1237 let r = _mm_mask_mul_epu32(a, 0, a, b);
1238 assert_eq_m128i(r, a);
1239 let r = _mm_mask_mul_epu32(a, 0b00000011, a, b);
1240 let e = _mm_set_epi64x(2, 4);
1241 assert_eq_m128i(r, e);
1242 }
1243
1244 #[simd_test(enable = "avx512f,avx512vl")]
1245 const unsafe fn test_mm_maskz_mul_epu32() {
1246 let a = _mm_set1_epi32(1);
1247 let b = _mm_set_epi32(1, 2, 3, 4);
1248 let r = _mm_maskz_mul_epu32(0, a, b);
1249 assert_eq_m128i(r, _mm_setzero_si128());
1250 let r = _mm_maskz_mul_epu32(0b00000011, a, b);
1251 let e = _mm_set_epi64x(2, 4);
1252 assert_eq_m128i(r, e);
1253 }
1254
1255 #[simd_test(enable = "avx512f")]
1256 const unsafe fn test_mm512_mullox_epi64() {
1257 let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1258 let b = _mm512_set1_epi64(2);
1259 let r = _mm512_mullox_epi64(a, b);
1260 let e = _mm512_setr_epi64(0, 2, -2, 0, -2, 200, -200, -64);
1261 assert_eq_m512i(r, e);
1262 }
1263
1264 #[simd_test(enable = "avx512f")]
1265 const unsafe fn test_mm512_mask_mullox_epi64() {
1266 let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1267 let b = _mm512_set1_epi64(2);
1268 let r = _mm512_mask_mullox_epi64(a, 0, a, b);
1269 assert_eq_m512i(r, a);
1270 let r = _mm512_mask_mullox_epi64(a, 0b00001111, a, b);
1271 let e = _mm512_setr_epi64(0, 2, -2, 0, i64::MAX, 100, -100, -32);
1272 assert_eq_m512i(r, e);
1273 }
1274
1275 #[simd_test(enable = "avx512f")]
1276 const unsafe fn test_mm512_mul_pd() {
1277 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1278 let b = _mm512_set1_pd(2.);
1279 let r = _mm512_mul_pd(a, b);
1280 #[rustfmt::skip]
1281 let e = _mm512_setr_pd(
1282 0., 2., f64::INFINITY, f64::NEG_INFINITY,
1283 f64::INFINITY, f64::NEG_INFINITY, -200., -64.,
1284 );
1285 assert_eq_m512d(r, e);
1286 }
1287
1288 #[simd_test(enable = "avx512f")]
1289 const unsafe fn test_mm512_mask_mul_pd() {
1290 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1291 let b = _mm512_set1_pd(2.);
1292 let r = _mm512_mask_mul_pd(a, 0, a, b);
1293 assert_eq_m512d(r, a);
1294 let r = _mm512_mask_mul_pd(a, 0b00001111, a, b);
1295 #[rustfmt::skip]
1296 let e = _mm512_setr_pd(
1297 0., 2., f64::INFINITY, f64::NEG_INFINITY,
1298 f64::MAX, f64::MIN, -100., -32.,
1299 );
1300 assert_eq_m512d(r, e);
1301 }
1302
1303 #[simd_test(enable = "avx512f")]
1304 const unsafe fn test_mm512_maskz_mul_pd() {
1305 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1306 let b = _mm512_set1_pd(2.);
1307 let r = _mm512_maskz_mul_pd(0, a, b);
1308 assert_eq_m512d(r, _mm512_setzero_pd());
1309 let r = _mm512_maskz_mul_pd(0b00001111, a, b);
1310 let e = _mm512_setr_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1311 assert_eq_m512d(r, e);
1312 }
1313
1314 #[simd_test(enable = "avx512f,avx512vl")]
1315 const unsafe fn test_mm256_mask_mul_pd() {
1316 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1317 let b = _mm256_set1_pd(2.);
1318 let r = _mm256_mask_mul_pd(a, 0, a, b);
1319 assert_eq_m256d(r, a);
1320 let r = _mm256_mask_mul_pd(a, 0b00001111, a, b);
1321 let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1322 assert_eq_m256d(r, e);
1323 }
1324
1325 #[simd_test(enable = "avx512f,avx512vl")]
1326 const unsafe fn test_mm256_maskz_mul_pd() {
1327 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1328 let b = _mm256_set1_pd(2.);
1329 let r = _mm256_maskz_mul_pd(0, a, b);
1330 assert_eq_m256d(r, _mm256_setzero_pd());
1331 let r = _mm256_maskz_mul_pd(0b00001111, a, b);
1332 let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1333 assert_eq_m256d(r, e);
1334 }
1335
1336 #[simd_test(enable = "avx512f,avx512vl")]
1337 const unsafe fn test_mm_mask_mul_pd() {
1338 let a = _mm_set_pd(f64::MAX, f64::MIN);
1339 let b = _mm_set1_pd(2.);
1340 let r = _mm_mask_mul_pd(a, 0, a, b);
1341 assert_eq_m128d(r, a);
1342 let r = _mm_mask_mul_pd(a, 0b00000011, a, b);
1343 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1344 assert_eq_m128d(r, e);
1345 }
1346
1347 #[simd_test(enable = "avx512f,avx512vl")]
1348 const unsafe fn test_mm_maskz_mul_pd() {
1349 let a = _mm_set_pd(f64::MAX, f64::MIN);
1350 let b = _mm_set1_pd(2.);
1351 let r = _mm_maskz_mul_pd(0, a, b);
1352 assert_eq_m128d(r, _mm_setzero_pd());
1353 let r = _mm_maskz_mul_pd(0b00000011, a, b);
1354 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1355 assert_eq_m128d(r, e);
1356 }
1357
1358 #[simd_test(enable = "avx512f")]
1359 const unsafe fn test_mm512_div_pd() {
1360 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1361 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1362 let r = _mm512_div_pd(a, b);
1363 #[rustfmt::skip]
1364 let e = _mm512_setr_pd(
1365 0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1366 f64::INFINITY, f64::NEG_INFINITY, -50., -16.,
1367 );
1368 assert_eq_m512d(r, e);
1369 }
1370
1371 #[simd_test(enable = "avx512f")]
1372 const unsafe fn test_mm512_mask_div_pd() {
1373 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1374 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1375 let r = _mm512_mask_div_pd(a, 0, a, b);
1376 assert_eq_m512d(r, a);
1377 let r = _mm512_mask_div_pd(a, 0b00001111, a, b);
1378 #[rustfmt::skip]
1379 let e = _mm512_setr_pd(
1380 0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1381 f64::MAX, f64::MIN, -100., -32.,
1382 );
1383 assert_eq_m512d(r, e);
1384 }
1385
1386 #[simd_test(enable = "avx512f")]
1387 const unsafe fn test_mm512_maskz_div_pd() {
1388 let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1389 let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1390 let r = _mm512_maskz_div_pd(0, a, b);
1391 assert_eq_m512d(r, _mm512_setzero_pd());
1392 let r = _mm512_maskz_div_pd(0b00001111, a, b);
1393 let e = _mm512_setr_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1394 assert_eq_m512d(r, e);
1395 }
1396
1397 #[simd_test(enable = "avx512f,avx512vl")]
1398 const unsafe fn test_mm256_mask_div_pd() {
1399 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1400 let b = _mm256_set_pd(2., 2., 0., 0.);
1401 let r = _mm256_mask_div_pd(a, 0, a, b);
1402 assert_eq_m256d(r, a);
1403 let r = _mm256_mask_div_pd(a, 0b00001111, a, b);
1404 let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1405 assert_eq_m256d(r, e);
1406 }
1407
1408 #[simd_test(enable = "avx512f,avx512vl")]
1409 const unsafe fn test_mm256_maskz_div_pd() {
1410 let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1411 let b = _mm256_set_pd(2., 2., 0., 0.);
1412 let r = _mm256_maskz_div_pd(0, a, b);
1413 assert_eq_m256d(r, _mm256_setzero_pd());
1414 let r = _mm256_maskz_div_pd(0b00001111, a, b);
1415 let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1416 assert_eq_m256d(r, e);
1417 }
1418
1419 #[simd_test(enable = "avx512f,avx512vl")]
1420 const unsafe fn test_mm_mask_div_pd() {
1421 let a = _mm_set_pd(f64::MAX, f64::MIN);
1422 let b = _mm_set_pd(0., 0.);
1423 let r = _mm_mask_div_pd(a, 0, a, b);
1424 assert_eq_m128d(r, a);
1425 let r = _mm_mask_div_pd(a, 0b00000011, a, b);
1426 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1427 assert_eq_m128d(r, e);
1428 }
1429
1430 #[simd_test(enable = "avx512f,avx512vl")]
1431 const unsafe fn test_mm_maskz_div_pd() {
1432 let a = _mm_set_pd(f64::MAX, f64::MIN);
1433 let b = _mm_set_pd(0., 0.);
1434 let r = _mm_maskz_div_pd(0, a, b);
1435 assert_eq_m128d(r, _mm_setzero_pd());
1436 let r = _mm_maskz_div_pd(0b00000011, a, b);
1437 let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1438 assert_eq_m128d(r, e);
1439 }
1440
1441 #[simd_test(enable = "avx512f")]
1442 const unsafe fn test_mm512_max_epi64() {
1443 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1444 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1445 let r = _mm512_max_epi64(a, b);
1446 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1447 assert_eq_m512i(r, e);
1448 }
1449
1450 #[simd_test(enable = "avx512f")]
1451 const unsafe fn test_mm512_mask_max_epi64() {
1452 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1453 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1454 let r = _mm512_mask_max_epi64(a, 0, a, b);
1455 assert_eq_m512i(r, a);
1456 let r = _mm512_mask_max_epi64(a, 0b00001111, a, b);
1457 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1458 assert_eq_m512i(r, e);
1459 }
1460
1461 #[simd_test(enable = "avx512f")]
1462 const unsafe fn test_mm512_maskz_max_epi64() {
1463 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1464 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1465 let r = _mm512_maskz_max_epi64(0, a, b);
1466 assert_eq_m512i(r, _mm512_setzero_si512());
1467 let r = _mm512_maskz_max_epi64(0b00001111, a, b);
1468 let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1469 assert_eq_m512i(r, e);
1470 }
1471
1472 #[simd_test(enable = "avx512f,avx512vl")]
1473 const unsafe fn test_mm256_max_epi64() {
1474 let a = _mm256_set_epi64x(0, 1, 2, 3);
1475 let b = _mm256_set_epi64x(3, 2, 1, 0);
1476 let r = _mm256_max_epi64(a, b);
1477 let e = _mm256_set_epi64x(3, 2, 2, 3);
1478 assert_eq_m256i(r, e);
1479 }
1480
1481 #[simd_test(enable = "avx512f,avx512vl")]
1482 const unsafe fn test_mm256_mask_max_epi64() {
1483 let a = _mm256_set_epi64x(0, 1, 2, 3);
1484 let b = _mm256_set_epi64x(3, 2, 1, 0);
1485 let r = _mm256_mask_max_epi64(a, 0, a, b);
1486 assert_eq_m256i(r, a);
1487 let r = _mm256_mask_max_epi64(a, 0b00001111, a, b);
1488 let e = _mm256_set_epi64x(3, 2, 2, 3);
1489 assert_eq_m256i(r, e);
1490 }
1491
1492 #[simd_test(enable = "avx512f,avx512vl")]
1493 const unsafe fn test_mm256_maskz_max_epi64() {
1494 let a = _mm256_set_epi64x(0, 1, 2, 3);
1495 let b = _mm256_set_epi64x(3, 2, 1, 0);
1496 let r = _mm256_maskz_max_epi64(0, a, b);
1497 assert_eq_m256i(r, _mm256_setzero_si256());
1498 let r = _mm256_maskz_max_epi64(0b00001111, a, b);
1499 let e = _mm256_set_epi64x(3, 2, 2, 3);
1500 assert_eq_m256i(r, e);
1501 }
1502
1503 #[simd_test(enable = "avx512f,avx512vl")]
1504 const unsafe fn test_mm_max_epi64() {
1505 let a = _mm_set_epi64x(2, 3);
1506 let b = _mm_set_epi64x(3, 2);
1507 let r = _mm_max_epi64(a, b);
1508 let e = _mm_set_epi64x(3, 3);
1509 assert_eq_m128i(r, e);
1510 }
1511
1512 #[simd_test(enable = "avx512f,avx512vl")]
1513 const unsafe fn test_mm_mask_max_epi64() {
1514 let a = _mm_set_epi64x(2, 3);
1515 let b = _mm_set_epi64x(3, 2);
1516 let r = _mm_mask_max_epi64(a, 0, a, b);
1517 assert_eq_m128i(r, a);
1518 let r = _mm_mask_max_epi64(a, 0b00000011, a, b);
1519 let e = _mm_set_epi64x(3, 3);
1520 assert_eq_m128i(r, e);
1521 }
1522
1523 #[simd_test(enable = "avx512f,avx512vl")]
1524 const unsafe fn test_mm_maskz_max_epi64() {
1525 let a = _mm_set_epi64x(2, 3);
1526 let b = _mm_set_epi64x(3, 2);
1527 let r = _mm_maskz_max_epi64(0, a, b);
1528 assert_eq_m128i(r, _mm_setzero_si128());
1529 let r = _mm_maskz_max_epi64(0b00000011, a, b);
1530 let e = _mm_set_epi64x(3, 3);
1531 assert_eq_m128i(r, e);
1532 }
1533
1534 #[simd_test(enable = "avx512f")]
1535 unsafe fn test_mm512_max_pd() {
1536 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1537 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1538 let r = _mm512_max_pd(a, b);
1539 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1540 assert_eq_m512d(r, e);
1541 }
1542
1543 #[simd_test(enable = "avx512f")]
1544 unsafe fn test_mm512_mask_max_pd() {
1545 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1546 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1547 let r = _mm512_mask_max_pd(a, 0, a, b);
1548 assert_eq_m512d(r, a);
1549 let r = _mm512_mask_max_pd(a, 0b00001111, a, b);
1550 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1551 assert_eq_m512d(r, e);
1552 }
1553
1554 #[simd_test(enable = "avx512f")]
1555 unsafe fn test_mm512_maskz_max_pd() {
1556 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1557 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1558 let r = _mm512_maskz_max_pd(0, a, b);
1559 assert_eq_m512d(r, _mm512_setzero_pd());
1560 let r = _mm512_maskz_max_pd(0b00001111, a, b);
1561 let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
1562 assert_eq_m512d(r, e);
1563 }
1564
1565 #[simd_test(enable = "avx512f,avx512vl")]
1566 unsafe fn test_mm256_mask_max_pd() {
1567 let a = _mm256_set_pd(0., 1., 2., 3.);
1568 let b = _mm256_set_pd(3., 2., 1., 0.);
1569 let r = _mm256_mask_max_pd(a, 0, a, b);
1570 assert_eq_m256d(r, a);
1571 let r = _mm256_mask_max_pd(a, 0b00001111, a, b);
1572 let e = _mm256_set_pd(3., 2., 2., 3.);
1573 assert_eq_m256d(r, e);
1574 }
1575
1576 #[simd_test(enable = "avx512f,avx512vl")]
1577 unsafe fn test_mm256_maskz_max_pd() {
1578 let a = _mm256_set_pd(0., 1., 2., 3.);
1579 let b = _mm256_set_pd(3., 2., 1., 0.);
1580 let r = _mm256_maskz_max_pd(0, a, b);
1581 assert_eq_m256d(r, _mm256_setzero_pd());
1582 let r = _mm256_maskz_max_pd(0b00001111, a, b);
1583 let e = _mm256_set_pd(3., 2., 2., 3.);
1584 assert_eq_m256d(r, e);
1585 }
1586
1587 #[simd_test(enable = "avx512f,avx512vl")]
1588 unsafe fn test_mm_mask_max_pd() {
1589 let a = _mm_set_pd(2., 3.);
1590 let b = _mm_set_pd(3., 2.);
1591 let r = _mm_mask_max_pd(a, 0, a, b);
1592 assert_eq_m128d(r, a);
1593 let r = _mm_mask_max_pd(a, 0b00000011, a, b);
1594 let e = _mm_set_pd(3., 3.);
1595 assert_eq_m128d(r, e);
1596 }
1597
1598 #[simd_test(enable = "avx512f,avx512vl")]
1599 unsafe fn test_mm_maskz_max_pd() {
1600 let a = _mm_set_pd(2., 3.);
1601 let b = _mm_set_pd(3., 2.);
1602 let r = _mm_maskz_max_pd(0, a, b);
1603 assert_eq_m128d(r, _mm_setzero_pd());
1604 let r = _mm_maskz_max_pd(0b00000011, a, b);
1605 let e = _mm_set_pd(3., 3.);
1606 assert_eq_m128d(r, e);
1607 }
1608
1609 #[simd_test(enable = "avx512f")]
1610 const unsafe fn test_mm512_max_epu64() {
1611 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1612 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1613 let r = _mm512_max_epu64(a, b);
1614 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1615 assert_eq_m512i(r, e);
1616 }
1617
1618 #[simd_test(enable = "avx512f")]
1619 const unsafe fn test_mm512_mask_max_epu64() {
1620 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1621 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1622 let r = _mm512_mask_max_epu64(a, 0, a, b);
1623 assert_eq_m512i(r, a);
1624 let r = _mm512_mask_max_epu64(a, 0b00001111, a, b);
1625 let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1626 assert_eq_m512i(r, e);
1627 }
1628
1629 #[simd_test(enable = "avx512f")]
1630 const unsafe fn test_mm512_maskz_max_epu64() {
1631 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1632 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1633 let r = _mm512_maskz_max_epu64(0, a, b);
1634 assert_eq_m512i(r, _mm512_setzero_si512());
1635 let r = _mm512_maskz_max_epu64(0b00001111, a, b);
1636 let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1637 assert_eq_m512i(r, e);
1638 }
1639
1640 #[simd_test(enable = "avx512f,avx512vl")]
1641 const unsafe fn test_mm256_max_epu64() {
1642 let a = _mm256_set_epi64x(0, 1, 2, 3);
1643 let b = _mm256_set_epi64x(3, 2, 1, 0);
1644 let r = _mm256_max_epu64(a, b);
1645 let e = _mm256_set_epi64x(3, 2, 2, 3);
1646 assert_eq_m256i(r, e);
1647 }
1648
1649 #[simd_test(enable = "avx512f,avx512vl")]
1650 const unsafe fn test_mm256_mask_max_epu64() {
1651 let a = _mm256_set_epi64x(0, 1, 2, 3);
1652 let b = _mm256_set_epi64x(3, 2, 1, 0);
1653 let r = _mm256_mask_max_epu64(a, 0, a, b);
1654 assert_eq_m256i(r, a);
1655 let r = _mm256_mask_max_epu64(a, 0b00001111, a, b);
1656 let e = _mm256_set_epi64x(3, 2, 2, 3);
1657 assert_eq_m256i(r, e);
1658 }
1659
1660 #[simd_test(enable = "avx512f,avx512vl")]
1661 const unsafe fn test_mm256_maskz_max_epu64() {
1662 let a = _mm256_set_epi64x(0, 1, 2, 3);
1663 let b = _mm256_set_epi64x(3, 2, 1, 0);
1664 let r = _mm256_maskz_max_epu64(0, a, b);
1665 assert_eq_m256i(r, _mm256_setzero_si256());
1666 let r = _mm256_maskz_max_epu64(0b00001111, a, b);
1667 let e = _mm256_set_epi64x(3, 2, 2, 3);
1668 assert_eq_m256i(r, e);
1669 }
1670
1671 #[simd_test(enable = "avx512f,avx512vl")]
1672 const unsafe fn test_mm_max_epu64() {
1673 let a = _mm_set_epi64x(2, 3);
1674 let b = _mm_set_epi64x(3, 2);
1675 let r = _mm_max_epu64(a, b);
1676 let e = _mm_set_epi64x(3, 3);
1677 assert_eq_m128i(r, e);
1678 }
1679
1680 #[simd_test(enable = "avx512f,avx512vl")]
1681 const unsafe fn test_mm_mask_max_epu64() {
1682 let a = _mm_set_epi64x(2, 3);
1683 let b = _mm_set_epi64x(3, 2);
1684 let r = _mm_mask_max_epu64(a, 0, a, b);
1685 assert_eq_m128i(r, a);
1686 let r = _mm_mask_max_epu64(a, 0b00000011, a, b);
1687 let e = _mm_set_epi64x(3, 3);
1688 assert_eq_m128i(r, e);
1689 }
1690
1691 #[simd_test(enable = "avx512f,avx512vl")]
1692 const unsafe fn test_mm_maskz_max_epu64() {
1693 let a = _mm_set_epi64x(2, 3);
1694 let b = _mm_set_epi64x(3, 2);
1695 let r = _mm_maskz_max_epu64(0, a, b);
1696 assert_eq_m128i(r, _mm_setzero_si128());
1697 let r = _mm_maskz_max_epu64(0b00000011, a, b);
1698 let e = _mm_set_epi64x(3, 3);
1699 assert_eq_m128i(r, e);
1700 }
1701
1702 #[simd_test(enable = "avx512f")]
1703 const unsafe fn test_mm512_min_epi64() {
1704 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1705 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1706 let r = _mm512_min_epi64(a, b);
1707 let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1708 assert_eq_m512i(r, e);
1709 }
1710
1711 #[simd_test(enable = "avx512f")]
1712 const unsafe fn test_mm512_mask_min_epi64() {
1713 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1714 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1715 let r = _mm512_mask_min_epi64(a, 0, a, b);
1716 assert_eq_m512i(r, a);
1717 let r = _mm512_mask_min_epi64(a, 0b00001111, a, b);
1718 let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1719 assert_eq_m512i(r, e);
1720 }
1721
1722 #[simd_test(enable = "avx512f")]
1723 const unsafe fn test_mm512_maskz_min_epi64() {
1724 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1725 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1726 let r = _mm512_maskz_min_epi64(0, a, b);
1727 assert_eq_m512i(r, _mm512_setzero_si512());
1728 let r = _mm512_maskz_min_epi64(0b00001111, a, b);
1729 let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1730 assert_eq_m512i(r, e);
1731 }
1732
1733 #[simd_test(enable = "avx512f,avx512vl")]
1734 const unsafe fn test_mm256_min_epi64() {
1735 let a = _mm256_set_epi64x(0, 1, 2, 3);
1736 let b = _mm256_set_epi64x(3, 2, 1, 0);
1737 let r = _mm256_min_epi64(a, b);
1738 let e = _mm256_set_epi64x(0, 1, 1, 0);
1739 assert_eq_m256i(r, e);
1740 }
1741
1742 #[simd_test(enable = "avx512f,avx512vl")]
1743 const unsafe fn test_mm256_mask_min_epi64() {
1744 let a = _mm256_set_epi64x(0, 1, 2, 3);
1745 let b = _mm256_set_epi64x(3, 2, 1, 0);
1746 let r = _mm256_mask_min_epi64(a, 0, a, b);
1747 assert_eq_m256i(r, a);
1748 let r = _mm256_mask_min_epi64(a, 0b00001111, a, b);
1749 let e = _mm256_set_epi64x(0, 1, 1, 0);
1750 assert_eq_m256i(r, e);
1751 }
1752
1753 #[simd_test(enable = "avx512f,avx512vl")]
1754 const unsafe fn test_mm256_maskz_min_epi64() {
1755 let a = _mm256_set_epi64x(0, 1, 2, 3);
1756 let b = _mm256_set_epi64x(3, 2, 1, 0);
1757 let r = _mm256_maskz_min_epi64(0, a, b);
1758 assert_eq_m256i(r, _mm256_setzero_si256());
1759 let r = _mm256_maskz_min_epi64(0b00001111, a, b);
1760 let e = _mm256_set_epi64x(0, 1, 1, 0);
1761 assert_eq_m256i(r, e);
1762 }
1763
1764 #[simd_test(enable = "avx512f,avx512vl")]
1765 const unsafe fn test_mm_min_epi64() {
1766 let a = _mm_set_epi64x(0, 1);
1767 let b = _mm_set_epi64x(3, 2);
1768 let r = _mm_min_epi64(a, b);
1769 let e = _mm_set_epi64x(0, 1);
1770 assert_eq_m128i(r, e);
1771 let a = _mm_set_epi64x(2, 3);
1772 let b = _mm_set_epi64x(1, 0);
1773 let r = _mm_min_epi64(a, b);
1774 let e = _mm_set_epi64x(1, 0);
1775 assert_eq_m128i(r, e);
1776 }
1777
1778 #[simd_test(enable = "avx512f,avx512vl")]
1779 const unsafe fn test_mm_mask_min_epi64() {
1780 let a = _mm_set_epi64x(0, 1);
1781 let b = _mm_set_epi64x(3, 2);
1782 let r = _mm_mask_min_epi64(a, 0, a, b);
1783 assert_eq_m128i(r, a);
1784 let r = _mm_mask_min_epi64(a, 0b00000011, a, b);
1785 let e = _mm_set_epi64x(0, 1);
1786 assert_eq_m128i(r, e);
1787 }
1788
1789 #[simd_test(enable = "avx512f,avx512vl")]
1790 const unsafe fn test_mm_maskz_min_epi64() {
1791 let a = _mm_set_epi64x(0, 1);
1792 let b = _mm_set_epi64x(3, 2);
1793 let r = _mm_maskz_min_epi64(0, a, b);
1794 assert_eq_m128i(r, _mm_setzero_si128());
1795 let r = _mm_maskz_min_epi64(0b00000011, a, b);
1796 let e = _mm_set_epi64x(0, 1);
1797 assert_eq_m128i(r, e);
1798 }
1799
1800 #[simd_test(enable = "avx512f")]
1801 unsafe fn test_mm512_min_pd() {
1802 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1803 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1804 let r = _mm512_min_pd(a, b);
1805 let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
1806 assert_eq_m512d(r, e);
1807 }
1808
1809 #[simd_test(enable = "avx512f")]
1810 unsafe fn test_mm512_mask_min_pd() {
1811 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1812 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1813 let r = _mm512_mask_min_pd(a, 0, a, b);
1814 assert_eq_m512d(r, a);
1815 let r = _mm512_mask_min_pd(a, 0b00001111, a, b);
1816 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1817 assert_eq_m512d(r, e);
1818 }
1819
1820 #[simd_test(enable = "avx512f")]
1821 unsafe fn test_mm512_maskz_min_pd() {
1822 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1823 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1824 let r = _mm512_maskz_min_pd(0, a, b);
1825 assert_eq_m512d(r, _mm512_setzero_pd());
1826 let r = _mm512_maskz_min_pd(0b00001111, a, b);
1827 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1828 assert_eq_m512d(r, e);
1829 }
1830
1831 #[simd_test(enable = "avx512f,avx512vl")]
1832 unsafe fn test_mm256_mask_min_pd() {
1833 let a = _mm256_set_pd(0., 1., 2., 3.);
1834 let b = _mm256_set_pd(3., 2., 1., 0.);
1835 let r = _mm256_mask_min_pd(a, 0, a, b);
1836 assert_eq_m256d(r, a);
1837 let r = _mm256_mask_min_pd(a, 0b00001111, a, b);
1838 let e = _mm256_set_pd(0., 1., 1., 0.);
1839 assert_eq_m256d(r, e);
1840 }
1841
1842 #[simd_test(enable = "avx512f,avx512vl")]
1843 unsafe fn test_mm256_maskz_min_pd() {
1844 let a = _mm256_set_pd(0., 1., 2., 3.);
1845 let b = _mm256_set_pd(3., 2., 1., 0.);
1846 let r = _mm256_maskz_min_pd(0, a, b);
1847 assert_eq_m256d(r, _mm256_setzero_pd());
1848 let r = _mm256_maskz_min_pd(0b00001111, a, b);
1849 let e = _mm256_set_pd(0., 1., 1., 0.);
1850 assert_eq_m256d(r, e);
1851 }
1852
1853 #[simd_test(enable = "avx512f,avx512vl")]
1854 unsafe fn test_mm_mask_min_pd() {
1855 let a = _mm_set_pd(0., 1.);
1856 let b = _mm_set_pd(1., 0.);
1857 let r = _mm_mask_min_pd(a, 0, a, b);
1858 assert_eq_m128d(r, a);
1859 let r = _mm_mask_min_pd(a, 0b00000011, a, b);
1860 let e = _mm_set_pd(0., 0.);
1861 assert_eq_m128d(r, e);
1862 }
1863
1864 #[simd_test(enable = "avx512f,avx512vl")]
1865 unsafe fn test_mm_maskz_min_pd() {
1866 let a = _mm_set_pd(0., 1.);
1867 let b = _mm_set_pd(1., 0.);
1868 let r = _mm_maskz_min_pd(0, a, b);
1869 assert_eq_m128d(r, _mm_setzero_pd());
1870 let r = _mm_maskz_min_pd(0b00000011, a, b);
1871 let e = _mm_set_pd(0., 0.);
1872 assert_eq_m128d(r, e);
1873 }
1874
1875 #[simd_test(enable = "avx512f")]
1876 const unsafe fn test_mm512_min_epu64() {
1877 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1878 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1879 let r = _mm512_min_epu64(a, b);
1880 let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1881 assert_eq_m512i(r, e);
1882 }
1883
1884 #[simd_test(enable = "avx512f")]
1885 const unsafe fn test_mm512_mask_min_epu64() {
1886 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1887 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1888 let r = _mm512_mask_min_epu64(a, 0, a, b);
1889 assert_eq_m512i(r, a);
1890 let r = _mm512_mask_min_epu64(a, 0b00001111, a, b);
1891 let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1892 assert_eq_m512i(r, e);
1893 }
1894
1895 #[simd_test(enable = "avx512f")]
1896 const unsafe fn test_mm512_maskz_min_epu64() {
1897 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1898 let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1899 let r = _mm512_maskz_min_epu64(0, a, b);
1900 assert_eq_m512i(r, _mm512_setzero_si512());
1901 let r = _mm512_maskz_min_epu64(0b00001111, a, b);
1902 let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1903 assert_eq_m512i(r, e);
1904 }
1905
1906 #[simd_test(enable = "avx512f,avx512vl")]
1907 const unsafe fn test_mm256_min_epu64() {
1908 let a = _mm256_set_epi64x(0, 1, 2, 3);
1909 let b = _mm256_set_epi64x(3, 2, 1, 0);
1910 let r = _mm256_min_epu64(a, b);
1911 let e = _mm256_set_epi64x(0, 1, 1, 0);
1912 assert_eq_m256i(r, e);
1913 }
1914
1915 #[simd_test(enable = "avx512f,avx512vl")]
1916 const unsafe fn test_mm256_mask_min_epu64() {
1917 let a = _mm256_set_epi64x(0, 1, 2, 3);
1918 let b = _mm256_set_epi64x(3, 2, 1, 0);
1919 let r = _mm256_mask_min_epu64(a, 0, a, b);
1920 assert_eq_m256i(r, a);
1921 let r = _mm256_mask_min_epu64(a, 0b00001111, a, b);
1922 let e = _mm256_set_epi64x(0, 1, 1, 0);
1923 assert_eq_m256i(r, e);
1924 }
1925
1926 #[simd_test(enable = "avx512f,avx512vl")]
1927 const unsafe fn test_mm256_maskz_min_epu64() {
1928 let a = _mm256_set_epi64x(0, 1, 2, 3);
1929 let b = _mm256_set_epi64x(3, 2, 1, 0);
1930 let r = _mm256_maskz_min_epu64(0, a, b);
1931 assert_eq_m256i(r, _mm256_setzero_si256());
1932 let r = _mm256_maskz_min_epu64(0b00001111, a, b);
1933 let e = _mm256_set_epi64x(0, 1, 1, 0);
1934 assert_eq_m256i(r, e);
1935 }
1936
1937 #[simd_test(enable = "avx512f,avx512vl")]
1938 const unsafe fn test_mm_min_epu64() {
1939 let a = _mm_set_epi64x(0, 1);
1940 let b = _mm_set_epi64x(1, 0);
1941 let r = _mm_min_epu64(a, b);
1942 let e = _mm_set_epi64x(0, 0);
1943 assert_eq_m128i(r, e);
1944 }
1945
1946 #[simd_test(enable = "avx512f,avx512vl")]
1947 const unsafe fn test_mm_mask_min_epu64() {
1948 let a = _mm_set_epi64x(0, 1);
1949 let b = _mm_set_epi64x(1, 0);
1950 let r = _mm_mask_min_epu64(a, 0, a, b);
1951 assert_eq_m128i(r, a);
1952 let r = _mm_mask_min_epu64(a, 0b00000011, a, b);
1953 let e = _mm_set_epi64x(0, 0);
1954 assert_eq_m128i(r, e);
1955 }
1956
1957 #[simd_test(enable = "avx512f,avx512vl")]
1958 const unsafe fn test_mm_maskz_min_epu64() {
1959 let a = _mm_set_epi64x(0, 1);
1960 let b = _mm_set_epi64x(1, 0);
1961 let r = _mm_maskz_min_epu64(0, a, b);
1962 assert_eq_m128i(r, _mm_setzero_si128());
1963 let r = _mm_maskz_min_epu64(0b00000011, a, b);
1964 let e = _mm_set_epi64x(0, 0);
1965 assert_eq_m128i(r, e);
1966 }
1967
1968 #[simd_test(enable = "avx512f")]
1969 unsafe fn test_mm512_sqrt_pd() {
1970 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1971 let r = _mm512_sqrt_pd(a);
1972 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1973 assert_eq_m512d(r, e);
1974 }
1975
1976 #[simd_test(enable = "avx512f")]
1977 unsafe fn test_mm512_mask_sqrt_pd() {
1978 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1979 let r = _mm512_mask_sqrt_pd(a, 0, a);
1980 assert_eq_m512d(r, a);
1981 let r = _mm512_mask_sqrt_pd(a, 0b00001111, a);
1982 let e = _mm512_setr_pd(0., 1., 2., 3., 16., 25., 36., 49.);
1983 assert_eq_m512d(r, e);
1984 }
1985
1986 #[simd_test(enable = "avx512f")]
1987 unsafe fn test_mm512_maskz_sqrt_pd() {
1988 let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1989 let r = _mm512_maskz_sqrt_pd(0, a);
1990 assert_eq_m512d(r, _mm512_setzero_pd());
1991 let r = _mm512_maskz_sqrt_pd(0b00001111, a);
1992 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1993 assert_eq_m512d(r, e);
1994 }
1995
1996 #[simd_test(enable = "avx512f,avx512vl")]
1997 unsafe fn test_mm256_mask_sqrt_pd() {
1998 let a = _mm256_set_pd(0., 1., 4., 9.);
1999 let r = _mm256_mask_sqrt_pd(a, 0, a);
2000 assert_eq_m256d(r, a);
2001 let r = _mm256_mask_sqrt_pd(a, 0b00001111, a);
2002 let e = _mm256_set_pd(0., 1., 2., 3.);
2003 assert_eq_m256d(r, e);
2004 }
2005
2006 #[simd_test(enable = "avx512f,avx512vl")]
2007 unsafe fn test_mm256_maskz_sqrt_pd() {
2008 let a = _mm256_set_pd(0., 1., 4., 9.);
2009 let r = _mm256_maskz_sqrt_pd(0, a);
2010 assert_eq_m256d(r, _mm256_setzero_pd());
2011 let r = _mm256_maskz_sqrt_pd(0b00001111, a);
2012 let e = _mm256_set_pd(0., 1., 2., 3.);
2013 assert_eq_m256d(r, e);
2014 }
2015
2016 #[simd_test(enable = "avx512f,avx512vl")]
2017 unsafe fn test_mm_mask_sqrt_pd() {
2018 let a = _mm_set_pd(0., 1.);
2019 let r = _mm_mask_sqrt_pd(a, 0, a);
2020 assert_eq_m128d(r, a);
2021 let r = _mm_mask_sqrt_pd(a, 0b00000011, a);
2022 let e = _mm_set_pd(0., 1.);
2023 assert_eq_m128d(r, e);
2024 }
2025
2026 #[simd_test(enable = "avx512f,avx512vl")]
2027 unsafe fn test_mm_maskz_sqrt_pd() {
2028 let a = _mm_set_pd(0., 1.);
2029 let r = _mm_maskz_sqrt_pd(0, a);
2030 assert_eq_m128d(r, _mm_setzero_pd());
2031 let r = _mm_maskz_sqrt_pd(0b00000011, a);
2032 let e = _mm_set_pd(0., 1.);
2033 assert_eq_m128d(r, e);
2034 }
2035
2036 #[simd_test(enable = "avx512f")]
2037 const unsafe fn test_mm512_fmadd_pd() {
2038 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2039 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2040 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2041 let r = _mm512_fmadd_pd(a, b, c);
2042 let e = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
2043 assert_eq_m512d(r, e);
2044 }
2045
2046 #[simd_test(enable = "avx512f")]
2047 const unsafe fn test_mm512_mask_fmadd_pd() {
2048 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2049 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2050 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2051 let r = _mm512_mask_fmadd_pd(a, 0, b, c);
2052 assert_eq_m512d(r, a);
2053 let r = _mm512_mask_fmadd_pd(a, 0b00001111, b, c);
2054 let e = _mm512_setr_pd(1., 2., 3., 4., 1., 1., 1., 1.);
2055 assert_eq_m512d(r, e);
2056 }
2057
2058 #[simd_test(enable = "avx512f")]
2059 const unsafe fn test_mm512_maskz_fmadd_pd() {
2060 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2061 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2062 let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2063 let r = _mm512_maskz_fmadd_pd(0, a, b, c);
2064 assert_eq_m512d(r, _mm512_setzero_pd());
2065 let r = _mm512_maskz_fmadd_pd(0b00001111, a, b, c);
2066 let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
2067 assert_eq_m512d(r, e);
2068 }
2069
2070 #[simd_test(enable = "avx512f")]
2071 const unsafe fn test_mm512_mask3_fmadd_pd() {
2072 let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2073 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2074 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2075 let r = _mm512_mask3_fmadd_pd(a, b, c, 0);
2076 assert_eq_m512d(r, c);
2077 let r = _mm512_mask3_fmadd_pd(a, b, c, 0b00001111);
2078 let e = _mm512_setr_pd(1., 2., 3., 4., 2., 2., 2., 2.);
2079 assert_eq_m512d(r, e);
2080 }
2081
2082 #[simd_test(enable = "avx512f,avx512vl")]
2083 const unsafe fn test_mm256_mask_fmadd_pd() {
2084 let a = _mm256_set1_pd(1.);
2085 let b = _mm256_set_pd(0., 1., 2., 3.);
2086 let c = _mm256_set1_pd(1.);
2087 let r = _mm256_mask_fmadd_pd(a, 0, b, c);
2088 assert_eq_m256d(r, a);
2089 let r = _mm256_mask_fmadd_pd(a, 0b00001111, b, c);
2090 let e = _mm256_set_pd(1., 2., 3., 4.);
2091 assert_eq_m256d(r, e);
2092 }
2093
2094 #[simd_test(enable = "avx512f,avx512vl")]
2095 const unsafe fn test_mm256_maskz_fmadd_pd() {
2096 let a = _mm256_set1_pd(1.);
2097 let b = _mm256_set_pd(0., 1., 2., 3.);
2098 let c = _mm256_set1_pd(1.);
2099 let r = _mm256_maskz_fmadd_pd(0, a, b, c);
2100 assert_eq_m256d(r, _mm256_setzero_pd());
2101 let r = _mm256_maskz_fmadd_pd(0b00001111, a, b, c);
2102 let e = _mm256_set_pd(1., 2., 3., 4.);
2103 assert_eq_m256d(r, e);
2104 }
2105
2106 #[simd_test(enable = "avx512f,avx512vl")]
2107 const unsafe fn test_mm256_mask3_fmadd_pd() {
2108 let a = _mm256_set1_pd(1.);
2109 let b = _mm256_set_pd(0., 1., 2., 3.);
2110 let c = _mm256_set1_pd(1.);
2111 let r = _mm256_mask3_fmadd_pd(a, b, c, 0);
2112 assert_eq_m256d(r, c);
2113 let r = _mm256_mask3_fmadd_pd(a, b, c, 0b00001111);
2114 let e = _mm256_set_pd(1., 2., 3., 4.);
2115 assert_eq_m256d(r, e);
2116 }
2117
2118 #[simd_test(enable = "avx512f,avx512vl")]
2119 const unsafe fn test_mm_mask_fmadd_pd() {
2120 let a = _mm_set1_pd(1.);
2121 let b = _mm_set_pd(0., 1.);
2122 let c = _mm_set1_pd(1.);
2123 let r = _mm_mask_fmadd_pd(a, 0, b, c);
2124 assert_eq_m128d(r, a);
2125 let r = _mm_mask_fmadd_pd(a, 0b00000011, b, c);
2126 let e = _mm_set_pd(1., 2.);
2127 assert_eq_m128d(r, e);
2128 }
2129
2130 #[simd_test(enable = "avx512f,avx512vl")]
2131 const unsafe fn test_mm_maskz_fmadd_pd() {
2132 let a = _mm_set1_pd(1.);
2133 let b = _mm_set_pd(0., 1.);
2134 let c = _mm_set1_pd(1.);
2135 let r = _mm_maskz_fmadd_pd(0, a, b, c);
2136 assert_eq_m128d(r, _mm_setzero_pd());
2137 let r = _mm_maskz_fmadd_pd(0b00000011, a, b, c);
2138 let e = _mm_set_pd(1., 2.);
2139 assert_eq_m128d(r, e);
2140 }
2141
2142 #[simd_test(enable = "avx512f,avx512vl")]
2143 const unsafe fn test_mm_mask3_fmadd_pd() {
2144 let a = _mm_set1_pd(1.);
2145 let b = _mm_set_pd(0., 1.);
2146 let c = _mm_set1_pd(1.);
2147 let r = _mm_mask3_fmadd_pd(a, b, c, 0);
2148 assert_eq_m128d(r, c);
2149 let r = _mm_mask3_fmadd_pd(a, b, c, 0b00000011);
2150 let e = _mm_set_pd(1., 2.);
2151 assert_eq_m128d(r, e);
2152 }
2153
2154 #[simd_test(enable = "avx512f")]
2155 const unsafe fn test_mm512_fmsub_pd() {
2156 let a = _mm512_set1_pd(1.);
2157 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2158 let c = _mm512_set1_pd(1.);
2159 let r = _mm512_fmsub_pd(a, b, c);
2160 let e = _mm512_setr_pd(-1., 0., 1., 2., 3., 4., 5., 6.);
2161 assert_eq_m512d(r, e);
2162 }
2163
2164 #[simd_test(enable = "avx512f")]
2165 const unsafe fn test_mm512_mask_fmsub_pd() {
2166 let a = _mm512_set1_pd(1.);
2167 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2168 let c = _mm512_set1_pd(1.);
2169 let r = _mm512_mask_fmsub_pd(a, 0, b, c);
2170 assert_eq_m512d(r, a);
2171 let r = _mm512_mask_fmsub_pd(a, 0b00001111, b, c);
2172 let e = _mm512_setr_pd(-1., 0., 1., 2., 1., 1., 1., 1.);
2173 assert_eq_m512d(r, e);
2174 }
2175
2176 #[simd_test(enable = "avx512f")]
2177 const unsafe fn test_mm512_maskz_fmsub_pd() {
2178 let a = _mm512_set1_pd(1.);
2179 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2180 let c = _mm512_set1_pd(1.);
2181 let r = _mm512_maskz_fmsub_pd(0, a, b, c);
2182 assert_eq_m512d(r, _mm512_setzero_pd());
2183 let r = _mm512_maskz_fmsub_pd(0b00001111, a, b, c);
2184 let e = _mm512_setr_pd(-1., 0., 1., 2., 0., 0., 0., 0.);
2185 assert_eq_m512d(r, e);
2186 }
2187
2188 #[simd_test(enable = "avx512f")]
2189 const unsafe fn test_mm512_mask3_fmsub_pd() {
2190 let a = _mm512_set1_pd(1.);
2191 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2192 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2193 let r = _mm512_mask3_fmsub_pd(a, b, c, 0);
2194 assert_eq_m512d(r, c);
2195 let r = _mm512_mask3_fmsub_pd(a, b, c, 0b00001111);
2196 let e = _mm512_setr_pd(-1., 0., 1., 2., 2., 2., 2., 2.);
2197 assert_eq_m512d(r, e);
2198 }
2199
2200 #[simd_test(enable = "avx512f,avx512vl")]
2201 const unsafe fn test_mm256_mask_fmsub_pd() {
2202 let a = _mm256_set1_pd(1.);
2203 let b = _mm256_set_pd(0., 1., 2., 3.);
2204 let c = _mm256_set1_pd(1.);
2205 let r = _mm256_mask_fmsub_pd(a, 0, b, c);
2206 assert_eq_m256d(r, a);
2207 let r = _mm256_mask_fmsub_pd(a, 0b00001111, b, c);
2208 let e = _mm256_set_pd(-1., 0., 1., 2.);
2209 assert_eq_m256d(r, e);
2210 }
2211
2212 #[simd_test(enable = "avx512f,avx512vl")]
2213 const unsafe fn test_mm256_maskz_fmsub_pd() {
2214 let a = _mm256_set1_pd(1.);
2215 let b = _mm256_set_pd(0., 1., 2., 3.);
2216 let c = _mm256_set1_pd(1.);
2217 let r = _mm256_maskz_fmsub_pd(0, a, b, c);
2218 assert_eq_m256d(r, _mm256_setzero_pd());
2219 let r = _mm256_maskz_fmsub_pd(0b00001111, a, b, c);
2220 let e = _mm256_set_pd(-1., 0., 1., 2.);
2221 assert_eq_m256d(r, e);
2222 }
2223
2224 #[simd_test(enable = "avx512f,avx512vl")]
2225 const unsafe fn test_mm256_mask3_fmsub_pd() {
2226 let a = _mm256_set1_pd(1.);
2227 let b = _mm256_set_pd(0., 1., 2., 3.);
2228 let c = _mm256_set1_pd(1.);
2229 let r = _mm256_mask3_fmsub_pd(a, b, c, 0);
2230 assert_eq_m256d(r, c);
2231 let r = _mm256_mask3_fmsub_pd(a, b, c, 0b00001111);
2232 let e = _mm256_set_pd(-1., 0., 1., 2.);
2233 assert_eq_m256d(r, e);
2234 }
2235
2236 #[simd_test(enable = "avx512f,avx512vl")]
2237 const unsafe fn test_mm_mask_fmsub_pd() {
2238 let a = _mm_set1_pd(1.);
2239 let b = _mm_set_pd(0., 1.);
2240 let c = _mm_set1_pd(1.);
2241 let r = _mm_mask_fmsub_pd(a, 0, b, c);
2242 assert_eq_m128d(r, a);
2243 let r = _mm_mask_fmsub_pd(a, 0b00000011, b, c);
2244 let e = _mm_set_pd(-1., 0.);
2245 assert_eq_m128d(r, e);
2246 }
2247
2248 #[simd_test(enable = "avx512f,avx512vl")]
2249 const unsafe fn test_mm_maskz_fmsub_pd() {
2250 let a = _mm_set1_pd(1.);
2251 let b = _mm_set_pd(0., 1.);
2252 let c = _mm_set1_pd(1.);
2253 let r = _mm_maskz_fmsub_pd(0, a, b, c);
2254 assert_eq_m128d(r, _mm_setzero_pd());
2255 let r = _mm_maskz_fmsub_pd(0b00000011, a, b, c);
2256 let e = _mm_set_pd(-1., 0.);
2257 assert_eq_m128d(r, e);
2258 }
2259
2260 #[simd_test(enable = "avx512f,avx512vl")]
2261 const unsafe fn test_mm_mask3_fmsub_pd() {
2262 let a = _mm_set1_pd(1.);
2263 let b = _mm_set_pd(0., 1.);
2264 let c = _mm_set1_pd(1.);
2265 let r = _mm_mask3_fmsub_pd(a, b, c, 0);
2266 assert_eq_m128d(r, c);
2267 let r = _mm_mask3_fmsub_pd(a, b, c, 0b00000011);
2268 let e = _mm_set_pd(-1., 0.);
2269 assert_eq_m128d(r, e);
2270 }
2271
2272 #[simd_test(enable = "avx512f")]
2273 const unsafe fn test_mm512_fmaddsub_pd() {
2274 let a = _mm512_set1_pd(1.);
2275 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2276 let c = _mm512_set1_pd(1.);
2277 let r = _mm512_fmaddsub_pd(a, b, c);
2278 let e = _mm512_setr_pd(-1., 2., 1., 4., 3., 6., 5., 8.);
2279 assert_eq_m512d(r, e);
2280 }
2281
2282 #[simd_test(enable = "avx512f")]
2283 const unsafe fn test_mm512_mask_fmaddsub_pd() {
2284 let a = _mm512_set1_pd(1.);
2285 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2286 let c = _mm512_set1_pd(1.);
2287 let r = _mm512_mask_fmaddsub_pd(a, 0, b, c);
2288 assert_eq_m512d(r, a);
2289 let r = _mm512_mask_fmaddsub_pd(a, 0b00001111, b, c);
2290 let e = _mm512_setr_pd(-1., 2., 1., 4., 1., 1., 1., 1.);
2291 assert_eq_m512d(r, e);
2292 }
2293
2294 #[simd_test(enable = "avx512f")]
2295 const unsafe fn test_mm512_maskz_fmaddsub_pd() {
2296 let a = _mm512_set1_pd(1.);
2297 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2298 let c = _mm512_set1_pd(1.);
2299 let r = _mm512_maskz_fmaddsub_pd(0, a, b, c);
2300 assert_eq_m512d(r, _mm512_setzero_pd());
2301 let r = _mm512_maskz_fmaddsub_pd(0b00001111, a, b, c);
2302 let e = _mm512_setr_pd(-1., 2., 1., 4., 0., 0., 0., 0.);
2303 assert_eq_m512d(r, e);
2304 }
2305
2306 #[simd_test(enable = "avx512f")]
2307 const unsafe fn test_mm512_mask3_fmaddsub_pd() {
2308 let a = _mm512_set1_pd(1.);
2309 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2310 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2311 let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0);
2312 assert_eq_m512d(r, c);
2313 let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2314 let e = _mm512_setr_pd(-1., 2., 1., 4., 2., 2., 2., 2.);
2315 assert_eq_m512d(r, e);
2316 }
2317
2318 #[simd_test(enable = "avx512f,avx512vl")]
2319 const unsafe fn test_mm256_mask_fmaddsub_pd() {
2320 let a = _mm256_set1_pd(1.);
2321 let b = _mm256_set_pd(0., 1., 2., 3.);
2322 let c = _mm256_set1_pd(1.);
2323 let r = _mm256_mask_fmaddsub_pd(a, 0, b, c);
2324 assert_eq_m256d(r, a);
2325 let r = _mm256_mask_fmaddsub_pd(a, 0b00001111, b, c);
2326 let e = _mm256_set_pd(1., 0., 3., 2.);
2327 assert_eq_m256d(r, e);
2328 }
2329
2330 #[simd_test(enable = "avx512f,avx512vl")]
2331 const unsafe fn test_mm256_maskz_fmaddsub_pd() {
2332 let a = _mm256_set1_pd(1.);
2333 let b = _mm256_set_pd(0., 1., 2., 3.);
2334 let c = _mm256_set1_pd(1.);
2335 let r = _mm256_maskz_fmaddsub_pd(0, a, b, c);
2336 assert_eq_m256d(r, _mm256_setzero_pd());
2337 let r = _mm256_maskz_fmaddsub_pd(0b00001111, a, b, c);
2338 let e = _mm256_set_pd(1., 0., 3., 2.);
2339 assert_eq_m256d(r, e);
2340 }
2341
2342 #[simd_test(enable = "avx512f,avx512vl")]
2343 const unsafe fn test_mm256_mask3_fmaddsub_pd() {
2344 let a = _mm256_set1_pd(1.);
2345 let b = _mm256_set_pd(0., 1., 2., 3.);
2346 let c = _mm256_set1_pd(1.);
2347 let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0);
2348 assert_eq_m256d(r, c);
2349 let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2350 let e = _mm256_set_pd(1., 0., 3., 2.);
2351 assert_eq_m256d(r, e);
2352 }
2353
2354 #[simd_test(enable = "avx512f,avx512vl")]
2355 const unsafe fn test_mm_mask_fmaddsub_pd() {
2356 let a = _mm_set1_pd(1.);
2357 let b = _mm_set_pd(0., 1.);
2358 let c = _mm_set1_pd(1.);
2359 let r = _mm_mask_fmaddsub_pd(a, 0, b, c);
2360 assert_eq_m128d(r, a);
2361 let r = _mm_mask_fmaddsub_pd(a, 0b00000011, b, c);
2362 let e = _mm_set_pd(1., 0.);
2363 assert_eq_m128d(r, e);
2364 }
2365
2366 #[simd_test(enable = "avx512f,avx512vl")]
2367 const unsafe fn test_mm_maskz_fmaddsub_pd() {
2368 let a = _mm_set1_pd(1.);
2369 let b = _mm_set_pd(0., 1.);
2370 let c = _mm_set1_pd(1.);
2371 let r = _mm_maskz_fmaddsub_pd(0, a, b, c);
2372 assert_eq_m128d(r, _mm_setzero_pd());
2373 let r = _mm_maskz_fmaddsub_pd(0b00000011, a, b, c);
2374 let e = _mm_set_pd(1., 0.);
2375 assert_eq_m128d(r, e);
2376 }
2377
2378 #[simd_test(enable = "avx512f,avx512vl")]
2379 const unsafe fn test_mm_mask3_fmaddsub_pd() {
2380 let a = _mm_set1_pd(1.);
2381 let b = _mm_set_pd(0., 1.);
2382 let c = _mm_set1_pd(1.);
2383 let r = _mm_mask3_fmaddsub_pd(a, b, c, 0);
2384 assert_eq_m128d(r, c);
2385 let r = _mm_mask3_fmaddsub_pd(a, b, c, 0b00000011);
2386 let e = _mm_set_pd(1., 0.);
2387 assert_eq_m128d(r, e);
2388 }
2389
2390 #[simd_test(enable = "avx512f")]
2391 const unsafe fn test_mm512_fmsubadd_pd() {
2392 let a = _mm512_set1_pd(1.);
2393 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2394 let c = _mm512_set1_pd(1.);
2395 let r = _mm512_fmsubadd_pd(a, b, c);
2396 let e = _mm512_setr_pd(1., 0., 3., 2., 5., 4., 7., 6.);
2397 assert_eq_m512d(r, e);
2398 }
2399
2400 #[simd_test(enable = "avx512f")]
2401 const unsafe fn test_mm512_mask_fmsubadd_pd() {
2402 let a = _mm512_set1_pd(1.);
2403 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2404 let c = _mm512_set1_pd(1.);
2405 let r = _mm512_mask_fmsubadd_pd(a, 0, b, c);
2406 assert_eq_m512d(r, a);
2407 let r = _mm512_mask_fmsubadd_pd(a, 0b00001111, b, c);
2408 let e = _mm512_setr_pd(1., 0., 3., 2., 1., 1., 1., 1.);
2409 assert_eq_m512d(r, e);
2410 }
2411
2412 #[simd_test(enable = "avx512f")]
2413 const unsafe fn test_mm512_maskz_fmsubadd_pd() {
2414 let a = _mm512_set1_pd(1.);
2415 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2416 let c = _mm512_set1_pd(1.);
2417 let r = _mm512_maskz_fmsubadd_pd(0, a, b, c);
2418 assert_eq_m512d(r, _mm512_setzero_pd());
2419 let r = _mm512_maskz_fmsubadd_pd(0b00001111, a, b, c);
2420 let e = _mm512_setr_pd(1., 0., 3., 2., 0., 0., 0., 0.);
2421 assert_eq_m512d(r, e);
2422 }
2423
2424 #[simd_test(enable = "avx512f")]
2425 const unsafe fn test_mm512_mask3_fmsubadd_pd() {
2426 let a = _mm512_set1_pd(1.);
2427 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2428 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2429 let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0);
2430 assert_eq_m512d(r, c);
2431 let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2432 let e = _mm512_setr_pd(1., 0., 3., 2., 2., 2., 2., 2.);
2433 assert_eq_m512d(r, e);
2434 }
2435
2436 #[simd_test(enable = "avx512f,avx512vl")]
2437 const unsafe fn test_mm256_mask_fmsubadd_pd() {
2438 let a = _mm256_set1_pd(1.);
2439 let b = _mm256_set_pd(0., 1., 2., 3.);
2440 let c = _mm256_set1_pd(1.);
2441 let r = _mm256_mask_fmsubadd_pd(a, 0, b, c);
2442 assert_eq_m256d(r, a);
2443 let r = _mm256_mask_fmsubadd_pd(a, 0b00001111, b, c);
2444 let e = _mm256_set_pd(-1., 2., 1., 4.);
2445 assert_eq_m256d(r, e);
2446 }
2447
2448 #[simd_test(enable = "avx512f,avx512vl")]
2449 const unsafe fn test_mm256_maskz_fmsubadd_pd() {
2450 let a = _mm256_set1_pd(1.);
2451 let b = _mm256_set_pd(0., 1., 2., 3.);
2452 let c = _mm256_set1_pd(1.);
2453 let r = _mm256_maskz_fmsubadd_pd(0, a, b, c);
2454 assert_eq_m256d(r, _mm256_setzero_pd());
2455 let r = _mm256_maskz_fmsubadd_pd(0b00001111, a, b, c);
2456 let e = _mm256_set_pd(-1., 2., 1., 4.);
2457 assert_eq_m256d(r, e);
2458 }
2459
2460 #[simd_test(enable = "avx512f,avx512vl")]
2461 const unsafe fn test_mm256_mask3_fmsubadd_pd() {
2462 let a = _mm256_set1_pd(1.);
2463 let b = _mm256_set_pd(0., 1., 2., 3.);
2464 let c = _mm256_set1_pd(1.);
2465 let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0);
2466 assert_eq_m256d(r, c);
2467 let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2468 let e = _mm256_set_pd(-1., 2., 1., 4.);
2469 assert_eq_m256d(r, e);
2470 }
2471
2472 #[simd_test(enable = "avx512f,avx512vl")]
2473 const unsafe fn test_mm_mask_fmsubadd_pd() {
2474 let a = _mm_set1_pd(1.);
2475 let b = _mm_set_pd(0., 1.);
2476 let c = _mm_set1_pd(1.);
2477 let r = _mm_mask_fmsubadd_pd(a, 0, b, c);
2478 assert_eq_m128d(r, a);
2479 let r = _mm_mask_fmsubadd_pd(a, 0b00000011, b, c);
2480 let e = _mm_set_pd(-1., 2.);
2481 assert_eq_m128d(r, e);
2482 }
2483
2484 #[simd_test(enable = "avx512f,avx512vl")]
2485 const unsafe fn test_mm_maskz_fmsubadd_pd() {
2486 let a = _mm_set1_pd(1.);
2487 let b = _mm_set_pd(0., 1.);
2488 let c = _mm_set1_pd(1.);
2489 let r = _mm_maskz_fmsubadd_pd(0, a, b, c);
2490 assert_eq_m128d(r, _mm_setzero_pd());
2491 let r = _mm_maskz_fmsubadd_pd(0b00000011, a, b, c);
2492 let e = _mm_set_pd(-1., 2.);
2493 assert_eq_m128d(r, e);
2494 }
2495
2496 #[simd_test(enable = "avx512f,avx512vl")]
2497 const unsafe fn test_mm_mask3_fmsubadd_pd() {
2498 let a = _mm_set1_pd(1.);
2499 let b = _mm_set_pd(0., 1.);
2500 let c = _mm_set1_pd(1.);
2501 let r = _mm_mask3_fmsubadd_pd(a, b, c, 0);
2502 assert_eq_m128d(r, c);
2503 let r = _mm_mask3_fmsubadd_pd(a, b, c, 0b00000011);
2504 let e = _mm_set_pd(-1., 2.);
2505 assert_eq_m128d(r, e);
2506 }
2507
2508 #[simd_test(enable = "avx512f")]
2509 const unsafe fn test_mm512_fnmadd_pd() {
2510 let a = _mm512_set1_pd(1.);
2511 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2512 let c = _mm512_set1_pd(1.);
2513 let r = _mm512_fnmadd_pd(a, b, c);
2514 let e = _mm512_setr_pd(1., 0., -1., -2., -3., -4., -5., -6.);
2515 assert_eq_m512d(r, e);
2516 }
2517
2518 #[simd_test(enable = "avx512f")]
2519 const unsafe fn test_mm512_mask_fnmadd_pd() {
2520 let a = _mm512_set1_pd(1.);
2521 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2522 let c = _mm512_set1_pd(1.);
2523 let r = _mm512_mask_fnmadd_pd(a, 0, b, c);
2524 assert_eq_m512d(r, a);
2525 let r = _mm512_mask_fnmadd_pd(a, 0b00001111, b, c);
2526 let e = _mm512_setr_pd(1., 0., -1., -2., 1., 1., 1., 1.);
2527 assert_eq_m512d(r, e);
2528 }
2529
2530 #[simd_test(enable = "avx512f")]
2531 const unsafe fn test_mm512_maskz_fnmadd_pd() {
2532 let a = _mm512_set1_pd(1.);
2533 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2534 let c = _mm512_set1_pd(1.);
2535 let r = _mm512_maskz_fnmadd_pd(0, a, b, c);
2536 assert_eq_m512d(r, _mm512_setzero_pd());
2537 let r = _mm512_maskz_fnmadd_pd(0b00001111, a, b, c);
2538 let e = _mm512_setr_pd(1., 0., -1., -2., 0., 0., 0., 0.);
2539 assert_eq_m512d(r, e);
2540 }
2541
2542 #[simd_test(enable = "avx512f")]
2543 const unsafe fn test_mm512_mask3_fnmadd_pd() {
2544 let a = _mm512_set1_pd(1.);
2545 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2546 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2547 let r = _mm512_mask3_fnmadd_pd(a, b, c, 0);
2548 assert_eq_m512d(r, c);
2549 let r = _mm512_mask3_fnmadd_pd(a, b, c, 0b00001111);
2550 let e = _mm512_setr_pd(1., 0., -1., -2., 2., 2., 2., 2.);
2551 assert_eq_m512d(r, e);
2552 }
2553
2554 #[simd_test(enable = "avx512f,avx512vl")]
2555 const unsafe fn test_mm256_mask_fnmadd_pd() {
2556 let a = _mm256_set1_pd(1.);
2557 let b = _mm256_set_pd(0., 1., 2., 3.);
2558 let c = _mm256_set1_pd(1.);
2559 let r = _mm256_mask_fnmadd_pd(a, 0, b, c);
2560 assert_eq_m256d(r, a);
2561 let r = _mm256_mask_fnmadd_pd(a, 0b00001111, b, c);
2562 let e = _mm256_set_pd(1., 0., -1., -2.);
2563 assert_eq_m256d(r, e);
2564 }
2565
2566 #[simd_test(enable = "avx512f,avx512vl")]
2567 const unsafe fn test_mm256_maskz_fnmadd_pd() {
2568 let a = _mm256_set1_pd(1.);
2569 let b = _mm256_set_pd(0., 1., 2., 3.);
2570 let c = _mm256_set1_pd(1.);
2571 let r = _mm256_maskz_fnmadd_pd(0, a, b, c);
2572 assert_eq_m256d(r, _mm256_setzero_pd());
2573 let r = _mm256_maskz_fnmadd_pd(0b00001111, a, b, c);
2574 let e = _mm256_set_pd(1., 0., -1., -2.);
2575 assert_eq_m256d(r, e);
2576 }
2577
2578 #[simd_test(enable = "avx512f,avx512vl")]
2579 const unsafe fn test_mm256_mask3_fnmadd_pd() {
2580 let a = _mm256_set1_pd(1.);
2581 let b = _mm256_set_pd(0., 1., 2., 3.);
2582 let c = _mm256_set1_pd(1.);
2583 let r = _mm256_mask3_fnmadd_pd(a, b, c, 0);
2584 assert_eq_m256d(r, c);
2585 let r = _mm256_mask3_fnmadd_pd(a, b, c, 0b00001111);
2586 let e = _mm256_set_pd(1., 0., -1., -2.);
2587 assert_eq_m256d(r, e);
2588 }
2589
2590 #[simd_test(enable = "avx512f,avx512vl")]
2591 const unsafe fn test_mm_mask_fnmadd_pd() {
2592 let a = _mm_set1_pd(1.);
2593 let b = _mm_set_pd(0., 1.);
2594 let c = _mm_set1_pd(1.);
2595 let r = _mm_mask_fnmadd_pd(a, 0, b, c);
2596 assert_eq_m128d(r, a);
2597 let r = _mm_mask_fnmadd_pd(a, 0b00000011, b, c);
2598 let e = _mm_set_pd(1., 0.);
2599 assert_eq_m128d(r, e);
2600 }
2601
2602 #[simd_test(enable = "avx512f,avx512vl")]
2603 const unsafe fn test_mm_maskz_fnmadd_pd() {
2604 let a = _mm_set1_pd(1.);
2605 let b = _mm_set_pd(0., 1.);
2606 let c = _mm_set1_pd(1.);
2607 let r = _mm_maskz_fnmadd_pd(0, a, b, c);
2608 assert_eq_m128d(r, _mm_setzero_pd());
2609 let r = _mm_maskz_fnmadd_pd(0b00000011, a, b, c);
2610 let e = _mm_set_pd(1., 0.);
2611 assert_eq_m128d(r, e);
2612 }
2613
2614 #[simd_test(enable = "avx512f,avx512vl")]
2615 const unsafe fn test_mm_mask3_fnmadd_pd() {
2616 let a = _mm_set1_pd(1.);
2617 let b = _mm_set_pd(0., 1.);
2618 let c = _mm_set1_pd(1.);
2619 let r = _mm_mask3_fnmadd_pd(a, b, c, 0);
2620 assert_eq_m128d(r, c);
2621 let r = _mm_mask3_fnmadd_pd(a, b, c, 0b00000011);
2622 let e = _mm_set_pd(1., 0.);
2623 assert_eq_m128d(r, e);
2624 }
2625
2626 #[simd_test(enable = "avx512f")]
2627 const unsafe fn test_mm512_fnmsub_pd() {
2628 let a = _mm512_set1_pd(1.);
2629 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2630 let c = _mm512_set1_pd(1.);
2631 let r = _mm512_fnmsub_pd(a, b, c);
2632 let e = _mm512_setr_pd(-1., -2., -3., -4., -5., -6., -7., -8.);
2633 assert_eq_m512d(r, e);
2634 }
2635
2636 #[simd_test(enable = "avx512f")]
2637 const unsafe fn test_mm512_mask_fnmsub_pd() {
2638 let a = _mm512_set1_pd(1.);
2639 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2640 let c = _mm512_set1_pd(1.);
2641 let r = _mm512_mask_fnmsub_pd(a, 0, b, c);
2642 assert_eq_m512d(r, a);
2643 let r = _mm512_mask_fnmsub_pd(a, 0b00001111, b, c);
2644 let e = _mm512_setr_pd(-1., -2., -3., -4., 1., 1., 1., 1.);
2645 assert_eq_m512d(r, e);
2646 }
2647
2648 #[simd_test(enable = "avx512f")]
2649 const unsafe fn test_mm512_maskz_fnmsub_pd() {
2650 let a = _mm512_set1_pd(1.);
2651 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2652 let c = _mm512_set1_pd(1.);
2653 let r = _mm512_maskz_fnmsub_pd(0, a, b, c);
2654 assert_eq_m512d(r, _mm512_setzero_pd());
2655 let r = _mm512_maskz_fnmsub_pd(0b00001111, a, b, c);
2656 let e = _mm512_setr_pd(-1., -2., -3., -4., 0., 0., 0., 0.);
2657 assert_eq_m512d(r, e);
2658 }
2659
2660 #[simd_test(enable = "avx512f")]
2661 const unsafe fn test_mm512_mask3_fnmsub_pd() {
2662 let a = _mm512_set1_pd(1.);
2663 let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2664 let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2665 let r = _mm512_mask3_fnmsub_pd(a, b, c, 0);
2666 assert_eq_m512d(r, c);
2667 let r = _mm512_mask3_fnmsub_pd(a, b, c, 0b00001111);
2668 let e = _mm512_setr_pd(-1., -2., -3., -4., 2., 2., 2., 2.);
2669 assert_eq_m512d(r, e);
2670 }
2671
2672 #[simd_test(enable = "avx512f,avx512vl")]
2673 const unsafe fn test_mm256_mask_fnmsub_pd() {
2674 let a = _mm256_set1_pd(1.);
2675 let b = _mm256_set_pd(0., 1., 2., 3.);
2676 let c = _mm256_set1_pd(1.);
2677 let r = _mm256_mask_fnmsub_pd(a, 0, b, c);
2678 assert_eq_m256d(r, a);
2679 let r = _mm256_mask_fnmsub_pd(a, 0b00001111, b, c);
2680 let e = _mm256_set_pd(-1., -2., -3., -4.);
2681 assert_eq_m256d(r, e);
2682 }
2683
2684 #[simd_test(enable = "avx512f,avx512vl")]
2685 const unsafe fn test_mm256_maskz_fnmsub_pd() {
2686 let a = _mm256_set1_pd(1.);
2687 let b = _mm256_set_pd(0., 1., 2., 3.);
2688 let c = _mm256_set1_pd(1.);
2689 let r = _mm256_maskz_fnmsub_pd(0, a, b, c);
2690 assert_eq_m256d(r, _mm256_setzero_pd());
2691 let r = _mm256_maskz_fnmsub_pd(0b00001111, a, b, c);
2692 let e = _mm256_set_pd(-1., -2., -3., -4.);
2693 assert_eq_m256d(r, e);
2694 }
2695
2696 #[simd_test(enable = "avx512f,avx512vl")]
2697 const unsafe fn test_mm256_mask3_fnmsub_pd() {
2698 let a = _mm256_set1_pd(1.);
2699 let b = _mm256_set_pd(0., 1., 2., 3.);
2700 let c = _mm256_set1_pd(1.);
2701 let r = _mm256_mask3_fnmsub_pd(a, b, c, 0);
2702 assert_eq_m256d(r, c);
2703 let r = _mm256_mask3_fnmsub_pd(a, b, c, 0b00001111);
2704 let e = _mm256_set_pd(-1., -2., -3., -4.);
2705 assert_eq_m256d(r, e);
2706 }
2707
2708 #[simd_test(enable = "avx512f,avx512vl")]
2709 const unsafe fn test_mm_mask_fnmsub_pd() {
2710 let a = _mm_set1_pd(1.);
2711 let b = _mm_set_pd(0., 1.);
2712 let c = _mm_set1_pd(1.);
2713 let r = _mm_mask_fnmsub_pd(a, 0, b, c);
2714 assert_eq_m128d(r, a);
2715 let r = _mm_mask_fnmsub_pd(a, 0b00000011, b, c);
2716 let e = _mm_set_pd(-1., -2.);
2717 assert_eq_m128d(r, e);
2718 }
2719
2720 #[simd_test(enable = "avx512f,avx512vl")]
2721 const unsafe fn test_mm_maskz_fnmsub_pd() {
2722 let a = _mm_set1_pd(1.);
2723 let b = _mm_set_pd(0., 1.);
2724 let c = _mm_set1_pd(1.);
2725 let r = _mm_maskz_fnmsub_pd(0, a, b, c);
2726 assert_eq_m128d(r, _mm_setzero_pd());
2727 let r = _mm_maskz_fnmsub_pd(0b00000011, a, b, c);
2728 let e = _mm_set_pd(-1., -2.);
2729 assert_eq_m128d(r, e);
2730 }
2731
2732 #[simd_test(enable = "avx512f,avx512vl")]
2733 const unsafe fn test_mm_mask3_fnmsub_pd() {
2734 let a = _mm_set1_pd(1.);
2735 let b = _mm_set_pd(0., 1.);
2736 let c = _mm_set1_pd(1.);
2737 let r = _mm_mask3_fnmsub_pd(a, b, c, 0);
2738 assert_eq_m128d(r, c);
2739 let r = _mm_mask3_fnmsub_pd(a, b, c, 0b00000011);
2740 let e = _mm_set_pd(-1., -2.);
2741 assert_eq_m128d(r, e);
2742 }
2743
2744 #[simd_test(enable = "avx512f")]
2745 unsafe fn test_mm512_rcp14_pd() {
2746 let a = _mm512_set1_pd(3.);
2747 let r = _mm512_rcp14_pd(a);
2748 let e = _mm512_set1_pd(0.3333320617675781);
2749 assert_eq_m512d(r, e);
2750 }
2751
2752 #[simd_test(enable = "avx512f")]
2753 unsafe fn test_mm512_mask_rcp14_pd() {
2754 let a = _mm512_set1_pd(3.);
2755 let r = _mm512_mask_rcp14_pd(a, 0, a);
2756 assert_eq_m512d(r, a);
2757 let r = _mm512_mask_rcp14_pd(a, 0b11110000, a);
2758 #[rustfmt::skip]
2759 let e = _mm512_setr_pd(
2760 3., 3., 3., 3.,
2761 0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2762 );
2763 assert_eq_m512d(r, e);
2764 }
2765
2766 #[simd_test(enable = "avx512f")]
2767 unsafe fn test_mm512_maskz_rcp14_pd() {
2768 let a = _mm512_set1_pd(3.);
2769 let r = _mm512_maskz_rcp14_pd(0, a);
2770 assert_eq_m512d(r, _mm512_setzero_pd());
2771 let r = _mm512_maskz_rcp14_pd(0b11110000, a);
2772 #[rustfmt::skip]
2773 let e = _mm512_setr_pd(
2774 0., 0., 0., 0.,
2775 0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2776 );
2777 assert_eq_m512d(r, e);
2778 }
2779
2780 #[simd_test(enable = "avx512f,avx512vl")]
2781 unsafe fn test_mm256_rcp14_pd() {
2782 let a = _mm256_set1_pd(3.);
2783 let r = _mm256_rcp14_pd(a);
2784 let e = _mm256_set1_pd(0.3333320617675781);
2785 assert_eq_m256d(r, e);
2786 }
2787
2788 #[simd_test(enable = "avx512f,avx512vl")]
2789 unsafe fn test_mm256_mask_rcp14_pd() {
2790 let a = _mm256_set1_pd(3.);
2791 let r = _mm256_mask_rcp14_pd(a, 0, a);
2792 assert_eq_m256d(r, a);
2793 let r = _mm256_mask_rcp14_pd(a, 0b00001111, a);
2794 let e = _mm256_set1_pd(0.3333320617675781);
2795 assert_eq_m256d(r, e);
2796 }
2797
2798 #[simd_test(enable = "avx512f,avx512vl")]
2799 unsafe fn test_mm256_maskz_rcp14_pd() {
2800 let a = _mm256_set1_pd(3.);
2801 let r = _mm256_maskz_rcp14_pd(0, a);
2802 assert_eq_m256d(r, _mm256_setzero_pd());
2803 let r = _mm256_maskz_rcp14_pd(0b00001111, a);
2804 let e = _mm256_set1_pd(0.3333320617675781);
2805 assert_eq_m256d(r, e);
2806 }
2807
2808 #[simd_test(enable = "avx512f,avx512vl")]
2809 unsafe fn test_mm_rcp14_pd() {
2810 let a = _mm_set1_pd(3.);
2811 let r = _mm_rcp14_pd(a);
2812 let e = _mm_set1_pd(0.3333320617675781);
2813 assert_eq_m128d(r, e);
2814 }
2815
2816 #[simd_test(enable = "avx512f,avx512vl")]
2817 unsafe fn test_mm_mask_rcp14_pd() {
2818 let a = _mm_set1_pd(3.);
2819 let r = _mm_mask_rcp14_pd(a, 0, a);
2820 assert_eq_m128d(r, a);
2821 let r = _mm_mask_rcp14_pd(a, 0b00000011, a);
2822 let e = _mm_set1_pd(0.3333320617675781);
2823 assert_eq_m128d(r, e);
2824 }
2825
2826 #[simd_test(enable = "avx512f,avx512vl")]
2827 unsafe fn test_mm_maskz_rcp14_pd() {
2828 let a = _mm_set1_pd(3.);
2829 let r = _mm_maskz_rcp14_pd(0, a);
2830 assert_eq_m128d(r, _mm_setzero_pd());
2831 let r = _mm_maskz_rcp14_pd(0b00000011, a);
2832 let e = _mm_set1_pd(0.3333320617675781);
2833 assert_eq_m128d(r, e);
2834 }
2835
2836 #[simd_test(enable = "avx512f")]
2837 unsafe fn test_mm512_rsqrt14_pd() {
2838 let a = _mm512_set1_pd(3.);
2839 let r = _mm512_rsqrt14_pd(a);
2840 let e = _mm512_set1_pd(0.5773391723632813);
2841 assert_eq_m512d(r, e);
2842 }
2843
2844 #[simd_test(enable = "avx512f")]
2845 unsafe fn test_mm512_mask_rsqrt14_pd() {
2846 let a = _mm512_set1_pd(3.);
2847 let r = _mm512_mask_rsqrt14_pd(a, 0, a);
2848 assert_eq_m512d(r, a);
2849 let r = _mm512_mask_rsqrt14_pd(a, 0b11110000, a);
2850 #[rustfmt::skip]
2851 let e = _mm512_setr_pd(
2852 3., 3., 3., 3.,
2853 0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2854 );
2855 assert_eq_m512d(r, e);
2856 }
2857
2858 #[simd_test(enable = "avx512f")]
2859 unsafe fn test_mm512_maskz_rsqrt14_pd() {
2860 let a = _mm512_set1_pd(3.);
2861 let r = _mm512_maskz_rsqrt14_pd(0, a);
2862 assert_eq_m512d(r, _mm512_setzero_pd());
2863 let r = _mm512_maskz_rsqrt14_pd(0b11110000, a);
2864 #[rustfmt::skip]
2865 let e = _mm512_setr_pd(
2866 0., 0., 0., 0.,
2867 0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2868 );
2869 assert_eq_m512d(r, e);
2870 }
2871
2872 #[simd_test(enable = "avx512f,avx512vl")]
2873 unsafe fn test_mm256_rsqrt14_pd() {
2874 let a = _mm256_set1_pd(3.);
2875 let r = _mm256_rsqrt14_pd(a);
2876 let e = _mm256_set1_pd(0.5773391723632813);
2877 assert_eq_m256d(r, e);
2878 }
2879
2880 #[simd_test(enable = "avx512f,avx512vl")]
2881 unsafe fn test_mm256_mask_rsqrt14_pd() {
2882 let a = _mm256_set1_pd(3.);
2883 let r = _mm256_mask_rsqrt14_pd(a, 0, a);
2884 assert_eq_m256d(r, a);
2885 let r = _mm256_mask_rsqrt14_pd(a, 0b00001111, a);
2886 let e = _mm256_set1_pd(0.5773391723632813);
2887 assert_eq_m256d(r, e);
2888 }
2889
2890 #[simd_test(enable = "avx512f,avx512vl")]
2891 unsafe fn test_mm256_maskz_rsqrt14_pd() {
2892 let a = _mm256_set1_pd(3.);
2893 let r = _mm256_maskz_rsqrt14_pd(0, a);
2894 assert_eq_m256d(r, _mm256_setzero_pd());
2895 let r = _mm256_maskz_rsqrt14_pd(0b00001111, a);
2896 let e = _mm256_set1_pd(0.5773391723632813);
2897 assert_eq_m256d(r, e);
2898 }
2899
2900 #[simd_test(enable = "avx512f,avx512vl")]
2901 unsafe fn test_mm_rsqrt14_pd() {
2902 let a = _mm_set1_pd(3.);
2903 let r = _mm_rsqrt14_pd(a);
2904 let e = _mm_set1_pd(0.5773391723632813);
2905 assert_eq_m128d(r, e);
2906 }
2907
2908 #[simd_test(enable = "avx512f,avx512vl")]
2909 unsafe fn test_mm_mask_rsqrt14_pd() {
2910 let a = _mm_set1_pd(3.);
2911 let r = _mm_mask_rsqrt14_pd(a, 0, a);
2912 assert_eq_m128d(r, a);
2913 let r = _mm_mask_rsqrt14_pd(a, 0b00000011, a);
2914 let e = _mm_set1_pd(0.5773391723632813);
2915 assert_eq_m128d(r, e);
2916 }
2917
2918 #[simd_test(enable = "avx512f,avx512vl")]
2919 unsafe fn test_mm_maskz_rsqrt14_pd() {
2920 let a = _mm_set1_pd(3.);
2921 let r = _mm_maskz_rsqrt14_pd(0, a);
2922 assert_eq_m128d(r, _mm_setzero_pd());
2923 let r = _mm_maskz_rsqrt14_pd(0b00000011, a);
2924 let e = _mm_set1_pd(0.5773391723632813);
2925 assert_eq_m128d(r, e);
2926 }
2927
2928 #[simd_test(enable = "avx512f")]
2929 unsafe fn test_mm512_getexp_pd() {
2930 let a = _mm512_set1_pd(3.);
2931 let r = _mm512_getexp_pd(a);
2932 let e = _mm512_set1_pd(1.);
2933 assert_eq_m512d(r, e);
2934 }
2935
2936 #[simd_test(enable = "avx512f")]
2937 unsafe fn test_mm512_mask_getexp_pd() {
2938 let a = _mm512_set1_pd(3.);
2939 let r = _mm512_mask_getexp_pd(a, 0, a);
2940 assert_eq_m512d(r, a);
2941 let r = _mm512_mask_getexp_pd(a, 0b11110000, a);
2942 let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
2943 assert_eq_m512d(r, e);
2944 }
2945
2946 #[simd_test(enable = "avx512f")]
2947 unsafe fn test_mm512_maskz_getexp_pd() {
2948 let a = _mm512_set1_pd(3.);
2949 let r = _mm512_maskz_getexp_pd(0, a);
2950 assert_eq_m512d(r, _mm512_setzero_pd());
2951 let r = _mm512_maskz_getexp_pd(0b11110000, a);
2952 let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
2953 assert_eq_m512d(r, e);
2954 }
2955
2956 #[simd_test(enable = "avx512f,avx512vl")]
2957 unsafe fn test_mm256_getexp_pd() {
2958 let a = _mm256_set1_pd(3.);
2959 let r = _mm256_getexp_pd(a);
2960 let e = _mm256_set1_pd(1.);
2961 assert_eq_m256d(r, e);
2962 }
2963
2964 #[simd_test(enable = "avx512f,avx512vl")]
2965 unsafe fn test_mm256_mask_getexp_pd() {
2966 let a = _mm256_set1_pd(3.);
2967 let r = _mm256_mask_getexp_pd(a, 0, a);
2968 assert_eq_m256d(r, a);
2969 let r = _mm256_mask_getexp_pd(a, 0b00001111, a);
2970 let e = _mm256_set1_pd(1.);
2971 assert_eq_m256d(r, e);
2972 }
2973
2974 #[simd_test(enable = "avx512f,avx512vl")]
2975 unsafe fn test_mm256_maskz_getexp_pd() {
2976 let a = _mm256_set1_pd(3.);
2977 let r = _mm256_maskz_getexp_pd(0, a);
2978 assert_eq_m256d(r, _mm256_setzero_pd());
2979 let r = _mm256_maskz_getexp_pd(0b00001111, a);
2980 let e = _mm256_set1_pd(1.);
2981 assert_eq_m256d(r, e);
2982 }
2983
2984 #[simd_test(enable = "avx512f,avx512vl")]
2985 unsafe fn test_mm_getexp_pd() {
2986 let a = _mm_set1_pd(3.);
2987 let r = _mm_getexp_pd(a);
2988 let e = _mm_set1_pd(1.);
2989 assert_eq_m128d(r, e);
2990 }
2991
2992 #[simd_test(enable = "avx512f,avx512vl")]
2993 unsafe fn test_mm_mask_getexp_pd() {
2994 let a = _mm_set1_pd(3.);
2995 let r = _mm_mask_getexp_pd(a, 0, a);
2996 assert_eq_m128d(r, a);
2997 let r = _mm_mask_getexp_pd(a, 0b00000011, a);
2998 let e = _mm_set1_pd(1.);
2999 assert_eq_m128d(r, e);
3000 }
3001
3002 #[simd_test(enable = "avx512f,avx512vl")]
3003 unsafe fn test_mm_maskz_getexp_pd() {
3004 let a = _mm_set1_pd(3.);
3005 let r = _mm_maskz_getexp_pd(0, a);
3006 assert_eq_m128d(r, _mm_setzero_pd());
3007 let r = _mm_maskz_getexp_pd(0b00000011, a);
3008 let e = _mm_set1_pd(1.);
3009 assert_eq_m128d(r, e);
3010 }
3011
3012 #[simd_test(enable = "avx512f")]
3013 unsafe fn test_mm512_roundscale_pd() {
3014 let a = _mm512_set1_pd(1.1);
3015 let r = _mm512_roundscale_pd::<0b00_00_00_00>(a);
3016 let e = _mm512_set1_pd(1.0);
3017 assert_eq_m512d(r, e);
3018 }
3019
3020 #[simd_test(enable = "avx512f")]
3021 unsafe fn test_mm512_mask_roundscale_pd() {
3022 let a = _mm512_set1_pd(1.1);
3023 let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3024 let e = _mm512_set1_pd(1.1);
3025 assert_eq_m512d(r, e);
3026 let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0b11111111, a);
3027 let e = _mm512_set1_pd(1.0);
3028 assert_eq_m512d(r, e);
3029 }
3030
3031 #[simd_test(enable = "avx512f")]
3032 unsafe fn test_mm512_maskz_roundscale_pd() {
3033 let a = _mm512_set1_pd(1.1);
3034 let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3035 assert_eq_m512d(r, _mm512_setzero_pd());
3036 let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0b11111111, a);
3037 let e = _mm512_set1_pd(1.0);
3038 assert_eq_m512d(r, e);
3039 }
3040
3041 #[simd_test(enable = "avx512f,avx512vl")]
3042 unsafe fn test_mm256_roundscale_pd() {
3043 let a = _mm256_set1_pd(1.1);
3044 let r = _mm256_roundscale_pd::<0b00_00_00_00>(a);
3045 let e = _mm256_set1_pd(1.0);
3046 assert_eq_m256d(r, e);
3047 }
3048
3049 #[simd_test(enable = "avx512f,avx512vl")]
3050 unsafe fn test_mm256_mask_roundscale_pd() {
3051 let a = _mm256_set1_pd(1.1);
3052 let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3053 assert_eq_m256d(r, a);
3054 let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00001111, a);
3055 let e = _mm256_set1_pd(1.0);
3056 assert_eq_m256d(r, e);
3057 }
3058
3059 #[simd_test(enable = "avx512f,avx512vl")]
3060 unsafe fn test_mm256_maskz_roundscale_pd() {
3061 let a = _mm256_set1_pd(1.1);
3062 let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3063 assert_eq_m256d(r, _mm256_setzero_pd());
3064 let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0b00001111, a);
3065 let e = _mm256_set1_pd(1.0);
3066 assert_eq_m256d(r, e);
3067 }
3068
3069 #[simd_test(enable = "avx512f,avx512vl")]
3070 unsafe fn test_mm_roundscale_pd() {
3071 let a = _mm_set1_pd(1.1);
3072 let r = _mm_roundscale_pd::<0b00_00_00_00>(a);
3073 let e = _mm_set1_pd(1.0);
3074 assert_eq_m128d(r, e);
3075 }
3076
3077 #[simd_test(enable = "avx512f,avx512vl")]
3078 unsafe fn test_mm_mask_roundscale_pd() {
3079 let a = _mm_set1_pd(1.1);
3080 let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3081 let e = _mm_set1_pd(1.1);
3082 assert_eq_m128d(r, e);
3083 let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00000011, a);
3084 let e = _mm_set1_pd(1.0);
3085 assert_eq_m128d(r, e);
3086 }
3087
3088 #[simd_test(enable = "avx512f,avx512vl")]
3089 unsafe fn test_mm_maskz_roundscale_pd() {
3090 let a = _mm_set1_pd(1.1);
3091 let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3092 assert_eq_m128d(r, _mm_setzero_pd());
3093 let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0b00000011, a);
3094 let e = _mm_set1_pd(1.0);
3095 assert_eq_m128d(r, e);
3096 }
3097
3098 #[simd_test(enable = "avx512f")]
3099 unsafe fn test_mm512_scalef_pd() {
3100 let a = _mm512_set1_pd(1.);
3101 let b = _mm512_set1_pd(3.);
3102 let r = _mm512_scalef_pd(a, b);
3103 let e = _mm512_set1_pd(8.);
3104 assert_eq_m512d(r, e);
3105 }
3106
3107 #[simd_test(enable = "avx512f")]
3108 unsafe fn test_mm512_mask_scalef_pd() {
3109 let a = _mm512_set1_pd(1.);
3110 let b = _mm512_set1_pd(3.);
3111 let r = _mm512_mask_scalef_pd(a, 0, a, b);
3112 assert_eq_m512d(r, a);
3113 let r = _mm512_mask_scalef_pd(a, 0b11110000, a, b);
3114 let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
3115 assert_eq_m512d(r, e);
3116 }
3117
3118 #[simd_test(enable = "avx512f")]
3119 unsafe fn test_mm512_maskz_scalef_pd() {
3120 let a = _mm512_set1_pd(1.);
3121 let b = _mm512_set1_pd(3.);
3122 let r = _mm512_maskz_scalef_pd(0, a, b);
3123 assert_eq_m512d(r, _mm512_setzero_pd());
3124 let r = _mm512_maskz_scalef_pd(0b11110000, a, b);
3125 let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
3126 assert_eq_m512d(r, e);
3127 }
3128
3129 #[simd_test(enable = "avx512f,avx512vl")]
3130 unsafe fn test_mm256_scalef_pd() {
3131 let a = _mm256_set1_pd(1.);
3132 let b = _mm256_set1_pd(3.);
3133 let r = _mm256_scalef_pd(a, b);
3134 let e = _mm256_set1_pd(8.);
3135 assert_eq_m256d(r, e);
3136 }
3137
3138 #[simd_test(enable = "avx512f,avx512vl")]
3139 unsafe fn test_mm256_mask_scalef_pd() {
3140 let a = _mm256_set1_pd(1.);
3141 let b = _mm256_set1_pd(3.);
3142 let r = _mm256_mask_scalef_pd(a, 0, a, b);
3143 assert_eq_m256d(r, a);
3144 let r = _mm256_mask_scalef_pd(a, 0b00001111, a, b);
3145 let e = _mm256_set1_pd(8.);
3146 assert_eq_m256d(r, e);
3147 }
3148
3149 #[simd_test(enable = "avx512f,avx512vl")]
3150 unsafe fn test_mm256_maskz_scalef_pd() {
3151 let a = _mm256_set1_pd(1.);
3152 let b = _mm256_set1_pd(3.);
3153 let r = _mm256_maskz_scalef_pd(0, a, b);
3154 assert_eq_m256d(r, _mm256_setzero_pd());
3155 let r = _mm256_maskz_scalef_pd(0b00001111, a, b);
3156 let e = _mm256_set1_pd(8.);
3157 assert_eq_m256d(r, e);
3158 }
3159
3160 #[simd_test(enable = "avx512f,avx512vl")]
3161 unsafe fn test_mm_scalef_pd() {
3162 let a = _mm_set1_pd(1.);
3163 let b = _mm_set1_pd(3.);
3164 let r = _mm_scalef_pd(a, b);
3165 let e = _mm_set1_pd(8.);
3166 assert_eq_m128d(r, e);
3167 }
3168
3169 #[simd_test(enable = "avx512f,avx512vl")]
3170 unsafe fn test_mm_mask_scalef_pd() {
3171 let a = _mm_set1_pd(1.);
3172 let b = _mm_set1_pd(3.);
3173 let r = _mm_mask_scalef_pd(a, 0, a, b);
3174 assert_eq_m128d(r, a);
3175 let r = _mm_mask_scalef_pd(a, 0b00000011, a, b);
3176 let e = _mm_set1_pd(8.);
3177 assert_eq_m128d(r, e);
3178 }
3179
3180 #[simd_test(enable = "avx512f,avx512vl")]
3181 unsafe fn test_mm_maskz_scalef_pd() {
3182 let a = _mm_set1_pd(1.);
3183 let b = _mm_set1_pd(3.);
3184 let r = _mm_maskz_scalef_pd(0, a, b);
3185 assert_eq_m128d(r, _mm_setzero_pd());
3186 let r = _mm_maskz_scalef_pd(0b00000011, a, b);
3187 let e = _mm_set1_pd(8.);
3188 assert_eq_m128d(r, e);
3189 }
3190
3191 #[simd_test(enable = "avx512f")]
3192 unsafe fn test_mm512_fixupimm_pd() {
3193 let a = _mm512_set1_pd(f64::NAN);
3194 let b = _mm512_set1_pd(f64::MAX);
3195 let c = _mm512_set1_epi64(i32::MAX as i64);
3196 let r = _mm512_fixupimm_pd::<5>(a, b, c);
3197 let e = _mm512_set1_pd(0.0);
3198 assert_eq_m512d(r, e);
3199 }
3200
3201 #[simd_test(enable = "avx512f")]
3202 unsafe fn test_mm512_mask_fixupimm_pd() {
3203 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3204 let b = _mm512_set1_pd(f64::MAX);
3205 let c = _mm512_set1_epi64(i32::MAX as i64);
3206 let r = _mm512_mask_fixupimm_pd::<5>(a, 0b11110000, b, c);
3207 let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
3208 assert_eq_m512d(r, e);
3209 }
3210
3211 #[simd_test(enable = "avx512f")]
3212 unsafe fn test_mm512_maskz_fixupimm_pd() {
3213 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3214 let b = _mm512_set1_pd(f64::MAX);
3215 let c = _mm512_set1_epi64(i32::MAX as i64);
3216 let r = _mm512_maskz_fixupimm_pd::<5>(0b11110000, a, b, c);
3217 let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
3218 assert_eq_m512d(r, e);
3219 }
3220
3221 #[simd_test(enable = "avx512f,avx512vl")]
3222 unsafe fn test_mm256_fixupimm_pd() {
3223 let a = _mm256_set1_pd(f64::NAN);
3224 let b = _mm256_set1_pd(f64::MAX);
3225 let c = _mm256_set1_epi64x(i32::MAX as i64);
3226 let r = _mm256_fixupimm_pd::<5>(a, b, c);
3227 let e = _mm256_set1_pd(0.0);
3228 assert_eq_m256d(r, e);
3229 }
3230
3231 #[simd_test(enable = "avx512f,avx512vl")]
3232 unsafe fn test_mm256_mask_fixupimm_pd() {
3233 let a = _mm256_set1_pd(f64::NAN);
3234 let b = _mm256_set1_pd(f64::MAX);
3235 let c = _mm256_set1_epi64x(i32::MAX as i64);
3236 let r = _mm256_mask_fixupimm_pd::<5>(a, 0b00001111, b, c);
3237 let e = _mm256_set1_pd(0.0);
3238 assert_eq_m256d(r, e);
3239 }
3240
3241 #[simd_test(enable = "avx512f,avx512vl")]
3242 unsafe fn test_mm256_maskz_fixupimm_pd() {
3243 let a = _mm256_set1_pd(f64::NAN);
3244 let b = _mm256_set1_pd(f64::MAX);
3245 let c = _mm256_set1_epi64x(i32::MAX as i64);
3246 let r = _mm256_maskz_fixupimm_pd::<5>(0b00001111, a, b, c);
3247 let e = _mm256_set1_pd(0.0);
3248 assert_eq_m256d(r, e);
3249 }
3250
3251 #[simd_test(enable = "avx512f,avx512vl")]
3252 unsafe fn test_mm_fixupimm_pd() {
3253 let a = _mm_set1_pd(f64::NAN);
3254 let b = _mm_set1_pd(f64::MAX);
3255 let c = _mm_set1_epi64x(i32::MAX as i64);
3256 let r = _mm_fixupimm_pd::<5>(a, b, c);
3257 let e = _mm_set1_pd(0.0);
3258 assert_eq_m128d(r, e);
3259 }
3260
3261 #[simd_test(enable = "avx512f,avx512vl")]
3262 unsafe fn test_mm_mask_fixupimm_pd() {
3263 let a = _mm_set1_pd(f64::NAN);
3264 let b = _mm_set1_pd(f64::MAX);
3265 let c = _mm_set1_epi64x(i32::MAX as i64);
3266 let r = _mm_mask_fixupimm_pd::<5>(a, 0b00000011, b, c);
3267 let e = _mm_set1_pd(0.0);
3268 assert_eq_m128d(r, e);
3269 }
3270
3271 #[simd_test(enable = "avx512f,avx512vl")]
3272 unsafe fn test_mm_maskz_fixupimm_pd() {
3273 let a = _mm_set1_pd(f64::NAN);
3274 let b = _mm_set1_pd(f64::MAX);
3275 let c = _mm_set1_epi64x(i32::MAX as i64);
3276 let r = _mm_maskz_fixupimm_pd::<5>(0b00000011, a, b, c);
3277 let e = _mm_set1_pd(0.0);
3278 assert_eq_m128d(r, e);
3279 }
3280
3281 #[simd_test(enable = "avx512f")]
3282 unsafe fn test_mm512_ternarylogic_epi64() {
3283 let a = _mm512_set1_epi64(1 << 2);
3284 let b = _mm512_set1_epi64(1 << 1);
3285 let c = _mm512_set1_epi64(1 << 0);
3286 let r = _mm512_ternarylogic_epi64::<8>(a, b, c);
3287 let e = _mm512_set1_epi64(0);
3288 assert_eq_m512i(r, e);
3289 }
3290
3291 #[simd_test(enable = "avx512f")]
3292 unsafe fn test_mm512_mask_ternarylogic_epi64() {
3293 let src = _mm512_set1_epi64(1 << 2);
3294 let a = _mm512_set1_epi64(1 << 1);
3295 let b = _mm512_set1_epi64(1 << 0);
3296 let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3297 assert_eq_m512i(r, src);
3298 let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0b11111111, a, b);
3299 let e = _mm512_set1_epi64(0);
3300 assert_eq_m512i(r, e);
3301 }
3302
3303 #[simd_test(enable = "avx512f")]
3304 unsafe fn test_mm512_maskz_ternarylogic_epi64() {
3305 let a = _mm512_set1_epi64(1 << 2);
3306 let b = _mm512_set1_epi64(1 << 1);
3307 let c = _mm512_set1_epi64(1 << 0);
3308 let r = _mm512_maskz_ternarylogic_epi64::<8>(0, a, b, c);
3309 assert_eq_m512i(r, _mm512_setzero_si512());
3310 let r = _mm512_maskz_ternarylogic_epi64::<8>(0b11111111, a, b, c);
3311 let e = _mm512_set1_epi64(0);
3312 assert_eq_m512i(r, e);
3313 }
3314
3315 #[simd_test(enable = "avx512f,avx512vl")]
3316 unsafe fn test_mm256_ternarylogic_epi64() {
3317 let a = _mm256_set1_epi64x(1 << 2);
3318 let b = _mm256_set1_epi64x(1 << 1);
3319 let c = _mm256_set1_epi64x(1 << 0);
3320 let r = _mm256_ternarylogic_epi64::<8>(a, b, c);
3321 let e = _mm256_set1_epi64x(0);
3322 assert_eq_m256i(r, e);
3323 }
3324
3325 #[simd_test(enable = "avx512f,avx512vl")]
3326 unsafe fn test_mm256_mask_ternarylogic_epi64() {
3327 let src = _mm256_set1_epi64x(1 << 2);
3328 let a = _mm256_set1_epi64x(1 << 1);
3329 let b = _mm256_set1_epi64x(1 << 0);
3330 let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3331 assert_eq_m256i(r, src);
3332 let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0b00001111, a, b);
3333 let e = _mm256_set1_epi64x(0);
3334 assert_eq_m256i(r, e);
3335 }
3336
3337 #[simd_test(enable = "avx512f,avx512vl")]
3338 unsafe fn test_mm256_maskz_ternarylogic_epi64() {
3339 let a = _mm256_set1_epi64x(1 << 2);
3340 let b = _mm256_set1_epi64x(1 << 1);
3341 let c = _mm256_set1_epi64x(1 << 0);
3342 let r = _mm256_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3343 assert_eq_m256i(r, _mm256_setzero_si256());
3344 let r = _mm256_maskz_ternarylogic_epi64::<8>(0b00001111, a, b, c);
3345 let e = _mm256_set1_epi64x(0);
3346 assert_eq_m256i(r, e);
3347 }
3348
3349 #[simd_test(enable = "avx512f,avx512vl")]
3350 unsafe fn test_mm_ternarylogic_epi64() {
3351 let a = _mm_set1_epi64x(1 << 2);
3352 let b = _mm_set1_epi64x(1 << 1);
3353 let c = _mm_set1_epi64x(1 << 0);
3354 let r = _mm_ternarylogic_epi64::<8>(a, b, c);
3355 let e = _mm_set1_epi64x(0);
3356 assert_eq_m128i(r, e);
3357 }
3358
3359 #[simd_test(enable = "avx512f,avx512vl")]
3360 unsafe fn test_mm_mask_ternarylogic_epi64() {
3361 let src = _mm_set1_epi64x(1 << 2);
3362 let a = _mm_set1_epi64x(1 << 1);
3363 let b = _mm_set1_epi64x(1 << 0);
3364 let r = _mm_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3365 assert_eq_m128i(r, src);
3366 let r = _mm_mask_ternarylogic_epi64::<8>(src, 0b00000011, a, b);
3367 let e = _mm_set1_epi64x(0);
3368 assert_eq_m128i(r, e);
3369 }
3370
3371 #[simd_test(enable = "avx512f,avx512vl")]
3372 unsafe fn test_mm_maskz_ternarylogic_epi64() {
3373 let a = _mm_set1_epi64x(1 << 2);
3374 let b = _mm_set1_epi64x(1 << 1);
3375 let c = _mm_set1_epi64x(1 << 0);
3376 let r = _mm_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3377 assert_eq_m128i(r, _mm_setzero_si128());
3378 let r = _mm_maskz_ternarylogic_epi64::<8>(0b00000011, a, b, c);
3379 let e = _mm_set1_epi64x(0);
3380 assert_eq_m128i(r, e);
3381 }
3382
3383 #[simd_test(enable = "avx512f")]
3384 unsafe fn test_mm512_getmant_pd() {
3385 let a = _mm512_set1_pd(10.);
3386 let r = _mm512_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3387 let e = _mm512_set1_pd(1.25);
3388 assert_eq_m512d(r, e);
3389 }
3390
3391 #[simd_test(enable = "avx512f")]
3392 unsafe fn test_mm512_mask_getmant_pd() {
3393 let a = _mm512_set1_pd(10.);
3394 let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3395 assert_eq_m512d(r, a);
3396 let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11110000, a);
3397 let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
3398 assert_eq_m512d(r, e);
3399 }
3400
3401 #[simd_test(enable = "avx512f")]
3402 unsafe fn test_mm512_maskz_getmant_pd() {
3403 let a = _mm512_set1_pd(10.);
3404 let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3405 assert_eq_m512d(r, _mm512_setzero_pd());
3406 let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11110000, a);
3407 let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
3408 assert_eq_m512d(r, e);
3409 }
3410
3411 #[simd_test(enable = "avx512f,avx512vl")]
3412 unsafe fn test_mm256_getmant_pd() {
3413 let a = _mm256_set1_pd(10.);
3414 let r = _mm256_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3415 let e = _mm256_set1_pd(1.25);
3416 assert_eq_m256d(r, e);
3417 }
3418
3419 #[simd_test(enable = "avx512f,avx512vl")]
3420 unsafe fn test_mm256_mask_getmant_pd() {
3421 let a = _mm256_set1_pd(10.);
3422 let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3423 assert_eq_m256d(r, a);
3424 let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00001111, a);
3425 let e = _mm256_set1_pd(1.25);
3426 assert_eq_m256d(r, e);
3427 }
3428
3429 #[simd_test(enable = "avx512f,avx512vl")]
3430 unsafe fn test_mm256_maskz_getmant_pd() {
3431 let a = _mm256_set1_pd(10.);
3432 let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3433 assert_eq_m256d(r, _mm256_setzero_pd());
3434 let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00001111, a);
3435 let e = _mm256_set1_pd(1.25);
3436 assert_eq_m256d(r, e);
3437 }
3438
3439 #[simd_test(enable = "avx512f,avx512vl")]
3440 unsafe fn test_mm_getmant_pd() {
3441 let a = _mm_set1_pd(10.);
3442 let r = _mm_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3443 let e = _mm_set1_pd(1.25);
3444 assert_eq_m128d(r, e);
3445 }
3446
3447 #[simd_test(enable = "avx512f,avx512vl")]
3448 unsafe fn test_mm_mask_getmant_pd() {
3449 let a = _mm_set1_pd(10.);
3450 let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3451 assert_eq_m128d(r, a);
3452 let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00000011, a);
3453 let e = _mm_set1_pd(1.25);
3454 assert_eq_m128d(r, e);
3455 }
3456
3457 #[simd_test(enable = "avx512f,avx512vl")]
3458 unsafe fn test_mm_maskz_getmant_pd() {
3459 let a = _mm_set1_pd(10.);
3460 let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3461 assert_eq_m128d(r, _mm_setzero_pd());
3462 let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00000011, a);
3463 let e = _mm_set1_pd(1.25);
3464 assert_eq_m128d(r, e);
3465 }
3466
3467 #[simd_test(enable = "avx512f")]
3468 unsafe fn test_mm512_cvtps_pd() {
3469 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3470 let r = _mm512_cvtps_pd(a);
3471 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3472 assert_eq_m512d(r, e);
3473 }
3474
3475 #[simd_test(enable = "avx512f")]
3476 unsafe fn test_mm512_mask_cvtps_pd() {
3477 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3478 let src = _mm512_set1_pd(0.);
3479 let r = _mm512_mask_cvtps_pd(src, 0, a);
3480 assert_eq_m512d(r, src);
3481 let r = _mm512_mask_cvtps_pd(src, 0b00001111, a);
3482 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3483 assert_eq_m512d(r, e);
3484 }
3485
3486 #[simd_test(enable = "avx512f")]
3487 unsafe fn test_mm512_maskz_cvtps_pd() {
3488 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3489 let r = _mm512_maskz_cvtps_pd(0, a);
3490 assert_eq_m512d(r, _mm512_setzero_pd());
3491 let r = _mm512_maskz_cvtps_pd(0b00001111, a);
3492 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3493 assert_eq_m512d(r, e);
3494 }
3495
3496 #[simd_test(enable = "avx512f")]
3497 unsafe fn test_mm512_cvtpslo_pd() {
3498 let v2 = _mm512_setr_ps(
3499 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3500 );
3501 let r = _mm512_cvtpslo_pd(v2);
3502 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3503 assert_eq_m512d(r, e);
3504 }
3505
3506 #[simd_test(enable = "avx512f")]
3507 unsafe fn test_mm512_mask_cvtpslo_pd() {
3508 let v2 = _mm512_setr_ps(
3509 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3510 );
3511 let src = _mm512_set1_pd(0.);
3512 let r = _mm512_mask_cvtpslo_pd(src, 0, v2);
3513 assert_eq_m512d(r, src);
3514 let r = _mm512_mask_cvtpslo_pd(src, 0b00001111, v2);
3515 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3516 assert_eq_m512d(r, e);
3517 }
3518
3519 #[simd_test(enable = "avx512f")]
3520 unsafe fn test_mm512_cvtpd_ps() {
3521 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3522 let r = _mm512_cvtpd_ps(a);
3523 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3524 assert_eq_m256(r, e);
3525 }
3526
3527 #[simd_test(enable = "avx512f")]
3528 unsafe fn test_mm512_mask_cvtpd_ps() {
3529 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3530 let src = _mm256_set1_ps(0.);
3531 let r = _mm512_mask_cvtpd_ps(src, 0, a);
3532 assert_eq_m256(r, src);
3533 let r = _mm512_mask_cvtpd_ps(src, 0b00001111, a);
3534 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3535 assert_eq_m256(r, e);
3536 }
3537
3538 #[simd_test(enable = "avx512f")]
3539 unsafe fn test_mm512_maskz_cvtpd_ps() {
3540 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3541 let r = _mm512_maskz_cvtpd_ps(0, a);
3542 assert_eq_m256(r, _mm256_setzero_ps());
3543 let r = _mm512_maskz_cvtpd_ps(0b00001111, a);
3544 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3545 assert_eq_m256(r, e);
3546 }
3547
3548 #[simd_test(enable = "avx512f,avx512vl")]
3549 unsafe fn test_mm256_mask_cvtpd_ps() {
3550 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3551 let src = _mm_set1_ps(0.);
3552 let r = _mm256_mask_cvtpd_ps(src, 0, a);
3553 assert_eq_m128(r, src);
3554 let r = _mm256_mask_cvtpd_ps(src, 0b00001111, a);
3555 let e = _mm_set_ps(4., -5.5, 6., -7.5);
3556 assert_eq_m128(r, e);
3557 }
3558
3559 #[simd_test(enable = "avx512f,avx512vl")]
3560 unsafe fn test_mm256_maskz_cvtpd_ps() {
3561 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3562 let r = _mm256_maskz_cvtpd_ps(0, a);
3563 assert_eq_m128(r, _mm_setzero_ps());
3564 let r = _mm256_maskz_cvtpd_ps(0b00001111, a);
3565 let e = _mm_set_ps(4., -5.5, 6., -7.5);
3566 assert_eq_m128(r, e);
3567 }
3568
3569 #[simd_test(enable = "avx512f,avx512vl")]
3570 unsafe fn test_mm_mask_cvtpd_ps() {
3571 let a = _mm_set_pd(6., -7.5);
3572 let src = _mm_set1_ps(0.);
3573 let r = _mm_mask_cvtpd_ps(src, 0, a);
3574 assert_eq_m128(r, src);
3575 let r = _mm_mask_cvtpd_ps(src, 0b00000011, a);
3576 let e = _mm_set_ps(0., 0., 6., -7.5);
3577 assert_eq_m128(r, e);
3578 }
3579
3580 #[simd_test(enable = "avx512f,avx512vl")]
3581 unsafe fn test_mm_maskz_cvtpd_ps() {
3582 let a = _mm_set_pd(6., -7.5);
3583 let r = _mm_maskz_cvtpd_ps(0, a);
3584 assert_eq_m128(r, _mm_setzero_ps());
3585 let r = _mm_maskz_cvtpd_ps(0b00000011, a);
3586 let e = _mm_set_ps(0., 0., 6., -7.5);
3587 assert_eq_m128(r, e);
3588 }
3589
3590 #[simd_test(enable = "avx512f")]
3591 unsafe fn test_mm512_cvtpd_epi32() {
3592 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3593 let r = _mm512_cvtpd_epi32(a);
3594 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3595 assert_eq_m256i(r, e);
3596 }
3597
3598 #[simd_test(enable = "avx512f")]
3599 unsafe fn test_mm512_mask_cvtpd_epi32() {
3600 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3601 let src = _mm256_set1_epi32(0);
3602 let r = _mm512_mask_cvtpd_epi32(src, 0, a);
3603 assert_eq_m256i(r, src);
3604 let r = _mm512_mask_cvtpd_epi32(src, 0b11111111, a);
3605 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3606 assert_eq_m256i(r, e);
3607 }
3608
3609 #[simd_test(enable = "avx512f")]
3610 unsafe fn test_mm512_maskz_cvtpd_epi32() {
3611 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3612 let r = _mm512_maskz_cvtpd_epi32(0, a);
3613 assert_eq_m256i(r, _mm256_setzero_si256());
3614 let r = _mm512_maskz_cvtpd_epi32(0b11111111, a);
3615 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3616 assert_eq_m256i(r, e);
3617 }
3618
3619 #[simd_test(enable = "avx512f,avx512vl")]
3620 unsafe fn test_mm256_mask_cvtpd_epi32() {
3621 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3622 let src = _mm_set1_epi32(0);
3623 let r = _mm256_mask_cvtpd_epi32(src, 0, a);
3624 assert_eq_m128i(r, src);
3625 let r = _mm256_mask_cvtpd_epi32(src, 0b00001111, a);
3626 let e = _mm_set_epi32(4, -6, 6, -8);
3627 assert_eq_m128i(r, e);
3628 }
3629
3630 #[simd_test(enable = "avx512f,avx512vl")]
3631 unsafe fn test_mm256_maskz_cvtpd_epi32() {
3632 let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3633 let r = _mm256_maskz_cvtpd_epi32(0, a);
3634 assert_eq_m128i(r, _mm_setzero_si128());
3635 let r = _mm256_maskz_cvtpd_epi32(0b00001111, a);
3636 let e = _mm_set_epi32(4, -6, 6, -8);
3637 assert_eq_m128i(r, e);
3638 }
3639
3640 #[simd_test(enable = "avx512f,avx512vl")]
3641 unsafe fn test_mm_mask_cvtpd_epi32() {
3642 let a = _mm_set_pd(6., -7.5);
3643 let src = _mm_set1_epi32(0);
3644 let r = _mm_mask_cvtpd_epi32(src, 0, a);
3645 assert_eq_m128i(r, src);
3646 let r = _mm_mask_cvtpd_epi32(src, 0b00000011, a);
3647 let e = _mm_set_epi32(0, 0, 6, -8);
3648 assert_eq_m128i(r, e);
3649 }
3650
3651 #[simd_test(enable = "avx512f,avx512vl")]
3652 unsafe fn test_mm_maskz_cvtpd_epi32() {
3653 let a = _mm_set_pd(6., -7.5);
3654 let r = _mm_maskz_cvtpd_epi32(0, a);
3655 assert_eq_m128i(r, _mm_setzero_si128());
3656 let r = _mm_maskz_cvtpd_epi32(0b00000011, a);
3657 let e = _mm_set_epi32(0, 0, 6, -8);
3658 assert_eq_m128i(r, e);
3659 }
3660
3661 #[simd_test(enable = "avx512f")]
3662 unsafe fn test_mm512_cvtpd_epu32() {
3663 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3664 let r = _mm512_cvtpd_epu32(a);
3665 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3666 assert_eq_m256i(r, e);
3667 }
3668
3669 #[simd_test(enable = "avx512f")]
3670 unsafe fn test_mm512_mask_cvtpd_epu32() {
3671 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3672 let src = _mm256_set1_epi32(0);
3673 let r = _mm512_mask_cvtpd_epu32(src, 0, a);
3674 assert_eq_m256i(r, src);
3675 let r = _mm512_mask_cvtpd_epu32(src, 0b11111111, a);
3676 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3677 assert_eq_m256i(r, e);
3678 }
3679
3680 #[simd_test(enable = "avx512f")]
3681 unsafe fn test_mm512_maskz_cvtpd_epu32() {
3682 let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3683 let r = _mm512_maskz_cvtpd_epu32(0, a);
3684 assert_eq_m256i(r, _mm256_setzero_si256());
3685 let r = _mm512_maskz_cvtpd_epu32(0b11111111, a);
3686 let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3687 assert_eq_m256i(r, e);
3688 }
3689
3690 #[simd_test(enable = "avx512f,avx512vl")]
3691 unsafe fn test_mm256_cvtpd_epu32() {
3692 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3693 let r = _mm256_cvtpd_epu32(a);
3694 let e = _mm_set_epi32(4, 6, 6, 8);
3695 assert_eq_m128i(r, e);
3696 }
3697
3698 #[simd_test(enable = "avx512f,avx512vl")]
3699 unsafe fn test_mm256_mask_cvtpd_epu32() {
3700 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3701 let src = _mm_set1_epi32(0);
3702 let r = _mm256_mask_cvtpd_epu32(src, 0, a);
3703 assert_eq_m128i(r, src);
3704 let r = _mm256_mask_cvtpd_epu32(src, 0b00001111, a);
3705 let e = _mm_set_epi32(4, 6, 6, 8);
3706 assert_eq_m128i(r, e);
3707 }
3708
3709 #[simd_test(enable = "avx512f,avx512vl")]
3710 unsafe fn test_mm256_maskz_cvtpd_epu32() {
3711 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3712 let r = _mm256_maskz_cvtpd_epu32(0, a);
3713 assert_eq_m128i(r, _mm_setzero_si128());
3714 let r = _mm256_maskz_cvtpd_epu32(0b00001111, a);
3715 let e = _mm_set_epi32(4, 6, 6, 8);
3716 assert_eq_m128i(r, e);
3717 }
3718
3719 #[simd_test(enable = "avx512f,avx512vl")]
3720 unsafe fn test_mm_cvtpd_epu32() {
3721 let a = _mm_set_pd(6., 7.5);
3722 let r = _mm_cvtpd_epu32(a);
3723 let e = _mm_set_epi32(0, 0, 6, 8);
3724 assert_eq_m128i(r, e);
3725 }
3726
3727 #[simd_test(enable = "avx512f,avx512vl")]
3728 unsafe fn test_mm_mask_cvtpd_epu32() {
3729 let a = _mm_set_pd(6., 7.5);
3730 let src = _mm_set1_epi32(0);
3731 let r = _mm_mask_cvtpd_epu32(src, 0, a);
3732 assert_eq_m128i(r, src);
3733 let r = _mm_mask_cvtpd_epu32(src, 0b00000011, a);
3734 let e = _mm_set_epi32(0, 0, 6, 8);
3735 assert_eq_m128i(r, e);
3736 }
3737
3738 #[simd_test(enable = "avx512f,avx512vl")]
3739 unsafe fn test_mm_maskz_cvtpd_epu32() {
3740 let a = _mm_set_pd(6., 7.5);
3741 let r = _mm_maskz_cvtpd_epu32(0, a);
3742 assert_eq_m128i(r, _mm_setzero_si128());
3743 let r = _mm_maskz_cvtpd_epu32(0b00000011, a);
3744 let e = _mm_set_epi32(0, 0, 6, 8);
3745 assert_eq_m128i(r, e);
3746 }
3747
3748 #[simd_test(enable = "avx512f")]
3749 unsafe fn test_mm512_cvtpd_pslo() {
3750 let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3751 let r = _mm512_cvtpd_pslo(v2);
3752 let e = _mm512_setr_ps(
3753 0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 0., 0., 0., 0., 0., 0., 0., 0.,
3754 );
3755 assert_eq_m512(r, e);
3756 }
3757
3758 #[simd_test(enable = "avx512f")]
3759 unsafe fn test_mm512_mask_cvtpd_pslo() {
3760 let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3761 let src = _mm512_set1_ps(0.);
3762 let r = _mm512_mask_cvtpd_pslo(src, 0, v2);
3763 assert_eq_m512(r, src);
3764 let r = _mm512_mask_cvtpd_pslo(src, 0b00001111, v2);
3765 let e = _mm512_setr_ps(
3766 0., -1.5, 2., -3.5, 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,
3767 );
3768 assert_eq_m512(r, e);
3769 }
3770
3771 #[simd_test(enable = "avx512f")]
3772 const unsafe fn test_mm512_cvtepi8_epi64() {
3773 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3774 let r = _mm512_cvtepi8_epi64(a);
3775 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3776 assert_eq_m512i(r, e);
3777 }
3778
3779 #[simd_test(enable = "avx512f")]
3780 const unsafe fn test_mm512_mask_cvtepi8_epi64() {
3781 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3782 let src = _mm512_set1_epi64(-1);
3783 let r = _mm512_mask_cvtepi8_epi64(src, 0, a);
3784 assert_eq_m512i(r, src);
3785 let r = _mm512_mask_cvtepi8_epi64(src, 0b00001111, a);
3786 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3787 assert_eq_m512i(r, e);
3788 }
3789
3790 #[simd_test(enable = "avx512f")]
3791 const unsafe fn test_mm512_maskz_cvtepi8_epi64() {
3792 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3793 let r = _mm512_maskz_cvtepi8_epi64(0, a);
3794 assert_eq_m512i(r, _mm512_setzero_si512());
3795 let r = _mm512_maskz_cvtepi8_epi64(0b00001111, a);
3796 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3797 assert_eq_m512i(r, e);
3798 }
3799
3800 #[simd_test(enable = "avx512f,avx512vl")]
3801 const unsafe fn test_mm256_mask_cvtepi8_epi64() {
3802 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3803 let src = _mm256_set1_epi64x(-1);
3804 let r = _mm256_mask_cvtepi8_epi64(src, 0, a);
3805 assert_eq_m256i(r, src);
3806 let r = _mm256_mask_cvtepi8_epi64(src, 0b00001111, a);
3807 let e = _mm256_set_epi64x(12, 13, 14, 15);
3808 assert_eq_m256i(r, e);
3809 }
3810
3811 #[simd_test(enable = "avx512f,avx512vl")]
3812 const unsafe fn test_mm256_maskz_cvtepi8_epi64() {
3813 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3814 let r = _mm256_maskz_cvtepi8_epi64(0, a);
3815 assert_eq_m256i(r, _mm256_setzero_si256());
3816 let r = _mm256_maskz_cvtepi8_epi64(0b00001111, a);
3817 let e = _mm256_set_epi64x(12, 13, 14, 15);
3818 assert_eq_m256i(r, e);
3819 }
3820
3821 #[simd_test(enable = "avx512f,avx512vl")]
3822 const unsafe fn test_mm_mask_cvtepi8_epi64() {
3823 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3824 let src = _mm_set1_epi64x(-1);
3825 let r = _mm_mask_cvtepi8_epi64(src, 0, a);
3826 assert_eq_m128i(r, src);
3827 let r = _mm_mask_cvtepi8_epi64(src, 0b00000011, a);
3828 let e = _mm_set_epi64x(14, 15);
3829 assert_eq_m128i(r, e);
3830 }
3831
3832 #[simd_test(enable = "avx512f,avx512vl")]
3833 const unsafe fn test_mm_maskz_cvtepi8_epi64() {
3834 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3835 let r = _mm_maskz_cvtepi8_epi64(0, a);
3836 assert_eq_m128i(r, _mm_setzero_si128());
3837 let r = _mm_maskz_cvtepi8_epi64(0b00000011, a);
3838 let e = _mm_set_epi64x(14, 15);
3839 assert_eq_m128i(r, e);
3840 }
3841
3842 #[simd_test(enable = "avx512f")]
3843 const unsafe fn test_mm512_cvtepu8_epi64() {
3844 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3845 let r = _mm512_cvtepu8_epi64(a);
3846 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3847 assert_eq_m512i(r, e);
3848 }
3849
3850 #[simd_test(enable = "avx512f")]
3851 const unsafe fn test_mm512_mask_cvtepu8_epi64() {
3852 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3853 let src = _mm512_set1_epi64(-1);
3854 let r = _mm512_mask_cvtepu8_epi64(src, 0, a);
3855 assert_eq_m512i(r, src);
3856 let r = _mm512_mask_cvtepu8_epi64(src, 0b00001111, a);
3857 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3858 assert_eq_m512i(r, e);
3859 }
3860
3861 #[simd_test(enable = "avx512f")]
3862 const unsafe fn test_mm512_maskz_cvtepu8_epi64() {
3863 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3864 let r = _mm512_maskz_cvtepu8_epi64(0, a);
3865 assert_eq_m512i(r, _mm512_setzero_si512());
3866 let r = _mm512_maskz_cvtepu8_epi64(0b00001111, a);
3867 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3868 assert_eq_m512i(r, e);
3869 }
3870
3871 #[simd_test(enable = "avx512f,avx512vl")]
3872 const unsafe fn test_mm256_mask_cvtepu8_epi64() {
3873 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3874 let src = _mm256_set1_epi64x(-1);
3875 let r = _mm256_mask_cvtepu8_epi64(src, 0, a);
3876 assert_eq_m256i(r, src);
3877 let r = _mm256_mask_cvtepu8_epi64(src, 0b00001111, a);
3878 let e = _mm256_set_epi64x(12, 13, 14, 15);
3879 assert_eq_m256i(r, e);
3880 }
3881
3882 #[simd_test(enable = "avx512f,avx512vl")]
3883 const unsafe fn test_mm256_maskz_cvtepu8_epi64() {
3884 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3885 let r = _mm256_maskz_cvtepu8_epi64(0, a);
3886 assert_eq_m256i(r, _mm256_setzero_si256());
3887 let r = _mm256_maskz_cvtepu8_epi64(0b00001111, a);
3888 let e = _mm256_set_epi64x(12, 13, 14, 15);
3889 assert_eq_m256i(r, e);
3890 }
3891
3892 #[simd_test(enable = "avx512f,avx512vl")]
3893 const unsafe fn test_mm_mask_cvtepu8_epi64() {
3894 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3895 let src = _mm_set1_epi64x(-1);
3896 let r = _mm_mask_cvtepu8_epi64(src, 0, a);
3897 assert_eq_m128i(r, src);
3898 let r = _mm_mask_cvtepu8_epi64(src, 0b00000011, a);
3899 let e = _mm_set_epi64x(14, 15);
3900 assert_eq_m128i(r, e);
3901 }
3902
3903 #[simd_test(enable = "avx512f,avx512vl")]
3904 const unsafe fn test_mm_maskz_cvtepu8_epi64() {
3905 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3906 let r = _mm_maskz_cvtepu8_epi64(0, a);
3907 assert_eq_m128i(r, _mm_setzero_si128());
3908 let r = _mm_maskz_cvtepu8_epi64(0b00000011, a);
3909 let e = _mm_set_epi64x(14, 15);
3910 assert_eq_m128i(r, e);
3911 }
3912
3913 #[simd_test(enable = "avx512f")]
3914 const unsafe fn test_mm512_cvtepi16_epi64() {
3915 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3916 let r = _mm512_cvtepi16_epi64(a);
3917 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3918 assert_eq_m512i(r, e);
3919 }
3920
3921 #[simd_test(enable = "avx512f")]
3922 const unsafe fn test_mm512_mask_cvtepi16_epi64() {
3923 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3924 let src = _mm512_set1_epi64(-1);
3925 let r = _mm512_mask_cvtepi16_epi64(src, 0, a);
3926 assert_eq_m512i(r, src);
3927 let r = _mm512_mask_cvtepi16_epi64(src, 0b00001111, a);
3928 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3929 assert_eq_m512i(r, e);
3930 }
3931
3932 #[simd_test(enable = "avx512f")]
3933 const unsafe fn test_mm512_maskz_cvtepi16_epi64() {
3934 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3935 let r = _mm512_maskz_cvtepi16_epi64(0, a);
3936 assert_eq_m512i(r, _mm512_setzero_si512());
3937 let r = _mm512_maskz_cvtepi16_epi64(0b00001111, a);
3938 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3939 assert_eq_m512i(r, e);
3940 }
3941
3942 #[simd_test(enable = "avx512f,avx512vl")]
3943 const unsafe fn test_mm256_mask_cvtepi16_epi64() {
3944 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3945 let src = _mm256_set1_epi64x(-1);
3946 let r = _mm256_mask_cvtepi16_epi64(src, 0, a);
3947 assert_eq_m256i(r, src);
3948 let r = _mm256_mask_cvtepi16_epi64(src, 0b00001111, a);
3949 let e = _mm256_set_epi64x(12, 13, 14, 15);
3950 assert_eq_m256i(r, e);
3951 }
3952
3953 #[simd_test(enable = "avx512f,avx512vl")]
3954 const unsafe fn test_mm256_maskz_cvtepi16_epi64() {
3955 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3956 let r = _mm256_maskz_cvtepi16_epi64(0, a);
3957 assert_eq_m256i(r, _mm256_setzero_si256());
3958 let r = _mm256_maskz_cvtepi16_epi64(0b00001111, a);
3959 let e = _mm256_set_epi64x(12, 13, 14, 15);
3960 assert_eq_m256i(r, e);
3961 }
3962
3963 #[simd_test(enable = "avx512f,avx512vl")]
3964 const unsafe fn test_mm_mask_cvtepi16_epi64() {
3965 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3966 let src = _mm_set1_epi64x(-1);
3967 let r = _mm_mask_cvtepi16_epi64(src, 0, a);
3968 assert_eq_m128i(r, src);
3969 let r = _mm_mask_cvtepi16_epi64(src, 0b00000011, a);
3970 let e = _mm_set_epi64x(14, 15);
3971 assert_eq_m128i(r, e);
3972 }
3973
3974 #[simd_test(enable = "avx512f,avx512vl")]
3975 const unsafe fn test_mm_maskz_cvtepi16_epi64() {
3976 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3977 let r = _mm_maskz_cvtepi16_epi64(0, a);
3978 assert_eq_m128i(r, _mm_setzero_si128());
3979 let r = _mm_maskz_cvtepi16_epi64(0b00000011, a);
3980 let e = _mm_set_epi64x(14, 15);
3981 assert_eq_m128i(r, e);
3982 }
3983
3984 #[simd_test(enable = "avx512f")]
3985 const unsafe fn test_mm512_cvtepu16_epi64() {
3986 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3987 let r = _mm512_cvtepu16_epi64(a);
3988 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3989 assert_eq_m512i(r, e);
3990 }
3991
3992 #[simd_test(enable = "avx512f")]
3993 const unsafe fn test_mm512_mask_cvtepu16_epi64() {
3994 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3995 let src = _mm512_set1_epi64(-1);
3996 let r = _mm512_mask_cvtepu16_epi64(src, 0, a);
3997 assert_eq_m512i(r, src);
3998 let r = _mm512_mask_cvtepu16_epi64(src, 0b00001111, a);
3999 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4000 assert_eq_m512i(r, e);
4001 }
4002
4003 #[simd_test(enable = "avx512f")]
4004 const unsafe fn test_mm512_maskz_cvtepu16_epi64() {
4005 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4006 let r = _mm512_maskz_cvtepu16_epi64(0, a);
4007 assert_eq_m512i(r, _mm512_setzero_si512());
4008 let r = _mm512_maskz_cvtepu16_epi64(0b00001111, a);
4009 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4010 assert_eq_m512i(r, e);
4011 }
4012
4013 #[simd_test(enable = "avx512f,avx512vl")]
4014 const unsafe fn test_mm256_mask_cvtepu16_epi64() {
4015 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4016 let src = _mm256_set1_epi64x(-1);
4017 let r = _mm256_mask_cvtepu16_epi64(src, 0, a);
4018 assert_eq_m256i(r, src);
4019 let r = _mm256_mask_cvtepu16_epi64(src, 0b00001111, a);
4020 let e = _mm256_set_epi64x(12, 13, 14, 15);
4021 assert_eq_m256i(r, e);
4022 }
4023
4024 #[simd_test(enable = "avx512f,avx512vl")]
4025 const unsafe fn test_mm256_maskz_cvtepu16_epi64() {
4026 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4027 let r = _mm256_maskz_cvtepu16_epi64(0, a);
4028 assert_eq_m256i(r, _mm256_setzero_si256());
4029 let r = _mm256_maskz_cvtepu16_epi64(0b00001111, a);
4030 let e = _mm256_set_epi64x(12, 13, 14, 15);
4031 assert_eq_m256i(r, e);
4032 }
4033
4034 #[simd_test(enable = "avx512f,avx512vl")]
4035 const unsafe fn test_mm_mask_cvtepu16_epi64() {
4036 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4037 let src = _mm_set1_epi64x(-1);
4038 let r = _mm_mask_cvtepu16_epi64(src, 0, a);
4039 assert_eq_m128i(r, src);
4040 let r = _mm_mask_cvtepu16_epi64(src, 0b00000011, a);
4041 let e = _mm_set_epi64x(14, 15);
4042 assert_eq_m128i(r, e);
4043 }
4044
4045 #[simd_test(enable = "avx512f,avx512vl")]
4046 const unsafe fn test_mm_maskz_cvtepu16_epi64() {
4047 let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4048 let r = _mm_maskz_cvtepu16_epi64(0, a);
4049 assert_eq_m128i(r, _mm_setzero_si128());
4050 let r = _mm_maskz_cvtepu16_epi64(0b00000011, a);
4051 let e = _mm_set_epi64x(14, 15);
4052 assert_eq_m128i(r, e);
4053 }
4054
4055 #[simd_test(enable = "avx512f")]
4056 const unsafe fn test_mm512_cvtepi32_epi64() {
4057 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4058 let r = _mm512_cvtepi32_epi64(a);
4059 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4060 assert_eq_m512i(r, e);
4061 }
4062
4063 #[simd_test(enable = "avx512f")]
4064 const unsafe fn test_mm512_mask_cvtepi32_epi64() {
4065 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4066 let src = _mm512_set1_epi64(-1);
4067 let r = _mm512_mask_cvtepi32_epi64(src, 0, a);
4068 assert_eq_m512i(r, src);
4069 let r = _mm512_mask_cvtepi32_epi64(src, 0b00001111, a);
4070 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4071 assert_eq_m512i(r, e);
4072 }
4073
4074 #[simd_test(enable = "avx512f")]
4075 const unsafe fn test_mm512_maskz_cvtepi32_epi64() {
4076 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4077 let r = _mm512_maskz_cvtepi32_epi64(0, a);
4078 assert_eq_m512i(r, _mm512_setzero_si512());
4079 let r = _mm512_maskz_cvtepi32_epi64(0b00001111, a);
4080 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4081 assert_eq_m512i(r, e);
4082 }
4083
4084 #[simd_test(enable = "avx512f,avx512vl")]
4085 const unsafe fn test_mm256_mask_cvtepi32_epi64() {
4086 let a = _mm_set_epi32(8, 9, 10, 11);
4087 let src = _mm256_set1_epi64x(-1);
4088 let r = _mm256_mask_cvtepi32_epi64(src, 0, a);
4089 assert_eq_m256i(r, src);
4090 let r = _mm256_mask_cvtepi32_epi64(src, 0b00001111, a);
4091 let e = _mm256_set_epi64x(8, 9, 10, 11);
4092 assert_eq_m256i(r, e);
4093 }
4094
4095 #[simd_test(enable = "avx512f,avx512vl")]
4096 const unsafe fn test_mm256_maskz_cvtepi32_epi64() {
4097 let a = _mm_set_epi32(8, 9, 10, 11);
4098 let r = _mm256_maskz_cvtepi32_epi64(0, a);
4099 assert_eq_m256i(r, _mm256_setzero_si256());
4100 let r = _mm256_maskz_cvtepi32_epi64(0b00001111, a);
4101 let e = _mm256_set_epi64x(8, 9, 10, 11);
4102 assert_eq_m256i(r, e);
4103 }
4104
4105 #[simd_test(enable = "avx512f,avx512vl")]
4106 const unsafe fn test_mm_mask_cvtepi32_epi64() {
4107 let a = _mm_set_epi32(8, 9, 10, 11);
4108 let src = _mm_set1_epi64x(0);
4109 let r = _mm_mask_cvtepi32_epi64(src, 0, a);
4110 assert_eq_m128i(r, src);
4111 let r = _mm_mask_cvtepi32_epi64(src, 0b00000011, a);
4112 let e = _mm_set_epi64x(10, 11);
4113 assert_eq_m128i(r, e);
4114 }
4115
4116 #[simd_test(enable = "avx512f,avx512vl")]
4117 const unsafe fn test_mm_maskz_cvtepi32_epi64() {
4118 let a = _mm_set_epi32(8, 9, 10, 11);
4119 let r = _mm_maskz_cvtepi32_epi64(0, a);
4120 assert_eq_m128i(r, _mm_setzero_si128());
4121 let r = _mm_maskz_cvtepi32_epi64(0b00000011, a);
4122 let e = _mm_set_epi64x(10, 11);
4123 assert_eq_m128i(r, e);
4124 }
4125
4126 #[simd_test(enable = "avx512f")]
4127 const unsafe fn test_mm512_cvtepu32_epi64() {
4128 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4129 let r = _mm512_cvtepu32_epi64(a);
4130 let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4131 assert_eq_m512i(r, e);
4132 }
4133
4134 #[simd_test(enable = "avx512f")]
4135 const unsafe fn test_mm512_mask_cvtepu32_epi64() {
4136 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4137 let src = _mm512_set1_epi64(-1);
4138 let r = _mm512_mask_cvtepu32_epi64(src, 0, a);
4139 assert_eq_m512i(r, src);
4140 let r = _mm512_mask_cvtepu32_epi64(src, 0b00001111, a);
4141 let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4142 assert_eq_m512i(r, e);
4143 }
4144
4145 #[simd_test(enable = "avx512f")]
4146 const unsafe fn test_mm512_maskz_cvtepu32_epi64() {
4147 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4148 let r = _mm512_maskz_cvtepu32_epi64(0, a);
4149 assert_eq_m512i(r, _mm512_setzero_si512());
4150 let r = _mm512_maskz_cvtepu32_epi64(0b00001111, a);
4151 let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4152 assert_eq_m512i(r, e);
4153 }
4154
4155 #[simd_test(enable = "avx512f,avx512vl")]
4156 const unsafe fn test_mm256_mask_cvtepu32_epi64() {
4157 let a = _mm_set_epi32(12, 13, 14, 15);
4158 let src = _mm256_set1_epi64x(-1);
4159 let r = _mm256_mask_cvtepu32_epi64(src, 0, a);
4160 assert_eq_m256i(r, src);
4161 let r = _mm256_mask_cvtepu32_epi64(src, 0b00001111, a);
4162 let e = _mm256_set_epi64x(12, 13, 14, 15);
4163 assert_eq_m256i(r, e);
4164 }
4165
4166 #[simd_test(enable = "avx512f,avx512vl")]
4167 const unsafe fn test_mm256_maskz_cvtepu32_epi64() {
4168 let a = _mm_set_epi32(12, 13, 14, 15);
4169 let r = _mm256_maskz_cvtepu32_epi64(0, a);
4170 assert_eq_m256i(r, _mm256_setzero_si256());
4171 let r = _mm256_maskz_cvtepu32_epi64(0b00001111, a);
4172 let e = _mm256_set_epi64x(12, 13, 14, 15);
4173 assert_eq_m256i(r, e);
4174 }
4175
4176 #[simd_test(enable = "avx512f,avx512vl")]
4177 const unsafe fn test_mm_mask_cvtepu32_epi64() {
4178 let a = _mm_set_epi32(12, 13, 14, 15);
4179 let src = _mm_set1_epi64x(-1);
4180 let r = _mm_mask_cvtepu32_epi64(src, 0, a);
4181 assert_eq_m128i(r, src);
4182 let r = _mm_mask_cvtepu32_epi64(src, 0b00000011, a);
4183 let e = _mm_set_epi64x(14, 15);
4184 assert_eq_m128i(r, e);
4185 }
4186
4187 #[simd_test(enable = "avx512f,avx512vl")]
4188 const unsafe fn test_mm_maskz_cvtepu32_epi64() {
4189 let a = _mm_set_epi32(12, 13, 14, 15);
4190 let r = _mm_maskz_cvtepu32_epi64(0, a);
4191 assert_eq_m128i(r, _mm_setzero_si128());
4192 let r = _mm_maskz_cvtepu32_epi64(0b00000011, a);
4193 let e = _mm_set_epi64x(14, 15);
4194 assert_eq_m128i(r, e);
4195 }
4196
4197 #[simd_test(enable = "avx512f")]
4198 const unsafe fn test_mm512_cvtepi32_pd() {
4199 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4200 let r = _mm512_cvtepi32_pd(a);
4201 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4202 assert_eq_m512d(r, e);
4203 }
4204
4205 #[simd_test(enable = "avx512f")]
4206 const unsafe fn test_mm512_mask_cvtepi32_pd() {
4207 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4208 let src = _mm512_set1_pd(-1.);
4209 let r = _mm512_mask_cvtepi32_pd(src, 0, a);
4210 assert_eq_m512d(r, src);
4211 let r = _mm512_mask_cvtepi32_pd(src, 0b00001111, a);
4212 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4213 assert_eq_m512d(r, e);
4214 }
4215
4216 #[simd_test(enable = "avx512f")]
4217 const unsafe fn test_mm512_maskz_cvtepi32_pd() {
4218 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4219 let r = _mm512_maskz_cvtepi32_pd(0, a);
4220 assert_eq_m512d(r, _mm512_setzero_pd());
4221 let r = _mm512_maskz_cvtepi32_pd(0b00001111, a);
4222 let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4223 assert_eq_m512d(r, e);
4224 }
4225
4226 #[simd_test(enable = "avx512f,avx512vl")]
4227 const unsafe fn test_mm256_mask_cvtepi32_pd() {
4228 let a = _mm_set_epi32(12, 13, 14, 15);
4229 let src = _mm256_set1_pd(-1.);
4230 let r = _mm256_mask_cvtepi32_pd(src, 0, a);
4231 assert_eq_m256d(r, src);
4232 let r = _mm256_mask_cvtepi32_pd(src, 0b00001111, a);
4233 let e = _mm256_set_pd(12., 13., 14., 15.);
4234 assert_eq_m256d(r, e);
4235 }
4236
4237 #[simd_test(enable = "avx512f,avx512vl")]
4238 const unsafe fn test_mm256_maskz_cvtepi32_pd() {
4239 let a = _mm_set_epi32(12, 13, 14, 15);
4240 let r = _mm256_maskz_cvtepi32_pd(0, a);
4241 assert_eq_m256d(r, _mm256_setzero_pd());
4242 let r = _mm256_maskz_cvtepi32_pd(0b00001111, a);
4243 let e = _mm256_set_pd(12., 13., 14., 15.);
4244 assert_eq_m256d(r, e);
4245 }
4246
4247 #[simd_test(enable = "avx512f,avx512vl")]
4248 const unsafe fn test_mm_mask_cvtepi32_pd() {
4249 let a = _mm_set_epi32(12, 13, 14, 15);
4250 let src = _mm_set1_pd(-1.);
4251 let r = _mm_mask_cvtepi32_pd(src, 0, a);
4252 assert_eq_m128d(r, src);
4253 let r = _mm_mask_cvtepi32_pd(src, 0b00000011, a);
4254 let e = _mm_set_pd(14., 15.);
4255 assert_eq_m128d(r, e);
4256 }
4257
4258 #[simd_test(enable = "avx512f,avx512vl")]
4259 const unsafe fn test_mm_maskz_cvtepi32_pd() {
4260 let a = _mm_set_epi32(12, 13, 14, 15);
4261 let r = _mm_maskz_cvtepi32_pd(0, a);
4262 assert_eq_m128d(r, _mm_setzero_pd());
4263 let r = _mm_maskz_cvtepi32_pd(0b00000011, a);
4264 let e = _mm_set_pd(14., 15.);
4265 assert_eq_m128d(r, e);
4266 }
4267
4268 #[simd_test(enable = "avx512f")]
4269 const unsafe fn test_mm512_cvtepu32_pd() {
4270 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4271 let r = _mm512_cvtepu32_pd(a);
4272 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4273 assert_eq_m512d(r, e);
4274 }
4275
4276 #[simd_test(enable = "avx512f")]
4277 const unsafe fn test_mm512_mask_cvtepu32_pd() {
4278 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4279 let src = _mm512_set1_pd(-1.);
4280 let r = _mm512_mask_cvtepu32_pd(src, 0, a);
4281 assert_eq_m512d(r, src);
4282 let r = _mm512_mask_cvtepu32_pd(src, 0b00001111, a);
4283 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4284 assert_eq_m512d(r, e);
4285 }
4286
4287 #[simd_test(enable = "avx512f")]
4288 const unsafe fn test_mm512_maskz_cvtepu32_pd() {
4289 let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4290 let r = _mm512_maskz_cvtepu32_pd(0, a);
4291 assert_eq_m512d(r, _mm512_setzero_pd());
4292 let r = _mm512_maskz_cvtepu32_pd(0b00001111, a);
4293 let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4294 assert_eq_m512d(r, e);
4295 }
4296
4297 #[simd_test(enable = "avx512f,avx512vl")]
4298 const unsafe fn test_mm256_cvtepu32_pd() {
4299 let a = _mm_set_epi32(12, 13, 14, 15);
4300 let r = _mm256_cvtepu32_pd(a);
4301 let e = _mm256_set_pd(12., 13., 14., 15.);
4302 assert_eq_m256d(r, e);
4303 }
4304
4305 #[simd_test(enable = "avx512f,avx512vl")]
4306 const unsafe fn test_mm256_mask_cvtepu32_pd() {
4307 let a = _mm_set_epi32(12, 13, 14, 15);
4308 let src = _mm256_set1_pd(-1.);
4309 let r = _mm256_mask_cvtepu32_pd(src, 0, a);
4310 assert_eq_m256d(r, src);
4311 let r = _mm256_mask_cvtepu32_pd(src, 0b00001111, a);
4312 let e = _mm256_set_pd(12., 13., 14., 15.);
4313 assert_eq_m256d(r, e);
4314 }
4315
4316 #[simd_test(enable = "avx512f,avx512vl")]
4317 const unsafe fn test_mm256_maskz_cvtepu32_pd() {
4318 let a = _mm_set_epi32(12, 13, 14, 15);
4319 let r = _mm256_maskz_cvtepu32_pd(0, a);
4320 assert_eq_m256d(r, _mm256_setzero_pd());
4321 let r = _mm256_maskz_cvtepu32_pd(0b00001111, a);
4322 let e = _mm256_set_pd(12., 13., 14., 15.);
4323 assert_eq_m256d(r, e);
4324 }
4325
4326 #[simd_test(enable = "avx512f,avx512vl")]
4327 const unsafe fn test_mm_cvtepu32_pd() {
4328 let a = _mm_set_epi32(12, 13, 14, 15);
4329 let r = _mm_cvtepu32_pd(a);
4330 let e = _mm_set_pd(14., 15.);
4331 assert_eq_m128d(r, e);
4332 }
4333
4334 #[simd_test(enable = "avx512f,avx512vl")]
4335 const unsafe fn test_mm_mask_cvtepu32_pd() {
4336 let a = _mm_set_epi32(12, 13, 14, 15);
4337 let src = _mm_set1_pd(-1.);
4338 let r = _mm_mask_cvtepu32_pd(src, 0, a);
4339 assert_eq_m128d(r, src);
4340 let r = _mm_mask_cvtepu32_pd(src, 0b00000011, a);
4341 let e = _mm_set_pd(14., 15.);
4342 assert_eq_m128d(r, e);
4343 }
4344
4345 #[simd_test(enable = "avx512f,avx512vl")]
4346 const unsafe fn test_mm_maskz_cvtepu32_pd() {
4347 let a = _mm_set_epi32(12, 13, 14, 15);
4348 let r = _mm_maskz_cvtepu32_pd(0, a);
4349 assert_eq_m128d(r, _mm_setzero_pd());
4350 let r = _mm_maskz_cvtepu32_pd(0b00000011, a);
4351 let e = _mm_set_pd(14., 15.);
4352 assert_eq_m128d(r, e);
4353 }
4354
4355 #[simd_test(enable = "avx512f")]
4356 const unsafe fn test_mm512_cvtepi32lo_pd() {
4357 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4358 let r = _mm512_cvtepi32lo_pd(a);
4359 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4360 assert_eq_m512d(r, e);
4361 }
4362
4363 #[simd_test(enable = "avx512f")]
4364 const unsafe fn test_mm512_mask_cvtepi32lo_pd() {
4365 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4366 let src = _mm512_set1_pd(-1.);
4367 let r = _mm512_mask_cvtepi32lo_pd(src, 0, a);
4368 assert_eq_m512d(r, src);
4369 let r = _mm512_mask_cvtepi32lo_pd(src, 0b00001111, a);
4370 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4371 assert_eq_m512d(r, e);
4372 }
4373
4374 #[simd_test(enable = "avx512f")]
4375 const unsafe fn test_mm512_cvtepu32lo_pd() {
4376 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4377 let r = _mm512_cvtepu32lo_pd(a);
4378 let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4379 assert_eq_m512d(r, e);
4380 }
4381
4382 #[simd_test(enable = "avx512f")]
4383 const unsafe fn test_mm512_mask_cvtepu32lo_pd() {
4384 let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4385 let src = _mm512_set1_pd(-1.);
4386 let r = _mm512_mask_cvtepu32lo_pd(src, 0, a);
4387 assert_eq_m512d(r, src);
4388 let r = _mm512_mask_cvtepu32lo_pd(src, 0b00001111, a);
4389 let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4390 assert_eq_m512d(r, e);
4391 }
4392
4393 #[simd_test(enable = "avx512f")]
4394 const unsafe fn test_mm512_cvtepi64_epi32() {
4395 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4396 let r = _mm512_cvtepi64_epi32(a);
4397 let e = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4398 assert_eq_m256i(r, e);
4399 }
4400
4401 #[simd_test(enable = "avx512f")]
4402 const unsafe fn test_mm512_mask_cvtepi64_epi32() {
4403 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4404 let src = _mm256_set1_epi32(-1);
4405 let r = _mm512_mask_cvtepi64_epi32(src, 0, a);
4406 assert_eq_m256i(r, src);
4407 let r = _mm512_mask_cvtepi64_epi32(src, 0b00001111, a);
4408 let e = _mm256_set_epi32(-1, -1, -1, -1, 12, 13, 14, 15);
4409 assert_eq_m256i(r, e);
4410 }
4411
4412 #[simd_test(enable = "avx512f")]
4413 const unsafe fn test_mm512_maskz_cvtepi64_epi32() {
4414 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4415 let r = _mm512_maskz_cvtepi64_epi32(0, a);
4416 assert_eq_m256i(r, _mm256_setzero_si256());
4417 let r = _mm512_maskz_cvtepi64_epi32(0b00001111, a);
4418 let e = _mm256_set_epi32(0, 0, 0, 0, 12, 13, 14, 15);
4419 assert_eq_m256i(r, e);
4420 }
4421
4422 #[simd_test(enable = "avx512f,avx512vl")]
4423 const unsafe fn test_mm256_cvtepi64_epi32() {
4424 let a = _mm256_set_epi64x(1, 2, 3, 4);
4425 let r = _mm256_cvtepi64_epi32(a);
4426 let e = _mm_set_epi32(1, 2, 3, 4);
4427 assert_eq_m128i(r, e);
4428 }
4429
4430 #[simd_test(enable = "avx512f,avx512vl")]
4431 const unsafe fn test_mm256_mask_cvtepi64_epi32() {
4432 let a = _mm256_set_epi64x(1, 2, 3, 4);
4433 let src = _mm_set1_epi32(0);
4434 let r = _mm256_mask_cvtepi64_epi32(src, 0, a);
4435 assert_eq_m128i(r, src);
4436 let r = _mm256_mask_cvtepi64_epi32(src, 0b00001111, a);
4437 let e = _mm_set_epi32(1, 2, 3, 4);
4438 assert_eq_m128i(r, e);
4439 }
4440
4441 #[simd_test(enable = "avx512f,avx512vl")]
4442 const unsafe fn test_mm256_maskz_cvtepi64_epi32() {
4443 let a = _mm256_set_epi64x(1, 2, 3, 4);
4444 let r = _mm256_maskz_cvtepi64_epi32(0, a);
4445 assert_eq_m128i(r, _mm_setzero_si128());
4446 let r = _mm256_maskz_cvtepi64_epi32(0b00001111, a);
4447 let e = _mm_set_epi32(1, 2, 3, 4);
4448 assert_eq_m128i(r, e);
4449 }
4450
4451 #[simd_test(enable = "avx512f,avx512vl")]
4452 unsafe fn test_mm_cvtepi64_epi32() {
4453 let a = _mm_set_epi64x(3, 4);
4454 let r = _mm_cvtepi64_epi32(a);
4455 let e = _mm_set_epi32(0, 0, 3, 4);
4456 assert_eq_m128i(r, e);
4457 }
4458
4459 #[simd_test(enable = "avx512f,avx512vl")]
4460 unsafe fn test_mm_mask_cvtepi64_epi32() {
4461 let a = _mm_set_epi64x(3, 4);
4462 let src = _mm_set1_epi32(0);
4463 let r = _mm_mask_cvtepi64_epi32(src, 0, a);
4464 assert_eq_m128i(r, src);
4465 let r = _mm_mask_cvtepi64_epi32(src, 0b00000011, a);
4466 let e = _mm_set_epi32(0, 0, 3, 4);
4467 assert_eq_m128i(r, e);
4468 }
4469
4470 #[simd_test(enable = "avx512f,avx512vl")]
4471 unsafe fn test_mm_maskz_cvtepi64_epi32() {
4472 let a = _mm_set_epi64x(3, 4);
4473 let r = _mm_maskz_cvtepi64_epi32(0, a);
4474 assert_eq_m128i(r, _mm_setzero_si128());
4475 let r = _mm_maskz_cvtepi64_epi32(0b00000011, a);
4476 let e = _mm_set_epi32(0, 0, 3, 4);
4477 assert_eq_m128i(r, e);
4478 }
4479
4480 #[simd_test(enable = "avx512f")]
4481 const unsafe fn test_mm512_cvtepi64_epi16() {
4482 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4483 let r = _mm512_cvtepi64_epi16(a);
4484 let e = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4485 assert_eq_m128i(r, e);
4486 }
4487
4488 #[simd_test(enable = "avx512f")]
4489 const unsafe fn test_mm512_mask_cvtepi64_epi16() {
4490 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4491 let src = _mm_set1_epi16(-1);
4492 let r = _mm512_mask_cvtepi64_epi16(src, 0, a);
4493 assert_eq_m128i(r, src);
4494 let r = _mm512_mask_cvtepi64_epi16(src, 0b00001111, a);
4495 let e = _mm_set_epi16(-1, -1, -1, -1, 12, 13, 14, 15);
4496 assert_eq_m128i(r, e);
4497 }
4498
4499 #[simd_test(enable = "avx512f")]
4500 const unsafe fn test_mm512_maskz_cvtepi64_epi16() {
4501 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4502 let r = _mm512_maskz_cvtepi64_epi16(0, a);
4503 assert_eq_m128i(r, _mm_setzero_si128());
4504 let r = _mm512_maskz_cvtepi64_epi16(0b00001111, a);
4505 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4506 assert_eq_m128i(r, e);
4507 }
4508
4509 #[simd_test(enable = "avx512f,avx512vl")]
4510 unsafe fn test_mm256_cvtepi64_epi16() {
4511 let a = _mm256_set_epi64x(12, 13, 14, 15);
4512 let r = _mm256_cvtepi64_epi16(a);
4513 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4514 assert_eq_m128i(r, e);
4515 }
4516
4517 #[simd_test(enable = "avx512f,avx512vl")]
4518 unsafe fn test_mm256_mask_cvtepi64_epi16() {
4519 let a = _mm256_set_epi64x(12, 13, 14, 15);
4520 let src = _mm_set1_epi16(0);
4521 let r = _mm256_mask_cvtepi64_epi16(src, 0, a);
4522 assert_eq_m128i(r, src);
4523 let r = _mm256_mask_cvtepi64_epi16(src, 0b11111111, a);
4524 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4525 assert_eq_m128i(r, e);
4526 }
4527
4528 #[simd_test(enable = "avx512f,avx512vl")]
4529 unsafe fn test_mm256_maskz_cvtepi64_epi16() {
4530 let a = _mm256_set_epi64x(12, 13, 14, 15);
4531 let r = _mm256_maskz_cvtepi64_epi16(0, a);
4532 assert_eq_m128i(r, _mm_setzero_si128());
4533 let r = _mm256_maskz_cvtepi64_epi16(0b11111111, a);
4534 let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4535 assert_eq_m128i(r, e);
4536 }
4537
4538 #[simd_test(enable = "avx512f,avx512vl")]
4539 unsafe fn test_mm_cvtepi64_epi16() {
4540 let a = _mm_set_epi64x(14, 15);
4541 let r = _mm_cvtepi64_epi16(a);
4542 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4543 assert_eq_m128i(r, e);
4544 }
4545
4546 #[simd_test(enable = "avx512f,avx512vl")]
4547 unsafe fn test_mm_mask_cvtepi64_epi16() {
4548 let a = _mm_set_epi64x(14, 15);
4549 let src = _mm_set1_epi16(0);
4550 let r = _mm_mask_cvtepi64_epi16(src, 0, a);
4551 assert_eq_m128i(r, src);
4552 let r = _mm_mask_cvtepi64_epi16(src, 0b11111111, a);
4553 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4554 assert_eq_m128i(r, e);
4555 }
4556
4557 #[simd_test(enable = "avx512f,avx512vl")]
4558 unsafe fn test_mm_maskz_cvtepi64_epi16() {
4559 let a = _mm_set_epi64x(14, 15);
4560 let r = _mm_maskz_cvtepi64_epi16(0, a);
4561 assert_eq_m128i(r, _mm_setzero_si128());
4562 let r = _mm_maskz_cvtepi64_epi16(0b11111111, a);
4563 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4564 assert_eq_m128i(r, e);
4565 }
4566
4567 #[simd_test(enable = "avx512f")]
4568 unsafe fn test_mm512_cvtepi64_epi8() {
4569 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4570 let r = _mm512_cvtepi64_epi8(a);
4571 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
4572 assert_eq_m128i(r, e);
4573 }
4574
4575 #[simd_test(enable = "avx512f")]
4576 unsafe fn test_mm512_mask_cvtepi64_epi8() {
4577 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4578 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4579 let r = _mm512_mask_cvtepi64_epi8(src, 0, a);
4580 assert_eq_m128i(r, src);
4581 let r = _mm512_mask_cvtepi64_epi8(src, 0b00001111, a);
4582 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 12, 13, 14, 15);
4583 assert_eq_m128i(r, e);
4584 }
4585
4586 #[simd_test(enable = "avx512f")]
4587 unsafe fn test_mm512_maskz_cvtepi64_epi8() {
4588 let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4589 let r = _mm512_maskz_cvtepi64_epi8(0, a);
4590 assert_eq_m128i(r, _mm_setzero_si128());
4591 let r = _mm512_maskz_cvtepi64_epi8(0b00001111, a);
4592 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4593 assert_eq_m128i(r, e);
4594 }
4595
4596 #[simd_test(enable = "avx512f,avx512vl")]
4597 unsafe fn test_mm256_cvtepi64_epi8() {
4598 let a = _mm256_set_epi64x(12, 13, 14, 15);
4599 let r = _mm256_cvtepi64_epi8(a);
4600 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4601 assert_eq_m128i(r, e);
4602 }
4603
4604 #[simd_test(enable = "avx512f,avx512vl")]
4605 unsafe fn test_mm256_mask_cvtepi64_epi8() {
4606 let a = _mm256_set_epi64x(12, 13, 14, 15);
4607 let src = _mm_set1_epi8(0);
4608 let r = _mm256_mask_cvtepi64_epi8(src, 0, a);
4609 assert_eq_m128i(r, src);
4610 let r = _mm256_mask_cvtepi64_epi8(src, 0b00001111, a);
4611 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4612 assert_eq_m128i(r, e);
4613 }
4614
4615 #[simd_test(enable = "avx512f,avx512vl")]
4616 unsafe fn test_mm256_maskz_cvtepi64_epi8() {
4617 let a = _mm256_set_epi64x(12, 13, 14, 15);
4618 let r = _mm256_maskz_cvtepi64_epi8(0, a);
4619 assert_eq_m128i(r, _mm_setzero_si128());
4620 let r = _mm256_maskz_cvtepi64_epi8(0b00001111, a);
4621 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4622 assert_eq_m128i(r, e);
4623 }
4624
4625 #[simd_test(enable = "avx512f,avx512vl")]
4626 unsafe fn test_mm_cvtepi64_epi8() {
4627 let a = _mm_set_epi64x(14, 15);
4628 let r = _mm_cvtepi64_epi8(a);
4629 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4630 assert_eq_m128i(r, e);
4631 }
4632
4633 #[simd_test(enable = "avx512f,avx512vl")]
4634 unsafe fn test_mm_mask_cvtepi64_epi8() {
4635 let a = _mm_set_epi64x(14, 15);
4636 let src = _mm_set1_epi8(0);
4637 let r = _mm_mask_cvtepi64_epi8(src, 0, a);
4638 assert_eq_m128i(r, src);
4639 let r = _mm_mask_cvtepi64_epi8(src, 0b00000011, a);
4640 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4641 assert_eq_m128i(r, e);
4642 }
4643
4644 #[simd_test(enable = "avx512f,avx512vl")]
4645 unsafe fn test_mm_maskz_cvtepi64_epi8() {
4646 let a = _mm_set_epi64x(14, 15);
4647 let r = _mm_maskz_cvtepi64_epi8(0, a);
4648 assert_eq_m128i(r, _mm_setzero_si128());
4649 let r = _mm_maskz_cvtepi64_epi8(0b00000011, a);
4650 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4651 assert_eq_m128i(r, e);
4652 }
4653
4654 #[simd_test(enable = "avx512f")]
4655 unsafe fn test_mm512_cvtsepi64_epi32() {
4656 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4657 let r = _mm512_cvtsepi64_epi32(a);
4658 let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, i32::MIN, i32::MAX);
4659 assert_eq_m256i(r, e);
4660 }
4661
4662 #[simd_test(enable = "avx512f")]
4663 unsafe fn test_mm512_mask_cvtsepi64_epi32() {
4664 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4665 let src = _mm256_set1_epi32(-1);
4666 let r = _mm512_mask_cvtsepi64_epi32(src, 0, a);
4667 assert_eq_m256i(r, src);
4668 let r = _mm512_mask_cvtsepi64_epi32(src, 0b00001111, a);
4669 let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, i32::MIN, i32::MAX);
4670 assert_eq_m256i(r, e);
4671 }
4672
4673 #[simd_test(enable = "avx512f")]
4674 unsafe fn test_mm512_maskz_cvtsepi64_epi32() {
4675 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4676 let r = _mm512_maskz_cvtsepi64_epi32(0, a);
4677 assert_eq_m256i(r, _mm256_setzero_si256());
4678 let r = _mm512_maskz_cvtsepi64_epi32(0b00001111, a);
4679 let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, i32::MIN, i32::MAX);
4680 assert_eq_m256i(r, e);
4681 }
4682
4683 #[simd_test(enable = "avx512f,avx512vl")]
4684 unsafe fn test_mm256_cvtsepi64_epi32() {
4685 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4686 let r = _mm256_cvtsepi64_epi32(a);
4687 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4688 assert_eq_m128i(r, e);
4689 }
4690
4691 #[simd_test(enable = "avx512f,avx512vl")]
4692 unsafe fn test_mm256_mask_cvtsepi64_epi32() {
4693 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4694 let src = _mm_set1_epi32(-1);
4695 let r = _mm256_mask_cvtsepi64_epi32(src, 0, a);
4696 assert_eq_m128i(r, src);
4697 let r = _mm256_mask_cvtsepi64_epi32(src, 0b00001111, a);
4698 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4699 assert_eq_m128i(r, e);
4700 }
4701
4702 #[simd_test(enable = "avx512f,avx512vl")]
4703 unsafe fn test_mm256_maskz_cvtsepi64_epi32() {
4704 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4705 let r = _mm256_maskz_cvtsepi64_epi32(0, a);
4706 assert_eq_m128i(r, _mm_setzero_si128());
4707 let r = _mm256_maskz_cvtsepi64_epi32(0b00001111, a);
4708 let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4709 assert_eq_m128i(r, e);
4710 }
4711
4712 #[simd_test(enable = "avx512f,avx512vl")]
4713 unsafe fn test_mm_cvtsepi64_epi32() {
4714 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4715 let r = _mm_cvtsepi64_epi32(a);
4716 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4717 assert_eq_m128i(r, e);
4718 }
4719
4720 #[simd_test(enable = "avx512f,avx512vl")]
4721 unsafe fn test_mm_mask_cvtsepi64_epi32() {
4722 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4723 let src = _mm_set1_epi32(0);
4724 let r = _mm_mask_cvtsepi64_epi32(src, 0, a);
4725 assert_eq_m128i(r, src);
4726 let r = _mm_mask_cvtsepi64_epi32(src, 0b00000011, a);
4727 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4728 assert_eq_m128i(r, e);
4729 }
4730
4731 #[simd_test(enable = "avx512f,avx512vl")]
4732 unsafe fn test_mm_maskz_cvtsepi64_epi32() {
4733 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4734 let r = _mm_maskz_cvtsepi64_epi32(0, a);
4735 assert_eq_m128i(r, _mm_setzero_si128());
4736 let r = _mm_maskz_cvtsepi64_epi32(0b00000011, a);
4737 let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4738 assert_eq_m128i(r, e);
4739 }
4740
4741 #[simd_test(enable = "avx512f")]
4742 unsafe fn test_mm512_cvtsepi64_epi16() {
4743 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4744 let r = _mm512_cvtsepi64_epi16(a);
4745 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, i16::MIN, i16::MAX);
4746 assert_eq_m128i(r, e);
4747 }
4748
4749 #[simd_test(enable = "avx512f")]
4750 unsafe fn test_mm512_mask_cvtsepi64_epi16() {
4751 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4752 let src = _mm_set1_epi16(-1);
4753 let r = _mm512_mask_cvtsepi64_epi16(src, 0, a);
4754 assert_eq_m128i(r, src);
4755 let r = _mm512_mask_cvtsepi64_epi16(src, 0b00001111, a);
4756 let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, i16::MIN, i16::MAX);
4757 assert_eq_m128i(r, e);
4758 }
4759
4760 #[simd_test(enable = "avx512f")]
4761 unsafe fn test_mm512_maskz_cvtsepi64_epi16() {
4762 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4763 let r = _mm512_maskz_cvtsepi64_epi16(0, a);
4764 assert_eq_m128i(r, _mm_setzero_si128());
4765 let r = _mm512_maskz_cvtsepi64_epi16(0b00001111, a);
4766 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4767 assert_eq_m128i(r, e);
4768 }
4769
4770 #[simd_test(enable = "avx512f,avx512vl")]
4771 unsafe fn test_mm256_cvtsepi64_epi16() {
4772 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4773 let r = _mm256_cvtsepi64_epi16(a);
4774 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4775 assert_eq_m128i(r, e);
4776 }
4777
4778 #[simd_test(enable = "avx512f,avx512vl")]
4779 unsafe fn test_mm256_mask_cvtsepi64_epi16() {
4780 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4781 let src = _mm_set1_epi16(0);
4782 let r = _mm256_mask_cvtsepi64_epi16(src, 0, a);
4783 assert_eq_m128i(r, src);
4784 let r = _mm256_mask_cvtsepi64_epi16(src, 0b00001111, a);
4785 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4786 assert_eq_m128i(r, e);
4787 }
4788
4789 #[simd_test(enable = "avx512f,avx512vl")]
4790 unsafe fn test_mm256_maskz_cvtsepi64_epi16() {
4791 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4792 let r = _mm256_maskz_cvtsepi64_epi16(0, a);
4793 assert_eq_m128i(r, _mm_setzero_si128());
4794 let r = _mm256_maskz_cvtsepi64_epi16(0b00001111, a);
4795 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4796 assert_eq_m128i(r, e);
4797 }
4798
4799 #[simd_test(enable = "avx512f,avx512vl")]
4800 unsafe fn test_mm_cvtsepi64_epi16() {
4801 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4802 let r = _mm_cvtsepi64_epi16(a);
4803 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4804 assert_eq_m128i(r, e);
4805 }
4806
4807 #[simd_test(enable = "avx512f,avx512vl")]
4808 unsafe fn test_mm_mask_cvtsepi64_epi16() {
4809 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4810 let src = _mm_set1_epi16(0);
4811 let r = _mm_mask_cvtsepi64_epi16(src, 0, a);
4812 assert_eq_m128i(r, src);
4813 let r = _mm_mask_cvtsepi64_epi16(src, 0b00000011, a);
4814 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4815 assert_eq_m128i(r, e);
4816 }
4817
4818 #[simd_test(enable = "avx512f,avx512vl")]
4819 unsafe fn test_mm_maskz_cvtsepi64_epi16() {
4820 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4821 let r = _mm_maskz_cvtsepi64_epi16(0, a);
4822 assert_eq_m128i(r, _mm_setzero_si128());
4823 let r = _mm_maskz_cvtsepi64_epi16(0b00000011, a);
4824 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4825 assert_eq_m128i(r, e);
4826 }
4827
4828 #[simd_test(enable = "avx512f")]
4829 unsafe fn test_mm512_cvtsepi64_epi8() {
4830 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4831 let r = _mm512_cvtsepi64_epi8(a);
4832 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, i8::MIN, i8::MAX);
4833 assert_eq_m128i(r, e);
4834 }
4835
4836 #[simd_test(enable = "avx512f")]
4837 unsafe fn test_mm512_mask_cvtsepi64_epi8() {
4838 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4839 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4840 let r = _mm512_mask_cvtsepi64_epi8(src, 0, a);
4841 assert_eq_m128i(r, src);
4842 let r = _mm512_mask_cvtsepi64_epi8(src, 0b00001111, a);
4843 #[rustfmt::skip]
4844 let e = _mm_set_epi8(
4845 0, 0, 0, 0,
4846 0, 0, 0, 0,
4847 -1, -1, -1, -1,
4848 4, 5, i8::MIN, i8::MAX,
4849 );
4850 assert_eq_m128i(r, e);
4851 }
4852
4853 #[simd_test(enable = "avx512f")]
4854 unsafe fn test_mm512_maskz_cvtsepi64_epi8() {
4855 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4856 let r = _mm512_maskz_cvtsepi64_epi8(0, a);
4857 assert_eq_m128i(r, _mm_setzero_si128());
4858 let r = _mm512_maskz_cvtsepi64_epi8(0b00001111, a);
4859 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4860 assert_eq_m128i(r, e);
4861 }
4862
4863 #[simd_test(enable = "avx512f,avx512vl")]
4864 unsafe fn test_mm256_cvtsepi64_epi8() {
4865 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4866 let r = _mm256_cvtsepi64_epi8(a);
4867 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4868 assert_eq_m128i(r, e);
4869 }
4870
4871 #[simd_test(enable = "avx512f,avx512vl")]
4872 unsafe fn test_mm256_mask_cvtsepi64_epi8() {
4873 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4874 let src = _mm_set1_epi8(0);
4875 let r = _mm256_mask_cvtsepi64_epi8(src, 0, a);
4876 assert_eq_m128i(r, src);
4877 let r = _mm256_mask_cvtsepi64_epi8(src, 0b00001111, a);
4878 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4879 assert_eq_m128i(r, e);
4880 }
4881
4882 #[simd_test(enable = "avx512f,avx512vl")]
4883 unsafe fn test_mm256_maskz_cvtsepi64_epi8() {
4884 let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4885 let r = _mm256_maskz_cvtsepi64_epi8(0, a);
4886 assert_eq_m128i(r, _mm_setzero_si128());
4887 let r = _mm256_maskz_cvtsepi64_epi8(0b00001111, a);
4888 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4889 assert_eq_m128i(r, e);
4890 }
4891
4892 #[simd_test(enable = "avx512f,avx512vl")]
4893 unsafe fn test_mm_cvtsepi64_epi8() {
4894 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4895 let r = _mm_cvtsepi64_epi8(a);
4896 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4897 assert_eq_m128i(r, e);
4898 }
4899
4900 #[simd_test(enable = "avx512f,avx512vl")]
4901 unsafe fn test_mm_mask_cvtsepi64_epi8() {
4902 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4903 let src = _mm_set1_epi8(0);
4904 let r = _mm_mask_cvtsepi64_epi8(src, 0, a);
4905 assert_eq_m128i(r, src);
4906 let r = _mm_mask_cvtsepi64_epi8(src, 0b00000011, a);
4907 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4908 assert_eq_m128i(r, e);
4909 }
4910
4911 #[simd_test(enable = "avx512f,avx512vl")]
4912 unsafe fn test_mm_maskz_cvtsepi64_epi8() {
4913 let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4914 let r = _mm_maskz_cvtsepi64_epi8(0, a);
4915 assert_eq_m128i(r, _mm_setzero_si128());
4916 let r = _mm_maskz_cvtsepi64_epi8(0b00000011, a);
4917 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4918 assert_eq_m128i(r, e);
4919 }
4920
4921 #[simd_test(enable = "avx512f")]
4922 unsafe fn test_mm512_cvtusepi64_epi32() {
4923 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4924 let r = _mm512_cvtusepi64_epi32(a);
4925 let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, -1, -1);
4926 assert_eq_m256i(r, e);
4927 }
4928
4929 #[simd_test(enable = "avx512f")]
4930 unsafe fn test_mm512_mask_cvtusepi64_epi32() {
4931 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4932 let src = _mm256_set1_epi32(-1);
4933 let r = _mm512_mask_cvtusepi64_epi32(src, 0, a);
4934 assert_eq_m256i(r, src);
4935 let r = _mm512_mask_cvtusepi64_epi32(src, 0b00001111, a);
4936 let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, -1, -1);
4937 assert_eq_m256i(r, e);
4938 }
4939
4940 #[simd_test(enable = "avx512f")]
4941 unsafe fn test_mm512_maskz_cvtusepi64_epi32() {
4942 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4943 let r = _mm512_maskz_cvtusepi64_epi32(0, a);
4944 assert_eq_m256i(r, _mm256_setzero_si256());
4945 let r = _mm512_maskz_cvtusepi64_epi32(0b00001111, a);
4946 let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, -1, -1);
4947 assert_eq_m256i(r, e);
4948 }
4949
4950 #[simd_test(enable = "avx512f,avx512vl")]
4951 unsafe fn test_mm256_cvtusepi64_epi32() {
4952 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4953 let r = _mm256_cvtusepi64_epi32(a);
4954 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4955 assert_eq_m128i(r, e);
4956 }
4957
4958 #[simd_test(enable = "avx512f,avx512vl")]
4959 unsafe fn test_mm256_mask_cvtusepi64_epi32() {
4960 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4961 let src = _mm_set1_epi32(0);
4962 let r = _mm256_mask_cvtusepi64_epi32(src, 0, a);
4963 assert_eq_m128i(r, src);
4964 let r = _mm256_mask_cvtusepi64_epi32(src, 0b00001111, a);
4965 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4966 assert_eq_m128i(r, e);
4967 }
4968
4969 #[simd_test(enable = "avx512f,avx512vl")]
4970 unsafe fn test_mm256_maskz_cvtusepi64_epi32() {
4971 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4972 let r = _mm256_maskz_cvtusepi64_epi32(0, a);
4973 assert_eq_m128i(r, _mm_setzero_si128());
4974 let r = _mm256_maskz_cvtusepi64_epi32(0b00001111, a);
4975 let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4976 assert_eq_m128i(r, e);
4977 }
4978
4979 #[simd_test(enable = "avx512f,avx512vl")]
4980 unsafe fn test_mm_cvtusepi64_epi32() {
4981 let a = _mm_set_epi64x(6, i64::MAX);
4982 let r = _mm_cvtusepi64_epi32(a);
4983 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4984 assert_eq_m128i(r, e);
4985 }
4986
4987 #[simd_test(enable = "avx512f,avx512vl")]
4988 unsafe fn test_mm_mask_cvtusepi64_epi32() {
4989 let a = _mm_set_epi64x(6, i64::MAX);
4990 let src = _mm_set1_epi32(0);
4991 let r = _mm_mask_cvtusepi64_epi32(src, 0, a);
4992 assert_eq_m128i(r, src);
4993 let r = _mm_mask_cvtusepi64_epi32(src, 0b00000011, a);
4994 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4995 assert_eq_m128i(r, e);
4996 }
4997
4998 #[simd_test(enable = "avx512f,avx512vl")]
4999 unsafe fn test_mm_maskz_cvtusepi64_epi32() {
5000 let a = _mm_set_epi64x(6, i64::MAX);
5001 let r = _mm_maskz_cvtusepi64_epi32(0, a);
5002 assert_eq_m128i(r, _mm_setzero_si128());
5003 let r = _mm_maskz_cvtusepi64_epi32(0b00000011, a);
5004 let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
5005 assert_eq_m128i(r, e);
5006 }
5007
5008 #[simd_test(enable = "avx512f")]
5009 unsafe fn test_mm512_cvtusepi64_epi16() {
5010 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5011 let r = _mm512_cvtusepi64_epi16(a);
5012 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, -1, -1);
5013 assert_eq_m128i(r, e);
5014 }
5015
5016 #[simd_test(enable = "avx512f")]
5017 unsafe fn test_mm512_mask_cvtusepi64_epi16() {
5018 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5019 let src = _mm_set1_epi16(-1);
5020 let r = _mm512_mask_cvtusepi64_epi16(src, 0, a);
5021 assert_eq_m128i(r, src);
5022 let r = _mm512_mask_cvtusepi64_epi16(src, 0b00001111, a);
5023 let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, -1, -1);
5024 assert_eq_m128i(r, e);
5025 }
5026
5027 #[simd_test(enable = "avx512f")]
5028 unsafe fn test_mm512_maskz_cvtusepi64_epi16() {
5029 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5030 let r = _mm512_maskz_cvtusepi64_epi16(0, a);
5031 assert_eq_m128i(r, _mm_setzero_si128());
5032 let r = _mm512_maskz_cvtusepi64_epi16(0b00001111, a);
5033 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, -1, -1);
5034 assert_eq_m128i(r, e);
5035 }
5036
5037 #[simd_test(enable = "avx512f,avx512vl")]
5038 unsafe fn test_mm256_cvtusepi64_epi16() {
5039 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5040 let r = _mm256_cvtusepi64_epi16(a);
5041 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5042 assert_eq_m128i(r, e);
5043 }
5044
5045 #[simd_test(enable = "avx512f,avx512vl")]
5046 unsafe fn test_mm256_mask_cvtusepi64_epi16() {
5047 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5048 let src = _mm_set1_epi16(0);
5049 let r = _mm256_mask_cvtusepi64_epi16(src, 0, a);
5050 assert_eq_m128i(r, src);
5051 let r = _mm256_mask_cvtusepi64_epi16(src, 0b00001111, a);
5052 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5053 assert_eq_m128i(r, e);
5054 }
5055
5056 #[simd_test(enable = "avx512f,avx512vl")]
5057 unsafe fn test_mm256_maskz_cvtusepi64_epi16() {
5058 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5059 let r = _mm256_maskz_cvtusepi64_epi16(0, a);
5060 assert_eq_m128i(r, _mm_setzero_si128());
5061 let r = _mm256_maskz_cvtusepi64_epi16(0b00001111, a);
5062 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5063 assert_eq_m128i(r, e);
5064 }
5065
5066 #[simd_test(enable = "avx512f,avx512vl")]
5067 unsafe fn test_mm_cvtusepi64_epi16() {
5068 let a = _mm_set_epi64x(6, i64::MAX);
5069 let r = _mm_cvtusepi64_epi16(a);
5070 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5071 assert_eq_m128i(r, e);
5072 }
5073
5074 #[simd_test(enable = "avx512f,avx512vl")]
5075 unsafe fn test_mm_mask_cvtusepi64_epi16() {
5076 let a = _mm_set_epi64x(6, i64::MAX);
5077 let src = _mm_set1_epi16(0);
5078 let r = _mm_mask_cvtusepi64_epi16(src, 0, a);
5079 assert_eq_m128i(r, src);
5080 let r = _mm_mask_cvtusepi64_epi16(src, 0b00000011, a);
5081 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5082 assert_eq_m128i(r, e);
5083 }
5084
5085 #[simd_test(enable = "avx512f,avx512vl")]
5086 unsafe fn test_mm_maskz_cvtusepi64_epi16() {
5087 let a = _mm_set_epi64x(6, i64::MAX);
5088 let r = _mm_maskz_cvtusepi64_epi16(0, a);
5089 assert_eq_m128i(r, _mm_setzero_si128());
5090 let r = _mm_maskz_cvtusepi64_epi16(0b00000011, a);
5091 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5092 assert_eq_m128i(r, e);
5093 }
5094
5095 #[simd_test(enable = "avx512f")]
5096 unsafe fn test_mm512_cvtusepi64_epi8() {
5097 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5098 let r = _mm512_cvtusepi64_epi8(a);
5099 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, -1, -1);
5100 assert_eq_m128i(r, e);
5101 }
5102
5103 #[simd_test(enable = "avx512f")]
5104 unsafe fn test_mm512_mask_cvtusepi64_epi8() {
5105 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5106 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
5107 let r = _mm512_mask_cvtusepi64_epi8(src, 0, a);
5108 assert_eq_m128i(r, src);
5109 let r = _mm512_mask_cvtusepi64_epi8(src, 0b00001111, a);
5110 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 4, 5, -1, -1);
5111 assert_eq_m128i(r, e);
5112 }
5113
5114 #[simd_test(enable = "avx512f")]
5115 unsafe fn test_mm512_maskz_cvtusepi64_epi8() {
5116 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5117 let r = _mm512_maskz_cvtusepi64_epi8(0, a);
5118 assert_eq_m128i(r, _mm_setzero_si128());
5119 let r = _mm512_maskz_cvtusepi64_epi8(0b00001111, a);
5120 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, -1, -1);
5121 assert_eq_m128i(r, e);
5122 }
5123
5124 #[simd_test(enable = "avx512f,avx512vl")]
5125 unsafe fn test_mm256_cvtusepi64_epi8() {
5126 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5127 let r = _mm256_cvtusepi64_epi8(a);
5128 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5129 assert_eq_m128i(r, e);
5130 }
5131
5132 #[simd_test(enable = "avx512f,avx512vl")]
5133 unsafe fn test_mm256_mask_cvtusepi64_epi8() {
5134 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5135 let src = _mm_set1_epi8(0);
5136 let r = _mm256_mask_cvtusepi64_epi8(src, 0, a);
5137 assert_eq_m128i(r, src);
5138 let r = _mm256_mask_cvtusepi64_epi8(src, 0b00001111, a);
5139 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5140 assert_eq_m128i(r, e);
5141 }
5142
5143 #[simd_test(enable = "avx512f,avx512vl")]
5144 unsafe fn test_mm256_maskz_cvtusepi64_epi8() {
5145 let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5146 let r = _mm256_maskz_cvtusepi64_epi8(0, a);
5147 assert_eq_m128i(r, _mm_setzero_si128());
5148 let r = _mm256_maskz_cvtusepi64_epi8(0b00001111, a);
5149 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5150 assert_eq_m128i(r, e);
5151 }
5152
5153 #[simd_test(enable = "avx512f,avx512vl")]
5154 unsafe fn test_mm_cvtusepi64_epi8() {
5155 let a = _mm_set_epi64x(6, i64::MAX);
5156 let r = _mm_cvtusepi64_epi8(a);
5157 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5158 assert_eq_m128i(r, e);
5159 }
5160
5161 #[simd_test(enable = "avx512f,avx512vl")]
5162 unsafe fn test_mm_mask_cvtusepi64_epi8() {
5163 let a = _mm_set_epi64x(6, i64::MAX);
5164 let src = _mm_set1_epi8(0);
5165 let r = _mm_mask_cvtusepi64_epi8(src, 0, a);
5166 assert_eq_m128i(r, src);
5167 let r = _mm_mask_cvtusepi64_epi8(src, 0b00000011, a);
5168 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5169 assert_eq_m128i(r, e);
5170 }
5171
5172 #[simd_test(enable = "avx512f,avx512vl")]
5173 unsafe fn test_mm_maskz_cvtusepi64_epi8() {
5174 let a = _mm_set_epi64x(6, i64::MAX);
5175 let r = _mm_maskz_cvtusepi64_epi8(0, a);
5176 assert_eq_m128i(r, _mm_setzero_si128());
5177 let r = _mm_maskz_cvtusepi64_epi8(0b00000011, a);
5178 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5179 assert_eq_m128i(r, e);
5180 }
5181
5182 #[simd_test(enable = "avx512f")]
5183 unsafe fn test_mm512_cvtt_roundpd_epi32() {
5184 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5185 let r = _mm512_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(a);
5186 let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5187 assert_eq_m256i(r, e);
5188 }
5189
5190 #[simd_test(enable = "avx512f")]
5191 unsafe fn test_mm512_mask_cvtt_roundpd_epi32() {
5192 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5193 let src = _mm256_set1_epi32(0);
5194 let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0, a);
5195 assert_eq_m256i(r, src);
5196 let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5197 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5198 assert_eq_m256i(r, e);
5199 }
5200
5201 #[simd_test(enable = "avx512f")]
5202 unsafe fn test_mm512_maskz_cvtt_roundpd_epi32() {
5203 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5204 let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0, a);
5205 assert_eq_m256i(r, _mm256_setzero_si256());
5206 let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5207 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5208 assert_eq_m256i(r, e);
5209 }
5210
5211 #[simd_test(enable = "avx512f")]
5212 unsafe fn test_mm512_cvtt_roundpd_epu32() {
5213 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5214 let r = _mm512_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(a);
5215 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5216 assert_eq_m256i(r, e);
5217 }
5218
5219 #[simd_test(enable = "avx512f")]
5220 unsafe fn test_mm512_mask_cvtt_roundpd_epu32() {
5221 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5222 let src = _mm256_set1_epi32(0);
5223 let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0, a);
5224 assert_eq_m256i(r, src);
5225 let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5226 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5227 assert_eq_m256i(r, e);
5228 }
5229
5230 #[simd_test(enable = "avx512f")]
5231 unsafe fn test_mm512_maskz_cvtt_roundpd_epu32() {
5232 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5233 let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0, a);
5234 assert_eq_m256i(r, _mm256_setzero_si256());
5235 let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5236 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5237 assert_eq_m256i(r, e);
5238 }
5239
5240 #[simd_test(enable = "avx512f")]
5241 unsafe fn test_mm512_cvttpd_epi32() {
5242 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5243 let r = _mm512_cvttpd_epi32(a);
5244 let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5245 assert_eq_m256i(r, e);
5246 }
5247
5248 #[simd_test(enable = "avx512f")]
5249 unsafe fn test_mm512_mask_cvttpd_epi32() {
5250 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5251 let src = _mm256_set1_epi32(0);
5252 let r = _mm512_mask_cvttpd_epi32(src, 0, a);
5253 assert_eq_m256i(r, src);
5254 let r = _mm512_mask_cvttpd_epi32(src, 0b00001111, a);
5255 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5256 assert_eq_m256i(r, e);
5257 }
5258
5259 #[simd_test(enable = "avx512f")]
5260 unsafe fn test_mm512_maskz_cvttpd_epi32() {
5261 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5262 let r = _mm512_maskz_cvttpd_epi32(0, a);
5263 assert_eq_m256i(r, _mm256_setzero_si256());
5264 let r = _mm512_maskz_cvttpd_epi32(0b00001111, a);
5265 let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5266 assert_eq_m256i(r, e);
5267 }
5268
5269 #[simd_test(enable = "avx512f,avx512vl")]
5270 unsafe fn test_mm256_mask_cvttpd_epi32() {
5271 let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5272 let src = _mm_set1_epi32(0);
5273 let r = _mm256_mask_cvttpd_epi32(src, 0, a);
5274 assert_eq_m128i(r, src);
5275 let r = _mm256_mask_cvttpd_epi32(src, 0b00001111, a);
5276 let e = _mm_setr_epi32(4, -5, 6, -7);
5277 assert_eq_m128i(r, e);
5278 }
5279
5280 #[simd_test(enable = "avx512f,avx512vl")]
5281 unsafe fn test_mm256_maskz_cvttpd_epi32() {
5282 let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5283 let r = _mm256_maskz_cvttpd_epi32(0, a);
5284 assert_eq_m128i(r, _mm_setzero_si128());
5285 let r = _mm256_maskz_cvttpd_epi32(0b00001111, a);
5286 let e = _mm_setr_epi32(4, -5, 6, -7);
5287 assert_eq_m128i(r, e);
5288 }
5289
5290 #[simd_test(enable = "avx512f,avx512vl")]
5291 unsafe fn test_mm_mask_cvttpd_epi32() {
5292 let a = _mm_set_pd(6., -7.5);
5293 let src = _mm_set1_epi32(0);
5294 let r = _mm_mask_cvttpd_epi32(src, 0, a);
5295 assert_eq_m128i(r, src);
5296 let r = _mm_mask_cvttpd_epi32(src, 0b00000011, a);
5297 let e = _mm_set_epi32(0, 0, 6, -7);
5298 assert_eq_m128i(r, e);
5299 }
5300
5301 #[simd_test(enable = "avx512f,avx512vl")]
5302 unsafe fn test_mm_maskz_cvttpd_epi32() {
5303 let a = _mm_set_pd(6., -7.5);
5304 let r = _mm_maskz_cvttpd_epi32(0, a);
5305 assert_eq_m128i(r, _mm_setzero_si128());
5306 let r = _mm_maskz_cvttpd_epi32(0b00000011, a);
5307 let e = _mm_set_epi32(0, 0, 6, -7);
5308 assert_eq_m128i(r, e);
5309 }
5310
5311 #[simd_test(enable = "avx512f")]
5312 unsafe fn test_mm512_cvttpd_epu32() {
5313 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5314 let r = _mm512_cvttpd_epu32(a);
5315 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5316 assert_eq_m256i(r, e);
5317 }
5318
5319 #[simd_test(enable = "avx512f")]
5320 unsafe fn test_mm512_mask_cvttpd_epu32() {
5321 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5322 let src = _mm256_set1_epi32(0);
5323 let r = _mm512_mask_cvttpd_epu32(src, 0, a);
5324 assert_eq_m256i(r, src);
5325 let r = _mm512_mask_cvttpd_epu32(src, 0b00001111, a);
5326 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5327 assert_eq_m256i(r, e);
5328 }
5329
5330 #[simd_test(enable = "avx512f")]
5331 unsafe fn test_mm512_maskz_cvttpd_epu32() {
5332 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5333 let r = _mm512_maskz_cvttpd_epu32(0, a);
5334 assert_eq_m256i(r, _mm256_setzero_si256());
5335 let r = _mm512_maskz_cvttpd_epu32(0b00001111, a);
5336 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5337 assert_eq_m256i(r, e);
5338 }
5339
5340 #[simd_test(enable = "avx512f,avx512vl")]
5341 unsafe fn test_mm256_cvttpd_epu32() {
5342 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5343 let r = _mm256_cvttpd_epu32(a);
5344 let e = _mm_set_epi32(4, 5, 6, 7);
5345 assert_eq_m128i(r, e);
5346 }
5347
5348 #[simd_test(enable = "avx512f,avx512vl")]
5349 unsafe fn test_mm256_mask_cvttpd_epu32() {
5350 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5351 let src = _mm_set1_epi32(0);
5352 let r = _mm256_mask_cvttpd_epu32(src, 0, a);
5353 assert_eq_m128i(r, src);
5354 let r = _mm256_mask_cvttpd_epu32(src, 0b00001111, a);
5355 let e = _mm_set_epi32(4, 5, 6, 7);
5356 assert_eq_m128i(r, e);
5357 }
5358
5359 #[simd_test(enable = "avx512f,avx512vl")]
5360 unsafe fn test_mm256_maskz_cvttpd_epu32() {
5361 let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5362 let r = _mm256_maskz_cvttpd_epu32(0, a);
5363 assert_eq_m128i(r, _mm_setzero_si128());
5364 let r = _mm256_maskz_cvttpd_epu32(0b00001111, a);
5365 let e = _mm_set_epi32(4, 5, 6, 7);
5366 assert_eq_m128i(r, e);
5367 }
5368
5369 #[simd_test(enable = "avx512f,avx512vl")]
5370 unsafe fn test_mm_cvttpd_epu32() {
5371 let a = _mm_set_pd(6., 7.5);
5372 let r = _mm_cvttpd_epu32(a);
5373 let e = _mm_set_epi32(0, 0, 6, 7);
5374 assert_eq_m128i(r, e);
5375 }
5376
5377 #[simd_test(enable = "avx512f,avx512vl")]
5378 unsafe fn test_mm_mask_cvttpd_epu32() {
5379 let a = _mm_set_pd(6., 7.5);
5380 let src = _mm_set1_epi32(0);
5381 let r = _mm_mask_cvttpd_epu32(src, 0, a);
5382 assert_eq_m128i(r, src);
5383 let r = _mm_mask_cvttpd_epu32(src, 0b00000011, a);
5384 let e = _mm_set_epi32(0, 0, 6, 7);
5385 assert_eq_m128i(r, e);
5386 }
5387
5388 #[simd_test(enable = "avx512f,avx512vl")]
5389 unsafe fn test_mm_maskz_cvttpd_epu32() {
5390 let a = _mm_set_pd(6., 7.5);
5391 let r = _mm_maskz_cvttpd_epu32(0, a);
5392 assert_eq_m128i(r, _mm_setzero_si128());
5393 let r = _mm_maskz_cvttpd_epu32(0b00000011, a);
5394 let e = _mm_set_epi32(0, 0, 6, 7);
5395 assert_eq_m128i(r, e);
5396 }
5397
5398 #[simd_test(enable = "avx512f")]
5399 unsafe fn test_mm512_add_round_pd() {
5400 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5401 let b = _mm512_set1_pd(-1.);
5402 let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5403 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5404 assert_eq_m512d(r, e);
5405 let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5406 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5407 assert_eq_m512d(r, e);
5408 }
5409
5410 #[simd_test(enable = "avx512f")]
5411 unsafe fn test_mm512_mask_add_round_pd() {
5412 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5413 let b = _mm512_set1_pd(-1.);
5414 let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5415 a, 0, a, b,
5416 );
5417 assert_eq_m512d(r, a);
5418 let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5419 a, 0b11110000, a, b,
5420 );
5421 let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5422 assert_eq_m512d(r, e);
5423 }
5424
5425 #[simd_test(enable = "avx512f")]
5426 unsafe fn test_mm512_maskz_add_round_pd() {
5427 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5428 let b = _mm512_set1_pd(-1.);
5429 let r =
5430 _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5431 assert_eq_m512d(r, _mm512_setzero_pd());
5432 let r = _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5433 0b11110000, a, b,
5434 );
5435 let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5436 assert_eq_m512d(r, e);
5437 }
5438
5439 #[simd_test(enable = "avx512f")]
5440 unsafe fn test_mm512_sub_round_pd() {
5441 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5442 let b = _mm512_set1_pd(1.);
5443 let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5444 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5445 assert_eq_m512d(r, e);
5446 let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5447 let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5448 assert_eq_m512d(r, e);
5449 }
5450
5451 #[simd_test(enable = "avx512f")]
5452 unsafe fn test_mm512_mask_sub_round_pd() {
5453 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5454 let b = _mm512_set1_pd(1.);
5455 let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5456 a, 0, a, b,
5457 );
5458 assert_eq_m512d(r, a);
5459 let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5460 a, 0b11110000, a, b,
5461 );
5462 let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5463 assert_eq_m512d(r, e);
5464 }
5465
5466 #[simd_test(enable = "avx512f")]
5467 unsafe fn test_mm512_maskz_sub_round_pd() {
5468 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5469 let b = _mm512_set1_pd(1.);
5470 let r =
5471 _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5472 assert_eq_m512d(r, _mm512_setzero_pd());
5473 let r = _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5474 0b11110000, a, b,
5475 );
5476 let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5477 assert_eq_m512d(r, e);
5478 }
5479
5480 #[simd_test(enable = "avx512f")]
5481 unsafe fn test_mm512_mul_round_pd() {
5482 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5483 let b = _mm512_set1_pd(0.1);
5484 let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5485 let e = _mm512_setr_pd(
5486 0.8,
5487 0.9500000000000001,
5488 1.,
5489 1.1500000000000001,
5490 1.2000000000000002,
5491 1.35,
5492 1.4000000000000001,
5493 0.,
5494 );
5495 assert_eq_m512d(r, e);
5496 let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5497 let e = _mm512_setr_pd(0.8, 0.95, 1.0, 1.15, 1.2, 1.3499999999999999, 1.4, 0.0);
5498 assert_eq_m512d(r, e);
5499 }
5500
5501 #[simd_test(enable = "avx512f")]
5502 unsafe fn test_mm512_mask_mul_round_pd() {
5503 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5504 let b = _mm512_set1_pd(0.1);
5505 let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5506 a, 0, a, b,
5507 );
5508 assert_eq_m512d(r, a);
5509 let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5510 a, 0b11110000, a, b,
5511 );
5512 let e = _mm512_setr_pd(
5513 8.,
5514 9.5,
5515 10.,
5516 11.5,
5517 1.2000000000000002,
5518 1.35,
5519 1.4000000000000001,
5520 0.,
5521 );
5522 assert_eq_m512d(r, e);
5523 }
5524
5525 #[simd_test(enable = "avx512f")]
5526 unsafe fn test_mm512_maskz_mul_round_pd() {
5527 let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5528 let b = _mm512_set1_pd(0.1);
5529 let r =
5530 _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5531 assert_eq_m512d(r, _mm512_setzero_pd());
5532 let r = _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5533 0b11110000, a, b,
5534 );
5535 let e = _mm512_setr_pd(
5536 0.,
5537 0.,
5538 0.,
5539 0.,
5540 1.2000000000000002,
5541 1.35,
5542 1.4000000000000001,
5543 0.,
5544 );
5545 assert_eq_m512d(r, e);
5546 }
5547
5548 #[simd_test(enable = "avx512f")]
5549 unsafe fn test_mm512_div_round_pd() {
5550 let a = _mm512_set1_pd(1.);
5551 let b = _mm512_set1_pd(3.);
5552 let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5553 let e = _mm512_set1_pd(0.3333333333333333);
5554 assert_eq_m512d(r, e);
5555 let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5556 let e = _mm512_set1_pd(0.3333333333333333);
5557 assert_eq_m512d(r, e);
5558 }
5559
5560 #[simd_test(enable = "avx512f")]
5561 unsafe fn test_mm512_mask_div_round_pd() {
5562 let a = _mm512_set1_pd(1.);
5563 let b = _mm512_set1_pd(3.);
5564 let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5565 a, 0, a, b,
5566 );
5567 assert_eq_m512d(r, a);
5568 let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5569 a, 0b11110000, a, b,
5570 );
5571 let e = _mm512_setr_pd(
5572 1.,
5573 1.,
5574 1.,
5575 1.,
5576 0.3333333333333333,
5577 0.3333333333333333,
5578 0.3333333333333333,
5579 0.3333333333333333,
5580 );
5581 assert_eq_m512d(r, e);
5582 }
5583
5584 #[simd_test(enable = "avx512f")]
5585 unsafe fn test_mm512_maskz_div_round_pd() {
5586 let a = _mm512_set1_pd(1.);
5587 let b = _mm512_set1_pd(3.);
5588 let r =
5589 _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5590 assert_eq_m512d(r, _mm512_setzero_pd());
5591 let r = _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5592 0b11110000, a, b,
5593 );
5594 let e = _mm512_setr_pd(
5595 0.,
5596 0.,
5597 0.,
5598 0.,
5599 0.3333333333333333,
5600 0.3333333333333333,
5601 0.3333333333333333,
5602 0.3333333333333333,
5603 );
5604 assert_eq_m512d(r, e);
5605 }
5606
5607 #[simd_test(enable = "avx512f")]
5608 unsafe fn test_mm512_sqrt_round_pd() {
5609 let a = _mm512_set1_pd(3.);
5610 let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
5611 let e = _mm512_set1_pd(1.7320508075688772);
5612 assert_eq_m512d(r, e);
5613 let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC }>(a);
5614 let e = _mm512_set1_pd(1.7320508075688774);
5615 assert_eq_m512d(r, e);
5616 }
5617
5618 #[simd_test(enable = "avx512f")]
5619 unsafe fn test_mm512_mask_sqrt_round_pd() {
5620 let a = _mm512_set1_pd(3.);
5621 let r =
5622 _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 0, a);
5623 assert_eq_m512d(r, a);
5624 let r = _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5625 a, 0b11110000, a,
5626 );
5627 let e = _mm512_setr_pd(
5628 3.,
5629 3.,
5630 3.,
5631 3.,
5632 1.7320508075688772,
5633 1.7320508075688772,
5634 1.7320508075688772,
5635 1.7320508075688772,
5636 );
5637 assert_eq_m512d(r, e);
5638 }
5639
5640 #[simd_test(enable = "avx512f")]
5641 unsafe fn test_mm512_maskz_sqrt_round_pd() {
5642 let a = _mm512_set1_pd(3.);
5643 let r =
5644 _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a);
5645 assert_eq_m512d(r, _mm512_setzero_pd());
5646 let r = _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5647 0b11110000, a,
5648 );
5649 let e = _mm512_setr_pd(
5650 0.,
5651 0.,
5652 0.,
5653 0.,
5654 1.7320508075688772,
5655 1.7320508075688772,
5656 1.7320508075688772,
5657 1.7320508075688772,
5658 );
5659 assert_eq_m512d(r, e);
5660 }
5661
5662 #[simd_test(enable = "avx512f")]
5663 unsafe fn test_mm512_fmadd_round_pd() {
5664 let a = _mm512_set1_pd(0.000000000000000007);
5665 let b = _mm512_set1_pd(1.);
5666 let c = _mm512_set1_pd(-1.);
5667 let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5668 let e = _mm512_set1_pd(-1.);
5669 assert_eq_m512d(r, e);
5670 let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5671 let e = _mm512_set1_pd(-0.9999999999999999);
5672 assert_eq_m512d(r, e);
5673 }
5674
5675 #[simd_test(enable = "avx512f")]
5676 unsafe fn test_mm512_mask_fmadd_round_pd() {
5677 let a = _mm512_set1_pd(0.000000000000000007);
5678 let b = _mm512_set1_pd(1.);
5679 let c = _mm512_set1_pd(-1.);
5680 let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5681 a, 0, b, c,
5682 );
5683 assert_eq_m512d(r, a);
5684 let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5685 a, 0b00001111, b, c,
5686 );
5687 let e = _mm512_setr_pd(
5688 -1.,
5689 -1.,
5690 -1.,
5691 -1.,
5692 0.000000000000000007,
5693 0.000000000000000007,
5694 0.000000000000000007,
5695 0.000000000000000007,
5696 );
5697 assert_eq_m512d(r, e);
5698 }
5699
5700 #[simd_test(enable = "avx512f")]
5701 unsafe fn test_mm512_maskz_fmadd_round_pd() {
5702 let a = _mm512_set1_pd(0.000000000000000007);
5703 let b = _mm512_set1_pd(1.);
5704 let c = _mm512_set1_pd(-1.);
5705 let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5706 0, a, b, c,
5707 );
5708 assert_eq_m512d(r, _mm512_setzero_pd());
5709 let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5710 0b00001111, a, b, c,
5711 );
5712 let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5713 assert_eq_m512d(r, e);
5714 }
5715
5716 #[simd_test(enable = "avx512f")]
5717 unsafe fn test_mm512_mask3_fmadd_round_pd() {
5718 let a = _mm512_set1_pd(0.000000000000000007);
5719 let b = _mm512_set1_pd(1.);
5720 let c = _mm512_set1_pd(-1.);
5721 let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5722 a, b, c, 0,
5723 );
5724 assert_eq_m512d(r, c);
5725 let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5726 a, b, c, 0b00001111,
5727 );
5728 let e = _mm512_setr_pd(-1., -1., -1., -1., -1., -1., -1., -1.);
5729 assert_eq_m512d(r, e);
5730 }
5731
5732 #[simd_test(enable = "avx512f")]
5733 unsafe fn test_mm512_fmsub_round_pd() {
5734 let a = _mm512_set1_pd(0.000000000000000007);
5735 let b = _mm512_set1_pd(1.);
5736 let c = _mm512_set1_pd(1.);
5737 let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5738 let e = _mm512_set1_pd(-1.);
5739 assert_eq_m512d(r, e);
5740 let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5741 let e = _mm512_set1_pd(-0.9999999999999999);
5742 assert_eq_m512d(r, e);
5743 }
5744
5745 #[simd_test(enable = "avx512f")]
5746 unsafe fn test_mm512_mask_fmsub_round_pd() {
5747 let a = _mm512_set1_pd(0.000000000000000007);
5748 let b = _mm512_set1_pd(1.);
5749 let c = _mm512_set1_pd(1.);
5750 let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5751 a, 0, b, c,
5752 );
5753 assert_eq_m512d(r, a);
5754 let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5755 a, 0b00001111, b, c,
5756 );
5757 let e = _mm512_setr_pd(
5758 -1.,
5759 -1.,
5760 -1.,
5761 -1.,
5762 0.000000000000000007,
5763 0.000000000000000007,
5764 0.000000000000000007,
5765 0.000000000000000007,
5766 );
5767 assert_eq_m512d(r, e);
5768 }
5769
5770 #[simd_test(enable = "avx512f")]
5771 unsafe fn test_mm512_maskz_fmsub_round_pd() {
5772 let a = _mm512_set1_pd(0.000000000000000007);
5773 let b = _mm512_set1_pd(1.);
5774 let c = _mm512_set1_pd(1.);
5775 let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5776 0, a, b, c,
5777 );
5778 assert_eq_m512d(r, _mm512_setzero_pd());
5779 let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5780 0b00001111, a, b, c,
5781 );
5782 let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5783 assert_eq_m512d(r, e);
5784 }
5785
5786 #[simd_test(enable = "avx512f")]
5787 unsafe fn test_mm512_mask3_fmsub_round_pd() {
5788 let a = _mm512_set1_pd(0.000000000000000007);
5789 let b = _mm512_set1_pd(1.);
5790 let c = _mm512_set1_pd(1.);
5791 let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5792 a, b, c, 0,
5793 );
5794 assert_eq_m512d(r, c);
5795 let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5796 a, b, c, 0b00001111,
5797 );
5798 let e = _mm512_setr_pd(-1., -1., -1., -1., 1., 1., 1., 1.);
5799 assert_eq_m512d(r, e);
5800 }
5801
5802 #[simd_test(enable = "avx512f")]
5803 unsafe fn test_mm512_fmaddsub_round_pd() {
5804 let a = _mm512_set1_pd(0.000000000000000007);
5805 let b = _mm512_set1_pd(1.);
5806 let c = _mm512_set1_pd(-1.);
5807 let r =
5808 _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5809 let e = _mm512_setr_pd(1., -1., 1., -1., 1., -1., 1., -1.);
5810 assert_eq_m512d(r, e);
5811 let r = _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5812 let e = _mm512_setr_pd(
5813 1.,
5814 -0.9999999999999999,
5815 1.,
5816 -0.9999999999999999,
5817 1.,
5818 -0.9999999999999999,
5819 1.,
5820 -0.9999999999999999,
5821 );
5822 assert_eq_m512d(r, e);
5823 }
5824
5825 #[simd_test(enable = "avx512f")]
5826 unsafe fn test_mm512_mask_fmaddsub_round_pd() {
5827 let a = _mm512_set1_pd(0.000000000000000007);
5828 let b = _mm512_set1_pd(1.);
5829 let c = _mm512_set1_pd(-1.);
5830 let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5831 a, 0, b, c,
5832 );
5833 assert_eq_m512d(r, a);
5834 let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5835 a, 0b00001111, b, c,
5836 );
5837 let e = _mm512_setr_pd(
5838 1.,
5839 -1.,
5840 1.,
5841 -1.,
5842 0.000000000000000007,
5843 0.000000000000000007,
5844 0.000000000000000007,
5845 0.000000000000000007,
5846 );
5847 assert_eq_m512d(r, e);
5848 }
5849
5850 #[simd_test(enable = "avx512f")]
5851 unsafe fn test_mm512_maskz_fmaddsub_round_pd() {
5852 let a = _mm512_set1_pd(0.000000000000000007);
5853 let b = _mm512_set1_pd(1.);
5854 let c = _mm512_set1_pd(-1.);
5855 let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5856 0, a, b, c,
5857 );
5858 assert_eq_m512d(r, _mm512_setzero_pd());
5859 let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5860 0b00001111, a, b, c,
5861 );
5862 let e = _mm512_setr_pd(1., -1., 1., -1., 0., 0., 0., 0.);
5863 assert_eq_m512d(r, e);
5864 }
5865
5866 #[simd_test(enable = "avx512f")]
5867 unsafe fn test_mm512_mask3_fmaddsub_round_pd() {
5868 let a = _mm512_set1_pd(0.000000000000000007);
5869 let b = _mm512_set1_pd(1.);
5870 let c = _mm512_set1_pd(-1.);
5871 let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5872 a, b, c, 0,
5873 );
5874 assert_eq_m512d(r, c);
5875 let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5876 a, b, c, 0b00001111,
5877 );
5878 let e = _mm512_setr_pd(1., -1., 1., -1., -1., -1., -1., -1.);
5879 assert_eq_m512d(r, e);
5880 }
5881
5882 #[simd_test(enable = "avx512f")]
5883 unsafe fn test_mm512_fmsubadd_round_pd() {
5884 let a = _mm512_set1_pd(0.000000000000000007);
5885 let b = _mm512_set1_pd(1.);
5886 let c = _mm512_set1_pd(-1.);
5887 let r =
5888 _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5889 let e = _mm512_setr_pd(-1., 1., -1., 1., -1., 1., -1., 1.);
5890 assert_eq_m512d(r, e);
5891 let r = _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5892 let e = _mm512_setr_pd(
5893 -0.9999999999999999,
5894 1.,
5895 -0.9999999999999999,
5896 1.,
5897 -0.9999999999999999,
5898 1.,
5899 -0.9999999999999999,
5900 1.,
5901 );
5902 assert_eq_m512d(r, e);
5903 }
5904
5905 #[simd_test(enable = "avx512f")]
5906 unsafe fn test_mm512_mask_fmsubadd_round_pd() {
5907 let a = _mm512_set1_pd(0.000000000000000007);
5908 let b = _mm512_set1_pd(1.);
5909 let c = _mm512_set1_pd(-1.);
5910 let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5911 a, 0, b, c,
5912 );
5913 assert_eq_m512d(r, a);
5914 let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5915 a, 0b00001111, b, c,
5916 );
5917 let e = _mm512_setr_pd(
5918 -1.,
5919 1.,
5920 -1.,
5921 1.,
5922 0.000000000000000007,
5923 0.000000000000000007,
5924 0.000000000000000007,
5925 0.000000000000000007,
5926 );
5927 assert_eq_m512d(r, e);
5928 }
5929
5930 #[simd_test(enable = "avx512f")]
5931 unsafe fn test_mm512_maskz_fmsubadd_round_pd() {
5932 let a = _mm512_set1_pd(0.000000000000000007);
5933 let b = _mm512_set1_pd(1.);
5934 let c = _mm512_set1_pd(-1.);
5935 let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5936 0, a, b, c,
5937 );
5938 assert_eq_m512d(r, _mm512_setzero_pd());
5939 let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5940 0b00001111, a, b, c,
5941 );
5942 let e = _mm512_setr_pd(-1., 1., -1., 1., 0., 0., 0., 0.);
5943 assert_eq_m512d(r, e);
5944 }
5945
5946 #[simd_test(enable = "avx512f")]
5947 unsafe fn test_mm512_mask3_fmsubadd_round_pd() {
5948 let a = _mm512_set1_pd(0.000000000000000007);
5949 let b = _mm512_set1_pd(1.);
5950 let c = _mm512_set1_pd(-1.);
5951 let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5952 a, b, c, 0,
5953 );
5954 assert_eq_m512d(r, c);
5955 let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5956 a, b, c, 0b00001111,
5957 );
5958 let e = _mm512_setr_pd(-1., 1., -1., 1., -1., -1., -1., -1.);
5959 assert_eq_m512d(r, e);
5960 }
5961
5962 #[simd_test(enable = "avx512f")]
5963 unsafe fn test_mm512_fnmadd_round_pd() {
5964 let a = _mm512_set1_pd(0.000000000000000007);
5965 let b = _mm512_set1_pd(1.);
5966 let c = _mm512_set1_pd(1.);
5967 let r =
5968 _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5969 let e = _mm512_set1_pd(1.);
5970 assert_eq_m512d(r, e);
5971 let r = _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5972 let e = _mm512_set1_pd(0.9999999999999999);
5973 assert_eq_m512d(r, e);
5974 }
5975
5976 #[simd_test(enable = "avx512f")]
5977 unsafe fn test_mm512_mask_fnmadd_round_pd() {
5978 let a = _mm512_set1_pd(0.000000000000000007);
5979 let b = _mm512_set1_pd(1.);
5980 let c = _mm512_set1_pd(1.);
5981 let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5982 a, 0, b, c,
5983 );
5984 assert_eq_m512d(r, a);
5985 let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5986 a, 0b00001111, b, c,
5987 );
5988 let e = _mm512_setr_pd(
5989 1.,
5990 1.,
5991 1.,
5992 1.,
5993 0.000000000000000007,
5994 0.000000000000000007,
5995 0.000000000000000007,
5996 0.000000000000000007,
5997 );
5998 assert_eq_m512d(r, e);
5999 }
6000
6001 #[simd_test(enable = "avx512f")]
6002 unsafe fn test_mm512_maskz_fnmadd_round_pd() {
6003 let a = _mm512_set1_pd(0.000000000000000007);
6004 let b = _mm512_set1_pd(1.);
6005 let c = _mm512_set1_pd(1.);
6006 let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6007 0, a, b, c,
6008 );
6009 assert_eq_m512d(r, _mm512_setzero_pd());
6010 let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6011 0b00001111, a, b, c,
6012 );
6013 let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
6014 assert_eq_m512d(r, e);
6015 }
6016
6017 #[simd_test(enable = "avx512f")]
6018 unsafe fn test_mm512_mask3_fnmadd_round_pd() {
6019 let a = _mm512_set1_pd(0.000000000000000007);
6020 let b = _mm512_set1_pd(1.);
6021 let c = _mm512_set1_pd(1.);
6022 let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6023 a, b, c, 0,
6024 );
6025 assert_eq_m512d(r, c);
6026 let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6027 a, b, c, 0b00001111,
6028 );
6029 let e = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
6030 assert_eq_m512d(r, e);
6031 }
6032
6033 #[simd_test(enable = "avx512f")]
6034 unsafe fn test_mm512_fnmsub_round_pd() {
6035 let a = _mm512_set1_pd(0.000000000000000007);
6036 let b = _mm512_set1_pd(1.);
6037 let c = _mm512_set1_pd(-1.);
6038 let r =
6039 _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
6040 let e = _mm512_set1_pd(1.);
6041 assert_eq_m512d(r, e);
6042 let r = _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
6043 let e = _mm512_set1_pd(0.9999999999999999);
6044 assert_eq_m512d(r, e);
6045 }
6046
6047 #[simd_test(enable = "avx512f")]
6048 unsafe fn test_mm512_mask_fnmsub_round_pd() {
6049 let a = _mm512_set1_pd(0.000000000000000007);
6050 let b = _mm512_set1_pd(1.);
6051 let c = _mm512_set1_pd(-1.);
6052 let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6053 a, 0, b, c,
6054 );
6055 assert_eq_m512d(r, a);
6056 let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6057 a, 0b00001111, b, c,
6058 );
6059 let e = _mm512_setr_pd(
6060 1.,
6061 1.,
6062 1.,
6063 1.,
6064 0.000000000000000007,
6065 0.000000000000000007,
6066 0.000000000000000007,
6067 0.000000000000000007,
6068 );
6069 assert_eq_m512d(r, e);
6070 }
6071
6072 #[simd_test(enable = "avx512f")]
6073 unsafe fn test_mm512_maskz_fnmsub_round_pd() {
6074 let a = _mm512_set1_pd(0.000000000000000007);
6075 let b = _mm512_set1_pd(1.);
6076 let c = _mm512_set1_pd(-1.);
6077 let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6078 0, a, b, c,
6079 );
6080 assert_eq_m512d(r, _mm512_setzero_pd());
6081 let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6082 0b00001111, a, b, c,
6083 );
6084 let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
6085 assert_eq_m512d(r, e);
6086 }
6087
6088 #[simd_test(enable = "avx512f")]
6089 unsafe fn test_mm512_mask3_fnmsub_round_pd() {
6090 let a = _mm512_set1_pd(0.000000000000000007);
6091 let b = _mm512_set1_pd(1.);
6092 let c = _mm512_set1_pd(-1.);
6093 let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6094 a, b, c, 0,
6095 );
6096 assert_eq_m512d(r, c);
6097 let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6098 a, b, c, 0b00001111,
6099 );
6100 let e = _mm512_setr_pd(1., 1., 1., 1., -1., -1., -1., -1.);
6101 assert_eq_m512d(r, e);
6102 }
6103
6104 #[simd_test(enable = "avx512f")]
6105 unsafe fn test_mm512_max_round_pd() {
6106 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6107 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6108 let r = _mm512_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6109 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6110 assert_eq_m512d(r, e);
6111 }
6112
6113 #[simd_test(enable = "avx512f")]
6114 unsafe fn test_mm512_mask_max_round_pd() {
6115 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6116 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6117 let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6118 assert_eq_m512d(r, a);
6119 let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6120 let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6121 assert_eq_m512d(r, e);
6122 }
6123
6124 #[simd_test(enable = "avx512f")]
6125 unsafe fn test_mm512_maskz_max_round_pd() {
6126 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6127 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6128 let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6129 assert_eq_m512d(r, _mm512_setzero_pd());
6130 let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6131 let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
6132 assert_eq_m512d(r, e);
6133 }
6134
6135 #[simd_test(enable = "avx512f")]
6136 unsafe fn test_mm512_min_round_pd() {
6137 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6138 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6139 let r = _mm512_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6140 let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
6141 assert_eq_m512d(r, e);
6142 }
6143
6144 #[simd_test(enable = "avx512f")]
6145 unsafe fn test_mm512_mask_min_round_pd() {
6146 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6147 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6148 let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6149 assert_eq_m512d(r, a);
6150 let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6151 let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6152 assert_eq_m512d(r, e);
6153 }
6154
6155 #[simd_test(enable = "avx512f")]
6156 unsafe fn test_mm512_maskz_min_round_pd() {
6157 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6158 let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6159 let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6160 assert_eq_m512d(r, _mm512_setzero_pd());
6161 let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6162 let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
6163 assert_eq_m512d(r, e);
6164 }
6165
6166 #[simd_test(enable = "avx512f")]
6167 unsafe fn test_mm512_getexp_round_pd() {
6168 let a = _mm512_set1_pd(3.);
6169 let r = _mm512_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6170 let e = _mm512_set1_pd(1.);
6171 assert_eq_m512d(r, e);
6172 }
6173
6174 #[simd_test(enable = "avx512f")]
6175 unsafe fn test_mm512_mask_getexp_round_pd() {
6176 let a = _mm512_set1_pd(3.);
6177 let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a);
6178 assert_eq_m512d(r, a);
6179 let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b11110000, a);
6180 let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
6181 assert_eq_m512d(r, e);
6182 }
6183
6184 #[simd_test(enable = "avx512f")]
6185 unsafe fn test_mm512_maskz_getexp_round_pd() {
6186 let a = _mm512_set1_pd(3.);
6187 let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6188 assert_eq_m512d(r, _mm512_setzero_pd());
6189 let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b11110000, a);
6190 let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6191 assert_eq_m512d(r, e);
6192 }
6193
6194 #[simd_test(enable = "avx512f")]
6195 unsafe fn test_mm512_roundscale_round_pd() {
6196 let a = _mm512_set1_pd(1.1);
6197 let r = _mm512_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a);
6198 let e = _mm512_set1_pd(1.0);
6199 assert_eq_m512d(r, e);
6200 }
6201
6202 #[simd_test(enable = "avx512f")]
6203 unsafe fn test_mm512_mask_roundscale_round_pd() {
6204 let a = _mm512_set1_pd(1.1);
6205 let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a);
6206 let e = _mm512_set1_pd(1.1);
6207 assert_eq_m512d(r, e);
6208 let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, a);
6209 let e = _mm512_set1_pd(1.0);
6210 assert_eq_m512d(r, e);
6211 }
6212
6213 #[simd_test(enable = "avx512f")]
6214 unsafe fn test_mm512_maskz_roundscale_round_pd() {
6215 let a = _mm512_set1_pd(1.1);
6216 let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0, a);
6217 assert_eq_m512d(r, _mm512_setzero_pd());
6218 let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111, a);
6219 let e = _mm512_set1_pd(1.0);
6220 assert_eq_m512d(r, e);
6221 }
6222
6223 #[simd_test(enable = "avx512f")]
6224 unsafe fn test_mm512_scalef_round_pd() {
6225 let a = _mm512_set1_pd(1.);
6226 let b = _mm512_set1_pd(3.);
6227 let r = _mm512_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
6228 let e = _mm512_set1_pd(8.);
6229 assert_eq_m512d(r, e);
6230 }
6231
6232 #[simd_test(enable = "avx512f")]
6233 unsafe fn test_mm512_mask_scalef_round_pd() {
6234 let a = _mm512_set1_pd(1.);
6235 let b = _mm512_set1_pd(3.);
6236 let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6237 a, 0, a, b,
6238 );
6239 assert_eq_m512d(r, a);
6240 let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6241 a, 0b11110000, a, b,
6242 );
6243 let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
6244 assert_eq_m512d(r, e);
6245 }
6246
6247 #[simd_test(enable = "avx512f")]
6248 unsafe fn test_mm512_maskz_scalef_round_pd() {
6249 let a = _mm512_set1_pd(1.);
6250 let b = _mm512_set1_pd(3.);
6251 let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6252 0, a, b,
6253 );
6254 assert_eq_m512d(r, _mm512_setzero_pd());
6255 let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6256 0b11110000, a, b,
6257 );
6258 let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
6259 assert_eq_m512d(r, e);
6260 }
6261
6262 #[simd_test(enable = "avx512f")]
6263 unsafe fn test_mm512_fixupimm_round_pd() {
6264 let a = _mm512_set1_pd(f64::NAN);
6265 let b = _mm512_set1_pd(f64::MAX);
6266 let c = _mm512_set1_epi64(i32::MAX as i64);
6267 let r = _mm512_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c);
6268 let e = _mm512_set1_pd(0.0);
6269 assert_eq_m512d(r, e);
6270 }
6271
6272 #[simd_test(enable = "avx512f")]
6273 unsafe fn test_mm512_mask_fixupimm_round_pd() {
6274 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6275 let b = _mm512_set1_pd(f64::MAX);
6276 let c = _mm512_set1_epi64(i32::MAX as i64);
6277 let r = _mm512_mask_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11110000, b, c);
6278 let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6279 assert_eq_m512d(r, e);
6280 }
6281
6282 #[simd_test(enable = "avx512f")]
6283 unsafe fn test_mm512_maskz_fixupimm_round_pd() {
6284 let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6285 let b = _mm512_set1_pd(f64::MAX);
6286 let c = _mm512_set1_epi64(i32::MAX as i64);
6287 let r = _mm512_maskz_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(0b11110000, a, b, c);
6288 let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
6289 assert_eq_m512d(r, e);
6290 }
6291
6292 #[simd_test(enable = "avx512f")]
6293 unsafe fn test_mm512_getmant_round_pd() {
6294 let a = _mm512_set1_pd(10.);
6295 let r = _mm512_getmant_round_pd::<
6296 _MM_MANT_NORM_1_2,
6297 _MM_MANT_SIGN_SRC,
6298 _MM_FROUND_CUR_DIRECTION,
6299 >(a);
6300 let e = _mm512_set1_pd(1.25);
6301 assert_eq_m512d(r, e);
6302 }
6303
6304 #[simd_test(enable = "avx512f")]
6305 unsafe fn test_mm512_mask_getmant_round_pd() {
6306 let a = _mm512_set1_pd(10.);
6307 let r = _mm512_mask_getmant_round_pd::<
6308 _MM_MANT_NORM_1_2,
6309 _MM_MANT_SIGN_SRC,
6310 _MM_FROUND_CUR_DIRECTION,
6311 >(a, 0, a);
6312 assert_eq_m512d(r, a);
6313 let r = _mm512_mask_getmant_round_pd::<
6314 _MM_MANT_NORM_1_2,
6315 _MM_MANT_SIGN_SRC,
6316 _MM_FROUND_CUR_DIRECTION,
6317 >(a, 0b11110000, a);
6318 let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
6319 assert_eq_m512d(r, e);
6320 }
6321
6322 #[simd_test(enable = "avx512f")]
6323 unsafe fn test_mm512_maskz_getmant_round_pd() {
6324 let a = _mm512_set1_pd(10.);
6325 let r = _mm512_maskz_getmant_round_pd::<
6326 _MM_MANT_NORM_1_2,
6327 _MM_MANT_SIGN_SRC,
6328 _MM_FROUND_CUR_DIRECTION,
6329 >(0, a);
6330 assert_eq_m512d(r, _mm512_setzero_pd());
6331 let r = _mm512_maskz_getmant_round_pd::<
6332 _MM_MANT_NORM_1_2,
6333 _MM_MANT_SIGN_SRC,
6334 _MM_FROUND_CUR_DIRECTION,
6335 >(0b11110000, a);
6336 let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
6337 assert_eq_m512d(r, e);
6338 }
6339
6340 #[simd_test(enable = "avx512f")]
6341 unsafe fn test_mm512_cvt_roundps_pd() {
6342 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6343 let r = _mm512_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6344 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6345 assert_eq_m512d(r, e);
6346 }
6347
6348 #[simd_test(enable = "avx512f")]
6349 unsafe fn test_mm512_mask_cvt_roundps_pd() {
6350 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6351 let src = _mm512_set1_pd(0.);
6352 let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6353 assert_eq_m512d(r, src);
6354 let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6355 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6356 assert_eq_m512d(r, e);
6357 }
6358
6359 #[simd_test(enable = "avx512f")]
6360 unsafe fn test_mm512_maskz_cvt_roundps_pd() {
6361 let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6362 let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6363 assert_eq_m512d(r, _mm512_setzero_pd());
6364 let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6365 let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6366 assert_eq_m512d(r, e);
6367 }
6368
6369 #[simd_test(enable = "avx512f")]
6370 unsafe fn test_mm512_cvt_roundpd_ps() {
6371 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6372 let r = _mm512_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(a);
6373 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6374 assert_eq_m256(r, e);
6375 }
6376
6377 #[simd_test(enable = "avx512f")]
6378 unsafe fn test_mm512_mask_cvt_roundpd_ps() {
6379 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6380 let src = _mm256_set1_ps(0.);
6381 let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6382 assert_eq_m256(r, src);
6383 let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6384 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6385 assert_eq_m256(r, e);
6386 }
6387
6388 #[simd_test(enable = "avx512f")]
6389 unsafe fn test_mm512_maskz_cvt_roundpd_ps() {
6390 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6391 let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0, a);
6392 assert_eq_m256(r, _mm256_setzero_ps());
6393 let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6394 let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6395 assert_eq_m256(r, e);
6396 }
6397
6398 #[simd_test(enable = "avx512f")]
6399 unsafe fn test_mm512_cvt_roundpd_epi32() {
6400 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6401 let r = _mm512_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(a);
6402 let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
6403 assert_eq_m256i(r, e);
6404 }
6405
6406 #[simd_test(enable = "avx512f")]
6407 unsafe fn test_mm512_mask_cvt_roundpd_epi32() {
6408 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6409 let src = _mm256_set1_epi32(0);
6410 let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6411 assert_eq_m256i(r, src);
6412 let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6413 let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6414 assert_eq_m256i(r, e);
6415 }
6416
6417 #[simd_test(enable = "avx512f")]
6418 unsafe fn test_mm512_maskz_cvt_roundpd_epi32() {
6419 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6420 let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6421 assert_eq_m256i(r, _mm256_setzero_si256());
6422 let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6423 let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6424 assert_eq_m256i(r, e);
6425 }
6426
6427 #[simd_test(enable = "avx512f")]
6428 unsafe fn test_mm512_cvt_roundpd_epu32() {
6429 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6430 let r = _mm512_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(a);
6431 let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
6432 assert_eq_m256i(r, e);
6433 }
6434
6435 #[simd_test(enable = "avx512f")]
6436 unsafe fn test_mm512_mask_cvt_roundpd_epu32() {
6437 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6438 let src = _mm256_set1_epi32(0);
6439 let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6440 assert_eq_m256i(r, src);
6441 let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6442 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6443 assert_eq_m256i(r, e);
6444 }
6445
6446 #[simd_test(enable = "avx512f")]
6447 unsafe fn test_mm512_maskz_cvt_roundpd_epu32() {
6448 let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6449 let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6450 assert_eq_m256i(r, _mm256_setzero_si256());
6451 let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6452 let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6453 assert_eq_m256i(r, e);
6454 }
6455
6456 #[simd_test(enable = "avx512f")]
6457 const unsafe fn test_mm512_setzero_pd() {
6458 assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
6459 }
6460
6461 #[simd_test(enable = "avx512f")]
6462 const unsafe fn test_mm512_set1_epi64() {
6463 let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
6464 assert_eq_m512i(r, _mm512_set1_epi64(2));
6465 }
6466
6467 #[simd_test(enable = "avx512f")]
6468 const unsafe fn test_mm512_set1_pd() {
6469 let expected = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
6470 assert_eq_m512d(expected, _mm512_set1_pd(2.));
6471 }
6472
6473 #[simd_test(enable = "avx512f")]
6474 const unsafe fn test_mm512_set4_epi64() {
6475 let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6476 assert_eq_m512i(r, _mm512_set4_epi64(4, 3, 2, 1));
6477 }
6478
6479 #[simd_test(enable = "avx512f")]
6480 const unsafe fn test_mm512_set4_pd() {
6481 let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6482 assert_eq_m512d(r, _mm512_set4_pd(4., 3., 2., 1.));
6483 }
6484
6485 #[simd_test(enable = "avx512f")]
6486 const unsafe fn test_mm512_setr4_epi64() {
6487 let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6488 assert_eq_m512i(r, _mm512_setr4_epi64(1, 2, 3, 4));
6489 }
6490
6491 #[simd_test(enable = "avx512f")]
6492 const unsafe fn test_mm512_setr4_pd() {
6493 let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6494 assert_eq_m512d(r, _mm512_setr4_pd(1., 2., 3., 4.));
6495 }
6496
6497 #[simd_test(enable = "avx512f")]
6498 unsafe fn test_mm512_cmplt_pd_mask() {
6499 #[rustfmt::skip]
6500 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6501 let b = _mm512_set1_pd(-1.);
6502 let m = _mm512_cmplt_pd_mask(a, b);
6503 assert_eq!(m, 0b00000101);
6504 }
6505
6506 #[simd_test(enable = "avx512f")]
6507 unsafe fn test_mm512_mask_cmplt_pd_mask() {
6508 #[rustfmt::skip]
6509 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6510 let b = _mm512_set1_pd(-1.);
6511 let mask = 0b01100110;
6512 let r = _mm512_mask_cmplt_pd_mask(mask, a, b);
6513 assert_eq!(r, 0b00000100);
6514 }
6515
6516 #[simd_test(enable = "avx512f")]
6517 unsafe fn test_mm512_cmpnlt_pd_mask() {
6518 #[rustfmt::skip]
6519 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6520 let b = _mm512_set1_pd(-1.);
6521 assert_eq!(_mm512_cmpnlt_pd_mask(a, b), !_mm512_cmplt_pd_mask(a, b));
6522 }
6523
6524 #[simd_test(enable = "avx512f")]
6525 unsafe fn test_mm512_mask_cmpnlt_pd_mask() {
6526 #[rustfmt::skip]
6527 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6528 let b = _mm512_set1_pd(-1.);
6529 let mask = 0b01111010;
6530 assert_eq!(_mm512_mask_cmpnlt_pd_mask(mask, a, b), 0b01111010);
6531 }
6532
6533 #[simd_test(enable = "avx512f")]
6534 unsafe fn test_mm512_cmple_pd_mask() {
6535 #[rustfmt::skip]
6536 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6537 let b = _mm512_set1_pd(-1.);
6538 assert_eq!(_mm512_cmple_pd_mask(a, b), 0b00100101);
6539 }
6540
6541 #[simd_test(enable = "avx512f")]
6542 unsafe fn test_mm512_mask_cmple_pd_mask() {
6543 #[rustfmt::skip]
6544 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6545 let b = _mm512_set1_pd(-1.);
6546 let mask = 0b01111010;
6547 assert_eq!(_mm512_mask_cmple_pd_mask(mask, a, b), 0b00100000);
6548 }
6549
6550 #[simd_test(enable = "avx512f")]
6551 unsafe fn test_mm512_cmpnle_pd_mask() {
6552 #[rustfmt::skip]
6553 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6554 let b = _mm512_set1_pd(-1.);
6555 let m = _mm512_cmpnle_pd_mask(b, a);
6556 assert_eq!(m, 0b00001101);
6557 }
6558
6559 #[simd_test(enable = "avx512f")]
6560 unsafe fn test_mm512_mask_cmpnle_pd_mask() {
6561 #[rustfmt::skip]
6562 let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6563 let b = _mm512_set1_pd(-1.);
6564 let mask = 0b01100110;
6565 let r = _mm512_mask_cmpnle_pd_mask(mask, b, a);
6566 assert_eq!(r, 0b00000100);
6567 }
6568
6569 #[simd_test(enable = "avx512f")]
6570 unsafe fn test_mm512_cmpeq_pd_mask() {
6571 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6572 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6573 let m = _mm512_cmpeq_pd_mask(b, a);
6574 assert_eq!(m, 0b11001101);
6575 }
6576
6577 #[simd_test(enable = "avx512f")]
6578 unsafe fn test_mm512_mask_cmpeq_pd_mask() {
6579 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6580 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6581 let mask = 0b01111010;
6582 let r = _mm512_mask_cmpeq_pd_mask(mask, b, a);
6583 assert_eq!(r, 0b01001000);
6584 }
6585
6586 #[simd_test(enable = "avx512f")]
6587 unsafe fn test_mm512_cmpneq_pd_mask() {
6588 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6589 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6590 let m = _mm512_cmpneq_pd_mask(b, a);
6591 assert_eq!(m, 0b00110010);
6592 }
6593
6594 #[simd_test(enable = "avx512f")]
6595 unsafe fn test_mm512_mask_cmpneq_pd_mask() {
6596 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6597 let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6598 let mask = 0b01111010;
6599 let r = _mm512_mask_cmpneq_pd_mask(mask, b, a);
6600 assert_eq!(r, 0b00110010)
6601 }
6602
6603 #[simd_test(enable = "avx512f")]
6604 unsafe fn test_mm512_cmp_pd_mask() {
6605 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6606 let b = _mm512_set1_pd(-1.);
6607 let m = _mm512_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6608 assert_eq!(m, 0b00000101);
6609 }
6610
6611 #[simd_test(enable = "avx512f")]
6612 unsafe fn test_mm512_mask_cmp_pd_mask() {
6613 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6614 let b = _mm512_set1_pd(-1.);
6615 let mask = 0b01100110;
6616 let r = _mm512_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6617 assert_eq!(r, 0b00000100);
6618 }
6619
6620 #[simd_test(enable = "avx512f,avx512vl")]
6621 unsafe fn test_mm256_cmp_pd_mask() {
6622 let a = _mm256_set_pd(0., 1., -1., 13.);
6623 let b = _mm256_set1_pd(1.);
6624 let m = _mm256_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6625 assert_eq!(m, 0b00001010);
6626 }
6627
6628 #[simd_test(enable = "avx512f,avx512vl")]
6629 unsafe fn test_mm256_mask_cmp_pd_mask() {
6630 let a = _mm256_set_pd(0., 1., -1., 13.);
6631 let b = _mm256_set1_pd(1.);
6632 let mask = 0b11111111;
6633 let r = _mm256_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6634 assert_eq!(r, 0b00001010);
6635 }
6636
6637 #[simd_test(enable = "avx512f,avx512vl")]
6638 unsafe fn test_mm_cmp_pd_mask() {
6639 let a = _mm_set_pd(0., 1.);
6640 let b = _mm_set1_pd(1.);
6641 let m = _mm_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6642 assert_eq!(m, 0b00000010);
6643 }
6644
6645 #[simd_test(enable = "avx512f,avx512vl")]
6646 unsafe fn test_mm_mask_cmp_pd_mask() {
6647 let a = _mm_set_pd(0., 1.);
6648 let b = _mm_set1_pd(1.);
6649 let mask = 0b11111111;
6650 let r = _mm_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6651 assert_eq!(r, 0b00000010);
6652 }
6653
6654 #[simd_test(enable = "avx512f")]
6655 unsafe fn test_mm512_cmp_round_pd_mask() {
6656 #[rustfmt::skip]
6657 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6658 let b = _mm512_set1_pd(-1.);
6659 let m = _mm512_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(a, b);
6660 assert_eq!(m, 0b00000101);
6661 }
6662
6663 #[simd_test(enable = "avx512f")]
6664 unsafe fn test_mm512_mask_cmp_round_pd_mask() {
6665 #[rustfmt::skip]
6666 let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6667 let b = _mm512_set1_pd(-1.);
6668 let mask = 0b01100110;
6669 let r = _mm512_mask_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(mask, a, b);
6670 assert_eq!(r, 0b00000100);
6671 }
6672
6673 #[simd_test(enable = "avx512f")]
6674 unsafe fn test_mm512_cmpord_pd_mask() {
6675 #[rustfmt::skip]
6676 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6677 #[rustfmt::skip]
6678 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6679 let m = _mm512_cmpord_pd_mask(a, b);
6680 assert_eq!(m, 0b00000101);
6681 }
6682
6683 #[simd_test(enable = "avx512f")]
6684 unsafe fn test_mm512_mask_cmpord_pd_mask() {
6685 #[rustfmt::skip]
6686 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6687 #[rustfmt::skip]
6688 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6689 let mask = 0b11000011;
6690 let m = _mm512_mask_cmpord_pd_mask(mask, a, b);
6691 assert_eq!(m, 0b00000001);
6692 }
6693
6694 #[simd_test(enable = "avx512f")]
6695 unsafe fn test_mm512_cmpunord_pd_mask() {
6696 #[rustfmt::skip]
6697 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6698 #[rustfmt::skip]
6699 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6700 let m = _mm512_cmpunord_pd_mask(a, b);
6701
6702 assert_eq!(m, 0b11111010);
6703 }
6704
6705 #[simd_test(enable = "avx512f")]
6706 unsafe fn test_mm512_mask_cmpunord_pd_mask() {
6707 #[rustfmt::skip]
6708 let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6709 #[rustfmt::skip]
6710 let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6711 let mask = 0b00001111;
6712 let m = _mm512_mask_cmpunord_pd_mask(mask, a, b);
6713 assert_eq!(m, 0b000001010);
6714 }
6715
6716 #[simd_test(enable = "avx512f")]
6717 const unsafe fn test_mm512_cmplt_epu64_mask() {
6718 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6719 let b = _mm512_set1_epi64(-1);
6720 let m = _mm512_cmplt_epu64_mask(a, b);
6721 assert_eq!(m, 0b11001111);
6722 }
6723
6724 #[simd_test(enable = "avx512f")]
6725 const unsafe fn test_mm512_mask_cmplt_epu64_mask() {
6726 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6727 let b = _mm512_set1_epi64(-1);
6728 let mask = 0b01111010;
6729 let r = _mm512_mask_cmplt_epu64_mask(mask, a, b);
6730 assert_eq!(r, 0b01001010);
6731 }
6732
6733 #[simd_test(enable = "avx512f,avx512vl")]
6734 const unsafe fn test_mm256_cmplt_epu64_mask() {
6735 let a = _mm256_set_epi64x(0, 1, 2, 100);
6736 let b = _mm256_set1_epi64x(2);
6737 let r = _mm256_cmplt_epu64_mask(a, b);
6738 assert_eq!(r, 0b00001100);
6739 }
6740
6741 #[simd_test(enable = "avx512f,avx512vl")]
6742 const unsafe fn test_mm256_mask_cmplt_epu64_mask() {
6743 let a = _mm256_set_epi64x(0, 1, 2, 100);
6744 let b = _mm256_set1_epi64x(2);
6745 let mask = 0b11111111;
6746 let r = _mm256_mask_cmplt_epu64_mask(mask, a, b);
6747 assert_eq!(r, 0b00001100);
6748 }
6749
6750 #[simd_test(enable = "avx512f,avx512vl")]
6751 const unsafe fn test_mm_cmplt_epu64_mask() {
6752 let a = _mm_set_epi64x(0, 1);
6753 let b = _mm_set1_epi64x(2);
6754 let r = _mm_cmplt_epu64_mask(a, b);
6755 assert_eq!(r, 0b00000011);
6756 }
6757
6758 #[simd_test(enable = "avx512f,avx512vl")]
6759 const unsafe fn test_mm_mask_cmplt_epu64_mask() {
6760 let a = _mm_set_epi64x(0, 1);
6761 let b = _mm_set1_epi64x(2);
6762 let mask = 0b11111111;
6763 let r = _mm_mask_cmplt_epu64_mask(mask, a, b);
6764 assert_eq!(r, 0b00000011);
6765 }
6766
6767 #[simd_test(enable = "avx512f")]
6768 const unsafe fn test_mm512_cmpgt_epu64_mask() {
6769 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6770 let b = _mm512_set1_epi64(-1);
6771 let m = _mm512_cmpgt_epu64_mask(b, a);
6772 assert_eq!(m, 0b11001111);
6773 }
6774
6775 #[simd_test(enable = "avx512f")]
6776 const unsafe fn test_mm512_mask_cmpgt_epu64_mask() {
6777 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6778 let b = _mm512_set1_epi64(-1);
6779 let mask = 0b01111010;
6780 let r = _mm512_mask_cmpgt_epu64_mask(mask, b, a);
6781 assert_eq!(r, 0b01001010);
6782 }
6783
6784 #[simd_test(enable = "avx512f,avx512vl")]
6785 const unsafe fn test_mm256_cmpgt_epu64_mask() {
6786 let a = _mm256_set_epi64x(0, 1, 2, 3);
6787 let b = _mm256_set1_epi64x(1);
6788 let r = _mm256_cmpgt_epu64_mask(a, b);
6789 assert_eq!(r, 0b00000011);
6790 }
6791
6792 #[simd_test(enable = "avx512f,avx512vl")]
6793 const unsafe fn test_mm256_mask_cmpgt_epu64_mask() {
6794 let a = _mm256_set_epi64x(0, 1, 2, 3);
6795 let b = _mm256_set1_epi64x(1);
6796 let mask = 0b11111111;
6797 let r = _mm256_mask_cmpgt_epu64_mask(mask, a, b);
6798 assert_eq!(r, 0b00000011);
6799 }
6800
6801 #[simd_test(enable = "avx512f,avx512vl")]
6802 const unsafe fn test_mm_cmpgt_epu64_mask() {
6803 let a = _mm_set_epi64x(1, 2);
6804 let b = _mm_set1_epi64x(1);
6805 let r = _mm_cmpgt_epu64_mask(a, b);
6806 assert_eq!(r, 0b00000001);
6807 }
6808
6809 #[simd_test(enable = "avx512f,avx512vl")]
6810 const unsafe fn test_mm_mask_cmpgt_epu64_mask() {
6811 let a = _mm_set_epi64x(1, 2);
6812 let b = _mm_set1_epi64x(1);
6813 let mask = 0b11111111;
6814 let r = _mm_mask_cmpgt_epu64_mask(mask, a, b);
6815 assert_eq!(r, 0b00000001);
6816 }
6817
6818 #[simd_test(enable = "avx512f")]
6819 const unsafe fn test_mm512_cmple_epu64_mask() {
6820 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6821 let b = _mm512_set1_epi64(-1);
6822 assert_eq!(
6823 _mm512_cmple_epu64_mask(a, b),
6824 !_mm512_cmpgt_epu64_mask(a, b)
6825 )
6826 }
6827
6828 #[simd_test(enable = "avx512f")]
6829 const unsafe fn test_mm512_mask_cmple_epu64_mask() {
6830 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6831 let b = _mm512_set1_epi64(-1);
6832 let mask = 0b01111010;
6833 assert_eq!(_mm512_mask_cmple_epu64_mask(mask, a, b), 0b01111010);
6834 }
6835
6836 #[simd_test(enable = "avx512f,avx512vl")]
6837 const unsafe fn test_mm256_cmple_epu64_mask() {
6838 let a = _mm256_set_epi64x(0, 1, 2, 1);
6839 let b = _mm256_set1_epi64x(1);
6840 let r = _mm256_cmple_epu64_mask(a, b);
6841 assert_eq!(r, 0b00001101)
6842 }
6843
6844 #[simd_test(enable = "avx512f,avx512vl")]
6845 const unsafe fn test_mm256_mask_cmple_epu64_mask() {
6846 let a = _mm256_set_epi64x(0, 1, 2, 1);
6847 let b = _mm256_set1_epi64x(1);
6848 let mask = 0b11111111;
6849 let r = _mm256_mask_cmple_epu64_mask(mask, a, b);
6850 assert_eq!(r, 0b00001101)
6851 }
6852
6853 #[simd_test(enable = "avx512f,avx512vl")]
6854 const unsafe fn test_mm_cmple_epu64_mask() {
6855 let a = _mm_set_epi64x(0, 1);
6856 let b = _mm_set1_epi64x(1);
6857 let r = _mm_cmple_epu64_mask(a, b);
6858 assert_eq!(r, 0b00000011)
6859 }
6860
6861 #[simd_test(enable = "avx512f,avx512vl")]
6862 const unsafe fn test_mm_mask_cmple_epu64_mask() {
6863 let a = _mm_set_epi64x(0, 1);
6864 let b = _mm_set1_epi64x(1);
6865 let mask = 0b11111111;
6866 let r = _mm_mask_cmple_epu64_mask(mask, a, b);
6867 assert_eq!(r, 0b00000011)
6868 }
6869
6870 #[simd_test(enable = "avx512f")]
6871 const unsafe fn test_mm512_cmpge_epu64_mask() {
6872 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6873 let b = _mm512_set1_epi64(-1);
6874 assert_eq!(
6875 _mm512_cmpge_epu64_mask(a, b),
6876 !_mm512_cmplt_epu64_mask(a, b)
6877 );
6878 }
6879
6880 #[simd_test(enable = "avx512f")]
6881 const unsafe fn test_mm512_mask_cmpge_epu64_mask() {
6882 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6883 let b = _mm512_set1_epi64(-1);
6884 let mask = 0b11111111;
6885 let r = _mm512_mask_cmpge_epu64_mask(mask, a, b);
6886 assert_eq!(r, 0b00110000);
6887 }
6888
6889 #[simd_test(enable = "avx512f,avx512vl")]
6890 const unsafe fn test_mm256_cmpge_epu64_mask() {
6891 let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6892 let b = _mm256_set1_epi64x(1);
6893 let r = _mm256_cmpge_epu64_mask(a, b);
6894 assert_eq!(r, 0b00000111);
6895 }
6896
6897 #[simd_test(enable = "avx512f,avx512vl")]
6898 const unsafe fn test_mm256_mask_cmpge_epu64_mask() {
6899 let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6900 let b = _mm256_set1_epi64x(1);
6901 let mask = 0b11111111;
6902 let r = _mm256_mask_cmpge_epu64_mask(mask, a, b);
6903 assert_eq!(r, 0b00000111);
6904 }
6905
6906 #[simd_test(enable = "avx512f,avx512vl")]
6907 const unsafe fn test_mm_cmpge_epu64_mask() {
6908 let a = _mm_set_epi64x(0, 1);
6909 let b = _mm_set1_epi64x(1);
6910 let r = _mm_cmpge_epu64_mask(a, b);
6911 assert_eq!(r, 0b00000001);
6912 }
6913
6914 #[simd_test(enable = "avx512f,avx512vl")]
6915 const unsafe fn test_mm_mask_cmpge_epu64_mask() {
6916 let a = _mm_set_epi64x(0, 1);
6917 let b = _mm_set1_epi64x(1);
6918 let mask = 0b11111111;
6919 let r = _mm_mask_cmpge_epu64_mask(mask, a, b);
6920 assert_eq!(r, 0b00000001);
6921 }
6922
6923 #[simd_test(enable = "avx512f")]
6924 const unsafe fn test_mm512_cmpeq_epu64_mask() {
6925 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6926 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6927 let m = _mm512_cmpeq_epu64_mask(b, a);
6928 assert_eq!(m, 0b11001111);
6929 }
6930
6931 #[simd_test(enable = "avx512f")]
6932 const unsafe fn test_mm512_mask_cmpeq_epu64_mask() {
6933 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6934 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6935 let mask = 0b01111010;
6936 let r = _mm512_mask_cmpeq_epu64_mask(mask, b, a);
6937 assert_eq!(r, 0b01001010);
6938 }
6939
6940 #[simd_test(enable = "avx512f,avx512vl")]
6941 const unsafe fn test_mm256_cmpeq_epu64_mask() {
6942 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6943 let b = _mm256_set_epi64x(0, 1, 13, 42);
6944 let m = _mm256_cmpeq_epu64_mask(b, a);
6945 assert_eq!(m, 0b00001100);
6946 }
6947
6948 #[simd_test(enable = "avx512f,avx512vl")]
6949 const unsafe fn test_mm256_mask_cmpeq_epu64_mask() {
6950 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6951 let b = _mm256_set_epi64x(0, 1, 13, 42);
6952 let mask = 0b11111111;
6953 let r = _mm256_mask_cmpeq_epu64_mask(mask, b, a);
6954 assert_eq!(r, 0b00001100);
6955 }
6956
6957 #[simd_test(enable = "avx512f,avx512vl")]
6958 const unsafe fn test_mm_cmpeq_epu64_mask() {
6959 let a = _mm_set_epi64x(0, 1);
6960 let b = _mm_set_epi64x(0, 1);
6961 let m = _mm_cmpeq_epu64_mask(b, a);
6962 assert_eq!(m, 0b00000011);
6963 }
6964
6965 #[simd_test(enable = "avx512f,avx512vl")]
6966 const unsafe fn test_mm_mask_cmpeq_epu64_mask() {
6967 let a = _mm_set_epi64x(0, 1);
6968 let b = _mm_set_epi64x(0, 1);
6969 let mask = 0b11111111;
6970 let r = _mm_mask_cmpeq_epu64_mask(mask, b, a);
6971 assert_eq!(r, 0b00000011);
6972 }
6973
6974 #[simd_test(enable = "avx512f")]
6975 const unsafe fn test_mm512_cmpneq_epu64_mask() {
6976 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6977 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6978 let m = _mm512_cmpneq_epu64_mask(b, a);
6979 assert_eq!(m, !_mm512_cmpeq_epu64_mask(b, a));
6980 }
6981
6982 #[simd_test(enable = "avx512f")]
6983 const unsafe fn test_mm512_mask_cmpneq_epu64_mask() {
6984 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, -100, 100);
6985 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6986 let mask = 0b01111010;
6987 let r = _mm512_mask_cmpneq_epu64_mask(mask, b, a);
6988 assert_eq!(r, 0b00110010);
6989 }
6990
6991 #[simd_test(enable = "avx512f,avx512vl")]
6992 const unsafe fn test_mm256_cmpneq_epu64_mask() {
6993 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6994 let b = _mm256_set_epi64x(0, 1, 13, 42);
6995 let r = _mm256_cmpneq_epu64_mask(b, a);
6996 assert_eq!(r, 0b00000011);
6997 }
6998
6999 #[simd_test(enable = "avx512f,avx512vl")]
7000 const unsafe fn test_mm256_mask_cmpneq_epu64_mask() {
7001 let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
7002 let b = _mm256_set_epi64x(0, 1, 13, 42);
7003 let mask = 0b11111111;
7004 let r = _mm256_mask_cmpneq_epu64_mask(mask, b, a);
7005 assert_eq!(r, 0b00000011);
7006 }
7007
7008 #[simd_test(enable = "avx512f,avx512vl")]
7009 const unsafe fn test_mm_cmpneq_epu64_mask() {
7010 let a = _mm_set_epi64x(-1, u64::MAX as i64);
7011 let b = _mm_set_epi64x(13, 42);
7012 let r = _mm_cmpneq_epu64_mask(b, a);
7013 assert_eq!(r, 0b00000011);
7014 }
7015
7016 #[simd_test(enable = "avx512f,avx512vl")]
7017 const unsafe fn test_mm_mask_cmpneq_epu64_mask() {
7018 let a = _mm_set_epi64x(-1, u64::MAX as i64);
7019 let b = _mm_set_epi64x(13, 42);
7020 let mask = 0b11111111;
7021 let r = _mm_mask_cmpneq_epu64_mask(mask, b, a);
7022 assert_eq!(r, 0b00000011);
7023 }
7024
7025 #[simd_test(enable = "avx512f")]
7026 const unsafe fn test_mm512_cmp_epu64_mask() {
7027 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7028 let b = _mm512_set1_epi64(-1);
7029 let m = _mm512_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7030 assert_eq!(m, 0b11001111);
7031 }
7032
7033 #[simd_test(enable = "avx512f")]
7034 const unsafe fn test_mm512_mask_cmp_epu64_mask() {
7035 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7036 let b = _mm512_set1_epi64(-1);
7037 let mask = 0b01111010;
7038 let r = _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7039 assert_eq!(r, 0b01001010);
7040 }
7041
7042 #[simd_test(enable = "avx512f,avx512vl")]
7043 const unsafe fn test_mm256_cmp_epu64_mask() {
7044 let a = _mm256_set_epi64x(0, 1, -1, 100);
7045 let b = _mm256_set1_epi64x(1);
7046 let m = _mm256_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7047 assert_eq!(m, 0b00001000);
7048 }
7049
7050 #[simd_test(enable = "avx512f,avx512vl")]
7051 const unsafe fn test_mm256_mask_cmp_epu64_mask() {
7052 let a = _mm256_set_epi64x(0, 1, -1, 100);
7053 let b = _mm256_set1_epi64x(1);
7054 let mask = 0b11111111;
7055 let r = _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7056 assert_eq!(r, 0b00001000);
7057 }
7058
7059 #[simd_test(enable = "avx512f,avx512vl")]
7060 const unsafe fn test_mm_cmp_epu64_mask() {
7061 let a = _mm_set_epi64x(0, 1);
7062 let b = _mm_set1_epi64x(1);
7063 let m = _mm_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7064 assert_eq!(m, 0b00000010);
7065 }
7066
7067 #[simd_test(enable = "avx512f,avx512vl")]
7068 const unsafe fn test_mm_mask_cmp_epu64_mask() {
7069 let a = _mm_set_epi64x(0, 1);
7070 let b = _mm_set1_epi64x(1);
7071 let mask = 0b11111111;
7072 let r = _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7073 assert_eq!(r, 0b00000010);
7074 }
7075
7076 #[simd_test(enable = "avx512f")]
7077 const unsafe fn test_mm512_cmplt_epi64_mask() {
7078 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7079 let b = _mm512_set1_epi64(-1);
7080 let m = _mm512_cmplt_epi64_mask(a, b);
7081 assert_eq!(m, 0b00000101);
7082 }
7083
7084 #[simd_test(enable = "avx512f")]
7085 const unsafe fn test_mm512_mask_cmplt_epi64_mask() {
7086 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7087 let b = _mm512_set1_epi64(-1);
7088 let mask = 0b01100110;
7089 let r = _mm512_mask_cmplt_epi64_mask(mask, a, b);
7090 assert_eq!(r, 0b00000100);
7091 }
7092
7093 #[simd_test(enable = "avx512f,avx512vl")]
7094 const unsafe fn test_mm256_cmplt_epi64_mask() {
7095 let a = _mm256_set_epi64x(0, 1, -1, -13);
7096 let b = _mm256_set1_epi64x(-1);
7097 let r = _mm256_cmplt_epi64_mask(a, b);
7098 assert_eq!(r, 0b00000001);
7099 }
7100
7101 #[simd_test(enable = "avx512f,avx512vl")]
7102 const unsafe fn test_mm256_mask_cmplt_epi64_mask() {
7103 let a = _mm256_set_epi64x(0, 1, -1, -13);
7104 let b = _mm256_set1_epi64x(-1);
7105 let mask = 0b11111111;
7106 let r = _mm256_mask_cmplt_epi64_mask(mask, a, b);
7107 assert_eq!(r, 0b00000001);
7108 }
7109
7110 #[simd_test(enable = "avx512f,avx512vl")]
7111 const unsafe fn test_mm_cmplt_epi64_mask() {
7112 let a = _mm_set_epi64x(-1, -13);
7113 let b = _mm_set1_epi64x(-1);
7114 let r = _mm_cmplt_epi64_mask(a, b);
7115 assert_eq!(r, 0b00000001);
7116 }
7117
7118 #[simd_test(enable = "avx512f,avx512vl")]
7119 const unsafe fn test_mm_mask_cmplt_epi64_mask() {
7120 let a = _mm_set_epi64x(-1, -13);
7121 let b = _mm_set1_epi64x(-1);
7122 let mask = 0b11111111;
7123 let r = _mm_mask_cmplt_epi64_mask(mask, a, b);
7124 assert_eq!(r, 0b00000001);
7125 }
7126
7127 #[simd_test(enable = "avx512f")]
7128 const unsafe fn test_mm512_cmpgt_epi64_mask() {
7129 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7130 let b = _mm512_set1_epi64(-1);
7131 let m = _mm512_cmpgt_epi64_mask(b, a);
7132 assert_eq!(m, 0b00000101);
7133 }
7134
7135 #[simd_test(enable = "avx512f")]
7136 const unsafe fn test_mm512_mask_cmpgt_epi64_mask() {
7137 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7138 let b = _mm512_set1_epi64(-1);
7139 let mask = 0b01100110;
7140 let r = _mm512_mask_cmpgt_epi64_mask(mask, b, a);
7141 assert_eq!(r, 0b00000100);
7142 }
7143
7144 #[simd_test(enable = "avx512f,avx512vl")]
7145 const unsafe fn test_mm256_cmpgt_epi64_mask() {
7146 let a = _mm256_set_epi64x(0, 1, -1, 13);
7147 let b = _mm256_set1_epi64x(-1);
7148 let r = _mm256_cmpgt_epi64_mask(a, b);
7149 assert_eq!(r, 0b00001101);
7150 }
7151
7152 #[simd_test(enable = "avx512f,avx512vl")]
7153 const unsafe fn test_mm256_mask_cmpgt_epi64_mask() {
7154 let a = _mm256_set_epi64x(0, 1, -1, 13);
7155 let b = _mm256_set1_epi64x(-1);
7156 let mask = 0b11111111;
7157 let r = _mm256_mask_cmpgt_epi64_mask(mask, a, b);
7158 assert_eq!(r, 0b00001101);
7159 }
7160
7161 #[simd_test(enable = "avx512f,avx512vl")]
7162 const unsafe fn test_mm_cmpgt_epi64_mask() {
7163 let a = _mm_set_epi64x(0, -1);
7164 let b = _mm_set1_epi64x(-1);
7165 let r = _mm_cmpgt_epi64_mask(a, b);
7166 assert_eq!(r, 0b00000010);
7167 }
7168
7169 #[simd_test(enable = "avx512f,avx512vl")]
7170 const unsafe fn test_mm_mask_cmpgt_epi64_mask() {
7171 let a = _mm_set_epi64x(0, -1);
7172 let b = _mm_set1_epi64x(-1);
7173 let mask = 0b11111111;
7174 let r = _mm_mask_cmpgt_epi64_mask(mask, a, b);
7175 assert_eq!(r, 0b00000010);
7176 }
7177
7178 #[simd_test(enable = "avx512f")]
7179 const unsafe fn test_mm512_cmple_epi64_mask() {
7180 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7181 let b = _mm512_set1_epi64(-1);
7182 assert_eq!(
7183 _mm512_cmple_epi64_mask(a, b),
7184 !_mm512_cmpgt_epi64_mask(a, b)
7185 )
7186 }
7187
7188 #[simd_test(enable = "avx512f")]
7189 const unsafe fn test_mm512_mask_cmple_epi64_mask() {
7190 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7191 let b = _mm512_set1_epi64(-1);
7192 let mask = 0b01111010;
7193 assert_eq!(_mm512_mask_cmple_epi64_mask(mask, a, b), 0b00110000);
7194 }
7195
7196 #[simd_test(enable = "avx512f,avx512vl")]
7197 const unsafe fn test_mm256_cmple_epi64_mask() {
7198 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7199 let b = _mm256_set1_epi64x(-1);
7200 let r = _mm256_cmple_epi64_mask(a, b);
7201 assert_eq!(r, 0b00000010)
7202 }
7203
7204 #[simd_test(enable = "avx512f,avx512vl")]
7205 const unsafe fn test_mm256_mask_cmple_epi64_mask() {
7206 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7207 let b = _mm256_set1_epi64x(-1);
7208 let mask = 0b11111111;
7209 let r = _mm256_mask_cmple_epi64_mask(mask, a, b);
7210 assert_eq!(r, 0b00000010)
7211 }
7212
7213 #[simd_test(enable = "avx512f,avx512vl")]
7214 const unsafe fn test_mm_cmple_epi64_mask() {
7215 let a = _mm_set_epi64x(0, 1);
7216 let b = _mm_set1_epi64x(1);
7217 let r = _mm_cmple_epi64_mask(a, b);
7218 assert_eq!(r, 0b00000011)
7219 }
7220
7221 #[simd_test(enable = "avx512f,avx512vl")]
7222 const unsafe fn test_mm_mask_cmple_epi64_mask() {
7223 let a = _mm_set_epi64x(0, 1);
7224 let b = _mm_set1_epi64x(1);
7225 let mask = 0b11111111;
7226 let r = _mm_mask_cmple_epi64_mask(mask, a, b);
7227 assert_eq!(r, 0b00000011)
7228 }
7229
7230 #[simd_test(enable = "avx512f")]
7231 const unsafe fn test_mm512_cmpge_epi64_mask() {
7232 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7233 let b = _mm512_set1_epi64(-1);
7234 assert_eq!(
7235 _mm512_cmpge_epi64_mask(a, b),
7236 !_mm512_cmplt_epi64_mask(a, b)
7237 )
7238 }
7239
7240 #[simd_test(enable = "avx512f")]
7241 const unsafe fn test_mm512_mask_cmpge_epi64_mask() {
7242 let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7243 let b = _mm512_set1_epi64(-1);
7244 let mask = 0b11111111;
7245 let r = _mm512_mask_cmpge_epi64_mask(mask, a, b);
7246 assert_eq!(r, 0b11111010);
7247 }
7248
7249 #[simd_test(enable = "avx512f,avx512vl")]
7250 const unsafe fn test_mm256_cmpge_epi64_mask() {
7251 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7252 let b = _mm256_set1_epi64x(-1);
7253 let r = _mm256_cmpge_epi64_mask(a, b);
7254 assert_eq!(r, 0b00001111);
7255 }
7256
7257 #[simd_test(enable = "avx512f,avx512vl")]
7258 const unsafe fn test_mm256_mask_cmpge_epi64_mask() {
7259 let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7260 let b = _mm256_set1_epi64x(-1);
7261 let mask = 0b11111111;
7262 let r = _mm256_mask_cmpge_epi64_mask(mask, a, b);
7263 assert_eq!(r, 0b00001111);
7264 }
7265
7266 #[simd_test(enable = "avx512f,avx512vl")]
7267 const unsafe fn test_mm_cmpge_epi64_mask() {
7268 let a = _mm_set_epi64x(0, 1);
7269 let b = _mm_set1_epi64x(-1);
7270 let r = _mm_cmpge_epi64_mask(a, b);
7271 assert_eq!(r, 0b00000011);
7272 }
7273
7274 #[simd_test(enable = "avx512f,avx512vl")]
7275 const unsafe fn test_mm_mask_cmpge_epi64_mask() {
7276 let a = _mm_set_epi64x(0, 1);
7277 let b = _mm_set1_epi64x(-1);
7278 let mask = 0b11111111;
7279 let r = _mm_mask_cmpge_epi64_mask(mask, a, b);
7280 assert_eq!(r, 0b00000011);
7281 }
7282
7283 #[simd_test(enable = "avx512f")]
7284 const unsafe fn test_mm512_cmpeq_epi64_mask() {
7285 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7286 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7287 let m = _mm512_cmpeq_epi64_mask(b, a);
7288 assert_eq!(m, 0b11001111);
7289 }
7290
7291 #[simd_test(enable = "avx512f")]
7292 const unsafe fn test_mm512_mask_cmpeq_epi64_mask() {
7293 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7294 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7295 let mask = 0b01111010;
7296 let r = _mm512_mask_cmpeq_epi64_mask(mask, b, a);
7297 assert_eq!(r, 0b01001010);
7298 }
7299
7300 #[simd_test(enable = "avx512f,avx512vl")]
7301 const unsafe fn test_mm256_cmpeq_epi64_mask() {
7302 let a = _mm256_set_epi64x(0, 1, -1, 13);
7303 let b = _mm256_set_epi64x(0, 1, 13, 42);
7304 let m = _mm256_cmpeq_epi64_mask(b, a);
7305 assert_eq!(m, 0b00001100);
7306 }
7307
7308 #[simd_test(enable = "avx512f,avx512vl")]
7309 const unsafe fn test_mm256_mask_cmpeq_epi64_mask() {
7310 let a = _mm256_set_epi64x(0, 1, -1, 13);
7311 let b = _mm256_set_epi64x(0, 1, 13, 42);
7312 let mask = 0b11111111;
7313 let r = _mm256_mask_cmpeq_epi64_mask(mask, b, a);
7314 assert_eq!(r, 0b00001100);
7315 }
7316
7317 #[simd_test(enable = "avx512f,avx512vl")]
7318 const unsafe fn test_mm_cmpeq_epi64_mask() {
7319 let a = _mm_set_epi64x(0, 1);
7320 let b = _mm_set_epi64x(0, 1);
7321 let m = _mm_cmpeq_epi64_mask(b, a);
7322 assert_eq!(m, 0b00000011);
7323 }
7324
7325 #[simd_test(enable = "avx512f,avx512vl")]
7326 const unsafe fn test_mm_mask_cmpeq_epi64_mask() {
7327 let a = _mm_set_epi64x(0, 1);
7328 let b = _mm_set_epi64x(0, 1);
7329 let mask = 0b11111111;
7330 let r = _mm_mask_cmpeq_epi64_mask(mask, b, a);
7331 assert_eq!(r, 0b00000011);
7332 }
7333
7334 #[simd_test(enable = "avx512f")]
7335 const unsafe fn test_mm512_set_epi64() {
7336 let r = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7337 assert_eq_m512i(r, _mm512_set_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7338 }
7339
7340 #[simd_test(enable = "avx512f")]
7341 const unsafe fn test_mm512_setr_epi64() {
7342 let r = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7343 assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7344 }
7345
7346 #[simd_test(enable = "avx512f")]
7347 const unsafe fn test_mm512_cmpneq_epi64_mask() {
7348 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7349 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7350 let m = _mm512_cmpneq_epi64_mask(b, a);
7351 assert_eq!(m, !_mm512_cmpeq_epi64_mask(b, a));
7352 }
7353
7354 #[simd_test(enable = "avx512f")]
7355 const unsafe fn test_mm512_mask_cmpneq_epi64_mask() {
7356 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, -100, 100);
7357 let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7358 let mask = 0b01111010;
7359 let r = _mm512_mask_cmpneq_epi64_mask(mask, b, a);
7360 assert_eq!(r, 0b00110010)
7361 }
7362
7363 #[simd_test(enable = "avx512f,avx512vl")]
7364 const unsafe fn test_mm256_cmpneq_epi64_mask() {
7365 let a = _mm256_set_epi64x(0, 1, -1, 13);
7366 let b = _mm256_set_epi64x(0, 1, 13, 42);
7367 let r = _mm256_cmpneq_epi64_mask(b, a);
7368 assert_eq!(r, 0b00000011)
7369 }
7370
7371 #[simd_test(enable = "avx512f,avx512vl")]
7372 const unsafe fn test_mm256_mask_cmpneq_epi64_mask() {
7373 let a = _mm256_set_epi64x(0, 1, -1, 13);
7374 let b = _mm256_set_epi64x(0, 1, 13, 42);
7375 let mask = 0b11111111;
7376 let r = _mm256_mask_cmpneq_epi64_mask(mask, b, a);
7377 assert_eq!(r, 0b00000011)
7378 }
7379
7380 #[simd_test(enable = "avx512f,avx512vl")]
7381 const unsafe fn test_mm_cmpneq_epi64_mask() {
7382 let a = _mm_set_epi64x(-1, 13);
7383 let b = _mm_set_epi64x(13, 42);
7384 let r = _mm_cmpneq_epi64_mask(b, a);
7385 assert_eq!(r, 0b00000011)
7386 }
7387
7388 #[simd_test(enable = "avx512f,avx512vl")]
7389 const unsafe fn test_mm_mask_cmpneq_epi64_mask() {
7390 let a = _mm_set_epi64x(-1, 13);
7391 let b = _mm_set_epi64x(13, 42);
7392 let mask = 0b11111111;
7393 let r = _mm_mask_cmpneq_epi64_mask(mask, b, a);
7394 assert_eq!(r, 0b00000011)
7395 }
7396
7397 #[simd_test(enable = "avx512f")]
7398 const unsafe fn test_mm512_cmp_epi64_mask() {
7399 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7400 let b = _mm512_set1_epi64(-1);
7401 let m = _mm512_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7402 assert_eq!(m, 0b00000101);
7403 }
7404
7405 #[simd_test(enable = "avx512f")]
7406 const unsafe fn test_mm512_mask_cmp_epi64_mask() {
7407 let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7408 let b = _mm512_set1_epi64(-1);
7409 let mask = 0b01100110;
7410 let r = _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7411 assert_eq!(r, 0b00000100);
7412 }
7413
7414 #[simd_test(enable = "avx512f,avx512vl")]
7415 const unsafe fn test_mm256_cmp_epi64_mask() {
7416 let a = _mm256_set_epi64x(0, 1, -1, 13);
7417 let b = _mm256_set1_epi64x(1);
7418 let m = _mm256_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7419 assert_eq!(m, 0b00001010);
7420 }
7421
7422 #[simd_test(enable = "avx512f,avx512vl")]
7423 const unsafe fn test_mm256_mask_cmp_epi64_mask() {
7424 let a = _mm256_set_epi64x(0, 1, -1, 13);
7425 let b = _mm256_set1_epi64x(1);
7426 let mask = 0b11111111;
7427 let r = _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7428 assert_eq!(r, 0b00001010);
7429 }
7430
7431 #[simd_test(enable = "avx512f,avx512vl")]
7432 const unsafe fn test_mm_cmp_epi64_mask() {
7433 let a = _mm_set_epi64x(0, 1);
7434 let b = _mm_set1_epi64x(1);
7435 let m = _mm_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7436 assert_eq!(m, 0b00000010);
7437 }
7438
7439 #[simd_test(enable = "avx512f,avx512vl")]
7440 const unsafe fn test_mm_mask_cmp_epi64_mask() {
7441 let a = _mm_set_epi64x(0, 1);
7442 let b = _mm_set1_epi64x(1);
7443 let mask = 0b11111111;
7444 let r = _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7445 assert_eq!(r, 0b00000010);
7446 }
7447
7448 #[simd_test(enable = "avx512f")]
7449 unsafe fn test_mm512_i32gather_pd() {
7450 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7451 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7453 let r = _mm512_i32gather_pd::<8>(index, arr.as_ptr());
7454 assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7455 }
7456
7457 #[simd_test(enable = "avx512f")]
7458 unsafe fn test_mm512_mask_i32gather_pd() {
7459 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7460 let src = _mm512_set1_pd(2.);
7461 let mask = 0b10101010;
7462 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7463 let r = _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr());
7465 assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7466 }
7467
7468 #[simd_test(enable = "avx512f")]
7469 unsafe fn test_mm512_i64gather_pd() {
7470 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7471 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7473 let r = _mm512_i64gather_pd::<8>(index, arr.as_ptr());
7474 assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7475 }
7476
7477 #[simd_test(enable = "avx512f")]
7478 unsafe fn test_mm512_mask_i64gather_pd() {
7479 let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7480 let src = _mm512_set1_pd(2.);
7481 let mask = 0b10101010;
7482 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7483 let r = _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr());
7485 assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7486 }
7487
7488 #[simd_test(enable = "avx512f")]
7489 unsafe fn test_mm512_i64gather_ps() {
7490 let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7491 #[rustfmt::skip]
7493 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7494 let r = _mm512_i64gather_ps::<4>(index, arr.as_ptr());
7495 assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.));
7496 }
7497
7498 #[simd_test(enable = "avx512f")]
7499 unsafe fn test_mm512_mask_i64gather_ps() {
7500 let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7501 let src = _mm256_set1_ps(2.);
7502 let mask = 0b10101010;
7503 #[rustfmt::skip]
7504 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7505 let r = _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr());
7507 assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.));
7508 }
7509
7510 #[simd_test(enable = "avx512f")]
7511 unsafe fn test_mm512_i32gather_epi64() {
7512 let mut arr = [0i64; 128];
7513 for i in 0..128i64 {
7514 arr[i as usize] = i;
7515 }
7516 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7518 let r = _mm512_i32gather_epi64::<8>(index, arr.as_ptr());
7519 assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7520 }
7521
7522 #[simd_test(enable = "avx512f")]
7523 unsafe fn test_mm512_mask_i32gather_epi64() {
7524 let mut arr = [0i64; 128];
7525 for i in 0..128i64 {
7526 arr[i as usize] = i;
7527 }
7528 let src = _mm512_set1_epi64(2);
7529 let mask = 0b10101010;
7530 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7531 let r = _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr());
7533 assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7534 }
7535
7536 #[simd_test(enable = "avx512f")]
7537 unsafe fn test_mm512_i64gather_epi64() {
7538 let mut arr = [0i64; 128];
7539 for i in 0..128i64 {
7540 arr[i as usize] = i;
7541 }
7542 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7544 let r = _mm512_i64gather_epi64::<8>(index, arr.as_ptr());
7545 assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7546 }
7547
7548 #[simd_test(enable = "avx512f")]
7549 unsafe fn test_mm512_mask_i64gather_epi64() {
7550 let mut arr = [0i64; 128];
7551 for i in 0..128i64 {
7552 arr[i as usize] = i;
7553 }
7554 let src = _mm512_set1_epi64(2);
7555 let mask = 0b10101010;
7556 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7557 let r = _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr());
7559 assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7560 }
7561
7562 #[simd_test(enable = "avx512f")]
7563 unsafe fn test_mm512_i64gather_epi32() {
7564 let mut arr = [0i64; 128];
7565 for i in 0..128i64 {
7566 arr[i as usize] = i;
7567 }
7568 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7570 let r = _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32);
7571 assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112));
7572 }
7573
7574 #[simd_test(enable = "avx512f")]
7575 unsafe fn test_mm512_mask_i64gather_epi32() {
7576 let mut arr = [0i64; 128];
7577 for i in 0..128i64 {
7578 arr[i as usize] = i;
7579 }
7580 let src = _mm256_set1_epi32(2);
7581 let mask = 0b10101010;
7582 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7583 let r = _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32);
7585 assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112));
7586 }
7587
7588 #[simd_test(enable = "avx512f")]
7589 unsafe fn test_mm512_i32scatter_pd() {
7590 let mut arr = [0f64; 128];
7591 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7592 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7593 _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src);
7595 let mut expected = [0f64; 128];
7596 for i in 0..8 {
7597 expected[i * 16] = (i + 1) as f64;
7598 }
7599 assert_eq!(&arr[..], &expected[..],);
7600 }
7601
7602 #[simd_test(enable = "avx512f")]
7603 unsafe fn test_mm512_mask_i32scatter_pd() {
7604 let mut arr = [0f64; 128];
7605 let mask = 0b10101010;
7606 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7607 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7608 _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
7610 let mut expected = [0f64; 128];
7611 for i in 0..4 {
7612 expected[i * 32 + 16] = 2. * (i + 1) as f64;
7613 }
7614 assert_eq!(&arr[..], &expected[..],);
7615 }
7616
7617 #[simd_test(enable = "avx512f")]
7618 unsafe fn test_mm512_i64scatter_pd() {
7619 let mut arr = [0f64; 128];
7620 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7621 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7622 _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src);
7624 let mut expected = [0f64; 128];
7625 for i in 0..8 {
7626 expected[i * 16] = (i + 1) as f64;
7627 }
7628 assert_eq!(&arr[..], &expected[..],);
7629 }
7630
7631 #[simd_test(enable = "avx512f")]
7632 unsafe fn test_mm512_mask_i64scatter_pd() {
7633 let mut arr = [0f64; 128];
7634 let mask = 0b10101010;
7635 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7636 let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7637 _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
7639 let mut expected = [0f64; 128];
7640 for i in 0..4 {
7641 expected[i * 32 + 16] = 2. * (i + 1) as f64;
7642 }
7643 assert_eq!(&arr[..], &expected[..],);
7644 }
7645
7646 #[simd_test(enable = "avx512f")]
7647 unsafe fn test_mm512_i64scatter_ps() {
7648 let mut arr = [0f32; 128];
7649 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7650 let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7651 _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src);
7653 let mut expected = [0f32; 128];
7654 for i in 0..8 {
7655 expected[i * 16] = (i + 1) as f32;
7656 }
7657 assert_eq!(&arr[..], &expected[..],);
7658 }
7659
7660 #[simd_test(enable = "avx512f")]
7661 unsafe fn test_mm512_mask_i64scatter_ps() {
7662 let mut arr = [0f32; 128];
7663 let mask = 0b10101010;
7664 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7665 let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7666 _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
7668 let mut expected = [0f32; 128];
7669 for i in 0..4 {
7670 expected[i * 32 + 16] = 2. * (i + 1) as f32;
7671 }
7672 assert_eq!(&arr[..], &expected[..],);
7673 }
7674
7675 #[simd_test(enable = "avx512f")]
7676 unsafe fn test_mm512_i32scatter_epi64() {
7677 let mut arr = [0i64; 128];
7678 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7679 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7680 _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
7682 let mut expected = [0i64; 128];
7683 for i in 0..8 {
7684 expected[i * 16] = (i + 1) as i64;
7685 }
7686 assert_eq!(&arr[..], &expected[..],);
7687 }
7688
7689 #[simd_test(enable = "avx512f")]
7690 unsafe fn test_mm512_mask_i32scatter_epi64() {
7691 let mut arr = [0i64; 128];
7692 let mask = 0b10101010;
7693 let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7694 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7695 _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
7697 let mut expected = [0i64; 128];
7698 for i in 0..4 {
7699 expected[i * 32 + 16] = 2 * (i + 1) as i64;
7700 }
7701 assert_eq!(&arr[..], &expected[..],);
7702 }
7703
7704 #[simd_test(enable = "avx512f")]
7705 unsafe fn test_mm512_i64scatter_epi64() {
7706 let mut arr = [0i64; 128];
7707 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7708 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7709 _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
7711 let mut expected = [0i64; 128];
7712 for i in 0..8 {
7713 expected[i * 16] = (i + 1) as i64;
7714 }
7715 assert_eq!(&arr[..], &expected[..],);
7716 }
7717
7718 #[simd_test(enable = "avx512f")]
7719 unsafe fn test_mm512_mask_i64scatter_epi64() {
7720 let mut arr = [0i64; 128];
7721 let mask = 0b10101010;
7722 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7723 let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7724 _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
7726 let mut expected = [0i64; 128];
7727 for i in 0..4 {
7728 expected[i * 32 + 16] = 2 * (i + 1) as i64;
7729 }
7730 assert_eq!(&arr[..], &expected[..],);
7731 }
7732
7733 #[simd_test(enable = "avx512f")]
7734 unsafe fn test_mm512_i64scatter_epi32() {
7735 let mut arr = [0i32; 128];
7736 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7737 let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7738 _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
7740 let mut expected = [0i32; 128];
7741 for i in 0..8 {
7742 expected[i * 16] = (i + 1) as i32;
7743 }
7744 assert_eq!(&arr[..], &expected[..],);
7745 }
7746
7747 #[simd_test(enable = "avx512f")]
7748 unsafe fn test_mm512_mask_i64scatter_epi32() {
7749 let mut arr = [0i32; 128];
7750 let mask = 0b10101010;
7751 let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7752 let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7753 _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
7755 let mut expected = [0i32; 128];
7756 for i in 0..4 {
7757 expected[i * 32 + 16] = 2 * (i + 1) as i32;
7758 }
7759 assert_eq!(&arr[..], &expected[..],);
7760 }
7761
7762 #[simd_test(enable = "avx512f")]
7763 unsafe fn test_mm512_i32logather_epi64() {
7764 let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7765 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7766 let r = _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr());
7767 let expected = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7768 assert_eq_m512i(expected, r);
7769 }
7770
7771 #[simd_test(enable = "avx512f")]
7772 unsafe fn test_mm512_mask_i32logather_epi64() {
7773 let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7774 let src = _mm512_setr_epi64(9, 10, 11, 12, 13, 14, 15, 16);
7775 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7776 let r = _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr());
7777 let expected = _mm512_setr_epi64(2, 10, 4, 12, 6, 14, 8, 16);
7778 assert_eq_m512i(expected, r);
7779 }
7780
7781 #[simd_test(enable = "avx512f")]
7782 unsafe fn test_mm512_i32logather_pd() {
7783 let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7784 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7785 let r = _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr());
7786 let expected = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7787 assert_eq_m512d(expected, r);
7788 }
7789
7790 #[simd_test(enable = "avx512f")]
7791 unsafe fn test_mm512_mask_i32logather_pd() {
7792 let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7793 let src = _mm512_setr_pd(9., 10., 11., 12., 13., 14., 15., 16.);
7794 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7795 let r = _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr());
7796 let expected = _mm512_setr_pd(2., 10., 4., 12., 6., 14., 8., 16.);
7797 assert_eq_m512d(expected, r);
7798 }
7799
7800 #[simd_test(enable = "avx512f")]
7801 unsafe fn test_mm512_i32loscatter_epi64() {
7802 let mut base_addr: [i64; 8] = [0; 8];
7803 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7804 let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7805 _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
7806 let expected = [1, 2, 3, 4, 5, 6, 7, 8];
7807 assert_eq!(expected, base_addr);
7808 }
7809
7810 #[simd_test(enable = "avx512f")]
7811 unsafe fn test_mm512_mask_i32loscatter_epi64() {
7812 let mut base_addr: [i64; 8] = [0; 8];
7813 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7814 let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7815 _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
7816 let expected = [0, 2, 0, 4, 0, 6, 0, 8];
7817 assert_eq!(expected, base_addr);
7818 }
7819
7820 #[simd_test(enable = "avx512f")]
7821 unsafe fn test_mm512_i32loscatter_pd() {
7822 let mut base_addr: [f64; 8] = [0.; 8];
7823 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7824 let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7825 _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
7826 let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
7827 assert_eq!(expected, base_addr);
7828 }
7829
7830 #[simd_test(enable = "avx512f")]
7831 unsafe fn test_mm512_mask_i32loscatter_pd() {
7832 let mut base_addr: [f64; 8] = [0.; 8];
7833 let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7834 let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7835 _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
7836 let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
7837 assert_eq!(expected, base_addr);
7838 }
7839
7840 #[simd_test(enable = "avx512f,avx512vl")]
7841 unsafe fn test_mm_mmask_i32gather_epi32() {
7842 let base_addr: [i32; 4] = [1, 2, 3, 4];
7843 let src = _mm_setr_epi32(5, 6, 7, 8);
7844 let vindex = _mm_setr_epi32(1, 2, 3, 0);
7845 let r = _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7846 let expected = _mm_setr_epi32(2, 6, 4, 8);
7847 assert_eq_m128i(expected, r);
7848 }
7849
7850 #[simd_test(enable = "avx512f,avx512vl")]
7851 unsafe fn test_mm_mmask_i32gather_epi64() {
7852 let base_addr: [i64; 2] = [1, 2];
7853 let src = _mm_setr_epi64x(5, 6);
7854 let vindex = _mm_setr_epi32(1, 0, -1, -1);
7855 let r = _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr());
7856 let expected = _mm_setr_epi64x(2, 6);
7857 assert_eq_m128i(expected, r);
7858 }
7859
7860 #[simd_test(enable = "avx512f,avx512vl")]
7861 unsafe fn test_mm_mmask_i32gather_pd() {
7862 let base_addr: [f64; 2] = [1., 2.];
7863 let src = _mm_setr_pd(5., 6.);
7864 let vindex = _mm_setr_epi32(1, 0, -1, -1);
7865 let r = _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr());
7866 let expected = _mm_setr_pd(2., 6.);
7867 assert_eq_m128d(expected, r);
7868 }
7869
7870 #[simd_test(enable = "avx512f,avx512vl")]
7871 unsafe fn test_mm_mmask_i32gather_ps() {
7872 let base_addr: [f32; 4] = [1., 2., 3., 4.];
7873 let src = _mm_setr_ps(5., 6., 7., 8.);
7874 let vindex = _mm_setr_epi32(1, 2, 3, 0);
7875 let r = _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7876 let expected = _mm_setr_ps(2., 6., 4., 8.);
7877 assert_eq_m128(expected, r);
7878 }
7879
7880 #[simd_test(enable = "avx512f,avx512vl")]
7881 unsafe fn test_mm_mmask_i64gather_epi32() {
7882 let base_addr: [i32; 2] = [1, 2];
7883 let src = _mm_setr_epi32(5, 6, 7, 8);
7884 let vindex = _mm_setr_epi64x(1, 0);
7885 let r = _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr());
7886 let expected = _mm_setr_epi32(2, 6, 0, 0);
7887 assert_eq_m128i(expected, r);
7888 }
7889
7890 #[simd_test(enable = "avx512f,avx512vl")]
7891 unsafe fn test_mm_mmask_i64gather_epi64() {
7892 let base_addr: [i64; 2] = [1, 2];
7893 let src = _mm_setr_epi64x(5, 6);
7894 let vindex = _mm_setr_epi64x(1, 0);
7895 let r = _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr());
7896 let expected = _mm_setr_epi64x(2, 6);
7897 assert_eq_m128i(expected, r);
7898 }
7899
7900 #[simd_test(enable = "avx512f,avx512vl")]
7901 unsafe fn test_mm_mmask_i64gather_pd() {
7902 let base_addr: [f64; 2] = [1., 2.];
7903 let src = _mm_setr_pd(5., 6.);
7904 let vindex = _mm_setr_epi64x(1, 0);
7905 let r = _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr());
7906 let expected = _mm_setr_pd(2., 6.);
7907 assert_eq_m128d(expected, r);
7908 }
7909
7910 #[simd_test(enable = "avx512f,avx512vl")]
7911 unsafe fn test_mm_mmask_i64gather_ps() {
7912 let base_addr: [f32; 2] = [1., 2.];
7913 let src = _mm_setr_ps(5., 6., 7., 8.);
7914 let vindex = _mm_setr_epi64x(1, 0);
7915 let r = _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr());
7916 let expected = _mm_setr_ps(2., 6., 0., 0.);
7917 assert_eq_m128(expected, r);
7918 }
7919
7920 #[simd_test(enable = "avx512f,avx512vl")]
7921 unsafe fn test_mm256_mmask_i32gather_epi32() {
7922 let base_addr: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7923 let src = _mm256_setr_epi32(9, 10, 11, 12, 13, 14, 15, 16);
7924 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7925 let r = _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr());
7926 let expected = _mm256_setr_epi32(2, 10, 4, 12, 6, 14, 8, 16);
7927 assert_eq_m256i(expected, r);
7928 }
7929
7930 #[simd_test(enable = "avx512f,avx512vl")]
7931 unsafe fn test_mm256_mmask_i32gather_epi64() {
7932 let base_addr: [i64; 4] = [1, 2, 3, 4];
7933 let src = _mm256_setr_epi64x(9, 10, 11, 12);
7934 let vindex = _mm_setr_epi32(1, 2, 3, 4);
7935 let r = _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7936 let expected = _mm256_setr_epi64x(2, 10, 4, 12);
7937 assert_eq_m256i(expected, r);
7938 }
7939
7940 #[simd_test(enable = "avx512f,avx512vl")]
7941 unsafe fn test_mm256_mmask_i32gather_pd() {
7942 let base_addr: [f64; 4] = [1., 2., 3., 4.];
7943 let src = _mm256_setr_pd(9., 10., 11., 12.);
7944 let vindex = _mm_setr_epi32(1, 2, 3, 4);
7945 let r = _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7946 let expected = _mm256_setr_pd(2., 10., 4., 12.);
7947 assert_eq_m256d(expected, r);
7948 }
7949
7950 #[simd_test(enable = "avx512f,avx512vl")]
7951 unsafe fn test_mm256_mmask_i32gather_ps() {
7952 let base_addr: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7953 let src = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
7954 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7955 let r = _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr());
7956 let expected = _mm256_setr_ps(2., 10., 4., 12., 6., 14., 8., 16.);
7957 assert_eq_m256(expected, r);
7958 }
7959
7960 #[simd_test(enable = "avx512f,avx512vl")]
7961 unsafe fn test_mm256_mmask_i64gather_epi32() {
7962 let base_addr: [i32; 4] = [1, 2, 3, 4];
7963 let src = _mm_setr_epi32(9, 10, 11, 12);
7964 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7965 let r = _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7966 let expected = _mm_setr_epi32(2, 10, 4, 12);
7967 assert_eq_m128i(expected, r);
7968 }
7969
7970 #[simd_test(enable = "avx512f,avx512vl")]
7971 unsafe fn test_mm256_mmask_i64gather_epi64() {
7972 let base_addr: [i64; 4] = [1, 2, 3, 4];
7973 let src = _mm256_setr_epi64x(9, 10, 11, 12);
7974 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7975 let r = _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7976 let expected = _mm256_setr_epi64x(2, 10, 4, 12);
7977 assert_eq_m256i(expected, r);
7978 }
7979
7980 #[simd_test(enable = "avx512f,avx512vl")]
7981 unsafe fn test_mm256_mmask_i64gather_pd() {
7982 let base_addr: [f64; 4] = [1., 2., 3., 4.];
7983 let src = _mm256_setr_pd(9., 10., 11., 12.);
7984 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7985 let r = _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr());
7986 let expected = _mm256_setr_pd(2., 10., 4., 12.);
7987 assert_eq_m256d(expected, r);
7988 }
7989
7990 #[simd_test(enable = "avx512f,avx512vl")]
7991 unsafe fn test_mm256_mmask_i64gather_ps() {
7992 let base_addr: [f32; 4] = [1., 2., 3., 4.];
7993 let src = _mm_setr_ps(9., 10., 11., 12.);
7994 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
7995 let r = _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr());
7996 let expected = _mm_setr_ps(2., 10., 4., 12.);
7997 assert_eq_m128(expected, r);
7998 }
7999
8000 #[simd_test(enable = "avx512f,avx512vl")]
8001 unsafe fn test_mm_i32scatter_epi32() {
8002 let mut base_addr: [i32; 4] = [0; 4];
8003 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8004 let src = _mm_setr_epi32(2, 3, 4, 1);
8005 _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8006 let expected = [1, 2, 3, 4];
8007 assert_eq!(expected, base_addr);
8008 }
8009
8010 #[simd_test(enable = "avx512f,avx512vl")]
8011 unsafe fn test_mm_mask_i32scatter_epi32() {
8012 let mut base_addr: [i32; 4] = [0; 4];
8013 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8014 let src = _mm_setr_epi32(2, 3, 4, 1);
8015 _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8016 let expected = [0, 2, 0, 4];
8017 assert_eq!(expected, base_addr);
8018 }
8019
8020 #[simd_test(enable = "avx512f,avx512vl")]
8021 unsafe fn test_mm_i32scatter_epi64() {
8022 let mut base_addr: [i64; 2] = [0; 2];
8023 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8024 let src = _mm_setr_epi64x(2, 1);
8025 _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8026 let expected = [1, 2];
8027 assert_eq!(expected, base_addr);
8028 }
8029
8030 #[simd_test(enable = "avx512f,avx512vl")]
8031 unsafe fn test_mm_mask_i32scatter_epi64() {
8032 let mut base_addr: [i64; 2] = [0; 2];
8033 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8034 let src = _mm_setr_epi64x(2, 1);
8035 _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8036 let expected = [0, 2];
8037 assert_eq!(expected, base_addr);
8038 }
8039
8040 #[simd_test(enable = "avx512f,avx512vl")]
8041 unsafe fn test_mm_i32scatter_pd() {
8042 let mut base_addr: [f64; 2] = [0.; 2];
8043 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8044 let src = _mm_setr_pd(2., 1.);
8045 _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8046 let expected = [1., 2.];
8047 assert_eq!(expected, base_addr);
8048 }
8049
8050 #[simd_test(enable = "avx512f,avx512vl")]
8051 unsafe fn test_mm_mask_i32scatter_pd() {
8052 let mut base_addr: [f64; 2] = [0.; 2];
8053 let vindex = _mm_setr_epi32(1, 0, -1, -1);
8054 let src = _mm_setr_pd(2., 1.);
8055 _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8056 let expected = [0., 2.];
8057 assert_eq!(expected, base_addr);
8058 }
8059
8060 #[simd_test(enable = "avx512f,avx512vl")]
8061 unsafe fn test_mm_i32scatter_ps() {
8062 let mut base_addr: [f32; 4] = [0.; 4];
8063 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8064 let src = _mm_setr_ps(2., 3., 4., 1.);
8065 _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8066 let expected = [1., 2., 3., 4.];
8067 assert_eq!(expected, base_addr);
8068 }
8069
8070 #[simd_test(enable = "avx512f,avx512vl")]
8071 unsafe fn test_mm_mask_i32scatter_ps() {
8072 let mut base_addr: [f32; 4] = [0.; 4];
8073 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8074 let src = _mm_setr_ps(2., 3., 4., 1.);
8075 _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8076 let expected = [0., 2., 0., 4.];
8077 assert_eq!(expected, base_addr);
8078 }
8079
8080 #[simd_test(enable = "avx512f,avx512vl")]
8081 unsafe fn test_mm_i64scatter_epi32() {
8082 let mut base_addr: [i32; 2] = [0; 2];
8083 let vindex = _mm_setr_epi64x(1, 0);
8084 let src = _mm_setr_epi32(2, 1, -1, -1);
8085 _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8086 let expected = [1, 2];
8087 assert_eq!(expected, base_addr);
8088 }
8089
8090 #[simd_test(enable = "avx512f,avx512vl")]
8091 unsafe fn test_mm_mask_i64scatter_epi32() {
8092 let mut base_addr: [i32; 2] = [0; 2];
8093 let vindex = _mm_setr_epi64x(1, 0);
8094 let src = _mm_setr_epi32(2, 1, -1, -1);
8095 _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8096 let expected = [0, 2];
8097 assert_eq!(expected, base_addr);
8098 }
8099
8100 #[simd_test(enable = "avx512f,avx512vl")]
8101 unsafe fn test_mm_i64scatter_epi64() {
8102 let mut base_addr: [i64; 2] = [0; 2];
8103 let vindex = _mm_setr_epi64x(1, 0);
8104 let src = _mm_setr_epi64x(2, 1);
8105 _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8106 let expected = [1, 2];
8107 assert_eq!(expected, base_addr);
8108 }
8109
8110 #[simd_test(enable = "avx512f,avx512vl")]
8111 unsafe fn test_mm_mask_i64scatter_epi64() {
8112 let mut base_addr: [i64; 2] = [0; 2];
8113 let vindex = _mm_setr_epi64x(1, 0);
8114 let src = _mm_setr_epi64x(2, 1);
8115 _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8116 let expected = [0, 2];
8117 assert_eq!(expected, base_addr);
8118 }
8119
8120 #[simd_test(enable = "avx512f,avx512vl")]
8121 unsafe fn test_mm_i64scatter_pd() {
8122 let mut base_addr: [f64; 2] = [0.; 2];
8123 let vindex = _mm_setr_epi64x(1, 0);
8124 let src = _mm_setr_pd(2., 1.);
8125 _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8126 let expected = [1., 2.];
8127 assert_eq!(expected, base_addr);
8128 }
8129
8130 #[simd_test(enable = "avx512f,avx512vl")]
8131 unsafe fn test_mm_mask_i64scatter_pd() {
8132 let mut base_addr: [f64; 2] = [0.; 2];
8133 let vindex = _mm_setr_epi64x(1, 0);
8134 let src = _mm_setr_pd(2., 1.);
8135 _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8136 let expected = [0., 2.];
8137 assert_eq!(expected, base_addr);
8138 }
8139
8140 #[simd_test(enable = "avx512f,avx512vl")]
8141 unsafe fn test_mm_i64scatter_ps() {
8142 let mut base_addr: [f32; 2] = [0.; 2];
8143 let vindex = _mm_setr_epi64x(1, 0);
8144 let src = _mm_setr_ps(2., 1., -1., -1.);
8145 _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8146 let expected = [1., 2.];
8147 assert_eq!(expected, base_addr);
8148 }
8149
8150 #[simd_test(enable = "avx512f,avx512vl")]
8151 unsafe fn test_mm_mask_i64scatter_ps() {
8152 let mut base_addr: [f32; 2] = [0.; 2];
8153 let vindex = _mm_setr_epi64x(1, 0);
8154 let src = _mm_setr_ps(2., 1., -1., -1.);
8155 _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8156 let expected = [0., 2.];
8157 assert_eq!(expected, base_addr);
8158 }
8159
8160 #[simd_test(enable = "avx512f,avx512vl")]
8161 unsafe fn test_mm256_i32scatter_epi32() {
8162 let mut base_addr: [i32; 8] = [0; 8];
8163 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8164 let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8165 _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8166 let expected = [1, 2, 3, 4, 5, 6, 7, 8];
8167 assert_eq!(expected, base_addr);
8168 }
8169
8170 #[simd_test(enable = "avx512f,avx512vl")]
8171 unsafe fn test_mm256_mask_i32scatter_epi32() {
8172 let mut base_addr: [i32; 8] = [0; 8];
8173 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8174 let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8175 _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
8176 let expected = [0, 2, 0, 4, 0, 6, 0, 8];
8177 assert_eq!(expected, base_addr);
8178 }
8179
8180 #[simd_test(enable = "avx512f,avx512vl")]
8181 unsafe fn test_mm256_i32scatter_epi64() {
8182 let mut base_addr: [i64; 4] = [0; 4];
8183 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8184 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8185 _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8186 let expected = [1, 2, 3, 4];
8187 assert_eq!(expected, base_addr);
8188 }
8189
8190 #[simd_test(enable = "avx512f,avx512vl")]
8191 unsafe fn test_mm256_mask_i32scatter_epi64() {
8192 let mut base_addr: [i64; 4] = [0; 4];
8193 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8194 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8195 _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8196 let expected = [0, 2, 0, 4];
8197 assert_eq!(expected, base_addr);
8198 }
8199
8200 #[simd_test(enable = "avx512f,avx512vl")]
8201 unsafe fn test_mm256_i32scatter_pd() {
8202 let mut base_addr: [f64; 4] = [0.; 4];
8203 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8204 let src = _mm256_setr_pd(2., 3., 4., 1.);
8205 _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8206 let expected = [1., 2., 3., 4.];
8207 assert_eq!(expected, base_addr);
8208 }
8209
8210 #[simd_test(enable = "avx512f,avx512vl")]
8211 unsafe fn test_mm256_mask_i32scatter_pd() {
8212 let mut base_addr: [f64; 4] = [0.; 4];
8213 let vindex = _mm_setr_epi32(1, 2, 3, 0);
8214 let src = _mm256_setr_pd(2., 3., 4., 1.);
8215 _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8216 let expected = [0., 2., 0., 4.];
8217 assert_eq!(expected, base_addr);
8218 }
8219
8220 #[simd_test(enable = "avx512f,avx512vl")]
8221 unsafe fn test_mm256_i32scatter_ps() {
8222 let mut base_addr: [f32; 8] = [0.; 8];
8223 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8224 let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8225 _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8226 let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
8227 assert_eq!(expected, base_addr);
8228 }
8229
8230 #[simd_test(enable = "avx512f,avx512vl")]
8231 unsafe fn test_mm256_mask_i32scatter_ps() {
8232 let mut base_addr: [f32; 8] = [0.; 8];
8233 let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8234 let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8235 _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
8236 let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
8237 assert_eq!(expected, base_addr);
8238 }
8239
8240 #[simd_test(enable = "avx512f,avx512vl")]
8241 unsafe fn test_mm256_i64scatter_epi32() {
8242 let mut base_addr: [i32; 4] = [0; 4];
8243 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8244 let src = _mm_setr_epi32(2, 3, 4, 1);
8245 _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8246 let expected = [1, 2, 3, 4];
8247 assert_eq!(expected, base_addr);
8248 }
8249
8250 #[simd_test(enable = "avx512f,avx512vl")]
8251 unsafe fn test_mm256_mask_i64scatter_epi32() {
8252 let mut base_addr: [i32; 4] = [0; 4];
8253 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8254 let src = _mm_setr_epi32(2, 3, 4, 1);
8255 _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8256 let expected = [0, 2, 0, 4];
8257 assert_eq!(expected, base_addr);
8258 }
8259
8260 #[simd_test(enable = "avx512f,avx512vl")]
8261 unsafe fn test_mm256_i64scatter_epi64() {
8262 let mut base_addr: [i64; 4] = [0; 4];
8263 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8264 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8265 _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8266 let expected = [1, 2, 3, 4];
8267 assert_eq!(expected, base_addr);
8268 }
8269
8270 #[simd_test(enable = "avx512f,avx512vl")]
8271 unsafe fn test_mm256_mask_i64scatter_epi64() {
8272 let mut base_addr: [i64; 4] = [0; 4];
8273 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8274 let src = _mm256_setr_epi64x(2, 3, 4, 1);
8275 _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8276 let expected = [0, 2, 0, 4];
8277 assert_eq!(expected, base_addr);
8278 }
8279
8280 #[simd_test(enable = "avx512f,avx512vl")]
8281 unsafe fn test_mm256_i64scatter_pd() {
8282 let mut base_addr: [f64; 4] = [0.; 4];
8283 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8284 let src = _mm256_setr_pd(2., 3., 4., 1.);
8285 _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8286 let expected = [1., 2., 3., 4.];
8287 assert_eq!(expected, base_addr);
8288 }
8289
8290 #[simd_test(enable = "avx512f,avx512vl")]
8291 unsafe fn test_mm256_mask_i64scatter_pd() {
8292 let mut base_addr: [f64; 4] = [0.; 4];
8293 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8294 let src = _mm256_setr_pd(2., 3., 4., 1.);
8295 _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8296 let expected = [0., 2., 0., 4.];
8297 assert_eq!(expected, base_addr);
8298 }
8299
8300 #[simd_test(enable = "avx512f,avx512vl")]
8301 unsafe fn test_mm256_i64scatter_ps() {
8302 let mut base_addr: [f32; 4] = [0.; 4];
8303 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8304 let src = _mm_setr_ps(2., 3., 4., 1.);
8305 _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8306 let expected = [1., 2., 3., 4.];
8307 assert_eq!(expected, base_addr);
8308 }
8309
8310 #[simd_test(enable = "avx512f,avx512vl")]
8311 unsafe fn test_mm256_mask_i64scatter_ps() {
8312 let mut base_addr: [f32; 4] = [0.; 4];
8313 let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8314 let src = _mm_setr_ps(2., 3., 4., 1.);
8315 _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8316 let expected = [0., 2., 0., 4.];
8317 assert_eq!(expected, base_addr);
8318 }
8319
8320 #[simd_test(enable = "avx512f")]
8321 const unsafe fn test_mm512_rol_epi64() {
8322 #[rustfmt::skip]
8323 let a = _mm512_set_epi64(
8324 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8325 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8326 );
8327 let r = _mm512_rol_epi64::<1>(a);
8328 #[rustfmt::skip]
8329 let e = _mm512_set_epi64(
8330 1 << 0, 1 << 33, 1 << 33, 1 << 33,
8331 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8332 );
8333 assert_eq_m512i(r, e);
8334 }
8335
8336 #[simd_test(enable = "avx512f")]
8337 const unsafe fn test_mm512_mask_rol_epi64() {
8338 #[rustfmt::skip]
8339 let a = _mm512_set_epi64(
8340 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8341 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8342 );
8343 let r = _mm512_mask_rol_epi64::<1>(a, 0, a);
8344 assert_eq_m512i(r, a);
8345 let r = _mm512_mask_rol_epi64::<1>(a, 0b11111111, a);
8346 #[rustfmt::skip]
8347 let e = _mm512_set_epi64(
8348 1 << 0, 1 << 33, 1 << 33, 1 << 33,
8349 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8350 );
8351 assert_eq_m512i(r, e);
8352 }
8353
8354 #[simd_test(enable = "avx512f")]
8355 const unsafe fn test_mm512_maskz_rol_epi64() {
8356 #[rustfmt::skip]
8357 let a = _mm512_set_epi64(
8358 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8359 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8360 );
8361 let r = _mm512_maskz_rol_epi64::<1>(0, a);
8362 assert_eq_m512i(r, _mm512_setzero_si512());
8363 let r = _mm512_maskz_rol_epi64::<1>(0b00001111, a);
8364 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 1 << 0);
8365 assert_eq_m512i(r, e);
8366 }
8367
8368 #[simd_test(enable = "avx512f,avx512vl")]
8369 const unsafe fn test_mm256_rol_epi64() {
8370 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8371 let r = _mm256_rol_epi64::<1>(a);
8372 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8373 assert_eq_m256i(r, e);
8374 }
8375
8376 #[simd_test(enable = "avx512f,avx512vl")]
8377 const unsafe fn test_mm256_mask_rol_epi64() {
8378 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8379 let r = _mm256_mask_rol_epi64::<1>(a, 0, a);
8380 assert_eq_m256i(r, a);
8381 let r = _mm256_mask_rol_epi64::<1>(a, 0b00001111, a);
8382 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8383 assert_eq_m256i(r, e);
8384 }
8385
8386 #[simd_test(enable = "avx512f,avx512vl")]
8387 const unsafe fn test_mm256_maskz_rol_epi64() {
8388 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8389 let r = _mm256_maskz_rol_epi64::<1>(0, a);
8390 assert_eq_m256i(r, _mm256_setzero_si256());
8391 let r = _mm256_maskz_rol_epi64::<1>(0b00001111, a);
8392 let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8393 assert_eq_m256i(r, e);
8394 }
8395
8396 #[simd_test(enable = "avx512f,avx512vl")]
8397 const unsafe fn test_mm_rol_epi64() {
8398 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8399 let r = _mm_rol_epi64::<1>(a);
8400 let e = _mm_set_epi64x(1 << 0, 1 << 33);
8401 assert_eq_m128i(r, e);
8402 }
8403
8404 #[simd_test(enable = "avx512f,avx512vl")]
8405 const unsafe fn test_mm_mask_rol_epi64() {
8406 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8407 let r = _mm_mask_rol_epi64::<1>(a, 0, a);
8408 assert_eq_m128i(r, a);
8409 let r = _mm_mask_rol_epi64::<1>(a, 0b00000011, a);
8410 let e = _mm_set_epi64x(1 << 0, 1 << 33);
8411 assert_eq_m128i(r, e);
8412 }
8413
8414 #[simd_test(enable = "avx512f,avx512vl")]
8415 const unsafe fn test_mm_maskz_rol_epi64() {
8416 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8417 let r = _mm_maskz_rol_epi64::<1>(0, a);
8418 assert_eq_m128i(r, _mm_setzero_si128());
8419 let r = _mm_maskz_rol_epi64::<1>(0b00000011, a);
8420 let e = _mm_set_epi64x(1 << 0, 1 << 33);
8421 assert_eq_m128i(r, e);
8422 }
8423
8424 #[simd_test(enable = "avx512f")]
8425 const unsafe fn test_mm512_ror_epi64() {
8426 #[rustfmt::skip]
8427 let a = _mm512_set_epi64(
8428 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8429 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8430 );
8431 let r = _mm512_ror_epi64::<1>(a);
8432 #[rustfmt::skip]
8433 let e = _mm512_set_epi64(
8434 1 << 63, 1 << 31, 1 << 31, 1 << 31,
8435 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8436 );
8437 assert_eq_m512i(r, e);
8438 }
8439
8440 #[simd_test(enable = "avx512f")]
8441 const unsafe fn test_mm512_mask_ror_epi64() {
8442 #[rustfmt::skip]
8443 let a = _mm512_set_epi64(
8444 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8445 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8446 );
8447 let r = _mm512_mask_ror_epi64::<1>(a, 0, a);
8448 assert_eq_m512i(r, a);
8449 let r = _mm512_mask_ror_epi64::<1>(a, 0b11111111, a);
8450 #[rustfmt::skip]
8451 let e = _mm512_set_epi64(
8452 1 << 63, 1 << 31, 1 << 31, 1 << 31,
8453 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8454 );
8455 assert_eq_m512i(r, e);
8456 }
8457
8458 #[simd_test(enable = "avx512f")]
8459 const unsafe fn test_mm512_maskz_ror_epi64() {
8460 #[rustfmt::skip]
8461 let a = _mm512_set_epi64(
8462 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8463 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8464 );
8465 let r = _mm512_maskz_ror_epi64::<1>(0, a);
8466 assert_eq_m512i(r, _mm512_setzero_si512());
8467 let r = _mm512_maskz_ror_epi64::<1>(0b00001111, a);
8468 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 1 << 63);
8469 assert_eq_m512i(r, e);
8470 }
8471
8472 #[simd_test(enable = "avx512f,avx512vl")]
8473 const unsafe fn test_mm256_ror_epi64() {
8474 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8475 let r = _mm256_ror_epi64::<1>(a);
8476 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8477 assert_eq_m256i(r, e);
8478 }
8479
8480 #[simd_test(enable = "avx512f,avx512vl")]
8481 const unsafe fn test_mm256_mask_ror_epi64() {
8482 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8483 let r = _mm256_mask_ror_epi64::<1>(a, 0, a);
8484 assert_eq_m256i(r, a);
8485 let r = _mm256_mask_ror_epi64::<1>(a, 0b00001111, a);
8486 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8487 assert_eq_m256i(r, e);
8488 }
8489
8490 #[simd_test(enable = "avx512f,avx512vl")]
8491 const unsafe fn test_mm256_maskz_ror_epi64() {
8492 let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8493 let r = _mm256_maskz_ror_epi64::<1>(0, a);
8494 assert_eq_m256i(r, _mm256_setzero_si256());
8495 let r = _mm256_maskz_ror_epi64::<1>(0b00001111, a);
8496 let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8497 assert_eq_m256i(r, e);
8498 }
8499
8500 #[simd_test(enable = "avx512f,avx512vl")]
8501 const unsafe fn test_mm_ror_epi64() {
8502 let a = _mm_set_epi64x(1 << 0, 1 << 32);
8503 let r = _mm_ror_epi64::<1>(a);
8504 let e = _mm_set_epi64x(1 << 63, 1 << 31);
8505 assert_eq_m128i(r, e);
8506 }
8507
8508 #[simd_test(enable = "avx512f,avx512vl")]
8509 const unsafe fn test_mm_mask_ror_epi64() {
8510 let a = _mm_set_epi64x(1 << 0, 1 << 32);
8511 let r = _mm_mask_ror_epi64::<1>(a, 0, a);
8512 assert_eq_m128i(r, a);
8513 let r = _mm_mask_ror_epi64::<1>(a, 0b00000011, a);
8514 let e = _mm_set_epi64x(1 << 63, 1 << 31);
8515 assert_eq_m128i(r, e);
8516 }
8517
8518 #[simd_test(enable = "avx512f,avx512vl")]
8519 const unsafe fn test_mm_maskz_ror_epi64() {
8520 let a = _mm_set_epi64x(1 << 0, 1 << 32);
8521 let r = _mm_maskz_ror_epi64::<1>(0, a);
8522 assert_eq_m128i(r, _mm_setzero_si128());
8523 let r = _mm_maskz_ror_epi64::<1>(0b00000011, a);
8524 let e = _mm_set_epi64x(1 << 63, 1 << 31);
8525 assert_eq_m128i(r, e);
8526 }
8527
8528 #[simd_test(enable = "avx512f")]
8529 const unsafe fn test_mm512_slli_epi64() {
8530 #[rustfmt::skip]
8531 let a = _mm512_set_epi64(
8532 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8533 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8534 );
8535 let r = _mm512_slli_epi64::<1>(a);
8536 #[rustfmt::skip]
8537 let e = _mm512_set_epi64(
8538 0, 1 << 33, 1 << 33, 1 << 33,
8539 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8540 );
8541 assert_eq_m512i(r, e);
8542 }
8543
8544 #[simd_test(enable = "avx512f")]
8545 const unsafe fn test_mm512_mask_slli_epi64() {
8546 #[rustfmt::skip]
8547 let a = _mm512_set_epi64(
8548 1 << 63, 1 << 32, 1 << 32, 1 << 32,
8549 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8550 );
8551 let r = _mm512_mask_slli_epi64::<1>(a, 0, a);
8552 assert_eq_m512i(r, a);
8553 let r = _mm512_mask_slli_epi64::<1>(a, 0b11111111, a);
8554 #[rustfmt::skip]
8555 let e = _mm512_set_epi64(
8556 0, 1 << 33, 1 << 33, 1 << 33,
8557 1 << 33, 1 << 33, 1 << 33, 1 << 33,
8558 );
8559 assert_eq_m512i(r, e);
8560 }
8561
8562 #[simd_test(enable = "avx512f")]
8563 const unsafe fn test_mm512_maskz_slli_epi64() {
8564 #[rustfmt::skip]
8565 let a = _mm512_set_epi64(
8566 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8567 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8568 );
8569 let r = _mm512_maskz_slli_epi64::<1>(0, a);
8570 assert_eq_m512i(r, _mm512_setzero_si512());
8571 let r = _mm512_maskz_slli_epi64::<1>(0b00001111, a);
8572 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
8573 assert_eq_m512i(r, e);
8574 }
8575
8576 #[simd_test(enable = "avx512f,avx512vl")]
8577 const unsafe fn test_mm256_mask_slli_epi64() {
8578 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8579 let r = _mm256_mask_slli_epi64::<1>(a, 0, a);
8580 assert_eq_m256i(r, a);
8581 let r = _mm256_mask_slli_epi64::<1>(a, 0b00001111, a);
8582 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8583 assert_eq_m256i(r, e);
8584 }
8585
8586 #[simd_test(enable = "avx512f,avx512vl")]
8587 const unsafe fn test_mm256_maskz_slli_epi64() {
8588 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8589 let r = _mm256_maskz_slli_epi64::<1>(0, a);
8590 assert_eq_m256i(r, _mm256_setzero_si256());
8591 let r = _mm256_maskz_slli_epi64::<1>(0b00001111, a);
8592 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8593 assert_eq_m256i(r, e);
8594 }
8595
8596 #[simd_test(enable = "avx512f,avx512vl")]
8597 const unsafe fn test_mm_mask_slli_epi64() {
8598 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8599 let r = _mm_mask_slli_epi64::<1>(a, 0, a);
8600 assert_eq_m128i(r, a);
8601 let r = _mm_mask_slli_epi64::<1>(a, 0b00000011, a);
8602 let e = _mm_set_epi64x(0, 1 << 33);
8603 assert_eq_m128i(r, e);
8604 }
8605
8606 #[simd_test(enable = "avx512f,avx512vl")]
8607 const unsafe fn test_mm_maskz_slli_epi64() {
8608 let a = _mm_set_epi64x(1 << 63, 1 << 32);
8609 let r = _mm_maskz_slli_epi64::<1>(0, a);
8610 assert_eq_m128i(r, _mm_setzero_si128());
8611 let r = _mm_maskz_slli_epi64::<1>(0b00000011, a);
8612 let e = _mm_set_epi64x(0, 1 << 33);
8613 assert_eq_m128i(r, e);
8614 }
8615
8616 #[simd_test(enable = "avx512f")]
8617 const unsafe fn test_mm512_srli_epi64() {
8618 #[rustfmt::skip]
8619 let a = _mm512_set_epi64(
8620 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8621 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8622 );
8623 let r = _mm512_srli_epi64::<1>(a);
8624 #[rustfmt::skip]
8625 let e = _mm512_set_epi64(
8626 0, 1 << 31, 1 << 31, 1 << 31,
8627 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8628 );
8629 assert_eq_m512i(r, e);
8630 }
8631
8632 #[simd_test(enable = "avx512f")]
8633 const unsafe fn test_mm512_mask_srli_epi64() {
8634 #[rustfmt::skip]
8635 let a = _mm512_set_epi64(
8636 1 << 0, 1 << 32, 1 << 32, 1 << 32,
8637 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8638 );
8639 let r = _mm512_mask_srli_epi64::<1>(a, 0, a);
8640 assert_eq_m512i(r, a);
8641 let r = _mm512_mask_srli_epi64::<1>(a, 0b11111111, a);
8642 #[rustfmt::skip]
8643 let e = _mm512_set_epi64(
8644 0, 1 << 31, 1 << 31, 1 << 31,
8645 1 << 31, 1 << 31, 1 << 31, 1 << 31,
8646 );
8647 assert_eq_m512i(r, e);
8648 }
8649
8650 #[simd_test(enable = "avx512f")]
8651 const unsafe fn test_mm512_maskz_srli_epi64() {
8652 #[rustfmt::skip]
8653 let a = _mm512_set_epi64(
8654 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8655 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8656 );
8657 let r = _mm512_maskz_srli_epi64::<1>(0, a);
8658 assert_eq_m512i(r, _mm512_setzero_si512());
8659 let r = _mm512_maskz_srli_epi64::<1>(0b00001111, a);
8660 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
8661 assert_eq_m512i(r, e);
8662 }
8663
8664 #[simd_test(enable = "avx512f,avx512vl")]
8665 const unsafe fn test_mm256_mask_srli_epi64() {
8666 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8667 let r = _mm256_mask_srli_epi64::<1>(a, 0, a);
8668 assert_eq_m256i(r, a);
8669 let r = _mm256_mask_srli_epi64::<1>(a, 0b00001111, a);
8670 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8671 assert_eq_m256i(r, e);
8672 }
8673
8674 #[simd_test(enable = "avx512f,avx512vl")]
8675 const unsafe fn test_mm256_maskz_srli_epi64() {
8676 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8677 let r = _mm256_maskz_srli_epi64::<1>(0, a);
8678 assert_eq_m256i(r, _mm256_setzero_si256());
8679 let r = _mm256_maskz_srli_epi64::<1>(0b00001111, a);
8680 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8681 assert_eq_m256i(r, e);
8682 }
8683
8684 #[simd_test(enable = "avx512f,avx512vl")]
8685 const unsafe fn test_mm_mask_srli_epi64() {
8686 let a = _mm_set_epi64x(1 << 5, 0);
8687 let r = _mm_mask_srli_epi64::<1>(a, 0, a);
8688 assert_eq_m128i(r, a);
8689 let r = _mm_mask_srli_epi64::<1>(a, 0b00000011, a);
8690 let e = _mm_set_epi64x(1 << 4, 0);
8691 assert_eq_m128i(r, e);
8692 }
8693
8694 #[simd_test(enable = "avx512f,avx512vl")]
8695 const unsafe fn test_mm_maskz_srli_epi64() {
8696 let a = _mm_set_epi64x(1 << 5, 0);
8697 let r = _mm_maskz_srli_epi64::<1>(0, a);
8698 assert_eq_m128i(r, _mm_setzero_si128());
8699 let r = _mm_maskz_srli_epi64::<1>(0b00000011, a);
8700 let e = _mm_set_epi64x(1 << 4, 0);
8701 assert_eq_m128i(r, e);
8702 }
8703
8704 #[simd_test(enable = "avx512f")]
8705 const unsafe fn test_mm512_rolv_epi64() {
8706 #[rustfmt::skip]
8707 let a = _mm512_set_epi64(
8708 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8709 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8710 );
8711 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8712 let r = _mm512_rolv_epi64(a, b);
8713 #[rustfmt::skip]
8714 let e = _mm512_set_epi64(
8715 1 << 32, 1 << 0, 1 << 34, 1 << 35,
8716 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8717 );
8718 assert_eq_m512i(r, e);
8719 }
8720
8721 #[simd_test(enable = "avx512f")]
8722 const unsafe fn test_mm512_mask_rolv_epi64() {
8723 #[rustfmt::skip]
8724 let a = _mm512_set_epi64(
8725 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8726 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8727 );
8728 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8729 let r = _mm512_mask_rolv_epi64(a, 0, a, b);
8730 assert_eq_m512i(r, a);
8731 let r = _mm512_mask_rolv_epi64(a, 0b11111111, a, b);
8732 #[rustfmt::skip]
8733 let e = _mm512_set_epi64(
8734 1 << 32, 1 << 0, 1 << 34, 1 << 35,
8735 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8736 );
8737 assert_eq_m512i(r, e);
8738 }
8739
8740 #[simd_test(enable = "avx512f")]
8741 const unsafe fn test_mm512_maskz_rolv_epi64() {
8742 #[rustfmt::skip]
8743 let a = _mm512_set_epi64(
8744 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8745 1 << 32, 1 << 32, 1 << 32, 1 << 62,
8746 );
8747 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8748 let r = _mm512_maskz_rolv_epi64(0, a, b);
8749 assert_eq_m512i(r, _mm512_setzero_si512());
8750 let r = _mm512_maskz_rolv_epi64(0b00001111, a, b);
8751 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 1 << 0);
8752 assert_eq_m512i(r, e);
8753 }
8754
8755 #[simd_test(enable = "avx512f,avx512vl")]
8756 const unsafe fn test_mm256_rolv_epi64() {
8757 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8758 let b = _mm256_set_epi64x(0, 1, 2, 3);
8759 let r = _mm256_rolv_epi64(a, b);
8760 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8761 assert_eq_m256i(r, e);
8762 }
8763
8764 #[simd_test(enable = "avx512f,avx512vl")]
8765 const unsafe fn test_mm256_mask_rolv_epi64() {
8766 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8767 let b = _mm256_set_epi64x(0, 1, 2, 3);
8768 let r = _mm256_mask_rolv_epi64(a, 0, a, b);
8769 assert_eq_m256i(r, a);
8770 let r = _mm256_mask_rolv_epi64(a, 0b00001111, a, b);
8771 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8772 assert_eq_m256i(r, e);
8773 }
8774
8775 #[simd_test(enable = "avx512f,avx512vl")]
8776 const unsafe fn test_mm256_maskz_rolv_epi64() {
8777 let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8778 let b = _mm256_set_epi64x(0, 1, 2, 3);
8779 let r = _mm256_maskz_rolv_epi64(0, a, b);
8780 assert_eq_m256i(r, _mm256_setzero_si256());
8781 let r = _mm256_maskz_rolv_epi64(0b00001111, a, b);
8782 let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8783 assert_eq_m256i(r, e);
8784 }
8785
8786 #[simd_test(enable = "avx512f,avx512vl")]
8787 const unsafe fn test_mm_rolv_epi64() {
8788 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8789 let b = _mm_set_epi64x(0, 1);
8790 let r = _mm_rolv_epi64(a, b);
8791 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8792 assert_eq_m128i(r, e);
8793 }
8794
8795 #[simd_test(enable = "avx512f,avx512vl")]
8796 const unsafe fn test_mm_mask_rolv_epi64() {
8797 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8798 let b = _mm_set_epi64x(0, 1);
8799 let r = _mm_mask_rolv_epi64(a, 0, a, b);
8800 assert_eq_m128i(r, a);
8801 let r = _mm_mask_rolv_epi64(a, 0b00000011, a, b);
8802 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8803 assert_eq_m128i(r, e);
8804 }
8805
8806 #[simd_test(enable = "avx512f,avx512vl")]
8807 const unsafe fn test_mm_maskz_rolv_epi64() {
8808 let a = _mm_set_epi64x(1 << 32, 1 << 63);
8809 let b = _mm_set_epi64x(0, 1);
8810 let r = _mm_maskz_rolv_epi64(0, a, b);
8811 assert_eq_m128i(r, _mm_setzero_si128());
8812 let r = _mm_maskz_rolv_epi64(0b00000011, a, b);
8813 let e = _mm_set_epi64x(1 << 32, 1 << 0);
8814 assert_eq_m128i(r, e);
8815 }
8816
8817 #[simd_test(enable = "avx512f")]
8818 const unsafe fn test_mm512_rorv_epi64() {
8819 #[rustfmt::skip]
8820 let a = _mm512_set_epi64(
8821 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8822 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8823 );
8824 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8825 let r = _mm512_rorv_epi64(a, b);
8826 #[rustfmt::skip]
8827 let e = _mm512_set_epi64(
8828 1 << 32, 1 << 63, 1 << 30, 1 << 29,
8829 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8830 );
8831 assert_eq_m512i(r, e);
8832 }
8833
8834 #[simd_test(enable = "avx512f")]
8835 const unsafe fn test_mm512_mask_rorv_epi64() {
8836 #[rustfmt::skip]
8837 let a = _mm512_set_epi64(
8838 1 << 32, 1 << 0, 1 << 32, 1 << 32,
8839 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8840 );
8841 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8842 let r = _mm512_mask_rorv_epi64(a, 0, a, b);
8843 assert_eq_m512i(r, a);
8844 let r = _mm512_mask_rorv_epi64(a, 0b11111111, a, b);
8845 #[rustfmt::skip]
8846 let e = _mm512_set_epi64(
8847 1 << 32, 1 << 63, 1 << 30, 1 << 29,
8848 1 << 28, 1 << 27, 1 << 26, 1 << 25,
8849 );
8850 assert_eq_m512i(r, e);
8851 }
8852
8853 #[simd_test(enable = "avx512f")]
8854 const unsafe fn test_mm512_maskz_rorv_epi64() {
8855 #[rustfmt::skip]
8856 let a = _mm512_set_epi64(
8857 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8858 1 << 32, 1 << 32, 1 << 32, 1 << 0,
8859 );
8860 let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8861 let r = _mm512_maskz_rorv_epi64(0, a, b);
8862 assert_eq_m512i(r, _mm512_setzero_si512());
8863 let r = _mm512_maskz_rorv_epi64(0b00001111, a, b);
8864 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 1 << 62);
8865 assert_eq_m512i(r, e);
8866 }
8867
8868 #[simd_test(enable = "avx512f,avx512vl")]
8869 const unsafe fn test_mm256_rorv_epi64() {
8870 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8871 let b = _mm256_set_epi64x(0, 1, 2, 3);
8872 let r = _mm256_rorv_epi64(a, b);
8873 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8874 assert_eq_m256i(r, e);
8875 }
8876
8877 #[simd_test(enable = "avx512f,avx512vl")]
8878 const unsafe fn test_mm256_mask_rorv_epi64() {
8879 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8880 let b = _mm256_set_epi64x(0, 1, 2, 3);
8881 let r = _mm256_mask_rorv_epi64(a, 0, a, b);
8882 assert_eq_m256i(r, a);
8883 let r = _mm256_mask_rorv_epi64(a, 0b00001111, a, b);
8884 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8885 assert_eq_m256i(r, e);
8886 }
8887
8888 #[simd_test(enable = "avx512f,avx512vl")]
8889 const unsafe fn test_mm256_maskz_rorv_epi64() {
8890 let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8891 let b = _mm256_set_epi64x(0, 1, 2, 3);
8892 let r = _mm256_maskz_rorv_epi64(0, a, b);
8893 assert_eq_m256i(r, _mm256_setzero_si256());
8894 let r = _mm256_maskz_rorv_epi64(0b00001111, a, b);
8895 let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8896 assert_eq_m256i(r, e);
8897 }
8898
8899 #[simd_test(enable = "avx512f,avx512vl")]
8900 const unsafe fn test_mm_rorv_epi64() {
8901 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8902 let b = _mm_set_epi64x(0, 1);
8903 let r = _mm_rorv_epi64(a, b);
8904 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8905 assert_eq_m128i(r, e);
8906 }
8907
8908 #[simd_test(enable = "avx512f,avx512vl")]
8909 const unsafe fn test_mm_mask_rorv_epi64() {
8910 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8911 let b = _mm_set_epi64x(0, 1);
8912 let r = _mm_mask_rorv_epi64(a, 0, a, b);
8913 assert_eq_m128i(r, a);
8914 let r = _mm_mask_rorv_epi64(a, 0b00000011, a, b);
8915 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8916 assert_eq_m128i(r, e);
8917 }
8918
8919 #[simd_test(enable = "avx512f,avx512vl")]
8920 const unsafe fn test_mm_maskz_rorv_epi64() {
8921 let a = _mm_set_epi64x(1 << 32, 1 << 0);
8922 let b = _mm_set_epi64x(0, 1);
8923 let r = _mm_maskz_rorv_epi64(0, a, b);
8924 assert_eq_m128i(r, _mm_setzero_si128());
8925 let r = _mm_maskz_rorv_epi64(0b00000011, a, b);
8926 let e = _mm_set_epi64x(1 << 32, 1 << 63);
8927 assert_eq_m128i(r, e);
8928 }
8929
8930 #[simd_test(enable = "avx512f")]
8931 const unsafe fn test_mm512_sllv_epi64() {
8932 #[rustfmt::skip]
8933 let a = _mm512_set_epi64(
8934 1 << 32, 1 << 63, 1 << 32, 1 << 32,
8935 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8936 );
8937 let count = _mm512_set_epi64(0, 2, 2, 3, 4, 5, 6, 7);
8938 let r = _mm512_sllv_epi64(a, count);
8939 #[rustfmt::skip]
8940 let e = _mm512_set_epi64(
8941 1 << 32, 0, 1 << 34, 1 << 35,
8942 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8943 );
8944 assert_eq_m512i(r, e);
8945 }
8946
8947 #[simd_test(enable = "avx512f")]
8948 const unsafe fn test_mm512_mask_sllv_epi64() {
8949 #[rustfmt::skip]
8950 let a = _mm512_set_epi64(
8951 1 << 32, 1 << 32, 1 << 63, 1 << 32,
8952 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8953 );
8954 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8955 let r = _mm512_mask_sllv_epi64(a, 0, a, count);
8956 assert_eq_m512i(r, a);
8957 let r = _mm512_mask_sllv_epi64(a, 0b11111111, a, count);
8958 #[rustfmt::skip]
8959 let e = _mm512_set_epi64(
8960 1 << 32, 1 << 33, 0, 1 << 35,
8961 1 << 36, 1 << 37, 1 << 38, 1 << 39,
8962 );
8963 assert_eq_m512i(r, e);
8964 }
8965
8966 #[simd_test(enable = "avx512f")]
8967 const unsafe fn test_mm512_maskz_sllv_epi64() {
8968 #[rustfmt::skip]
8969 let a = _mm512_set_epi64(
8970 1 << 32, 1 << 32, 1 << 32, 1 << 32,
8971 1 << 32, 1 << 32, 1 << 32, 1 << 63,
8972 );
8973 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 1);
8974 let r = _mm512_maskz_sllv_epi64(0, a, count);
8975 assert_eq_m512i(r, _mm512_setzero_si512());
8976 let r = _mm512_maskz_sllv_epi64(0b00001111, a, count);
8977 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 0);
8978 assert_eq_m512i(r, e);
8979 }
8980
8981 #[simd_test(enable = "avx512f,avx512vl")]
8982 const unsafe fn test_mm256_mask_sllv_epi64() {
8983 let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8984 let count = _mm256_set_epi64x(0, 1, 2, 3);
8985 let r = _mm256_mask_sllv_epi64(a, 0, a, count);
8986 assert_eq_m256i(r, a);
8987 let r = _mm256_mask_sllv_epi64(a, 0b00001111, a, count);
8988 let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
8989 assert_eq_m256i(r, e);
8990 }
8991
8992 #[simd_test(enable = "avx512f,avx512vl")]
8993 const unsafe fn test_mm256_maskz_sllv_epi64() {
8994 let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
8995 let count = _mm256_set_epi64x(0, 1, 2, 3);
8996 let r = _mm256_maskz_sllv_epi64(0, a, count);
8997 assert_eq_m256i(r, _mm256_setzero_si256());
8998 let r = _mm256_maskz_sllv_epi64(0b00001111, a, count);
8999 let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
9000 assert_eq_m256i(r, e);
9001 }
9002
9003 #[simd_test(enable = "avx512f,avx512vl")]
9004 const unsafe fn test_mm_mask_sllv_epi64() {
9005 let a = _mm_set_epi64x(1 << 63, 1 << 32);
9006 let count = _mm_set_epi64x(2, 3);
9007 let r = _mm_mask_sllv_epi64(a, 0, a, count);
9008 assert_eq_m128i(r, a);
9009 let r = _mm_mask_sllv_epi64(a, 0b00000011, a, count);
9010 let e = _mm_set_epi64x(0, 1 << 35);
9011 assert_eq_m128i(r, e);
9012 }
9013
9014 #[simd_test(enable = "avx512f,avx512vl")]
9015 const unsafe fn test_mm_maskz_sllv_epi64() {
9016 let a = _mm_set_epi64x(1 << 63, 1 << 32);
9017 let count = _mm_set_epi64x(2, 3);
9018 let r = _mm_maskz_sllv_epi64(0, a, count);
9019 assert_eq_m128i(r, _mm_setzero_si128());
9020 let r = _mm_maskz_sllv_epi64(0b00000011, a, count);
9021 let e = _mm_set_epi64x(0, 1 << 35);
9022 assert_eq_m128i(r, e);
9023 }
9024
9025 #[simd_test(enable = "avx512f")]
9026 const unsafe fn test_mm512_srlv_epi64() {
9027 #[rustfmt::skip]
9028 let a = _mm512_set_epi64(
9029 1 << 32, 1 << 0, 1 << 32, 1 << 32,
9030 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9031 );
9032 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9033 let r = _mm512_srlv_epi64(a, count);
9034 #[rustfmt::skip]
9035 let e = _mm512_set_epi64(
9036 1 << 32, 0, 1 << 30, 1 << 29,
9037 1 << 28, 1 << 27, 1 << 26, 1 << 25,
9038 );
9039 assert_eq_m512i(r, e);
9040 }
9041
9042 #[simd_test(enable = "avx512f")]
9043 const unsafe fn test_mm512_mask_srlv_epi64() {
9044 #[rustfmt::skip]
9045 let a = _mm512_set_epi64(
9046 1 << 32, 1 << 0, 1 << 32, 1 << 32,
9047 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9048 );
9049 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9050 let r = _mm512_mask_srlv_epi64(a, 0, a, count);
9051 assert_eq_m512i(r, a);
9052 let r = _mm512_mask_srlv_epi64(a, 0b11111111, a, count);
9053 #[rustfmt::skip]
9054 let e = _mm512_set_epi64(
9055 1 << 32, 0, 1 << 30, 1 << 29,
9056 1 << 28, 1 << 27, 1 << 26, 1 << 25,
9057 );
9058 assert_eq_m512i(r, e);
9059 }
9060
9061 #[simd_test(enable = "avx512f")]
9062 const unsafe fn test_mm512_maskz_srlv_epi64() {
9063 #[rustfmt::skip]
9064 let a = _mm512_set_epi64(
9065 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9066 1 << 32, 1 << 32, 1 << 32, 1 << 0,
9067 );
9068 let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9069 let r = _mm512_maskz_srlv_epi64(0, a, count);
9070 assert_eq_m512i(r, _mm512_setzero_si512());
9071 let r = _mm512_maskz_srlv_epi64(0b00001111, a, count);
9072 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 0);
9073 assert_eq_m512i(r, e);
9074 }
9075
9076 #[simd_test(enable = "avx512f,avx512vl")]
9077 const unsafe fn test_mm256_mask_srlv_epi64() {
9078 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9079 let count = _mm256_set1_epi64x(1);
9080 let r = _mm256_mask_srlv_epi64(a, 0, a, count);
9081 assert_eq_m256i(r, a);
9082 let r = _mm256_mask_srlv_epi64(a, 0b00001111, a, count);
9083 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9084 assert_eq_m256i(r, e);
9085 }
9086
9087 #[simd_test(enable = "avx512f,avx512vl")]
9088 const unsafe fn test_mm256_maskz_srlv_epi64() {
9089 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9090 let count = _mm256_set1_epi64x(1);
9091 let r = _mm256_maskz_srlv_epi64(0, a, count);
9092 assert_eq_m256i(r, _mm256_setzero_si256());
9093 let r = _mm256_maskz_srlv_epi64(0b00001111, a, count);
9094 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9095 assert_eq_m256i(r, e);
9096 }
9097
9098 #[simd_test(enable = "avx512f,avx512vl")]
9099 const unsafe fn test_mm_mask_srlv_epi64() {
9100 let a = _mm_set_epi64x(1 << 5, 0);
9101 let count = _mm_set1_epi64x(1);
9102 let r = _mm_mask_srlv_epi64(a, 0, a, count);
9103 assert_eq_m128i(r, a);
9104 let r = _mm_mask_srlv_epi64(a, 0b00000011, a, count);
9105 let e = _mm_set_epi64x(1 << 4, 0);
9106 assert_eq_m128i(r, e);
9107 }
9108
9109 #[simd_test(enable = "avx512f,avx512vl")]
9110 const unsafe fn test_mm_maskz_srlv_epi64() {
9111 let a = _mm_set_epi64x(1 << 5, 0);
9112 let count = _mm_set1_epi64x(1);
9113 let r = _mm_maskz_srlv_epi64(0, a, count);
9114 assert_eq_m128i(r, _mm_setzero_si128());
9115 let r = _mm_maskz_srlv_epi64(0b00000011, a, count);
9116 let e = _mm_set_epi64x(1 << 4, 0);
9117 assert_eq_m128i(r, e);
9118 }
9119
9120 #[simd_test(enable = "avx512f")]
9121 unsafe fn test_mm512_sll_epi64() {
9122 #[rustfmt::skip]
9123 let a = _mm512_set_epi64(
9124 1 << 63, 1 << 32, 1 << 32, 1 << 32,
9125 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9126 );
9127 let count = _mm_set_epi64x(0, 1);
9128 let r = _mm512_sll_epi64(a, count);
9129 #[rustfmt::skip]
9130 let e = _mm512_set_epi64(
9131 0, 1 << 33, 1 << 33, 1 << 33,
9132 1 << 33, 1 << 33, 1 << 33, 1 << 33,
9133 );
9134 assert_eq_m512i(r, e);
9135 let count = _mm_set_epi64x(1, 0);
9136 let r = _mm512_sll_epi64(a, count);
9137 assert_eq_m512i(r, a);
9138 }
9139
9140 #[simd_test(enable = "avx512f")]
9141 unsafe fn test_mm512_mask_sll_epi64() {
9142 #[rustfmt::skip]
9143 let a = _mm512_set_epi64(
9144 1 << 63, 1 << 32, 1 << 32, 1 << 32,
9145 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9146 );
9147 let count = _mm_set_epi64x(0, 1);
9148 let r = _mm512_mask_sll_epi64(a, 0, a, count);
9149 assert_eq_m512i(r, a);
9150 let r = _mm512_mask_sll_epi64(a, 0b11111111, a, count);
9151 #[rustfmt::skip]
9152 let e = _mm512_set_epi64(
9153 0, 1 << 33, 1 << 33, 1 << 33,
9154 1 << 33, 1 << 33, 1 << 33, 1 << 33,
9155 );
9156 assert_eq_m512i(r, e);
9157 }
9158
9159 #[simd_test(enable = "avx512f")]
9160 unsafe fn test_mm512_maskz_sll_epi64() {
9161 #[rustfmt::skip]
9162 let a = _mm512_set_epi64(
9163 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9164 1 << 32, 1 << 32, 1 << 32, 1 << 63,
9165 );
9166 let count = _mm_set_epi64x(0, 1);
9167 let r = _mm512_maskz_sll_epi64(0, a, count);
9168 assert_eq_m512i(r, _mm512_setzero_si512());
9169 let r = _mm512_maskz_sll_epi64(0b00001111, a, count);
9170 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
9171 assert_eq_m512i(r, e);
9172 }
9173
9174 #[simd_test(enable = "avx512f,avx512vl")]
9175 unsafe fn test_mm256_mask_sll_epi64() {
9176 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9177 let count = _mm_set_epi64x(0, 1);
9178 let r = _mm256_mask_sll_epi64(a, 0, a, count);
9179 assert_eq_m256i(r, a);
9180 let r = _mm256_mask_sll_epi64(a, 0b00001111, a, count);
9181 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9182 assert_eq_m256i(r, e);
9183 }
9184
9185 #[simd_test(enable = "avx512f,avx512vl")]
9186 unsafe fn test_mm256_maskz_sll_epi64() {
9187 let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9188 let count = _mm_set_epi64x(0, 1);
9189 let r = _mm256_maskz_sll_epi64(0, a, count);
9190 assert_eq_m256i(r, _mm256_setzero_si256());
9191 let r = _mm256_maskz_sll_epi64(0b00001111, a, count);
9192 let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9193 assert_eq_m256i(r, e);
9194 }
9195
9196 #[simd_test(enable = "avx512f,avx512vl")]
9197 unsafe fn test_mm_mask_sll_epi64() {
9198 let a = _mm_set_epi64x(1 << 63, 1 << 32);
9199 let count = _mm_set_epi64x(0, 1);
9200 let r = _mm_mask_sll_epi64(a, 0, a, count);
9201 assert_eq_m128i(r, a);
9202 let r = _mm_mask_sll_epi64(a, 0b00000011, a, count);
9203 let e = _mm_set_epi64x(0, 1 << 33);
9204 assert_eq_m128i(r, e);
9205 }
9206
9207 #[simd_test(enable = "avx512f,avx512vl")]
9208 unsafe fn test_mm_maskz_sll_epi64() {
9209 let a = _mm_set_epi64x(1 << 63, 1 << 32);
9210 let count = _mm_set_epi64x(0, 1);
9211 let r = _mm_maskz_sll_epi64(0, a, count);
9212 assert_eq_m128i(r, _mm_setzero_si128());
9213 let r = _mm_maskz_sll_epi64(0b00000011, a, count);
9214 let e = _mm_set_epi64x(0, 1 << 33);
9215 assert_eq_m128i(r, e);
9216 }
9217
9218 #[simd_test(enable = "avx512f")]
9219 unsafe fn test_mm512_srl_epi64() {
9220 #[rustfmt::skip]
9221 let a = _mm512_set_epi64(
9222 1 << 0, 1 << 32, 1 << 32, 1 << 32,
9223 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9224 );
9225 let count = _mm_set_epi64x(0, 1);
9226 let r = _mm512_srl_epi64(a, count);
9227 #[rustfmt::skip]
9228 let e = _mm512_set_epi64(
9229 0, 1 << 31, 1 << 31, 1 << 31,
9230 1 << 31, 1 << 31, 1 << 31, 1 << 31,
9231 );
9232 assert_eq_m512i(r, e);
9233 }
9234
9235 #[simd_test(enable = "avx512f")]
9236 unsafe fn test_mm512_mask_srl_epi64() {
9237 #[rustfmt::skip]
9238 let a = _mm512_set_epi64(
9239 1 << 0, 1 << 32, 1 << 32, 1 << 32,
9240 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9241 );
9242 let count = _mm_set_epi64x(0, 1);
9243 let r = _mm512_mask_srl_epi64(a, 0, a, count);
9244 assert_eq_m512i(r, a);
9245 let r = _mm512_mask_srl_epi64(a, 0b11111111, a, count);
9246 #[rustfmt::skip]
9247 let e = _mm512_set_epi64(
9248 0, 1 << 31, 1 << 31, 1 << 31,
9249 1 << 31, 1 << 31, 1 << 31, 1 << 31,
9250 );
9251 assert_eq_m512i(r, e);
9252 }
9253
9254 #[simd_test(enable = "avx512f")]
9255 unsafe fn test_mm512_maskz_srl_epi64() {
9256 #[rustfmt::skip]
9257 let a = _mm512_set_epi64(
9258 1 << 32, 1 << 32, 1 << 32, 1 << 32,
9259 1 << 32, 1 << 32, 1 << 32, 1 << 0,
9260 );
9261 let count = _mm_set_epi64x(0, 1);
9262 let r = _mm512_maskz_srl_epi64(0, a, count);
9263 assert_eq_m512i(r, _mm512_setzero_si512());
9264 let r = _mm512_maskz_srl_epi64(0b00001111, a, count);
9265 let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
9266 assert_eq_m512i(r, e);
9267 }
9268
9269 #[simd_test(enable = "avx512f,avx512vl")]
9270 unsafe fn test_mm256_mask_srl_epi64() {
9271 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9272 let count = _mm_set_epi64x(0, 1);
9273 let r = _mm256_mask_srl_epi64(a, 0, a, count);
9274 assert_eq_m256i(r, a);
9275 let r = _mm256_mask_srl_epi64(a, 0b00001111, a, count);
9276 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9277 assert_eq_m256i(r, e);
9278 }
9279
9280 #[simd_test(enable = "avx512f,avx512vl")]
9281 unsafe fn test_mm256_maskz_srl_epi64() {
9282 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9283 let count = _mm_set_epi64x(0, 1);
9284 let r = _mm256_maskz_srl_epi64(0, a, count);
9285 assert_eq_m256i(r, _mm256_setzero_si256());
9286 let r = _mm256_maskz_srl_epi64(0b00001111, a, count);
9287 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9288 assert_eq_m256i(r, e);
9289 }
9290
9291 #[simd_test(enable = "avx512f,avx512vl")]
9292 unsafe fn test_mm_mask_srl_epi64() {
9293 let a = _mm_set_epi64x(1 << 5, 0);
9294 let count = _mm_set_epi64x(0, 1);
9295 let r = _mm_mask_srl_epi64(a, 0, a, count);
9296 assert_eq_m128i(r, a);
9297 let r = _mm_mask_srl_epi64(a, 0b00000011, a, count);
9298 let e = _mm_set_epi64x(1 << 4, 0);
9299 assert_eq_m128i(r, e);
9300 }
9301
9302 #[simd_test(enable = "avx512f,avx512vl")]
9303 unsafe fn test_mm_maskz_srl_epi64() {
9304 let a = _mm_set_epi64x(1 << 5, 0);
9305 let count = _mm_set_epi64x(0, 1);
9306 let r = _mm_maskz_srl_epi64(0, a, count);
9307 assert_eq_m128i(r, _mm_setzero_si128());
9308 let r = _mm_maskz_srl_epi64(0b00000011, a, count);
9309 let e = _mm_set_epi64x(1 << 4, 0);
9310 assert_eq_m128i(r, e);
9311 }
9312
9313 #[simd_test(enable = "avx512f")]
9314 unsafe fn test_mm512_sra_epi64() {
9315 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9316 let count = _mm_set_epi64x(0, 2);
9317 let r = _mm512_sra_epi64(a, count);
9318 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9319 assert_eq_m512i(r, e);
9320 }
9321
9322 #[simd_test(enable = "avx512f")]
9323 unsafe fn test_mm512_mask_sra_epi64() {
9324 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9325 let count = _mm_set_epi64x(0, 2);
9326 let r = _mm512_mask_sra_epi64(a, 0, a, count);
9327 assert_eq_m512i(r, a);
9328 let r = _mm512_mask_sra_epi64(a, 0b11111111, a, count);
9329 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9330 assert_eq_m512i(r, e);
9331 }
9332
9333 #[simd_test(enable = "avx512f")]
9334 unsafe fn test_mm512_maskz_sra_epi64() {
9335 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9336 let count = _mm_set_epi64x(0, 2);
9337 let r = _mm512_maskz_sra_epi64(0, a, count);
9338 assert_eq_m512i(r, _mm512_setzero_si512());
9339 let r = _mm512_maskz_sra_epi64(0b00001111, a, count);
9340 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -4);
9341 assert_eq_m512i(r, e);
9342 }
9343
9344 #[simd_test(enable = "avx512f,avx512vl")]
9345 unsafe fn test_mm256_sra_epi64() {
9346 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9347 let count = _mm_set_epi64x(0, 1);
9348 let r = _mm256_sra_epi64(a, count);
9349 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9350 assert_eq_m256i(r, e);
9351 }
9352
9353 #[simd_test(enable = "avx512f,avx512vl")]
9354 unsafe fn test_mm256_mask_sra_epi64() {
9355 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9356 let count = _mm_set_epi64x(0, 1);
9357 let r = _mm256_mask_sra_epi64(a, 0, a, count);
9358 assert_eq_m256i(r, a);
9359 let r = _mm256_mask_sra_epi64(a, 0b00001111, a, count);
9360 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9361 assert_eq_m256i(r, e);
9362 }
9363
9364 #[simd_test(enable = "avx512f,avx512vl")]
9365 unsafe fn test_mm256_maskz_sra_epi64() {
9366 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9367 let count = _mm_set_epi64x(0, 1);
9368 let r = _mm256_maskz_sra_epi64(0, a, count);
9369 assert_eq_m256i(r, _mm256_setzero_si256());
9370 let r = _mm256_maskz_sra_epi64(0b00001111, a, count);
9371 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9372 assert_eq_m256i(r, e);
9373 }
9374
9375 #[simd_test(enable = "avx512f,avx512vl")]
9376 unsafe fn test_mm_sra_epi64() {
9377 let a = _mm_set_epi64x(1 << 5, 0);
9378 let count = _mm_set_epi64x(0, 1);
9379 let r = _mm_sra_epi64(a, count);
9380 let e = _mm_set_epi64x(1 << 4, 0);
9381 assert_eq_m128i(r, e);
9382 }
9383
9384 #[simd_test(enable = "avx512f,avx512vl")]
9385 unsafe fn test_mm_mask_sra_epi64() {
9386 let a = _mm_set_epi64x(1 << 5, 0);
9387 let count = _mm_set_epi64x(0, 1);
9388 let r = _mm_mask_sra_epi64(a, 0, a, count);
9389 assert_eq_m128i(r, a);
9390 let r = _mm_mask_sra_epi64(a, 0b00000011, a, count);
9391 let e = _mm_set_epi64x(1 << 4, 0);
9392 assert_eq_m128i(r, e);
9393 }
9394
9395 #[simd_test(enable = "avx512f,avx512vl")]
9396 unsafe fn test_mm_maskz_sra_epi64() {
9397 let a = _mm_set_epi64x(1 << 5, 0);
9398 let count = _mm_set_epi64x(0, 1);
9399 let r = _mm_maskz_sra_epi64(0, a, count);
9400 assert_eq_m128i(r, _mm_setzero_si128());
9401 let r = _mm_maskz_sra_epi64(0b00000011, a, count);
9402 let e = _mm_set_epi64x(1 << 4, 0);
9403 assert_eq_m128i(r, e);
9404 }
9405
9406 #[simd_test(enable = "avx512f")]
9407 const unsafe fn test_mm512_srav_epi64() {
9408 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9409 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9410 let r = _mm512_srav_epi64(a, count);
9411 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9412 assert_eq_m512i(r, e);
9413 }
9414
9415 #[simd_test(enable = "avx512f")]
9416 const unsafe fn test_mm512_mask_srav_epi64() {
9417 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9418 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9419 let r = _mm512_mask_srav_epi64(a, 0, a, count);
9420 assert_eq_m512i(r, a);
9421 let r = _mm512_mask_srav_epi64(a, 0b11111111, a, count);
9422 let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9423 assert_eq_m512i(r, e);
9424 }
9425
9426 #[simd_test(enable = "avx512f")]
9427 const unsafe fn test_mm512_maskz_srav_epi64() {
9428 let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9429 let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9430 let r = _mm512_maskz_srav_epi64(0, a, count);
9431 assert_eq_m512i(r, _mm512_setzero_si512());
9432 let r = _mm512_maskz_srav_epi64(0b00001111, a, count);
9433 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -8);
9434 assert_eq_m512i(r, e);
9435 }
9436
9437 #[simd_test(enable = "avx512f,avx512vl")]
9438 const unsafe fn test_mm256_srav_epi64() {
9439 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9440 let count = _mm256_set1_epi64x(1);
9441 let r = _mm256_srav_epi64(a, count);
9442 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9443 assert_eq_m256i(r, e);
9444 }
9445
9446 #[simd_test(enable = "avx512f,avx512vl")]
9447 const unsafe fn test_mm256_mask_srav_epi64() {
9448 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9449 let count = _mm256_set1_epi64x(1);
9450 let r = _mm256_mask_srav_epi64(a, 0, a, count);
9451 assert_eq_m256i(r, a);
9452 let r = _mm256_mask_srav_epi64(a, 0b00001111, a, count);
9453 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9454 assert_eq_m256i(r, e);
9455 }
9456
9457 #[simd_test(enable = "avx512f,avx512vl")]
9458 const unsafe fn test_mm256_maskz_srav_epi64() {
9459 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9460 let count = _mm256_set1_epi64x(1);
9461 let r = _mm256_maskz_srav_epi64(0, a, count);
9462 assert_eq_m256i(r, _mm256_setzero_si256());
9463 let r = _mm256_maskz_srav_epi64(0b00001111, a, count);
9464 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9465 assert_eq_m256i(r, e);
9466 }
9467
9468 #[simd_test(enable = "avx512f,avx512vl")]
9469 const unsafe fn test_mm_srav_epi64() {
9470 let a = _mm_set_epi64x(1 << 5, 0);
9471 let count = _mm_set1_epi64x(1);
9472 let r = _mm_srav_epi64(a, count);
9473 let e = _mm_set_epi64x(1 << 4, 0);
9474 assert_eq_m128i(r, e);
9475 }
9476
9477 #[simd_test(enable = "avx512f,avx512vl")]
9478 const unsafe fn test_mm_mask_srav_epi64() {
9479 let a = _mm_set_epi64x(1 << 5, 0);
9480 let count = _mm_set1_epi64x(1);
9481 let r = _mm_mask_srav_epi64(a, 0, a, count);
9482 assert_eq_m128i(r, a);
9483 let r = _mm_mask_srav_epi64(a, 0b00000011, a, count);
9484 let e = _mm_set_epi64x(1 << 4, 0);
9485 assert_eq_m128i(r, e);
9486 }
9487
9488 #[simd_test(enable = "avx512f,avx512vl")]
9489 const unsafe fn test_mm_maskz_srav_epi64() {
9490 let a = _mm_set_epi64x(1 << 5, 0);
9491 let count = _mm_set1_epi64x(1);
9492 let r = _mm_maskz_srav_epi64(0, a, count);
9493 assert_eq_m128i(r, _mm_setzero_si128());
9494 let r = _mm_maskz_srav_epi64(0b00000011, a, count);
9495 let e = _mm_set_epi64x(1 << 4, 0);
9496 assert_eq_m128i(r, e);
9497 }
9498
9499 #[simd_test(enable = "avx512f")]
9500 const unsafe fn test_mm512_srai_epi64() {
9501 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9502 let r = _mm512_srai_epi64::<2>(a);
9503 let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9504 assert_eq_m512i(r, e);
9505 }
9506
9507 #[simd_test(enable = "avx512f")]
9508 const unsafe fn test_mm512_mask_srai_epi64() {
9509 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9510 let r = _mm512_mask_srai_epi64::<2>(a, 0, a);
9511 assert_eq_m512i(r, a);
9512 let r = _mm512_mask_srai_epi64::<2>(a, 0b11111111, a);
9513 let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9514 assert_eq_m512i(r, e);
9515 }
9516
9517 #[simd_test(enable = "avx512f")]
9518 const unsafe fn test_mm512_maskz_srai_epi64() {
9519 let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9520 let r = _mm512_maskz_srai_epi64::<2>(0, a);
9521 assert_eq_m512i(r, _mm512_setzero_si512());
9522 let r = _mm512_maskz_srai_epi64::<2>(0b00001111, a);
9523 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, -4);
9524 assert_eq_m512i(r, e);
9525 }
9526
9527 #[simd_test(enable = "avx512f,avx512vl")]
9528 const unsafe fn test_mm256_srai_epi64() {
9529 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9530 let r = _mm256_srai_epi64::<1>(a);
9531 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9532 assert_eq_m256i(r, e);
9533 }
9534
9535 #[simd_test(enable = "avx512f,avx512vl")]
9536 const unsafe fn test_mm256_mask_srai_epi64() {
9537 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9538 let r = _mm256_mask_srai_epi64::<1>(a, 0, a);
9539 assert_eq_m256i(r, a);
9540 let r = _mm256_mask_srai_epi64::<1>(a, 0b00001111, a);
9541 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9542 assert_eq_m256i(r, e);
9543 }
9544
9545 #[simd_test(enable = "avx512f,avx512vl")]
9546 const unsafe fn test_mm256_maskz_srai_epi64() {
9547 let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9548 let r = _mm256_maskz_srai_epi64::<1>(0, a);
9549 assert_eq_m256i(r, _mm256_setzero_si256());
9550 let r = _mm256_maskz_srai_epi64::<1>(0b00001111, a);
9551 let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9552 assert_eq_m256i(r, e);
9553 }
9554
9555 #[simd_test(enable = "avx512f,avx512vl")]
9556 const unsafe fn test_mm_srai_epi64() {
9557 let a = _mm_set_epi64x(1 << 5, 0);
9558 let r = _mm_srai_epi64::<1>(a);
9559 let e = _mm_set_epi64x(1 << 4, 0);
9560 assert_eq_m128i(r, e);
9561 }
9562
9563 #[simd_test(enable = "avx512f,avx512vl")]
9564 const unsafe fn test_mm_mask_srai_epi64() {
9565 let a = _mm_set_epi64x(1 << 5, 0);
9566 let r = _mm_mask_srai_epi64::<1>(a, 0, a);
9567 assert_eq_m128i(r, a);
9568 let r = _mm_mask_srai_epi64::<1>(a, 0b00000011, a);
9569 let e = _mm_set_epi64x(1 << 4, 0);
9570 assert_eq_m128i(r, e);
9571 }
9572
9573 #[simd_test(enable = "avx512f,avx512vl")]
9574 const unsafe fn test_mm_maskz_srai_epi64() {
9575 let a = _mm_set_epi64x(1 << 5, 0);
9576 let r = _mm_maskz_srai_epi64::<1>(0, a);
9577 assert_eq_m128i(r, _mm_setzero_si128());
9578 let r = _mm_maskz_srai_epi64::<1>(0b00000011, a);
9579 let e = _mm_set_epi64x(1 << 4, 0);
9580 assert_eq_m128i(r, e);
9581 }
9582
9583 #[simd_test(enable = "avx512f")]
9584 const unsafe fn test_mm512_permute_pd() {
9585 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9586 let r = _mm512_permute_pd::<0b11_11_11_11>(a);
9587 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9588 assert_eq_m512d(r, e);
9589 }
9590
9591 #[simd_test(enable = "avx512f")]
9592 const unsafe fn test_mm512_mask_permute_pd() {
9593 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9594 let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0, a);
9595 assert_eq_m512d(r, a);
9596 let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0b11111111, a);
9597 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9598 assert_eq_m512d(r, e);
9599 }
9600
9601 #[simd_test(enable = "avx512f")]
9602 const unsafe fn test_mm512_maskz_permute_pd() {
9603 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9604 let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0, a);
9605 assert_eq_m512d(r, _mm512_setzero_pd());
9606 let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0b11111111, a);
9607 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9608 assert_eq_m512d(r, e);
9609 }
9610
9611 #[simd_test(enable = "avx512f,avx512vl")]
9612 const unsafe fn test_mm256_mask_permute_pd() {
9613 let a = _mm256_set_pd(3., 2., 1., 0.);
9614 let r = _mm256_mask_permute_pd::<0b11_11>(a, 0, a);
9615 assert_eq_m256d(r, a);
9616 let r = _mm256_mask_permute_pd::<0b11_11>(a, 0b00001111, a);
9617 let e = _mm256_set_pd(3., 3., 1., 1.);
9618 assert_eq_m256d(r, e);
9619 }
9620
9621 #[simd_test(enable = "avx512f,avx512vl")]
9622 const unsafe fn test_mm256_maskz_permute_pd() {
9623 let a = _mm256_set_pd(3., 2., 1., 0.);
9624 let r = _mm256_maskz_permute_pd::<0b11_11>(0, a);
9625 assert_eq_m256d(r, _mm256_setzero_pd());
9626 let r = _mm256_maskz_permute_pd::<0b11_11>(0b00001111, a);
9627 let e = _mm256_set_pd(3., 3., 1., 1.);
9628 assert_eq_m256d(r, e);
9629 }
9630
9631 #[simd_test(enable = "avx512f,avx512vl")]
9632 const unsafe fn test_mm_mask_permute_pd() {
9633 let a = _mm_set_pd(1., 0.);
9634 let r = _mm_mask_permute_pd::<0b11>(a, 0, a);
9635 assert_eq_m128d(r, a);
9636 let r = _mm_mask_permute_pd::<0b11>(a, 0b00000011, a);
9637 let e = _mm_set_pd(1., 1.);
9638 assert_eq_m128d(r, e);
9639 }
9640
9641 #[simd_test(enable = "avx512f,avx512vl")]
9642 const unsafe fn test_mm_maskz_permute_pd() {
9643 let a = _mm_set_pd(1., 0.);
9644 let r = _mm_maskz_permute_pd::<0b11>(0, a);
9645 assert_eq_m128d(r, _mm_setzero_pd());
9646 let r = _mm_maskz_permute_pd::<0b11>(0b00000011, a);
9647 let e = _mm_set_pd(1., 1.);
9648 assert_eq_m128d(r, e);
9649 }
9650
9651 #[simd_test(enable = "avx512f")]
9652 const unsafe fn test_mm512_permutex_epi64() {
9653 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9654 let r = _mm512_permutex_epi64::<0b11_11_11_11>(a);
9655 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9656 assert_eq_m512i(r, e);
9657 }
9658
9659 #[simd_test(enable = "avx512f")]
9660 const unsafe fn test_mm512_mask_permutex_epi64() {
9661 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9662 let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9663 assert_eq_m512i(r, a);
9664 let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0b11111111, a);
9665 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9666 assert_eq_m512i(r, e);
9667 }
9668
9669 #[simd_test(enable = "avx512f")]
9670 const unsafe fn test_mm512_maskz_permutex_epi64() {
9671 let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9672 let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9673 assert_eq_m512i(r, _mm512_setzero_si512());
9674 let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0b11111111, a);
9675 let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9676 assert_eq_m512i(r, e);
9677 }
9678
9679 #[simd_test(enable = "avx512f,avx512vl")]
9680 const unsafe fn test_mm256_permutex_epi64() {
9681 let a = _mm256_set_epi64x(3, 2, 1, 0);
9682 let r = _mm256_permutex_epi64::<0b11_11_11_11>(a);
9683 let e = _mm256_set_epi64x(3, 3, 3, 3);
9684 assert_eq_m256i(r, e);
9685 }
9686
9687 #[simd_test(enable = "avx512f,avx512vl")]
9688 const unsafe fn test_mm256_mask_permutex_epi64() {
9689 let a = _mm256_set_epi64x(3, 2, 1, 0);
9690 let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9691 assert_eq_m256i(r, a);
9692 let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0b00001111, a);
9693 let e = _mm256_set_epi64x(3, 3, 3, 3);
9694 assert_eq_m256i(r, e);
9695 }
9696
9697 #[simd_test(enable = "avx512f,avx512vl")]
9698 const unsafe fn test_mm256_maskz_permutex_epi64() {
9699 let a = _mm256_set_epi64x(3, 2, 1, 0);
9700 let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9701 assert_eq_m256i(r, _mm256_setzero_si256());
9702 let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0b00001111, a);
9703 let e = _mm256_set_epi64x(3, 3, 3, 3);
9704 assert_eq_m256i(r, e);
9705 }
9706
9707 #[simd_test(enable = "avx512f")]
9708 const unsafe fn test_mm512_permutex_pd() {
9709 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9710 let r = _mm512_permutex_pd::<0b11_11_11_11>(a);
9711 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9712 assert_eq_m512d(r, e);
9713 }
9714
9715 #[simd_test(enable = "avx512f")]
9716 const unsafe fn test_mm512_mask_permutex_pd() {
9717 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9718 let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9719 assert_eq_m512d(r, a);
9720 let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0b11111111, a);
9721 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9722 assert_eq_m512d(r, e);
9723 }
9724
9725 #[simd_test(enable = "avx512f")]
9726 const unsafe fn test_mm512_maskz_permutex_pd() {
9727 let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9728 let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9729 assert_eq_m512d(r, _mm512_setzero_pd());
9730 let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0b11111111, a);
9731 let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9732 assert_eq_m512d(r, e);
9733 }
9734
9735 #[simd_test(enable = "avx512f,avx512vl")]
9736 const unsafe fn test_mm256_permutex_pd() {
9737 let a = _mm256_set_pd(0., 1., 2., 3.);
9738 let r = _mm256_permutex_pd::<0b11_11_11_11>(a);
9739 let e = _mm256_set_pd(0., 0., 0., 0.);
9740 assert_eq_m256d(r, e);
9741 }
9742
9743 #[simd_test(enable = "avx512f,avx512vl")]
9744 const unsafe fn test_mm256_mask_permutex_pd() {
9745 let a = _mm256_set_pd(0., 1., 2., 3.);
9746 let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9747 assert_eq_m256d(r, a);
9748 let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0b00001111, a);
9749 let e = _mm256_set_pd(0., 0., 0., 0.);
9750 assert_eq_m256d(r, e);
9751 }
9752
9753 #[simd_test(enable = "avx512f,avx512vl")]
9754 const unsafe fn test_mm256_maskz_permutex_pd() {
9755 let a = _mm256_set_pd(0., 1., 2., 3.);
9756 let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9757 assert_eq_m256d(r, _mm256_setzero_pd());
9758 let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0b00001111, a);
9759 let e = _mm256_set_pd(0., 0., 0., 0.);
9760 assert_eq_m256d(r, e);
9761 }
9762
9763 #[simd_test(enable = "avx512f")]
9764 unsafe fn test_mm512_permutevar_pd() {
9765 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9766 let b = _mm512_set1_epi64(0b1);
9767 let r = _mm512_permutevar_pd(a, b);
9768 let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9769 assert_eq_m512d(r, e);
9770 }
9771
9772 #[simd_test(enable = "avx512f")]
9773 unsafe fn test_mm512_mask_permutevar_pd() {
9774 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9775 let b = _mm512_set1_epi64(0b1);
9776 let r = _mm512_mask_permutevar_pd(a, 0, a, b);
9777 assert_eq_m512d(r, a);
9778 let r = _mm512_mask_permutevar_pd(a, 0b11111111, a, b);
9779 let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9780 assert_eq_m512d(r, e);
9781 }
9782
9783 #[simd_test(enable = "avx512f")]
9784 unsafe fn test_mm512_maskz_permutevar_pd() {
9785 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9786 let b = _mm512_set1_epi64(0b1);
9787 let r = _mm512_maskz_permutevar_pd(0, a, b);
9788 assert_eq_m512d(r, _mm512_setzero_pd());
9789 let r = _mm512_maskz_permutevar_pd(0b00001111, a, b);
9790 let e = _mm512_set_pd(0., 0., 0., 0., 5., 5., 7., 7.);
9791 assert_eq_m512d(r, e);
9792 }
9793
9794 #[simd_test(enable = "avx512f,avx512vl")]
9795 unsafe fn test_mm256_mask_permutevar_pd() {
9796 let a = _mm256_set_pd(0., 1., 2., 3.);
9797 let b = _mm256_set1_epi64x(0b1);
9798 let r = _mm256_mask_permutevar_pd(a, 0, a, b);
9799 assert_eq_m256d(r, a);
9800 let r = _mm256_mask_permutevar_pd(a, 0b00001111, a, b);
9801 let e = _mm256_set_pd(1., 1., 3., 3.);
9802 assert_eq_m256d(r, e);
9803 }
9804
9805 #[simd_test(enable = "avx512f,avx512vl")]
9806 unsafe fn test_mm256_maskz_permutevar_pd() {
9807 let a = _mm256_set_pd(0., 1., 2., 3.);
9808 let b = _mm256_set1_epi64x(0b1);
9809 let r = _mm256_maskz_permutevar_pd(0, a, b);
9810 assert_eq_m256d(r, _mm256_setzero_pd());
9811 let r = _mm256_maskz_permutevar_pd(0b00001111, a, b);
9812 let e = _mm256_set_pd(1., 1., 3., 3.);
9813 assert_eq_m256d(r, e);
9814 }
9815
9816 #[simd_test(enable = "avx512f,avx512vl")]
9817 unsafe fn test_mm_mask_permutevar_pd() {
9818 let a = _mm_set_pd(0., 1.);
9819 let b = _mm_set1_epi64x(0b1);
9820 let r = _mm_mask_permutevar_pd(a, 0, a, b);
9821 assert_eq_m128d(r, a);
9822 let r = _mm_mask_permutevar_pd(a, 0b00000011, a, b);
9823 let e = _mm_set_pd(1., 1.);
9824 assert_eq_m128d(r, e);
9825 }
9826
9827 #[simd_test(enable = "avx512f,avx512vl")]
9828 unsafe fn test_mm_maskz_permutevar_pd() {
9829 let a = _mm_set_pd(0., 1.);
9830 let b = _mm_set1_epi64x(0b1);
9831 let r = _mm_maskz_permutevar_pd(0, a, b);
9832 assert_eq_m128d(r, _mm_setzero_pd());
9833 let r = _mm_maskz_permutevar_pd(0b00000011, a, b);
9834 let e = _mm_set_pd(1., 1.);
9835 assert_eq_m128d(r, e);
9836 }
9837
9838 #[simd_test(enable = "avx512f")]
9839 unsafe fn test_mm512_permutexvar_epi64() {
9840 let idx = _mm512_set1_epi64(1);
9841 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9842 let r = _mm512_permutexvar_epi64(idx, a);
9843 let e = _mm512_set1_epi64(6);
9844 assert_eq_m512i(r, e);
9845 }
9846
9847 #[simd_test(enable = "avx512f")]
9848 unsafe fn test_mm512_mask_permutexvar_epi64() {
9849 let idx = _mm512_set1_epi64(1);
9850 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9851 let r = _mm512_mask_permutexvar_epi64(a, 0, idx, a);
9852 assert_eq_m512i(r, a);
9853 let r = _mm512_mask_permutexvar_epi64(a, 0b11111111, idx, a);
9854 let e = _mm512_set1_epi64(6);
9855 assert_eq_m512i(r, e);
9856 }
9857
9858 #[simd_test(enable = "avx512f")]
9859 unsafe fn test_mm512_maskz_permutexvar_epi64() {
9860 let idx = _mm512_set1_epi64(1);
9861 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9862 let r = _mm512_maskz_permutexvar_epi64(0, idx, a);
9863 assert_eq_m512i(r, _mm512_setzero_si512());
9864 let r = _mm512_maskz_permutexvar_epi64(0b00001111, idx, a);
9865 let e = _mm512_set_epi64(0, 0, 0, 0, 6, 6, 6, 6);
9866 assert_eq_m512i(r, e);
9867 }
9868
9869 #[simd_test(enable = "avx512f,avx512vl")]
9870 unsafe fn test_mm256_permutexvar_epi64() {
9871 let idx = _mm256_set1_epi64x(1);
9872 let a = _mm256_set_epi64x(0, 1, 2, 3);
9873 let r = _mm256_permutexvar_epi64(idx, a);
9874 let e = _mm256_set1_epi64x(2);
9875 assert_eq_m256i(r, e);
9876 }
9877
9878 #[simd_test(enable = "avx512f,avx512vl")]
9879 unsafe fn test_mm256_mask_permutexvar_epi64() {
9880 let idx = _mm256_set1_epi64x(1);
9881 let a = _mm256_set_epi64x(0, 1, 2, 3);
9882 let r = _mm256_mask_permutexvar_epi64(a, 0, idx, a);
9883 assert_eq_m256i(r, a);
9884 let r = _mm256_mask_permutexvar_epi64(a, 0b00001111, idx, a);
9885 let e = _mm256_set1_epi64x(2);
9886 assert_eq_m256i(r, e);
9887 }
9888
9889 #[simd_test(enable = "avx512f,avx512vl")]
9890 unsafe fn test_mm256_maskz_permutexvar_epi64() {
9891 let idx = _mm256_set1_epi64x(1);
9892 let a = _mm256_set_epi64x(0, 1, 2, 3);
9893 let r = _mm256_maskz_permutexvar_epi64(0, idx, a);
9894 assert_eq_m256i(r, _mm256_setzero_si256());
9895 let r = _mm256_maskz_permutexvar_epi64(0b00001111, idx, a);
9896 let e = _mm256_set1_epi64x(2);
9897 assert_eq_m256i(r, e);
9898 }
9899
9900 #[simd_test(enable = "avx512f")]
9901 unsafe fn test_mm512_permutexvar_pd() {
9902 let idx = _mm512_set1_epi64(1);
9903 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9904 let r = _mm512_permutexvar_pd(idx, a);
9905 let e = _mm512_set1_pd(6.);
9906 assert_eq_m512d(r, e);
9907 }
9908
9909 #[simd_test(enable = "avx512f")]
9910 unsafe fn test_mm512_mask_permutexvar_pd() {
9911 let idx = _mm512_set1_epi64(1);
9912 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9913 let r = _mm512_mask_permutexvar_pd(a, 0, idx, a);
9914 assert_eq_m512d(r, a);
9915 let r = _mm512_mask_permutexvar_pd(a, 0b11111111, idx, a);
9916 let e = _mm512_set1_pd(6.);
9917 assert_eq_m512d(r, e);
9918 }
9919
9920 #[simd_test(enable = "avx512f")]
9921 unsafe fn test_mm512_maskz_permutexvar_pd() {
9922 let idx = _mm512_set1_epi64(1);
9923 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9924 let r = _mm512_maskz_permutexvar_pd(0, idx, a);
9925 assert_eq_m512d(r, _mm512_setzero_pd());
9926 let r = _mm512_maskz_permutexvar_pd(0b00001111, idx, a);
9927 let e = _mm512_set_pd(0., 0., 0., 0., 6., 6., 6., 6.);
9928 assert_eq_m512d(r, e);
9929 }
9930
9931 #[simd_test(enable = "avx512f,avx512vl")]
9932 unsafe fn test_mm256_permutexvar_pd() {
9933 let idx = _mm256_set1_epi64x(1);
9934 let a = _mm256_set_pd(0., 1., 2., 3.);
9935 let r = _mm256_permutexvar_pd(idx, a);
9936 let e = _mm256_set1_pd(2.);
9937 assert_eq_m256d(r, e);
9938 }
9939
9940 #[simd_test(enable = "avx512f,avx512vl")]
9941 unsafe fn test_mm256_mask_permutexvar_pd() {
9942 let idx = _mm256_set1_epi64x(1);
9943 let a = _mm256_set_pd(0., 1., 2., 3.);
9944 let r = _mm256_mask_permutexvar_pd(a, 0, idx, a);
9945 assert_eq_m256d(r, a);
9946 let r = _mm256_mask_permutexvar_pd(a, 0b00001111, idx, a);
9947 let e = _mm256_set1_pd(2.);
9948 assert_eq_m256d(r, e);
9949 }
9950
9951 #[simd_test(enable = "avx512f,avx512vl")]
9952 unsafe fn test_mm256_maskz_permutexvar_pd() {
9953 let idx = _mm256_set1_epi64x(1);
9954 let a = _mm256_set_pd(0., 1., 2., 3.);
9955 let r = _mm256_maskz_permutexvar_pd(0, idx, a);
9956 assert_eq_m256d(r, _mm256_setzero_pd());
9957 let r = _mm256_maskz_permutexvar_pd(0b00001111, idx, a);
9958 let e = _mm256_set1_pd(2.);
9959 assert_eq_m256d(r, e);
9960 }
9961
9962 #[simd_test(enable = "avx512f")]
9963 unsafe fn test_mm512_permutex2var_epi64() {
9964 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9965 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9966 let b = _mm512_set1_epi64(100);
9967 let r = _mm512_permutex2var_epi64(a, idx, b);
9968 let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9969 assert_eq_m512i(r, e);
9970 }
9971
9972 #[simd_test(enable = "avx512f")]
9973 unsafe fn test_mm512_mask_permutex2var_epi64() {
9974 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9975 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9976 let b = _mm512_set1_epi64(100);
9977 let r = _mm512_mask_permutex2var_epi64(a, 0, idx, b);
9978 assert_eq_m512i(r, a);
9979 let r = _mm512_mask_permutex2var_epi64(a, 0b11111111, idx, b);
9980 let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
9981 assert_eq_m512i(r, e);
9982 }
9983
9984 #[simd_test(enable = "avx512f")]
9985 unsafe fn test_mm512_maskz_permutex2var_epi64() {
9986 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9987 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
9988 let b = _mm512_set1_epi64(100);
9989 let r = _mm512_maskz_permutex2var_epi64(0, a, idx, b);
9990 assert_eq_m512i(r, _mm512_setzero_si512());
9991 let r = _mm512_maskz_permutex2var_epi64(0b00001111, a, idx, b);
9992 let e = _mm512_set_epi64(0, 0, 0, 0, 4, 100, 3, 100);
9993 assert_eq_m512i(r, e);
9994 }
9995
9996 #[simd_test(enable = "avx512f")]
9997 unsafe fn test_mm512_mask2_permutex2var_epi64() {
9998 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9999 let idx = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10000 let b = _mm512_set1_epi64(100);
10001 let r = _mm512_mask2_permutex2var_epi64(a, idx, 0, b);
10002 assert_eq_m512i(r, idx);
10003 let r = _mm512_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
10004 let e = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 4, 100, 3, 100);
10005 assert_eq_m512i(r, e);
10006 }
10007
10008 #[simd_test(enable = "avx512f,avx512vl")]
10009 unsafe fn test_mm256_permutex2var_epi64() {
10010 let a = _mm256_set_epi64x(0, 1, 2, 3);
10011 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10012 let b = _mm256_set1_epi64x(100);
10013 let r = _mm256_permutex2var_epi64(a, idx, b);
10014 let e = _mm256_set_epi64x(2, 100, 1, 100);
10015 assert_eq_m256i(r, e);
10016 }
10017
10018 #[simd_test(enable = "avx512f,avx512vl")]
10019 unsafe fn test_mm256_mask_permutex2var_epi64() {
10020 let a = _mm256_set_epi64x(0, 1, 2, 3);
10021 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10022 let b = _mm256_set1_epi64x(100);
10023 let r = _mm256_mask_permutex2var_epi64(a, 0, idx, b);
10024 assert_eq_m256i(r, a);
10025 let r = _mm256_mask_permutex2var_epi64(a, 0b00001111, idx, b);
10026 let e = _mm256_set_epi64x(2, 100, 1, 100);
10027 assert_eq_m256i(r, e);
10028 }
10029
10030 #[simd_test(enable = "avx512f,avx512vl")]
10031 unsafe fn test_mm256_maskz_permutex2var_epi64() {
10032 let a = _mm256_set_epi64x(0, 1, 2, 3);
10033 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10034 let b = _mm256_set1_epi64x(100);
10035 let r = _mm256_maskz_permutex2var_epi64(0, a, idx, b);
10036 assert_eq_m256i(r, _mm256_setzero_si256());
10037 let r = _mm256_maskz_permutex2var_epi64(0b00001111, a, idx, b);
10038 let e = _mm256_set_epi64x(2, 100, 1, 100);
10039 assert_eq_m256i(r, e);
10040 }
10041
10042 #[simd_test(enable = "avx512f,avx512vl")]
10043 unsafe fn test_mm256_mask2_permutex2var_epi64() {
10044 let a = _mm256_set_epi64x(0, 1, 2, 3);
10045 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10046 let b = _mm256_set1_epi64x(100);
10047 let r = _mm256_mask2_permutex2var_epi64(a, idx, 0, b);
10048 assert_eq_m256i(r, idx);
10049 let r = _mm256_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
10050 let e = _mm256_set_epi64x(2, 100, 1, 100);
10051 assert_eq_m256i(r, e);
10052 }
10053
10054 #[simd_test(enable = "avx512f,avx512vl")]
10055 unsafe fn test_mm_permutex2var_epi64() {
10056 let a = _mm_set_epi64x(0, 1);
10057 let idx = _mm_set_epi64x(1, 1 << 1);
10058 let b = _mm_set1_epi64x(100);
10059 let r = _mm_permutex2var_epi64(a, idx, b);
10060 let e = _mm_set_epi64x(0, 100);
10061 assert_eq_m128i(r, e);
10062 }
10063
10064 #[simd_test(enable = "avx512f,avx512vl")]
10065 unsafe fn test_mm_mask_permutex2var_epi64() {
10066 let a = _mm_set_epi64x(0, 1);
10067 let idx = _mm_set_epi64x(1, 1 << 1);
10068 let b = _mm_set1_epi64x(100);
10069 let r = _mm_mask_permutex2var_epi64(a, 0, idx, b);
10070 assert_eq_m128i(r, a);
10071 let r = _mm_mask_permutex2var_epi64(a, 0b00000011, idx, b);
10072 let e = _mm_set_epi64x(0, 100);
10073 assert_eq_m128i(r, e);
10074 }
10075
10076 #[simd_test(enable = "avx512f,avx512vl")]
10077 unsafe fn test_mm_maskz_permutex2var_epi64() {
10078 let a = _mm_set_epi64x(0, 1);
10079 let idx = _mm_set_epi64x(1, 1 << 1);
10080 let b = _mm_set1_epi64x(100);
10081 let r = _mm_maskz_permutex2var_epi64(0, a, idx, b);
10082 assert_eq_m128i(r, _mm_setzero_si128());
10083 let r = _mm_maskz_permutex2var_epi64(0b00000011, a, idx, b);
10084 let e = _mm_set_epi64x(0, 100);
10085 assert_eq_m128i(r, e);
10086 }
10087
10088 #[simd_test(enable = "avx512f,avx512vl")]
10089 unsafe fn test_mm_mask2_permutex2var_epi64() {
10090 let a = _mm_set_epi64x(0, 1);
10091 let idx = _mm_set_epi64x(1, 1 << 1);
10092 let b = _mm_set1_epi64x(100);
10093 let r = _mm_mask2_permutex2var_epi64(a, idx, 0, b);
10094 assert_eq_m128i(r, idx);
10095 let r = _mm_mask2_permutex2var_epi64(a, idx, 0b00000011, b);
10096 let e = _mm_set_epi64x(0, 100);
10097 assert_eq_m128i(r, e);
10098 }
10099
10100 #[simd_test(enable = "avx512f")]
10101 unsafe fn test_mm512_permutex2var_pd() {
10102 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10103 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10104 let b = _mm512_set1_pd(100.);
10105 let r = _mm512_permutex2var_pd(a, idx, b);
10106 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10107 assert_eq_m512d(r, e);
10108 }
10109
10110 #[simd_test(enable = "avx512f")]
10111 unsafe fn test_mm512_mask_permutex2var_pd() {
10112 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10113 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10114 let b = _mm512_set1_pd(100.);
10115 let r = _mm512_mask_permutex2var_pd(a, 0, idx, b);
10116 assert_eq_m512d(r, a);
10117 let r = _mm512_mask_permutex2var_pd(a, 0b11111111, idx, b);
10118 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10119 assert_eq_m512d(r, e);
10120 }
10121
10122 #[simd_test(enable = "avx512f")]
10123 unsafe fn test_mm512_maskz_permutex2var_pd() {
10124 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10125 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10126 let b = _mm512_set1_pd(100.);
10127 let r = _mm512_maskz_permutex2var_pd(0, a, idx, b);
10128 assert_eq_m512d(r, _mm512_setzero_pd());
10129 let r = _mm512_maskz_permutex2var_pd(0b00001111, a, idx, b);
10130 let e = _mm512_set_pd(0., 0., 0., 0., 4., 100., 3., 100.);
10131 assert_eq_m512d(r, e);
10132 }
10133
10134 #[simd_test(enable = "avx512f")]
10135 unsafe fn test_mm512_mask2_permutex2var_pd() {
10136 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10137 let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10138 let b = _mm512_set1_pd(100.);
10139 let r = _mm512_mask2_permutex2var_pd(a, idx, 0, b);
10140 assert_eq_m512d(r, _mm512_castsi512_pd(idx));
10141 let r = _mm512_mask2_permutex2var_pd(a, idx, 0b11111111, b);
10142 let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10143 assert_eq_m512d(r, e);
10144 }
10145
10146 #[simd_test(enable = "avx512f,avx512vl")]
10147 unsafe fn test_mm256_permutex2var_pd() {
10148 let a = _mm256_set_pd(0., 1., 2., 3.);
10149 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10150 let b = _mm256_set1_pd(100.);
10151 let r = _mm256_permutex2var_pd(a, idx, b);
10152 let e = _mm256_set_pd(2., 100., 1., 100.);
10153 assert_eq_m256d(r, e);
10154 }
10155
10156 #[simd_test(enable = "avx512f,avx512vl")]
10157 unsafe fn test_mm256_mask_permutex2var_pd() {
10158 let a = _mm256_set_pd(0., 1., 2., 3.);
10159 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10160 let b = _mm256_set1_pd(100.);
10161 let r = _mm256_mask_permutex2var_pd(a, 0, idx, b);
10162 assert_eq_m256d(r, a);
10163 let r = _mm256_mask_permutex2var_pd(a, 0b00001111, idx, b);
10164 let e = _mm256_set_pd(2., 100., 1., 100.);
10165 assert_eq_m256d(r, e);
10166 }
10167
10168 #[simd_test(enable = "avx512f,avx512vl")]
10169 unsafe fn test_mm256_maskz_permutex2var_pd() {
10170 let a = _mm256_set_pd(0., 1., 2., 3.);
10171 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10172 let b = _mm256_set1_pd(100.);
10173 let r = _mm256_maskz_permutex2var_pd(0, a, idx, b);
10174 assert_eq_m256d(r, _mm256_setzero_pd());
10175 let r = _mm256_maskz_permutex2var_pd(0b00001111, a, idx, b);
10176 let e = _mm256_set_pd(2., 100., 1., 100.);
10177 assert_eq_m256d(r, e);
10178 }
10179
10180 #[simd_test(enable = "avx512f,avx512vl")]
10181 unsafe fn test_mm256_mask2_permutex2var_pd() {
10182 let a = _mm256_set_pd(0., 1., 2., 3.);
10183 let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10184 let b = _mm256_set1_pd(100.);
10185 let r = _mm256_mask2_permutex2var_pd(a, idx, 0, b);
10186 assert_eq_m256d(r, _mm256_castsi256_pd(idx));
10187 let r = _mm256_mask2_permutex2var_pd(a, idx, 0b00001111, b);
10188 let e = _mm256_set_pd(2., 100., 1., 100.);
10189 assert_eq_m256d(r, e);
10190 }
10191
10192 #[simd_test(enable = "avx512f,avx512vl")]
10193 unsafe fn test_mm_permutex2var_pd() {
10194 let a = _mm_set_pd(0., 1.);
10195 let idx = _mm_set_epi64x(1, 1 << 1);
10196 let b = _mm_set1_pd(100.);
10197 let r = _mm_permutex2var_pd(a, idx, b);
10198 let e = _mm_set_pd(0., 100.);
10199 assert_eq_m128d(r, e);
10200 }
10201
10202 #[simd_test(enable = "avx512f,avx512vl")]
10203 unsafe fn test_mm_mask_permutex2var_pd() {
10204 let a = _mm_set_pd(0., 1.);
10205 let idx = _mm_set_epi64x(1, 1 << 1);
10206 let b = _mm_set1_pd(100.);
10207 let r = _mm_mask_permutex2var_pd(a, 0, idx, b);
10208 assert_eq_m128d(r, a);
10209 let r = _mm_mask_permutex2var_pd(a, 0b00000011, idx, b);
10210 let e = _mm_set_pd(0., 100.);
10211 assert_eq_m128d(r, e);
10212 }
10213
10214 #[simd_test(enable = "avx512f,avx512vl")]
10215 unsafe fn test_mm_maskz_permutex2var_pd() {
10216 let a = _mm_set_pd(0., 1.);
10217 let idx = _mm_set_epi64x(1, 1 << 1);
10218 let b = _mm_set1_pd(100.);
10219 let r = _mm_maskz_permutex2var_pd(0, a, idx, b);
10220 assert_eq_m128d(r, _mm_setzero_pd());
10221 let r = _mm_maskz_permutex2var_pd(0b00000011, a, idx, b);
10222 let e = _mm_set_pd(0., 100.);
10223 assert_eq_m128d(r, e);
10224 }
10225
10226 #[simd_test(enable = "avx512f,avx512vl")]
10227 unsafe fn test_mm_mask2_permutex2var_pd() {
10228 let a = _mm_set_pd(0., 1.);
10229 let idx = _mm_set_epi64x(1, 1 << 1);
10230 let b = _mm_set1_pd(100.);
10231 let r = _mm_mask2_permutex2var_pd(a, idx, 0, b);
10232 assert_eq_m128d(r, _mm_castsi128_pd(idx));
10233 let r = _mm_mask2_permutex2var_pd(a, idx, 0b00000011, b);
10234 let e = _mm_set_pd(0., 100.);
10235 assert_eq_m128d(r, e);
10236 }
10237
10238 #[simd_test(enable = "avx512f,avx512vl")]
10239 const unsafe fn test_mm256_mask_shuffle_pd() {
10240 let a = _mm256_set_pd(1., 4., 5., 8.);
10241 let b = _mm256_set_pd(2., 3., 6., 7.);
10242 let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10243 assert_eq_m256d(r, a);
10244 let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00001111, a, b);
10245 let e = _mm256_set_pd(2., 1., 6., 5.);
10246 assert_eq_m256d(r, e);
10247 }
10248
10249 #[simd_test(enable = "avx512f,avx512vl")]
10250 const unsafe fn test_mm256_maskz_shuffle_pd() {
10251 let a = _mm256_set_pd(1., 4., 5., 8.);
10252 let b = _mm256_set_pd(2., 3., 6., 7.);
10253 let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10254 assert_eq_m256d(r, _mm256_setzero_pd());
10255 let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0b00001111, a, b);
10256 let e = _mm256_set_pd(2., 1., 6., 5.);
10257 assert_eq_m256d(r, e);
10258 }
10259
10260 #[simd_test(enable = "avx512f,avx512vl")]
10261 const unsafe fn test_mm_mask_shuffle_pd() {
10262 let a = _mm_set_pd(1., 4.);
10263 let b = _mm_set_pd(2., 3.);
10264 let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10265 assert_eq_m128d(r, a);
10266 let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00000011, a, b);
10267 let e = _mm_set_pd(2., 1.);
10268 assert_eq_m128d(r, e);
10269 }
10270
10271 #[simd_test(enable = "avx512f,avx512vl")]
10272 const unsafe fn test_mm_maskz_shuffle_pd() {
10273 let a = _mm_set_pd(1., 4.);
10274 let b = _mm_set_pd(2., 3.);
10275 let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10276 assert_eq_m128d(r, _mm_setzero_pd());
10277 let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0b00000011, a, b);
10278 let e = _mm_set_pd(2., 1.);
10279 assert_eq_m128d(r, e);
10280 }
10281
10282 #[simd_test(enable = "avx512f")]
10283 const unsafe fn test_mm512_shuffle_i64x2() {
10284 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10285 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10286 let r = _mm512_shuffle_i64x2::<0b00_00_00_00>(a, b);
10287 let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10288 assert_eq_m512i(r, e);
10289 }
10290
10291 #[simd_test(enable = "avx512f")]
10292 const unsafe fn test_mm512_mask_shuffle_i64x2() {
10293 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10294 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10295 let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0, a, b);
10296 assert_eq_m512i(r, a);
10297 let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10298 let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10299 assert_eq_m512i(r, e);
10300 }
10301
10302 #[simd_test(enable = "avx512f")]
10303 const unsafe fn test_mm512_maskz_shuffle_i64x2() {
10304 let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10305 let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10306 let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0, a, b);
10307 assert_eq_m512i(r, _mm512_setzero_si512());
10308 let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0b00001111, a, b);
10309 let e = _mm512_setr_epi64(1, 4, 1, 4, 0, 0, 0, 0);
10310 assert_eq_m512i(r, e);
10311 }
10312
10313 #[simd_test(enable = "avx512f,avx512vl")]
10314 const unsafe fn test_mm256_shuffle_i64x2() {
10315 let a = _mm256_set_epi64x(1, 4, 5, 8);
10316 let b = _mm256_set_epi64x(2, 3, 6, 7);
10317 let r = _mm256_shuffle_i64x2::<0b00>(a, b);
10318 let e = _mm256_set_epi64x(6, 7, 5, 8);
10319 assert_eq_m256i(r, e);
10320 }
10321
10322 #[simd_test(enable = "avx512f,avx512vl")]
10323 const unsafe fn test_mm256_mask_shuffle_i64x2() {
10324 let a = _mm256_set_epi64x(1, 4, 5, 8);
10325 let b = _mm256_set_epi64x(2, 3, 6, 7);
10326 let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0, a, b);
10327 assert_eq_m256i(r, a);
10328 let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0b00001111, a, b);
10329 let e = _mm256_set_epi64x(6, 7, 5, 8);
10330 assert_eq_m256i(r, e);
10331 }
10332
10333 #[simd_test(enable = "avx512f,avx512vl")]
10334 const unsafe fn test_mm256_maskz_shuffle_i64x2() {
10335 let a = _mm256_set_epi64x(1, 4, 5, 8);
10336 let b = _mm256_set_epi64x(2, 3, 6, 7);
10337 let r = _mm256_maskz_shuffle_i64x2::<0b00>(0, a, b);
10338 assert_eq_m256i(r, _mm256_setzero_si256());
10339 let r = _mm256_maskz_shuffle_i64x2::<0b00>(0b00001111, a, b);
10340 let e = _mm256_set_epi64x(6, 7, 5, 8);
10341 assert_eq_m256i(r, e);
10342 }
10343
10344 #[simd_test(enable = "avx512f")]
10345 const unsafe fn test_mm512_shuffle_f64x2() {
10346 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10347 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10348 let r = _mm512_shuffle_f64x2::<0b00_00_00_00>(a, b);
10349 let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10350 assert_eq_m512d(r, e);
10351 }
10352
10353 #[simd_test(enable = "avx512f")]
10354 const unsafe fn test_mm512_mask_shuffle_f64x2() {
10355 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10356 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10357 let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0, a, b);
10358 assert_eq_m512d(r, a);
10359 let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10360 let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10361 assert_eq_m512d(r, e);
10362 }
10363
10364 #[simd_test(enable = "avx512f")]
10365 const unsafe fn test_mm512_maskz_shuffle_f64x2() {
10366 let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10367 let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10368 let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0, a, b);
10369 assert_eq_m512d(r, _mm512_setzero_pd());
10370 let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0b00001111, a, b);
10371 let e = _mm512_setr_pd(1., 4., 1., 4., 0., 0., 0., 0.);
10372 assert_eq_m512d(r, e);
10373 }
10374
10375 #[simd_test(enable = "avx512f,avx512vl")]
10376 const unsafe fn test_mm256_shuffle_f64x2() {
10377 let a = _mm256_set_pd(1., 4., 5., 8.);
10378 let b = _mm256_set_pd(2., 3., 6., 7.);
10379 let r = _mm256_shuffle_f64x2::<0b00>(a, b);
10380 let e = _mm256_set_pd(6., 7., 5., 8.);
10381 assert_eq_m256d(r, e);
10382 }
10383
10384 #[simd_test(enable = "avx512f,avx512vl")]
10385 const unsafe fn test_mm256_mask_shuffle_f64x2() {
10386 let a = _mm256_set_pd(1., 4., 5., 8.);
10387 let b = _mm256_set_pd(2., 3., 6., 7.);
10388 let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0, a, b);
10389 assert_eq_m256d(r, a);
10390 let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0b00001111, a, b);
10391 let e = _mm256_set_pd(6., 7., 5., 8.);
10392 assert_eq_m256d(r, e);
10393 }
10394
10395 #[simd_test(enable = "avx512f,avx512vl")]
10396 const unsafe fn test_mm256_maskz_shuffle_f64x2() {
10397 let a = _mm256_set_pd(1., 4., 5., 8.);
10398 let b = _mm256_set_pd(2., 3., 6., 7.);
10399 let r = _mm256_maskz_shuffle_f64x2::<0b00>(0, a, b);
10400 assert_eq_m256d(r, _mm256_setzero_pd());
10401 let r = _mm256_maskz_shuffle_f64x2::<0b00>(0b00001111, a, b);
10402 let e = _mm256_set_pd(6., 7., 5., 8.);
10403 assert_eq_m256d(r, e);
10404 }
10405
10406 #[simd_test(enable = "avx512f")]
10407 const unsafe fn test_mm512_movedup_pd() {
10408 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10409 let r = _mm512_movedup_pd(a);
10410 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10411 assert_eq_m512d(r, e);
10412 }
10413
10414 #[simd_test(enable = "avx512f")]
10415 const unsafe fn test_mm512_mask_movedup_pd() {
10416 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10417 let r = _mm512_mask_movedup_pd(a, 0, a);
10418 assert_eq_m512d(r, a);
10419 let r = _mm512_mask_movedup_pd(a, 0b11111111, a);
10420 let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10421 assert_eq_m512d(r, e);
10422 }
10423
10424 #[simd_test(enable = "avx512f")]
10425 const unsafe fn test_mm512_maskz_movedup_pd() {
10426 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10427 let r = _mm512_maskz_movedup_pd(0, a);
10428 assert_eq_m512d(r, _mm512_setzero_pd());
10429 let r = _mm512_maskz_movedup_pd(0b00001111, a);
10430 let e = _mm512_setr_pd(1., 1., 3., 3., 0., 0., 0., 0.);
10431 assert_eq_m512d(r, e);
10432 }
10433
10434 #[simd_test(enable = "avx512f,avx512vl")]
10435 const unsafe fn test_mm256_mask_movedup_pd() {
10436 let a = _mm256_set_pd(1., 2., 3., 4.);
10437 let r = _mm256_mask_movedup_pd(a, 0, a);
10438 assert_eq_m256d(r, a);
10439 let r = _mm256_mask_movedup_pd(a, 0b00001111, a);
10440 let e = _mm256_set_pd(2., 2., 4., 4.);
10441 assert_eq_m256d(r, e);
10442 }
10443
10444 #[simd_test(enable = "avx512f,avx512vl")]
10445 const unsafe fn test_mm256_maskz_movedup_pd() {
10446 let a = _mm256_set_pd(1., 2., 3., 4.);
10447 let r = _mm256_maskz_movedup_pd(0, a);
10448 assert_eq_m256d(r, _mm256_setzero_pd());
10449 let r = _mm256_maskz_movedup_pd(0b00001111, a);
10450 let e = _mm256_set_pd(2., 2., 4., 4.);
10451 assert_eq_m256d(r, e);
10452 }
10453
10454 #[simd_test(enable = "avx512f,avx512vl")]
10455 const unsafe fn test_mm_mask_movedup_pd() {
10456 let a = _mm_set_pd(1., 2.);
10457 let r = _mm_mask_movedup_pd(a, 0, a);
10458 assert_eq_m128d(r, a);
10459 let r = _mm_mask_movedup_pd(a, 0b00000011, a);
10460 let e = _mm_set_pd(2., 2.);
10461 assert_eq_m128d(r, e);
10462 }
10463
10464 #[simd_test(enable = "avx512f,avx512vl")]
10465 const unsafe fn test_mm_maskz_movedup_pd() {
10466 let a = _mm_set_pd(1., 2.);
10467 let r = _mm_maskz_movedup_pd(0, a);
10468 assert_eq_m128d(r, _mm_setzero_pd());
10469 let r = _mm_maskz_movedup_pd(0b00000011, a);
10470 let e = _mm_set_pd(2., 2.);
10471 assert_eq_m128d(r, e);
10472 }
10473
10474 #[simd_test(enable = "avx512f")]
10475 const unsafe fn test_mm512_inserti64x4() {
10476 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10477 let b = _mm256_setr_epi64x(17, 18, 19, 20);
10478 let r = _mm512_inserti64x4::<1>(a, b);
10479 let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10480 assert_eq_m512i(r, e);
10481 }
10482
10483 #[simd_test(enable = "avx512f")]
10484 const unsafe fn test_mm512_mask_inserti64x4() {
10485 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10486 let b = _mm256_setr_epi64x(17, 18, 19, 20);
10487 let r = _mm512_mask_inserti64x4::<1>(a, 0, a, b);
10488 assert_eq_m512i(r, a);
10489 let r = _mm512_mask_inserti64x4::<1>(a, 0b11111111, a, b);
10490 let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10491 assert_eq_m512i(r, e);
10492 }
10493
10494 #[simd_test(enable = "avx512f")]
10495 const unsafe fn test_mm512_maskz_inserti64x4() {
10496 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10497 let b = _mm256_setr_epi64x(17, 18, 19, 20);
10498 let r = _mm512_maskz_inserti64x4::<1>(0, a, b);
10499 assert_eq_m512i(r, _mm512_setzero_si512());
10500 let r = _mm512_maskz_inserti64x4::<1>(0b00001111, a, b);
10501 let e = _mm512_setr_epi64(1, 2, 3, 4, 0, 0, 0, 0);
10502 assert_eq_m512i(r, e);
10503 }
10504
10505 #[simd_test(enable = "avx512f")]
10506 const unsafe fn test_mm512_insertf64x4() {
10507 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10508 let b = _mm256_setr_pd(17., 18., 19., 20.);
10509 let r = _mm512_insertf64x4::<1>(a, b);
10510 let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10511 assert_eq_m512d(r, e);
10512 }
10513
10514 #[simd_test(enable = "avx512f")]
10515 const unsafe fn test_mm512_mask_insertf64x4() {
10516 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10517 let b = _mm256_setr_pd(17., 18., 19., 20.);
10518 let r = _mm512_mask_insertf64x4::<1>(a, 0, a, b);
10519 assert_eq_m512d(r, a);
10520 let r = _mm512_mask_insertf64x4::<1>(a, 0b11111111, a, b);
10521 let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10522 assert_eq_m512d(r, e);
10523 }
10524
10525 #[simd_test(enable = "avx512f")]
10526 const unsafe fn test_mm512_maskz_insertf64x4() {
10527 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10528 let b = _mm256_setr_pd(17., 18., 19., 20.);
10529 let r = _mm512_maskz_insertf64x4::<1>(0, a, b);
10530 assert_eq_m512d(r, _mm512_setzero_pd());
10531 let r = _mm512_maskz_insertf64x4::<1>(0b00001111, a, b);
10532 let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
10533 assert_eq_m512d(r, e);
10534 }
10535
10536 #[simd_test(enable = "avx512f")]
10537 const unsafe fn test_mm512_castpd128_pd512() {
10538 let a = _mm_setr_pd(17., 18.);
10539 let r = _mm512_castpd128_pd512(a);
10540 assert_eq_m128d(_mm512_castpd512_pd128(r), a);
10541 }
10542
10543 #[simd_test(enable = "avx512f")]
10544 const unsafe fn test_mm512_castpd256_pd512() {
10545 let a = _mm256_setr_pd(17., 18., 19., 20.);
10546 let r = _mm512_castpd256_pd512(a);
10547 assert_eq_m256d(_mm512_castpd512_pd256(r), a);
10548 }
10549
10550 #[simd_test(enable = "avx512f")]
10551 const unsafe fn test_mm512_zextpd128_pd512() {
10552 let a = _mm_setr_pd(17., 18.);
10553 let r = _mm512_zextpd128_pd512(a);
10554 let e = _mm512_setr_pd(17., 18., 0., 0., 0., 0., 0., 0.);
10555 assert_eq_m512d(r, e);
10556 }
10557
10558 #[simd_test(enable = "avx512f")]
10559 const unsafe fn test_mm512_zextpd256_pd512() {
10560 let a = _mm256_setr_pd(17., 18., 19., 20.);
10561 let r = _mm512_zextpd256_pd512(a);
10562 let e = _mm512_setr_pd(17., 18., 19., 20., 0., 0., 0., 0.);
10563 assert_eq_m512d(r, e);
10564 }
10565
10566 #[simd_test(enable = "avx512f")]
10567 const unsafe fn test_mm512_castpd512_pd128() {
10568 let a = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
10569 let r = _mm512_castpd512_pd128(a);
10570 let e = _mm_setr_pd(17., 18.);
10571 assert_eq_m128d(r, e);
10572 }
10573
10574 #[simd_test(enable = "avx512f")]
10575 const unsafe fn test_mm512_castpd512_pd256() {
10576 let a = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
10577 let r = _mm512_castpd512_pd256(a);
10578 let e = _mm256_setr_pd(17., 18., 19., 20.);
10579 assert_eq_m256d(r, e);
10580 }
10581
10582 #[simd_test(enable = "avx512f")]
10583 const unsafe fn test_mm512_castpd_ps() {
10584 let a = _mm512_set1_pd(1.);
10585 let r = _mm512_castpd_ps(a);
10586 let e = _mm512_set_ps(
10587 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0,
10588 1.875, 0.0,
10589 );
10590 assert_eq_m512(r, e);
10591 }
10592
10593 #[simd_test(enable = "avx512f")]
10594 const unsafe fn test_mm512_castpd_si512() {
10595 let a = _mm512_set1_pd(1.);
10596 let r = _mm512_castpd_si512(a);
10597 let e = _mm512_set_epi32(
10598 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248,
10599 0, 1072693248, 0, 1072693248, 0,
10600 );
10601 assert_eq_m512i(r, e);
10602 }
10603
10604 #[simd_test(enable = "avx512f")]
10605 const unsafe fn test_mm512_castsi128_si512() {
10606 let a = _mm_setr_epi64x(17, 18);
10607 let r = _mm512_castsi128_si512(a);
10608 assert_eq_m128i(_mm512_castsi512_si128(r), a);
10609 }
10610
10611 #[simd_test(enable = "avx512f")]
10612 const unsafe fn test_mm512_castsi256_si512() {
10613 let a = _mm256_setr_epi64x(17, 18, 19, 20);
10614 let r = _mm512_castsi256_si512(a);
10615 assert_eq_m256i(_mm512_castsi512_si256(r), a);
10616 }
10617
10618 #[simd_test(enable = "avx512f")]
10619 const unsafe fn test_mm512_zextsi128_si512() {
10620 let a = _mm_setr_epi64x(17, 18);
10621 let r = _mm512_zextsi128_si512(a);
10622 let e = _mm512_setr_epi64(17, 18, 0, 0, 0, 0, 0, 0);
10623 assert_eq_m512i(r, e);
10624 }
10625
10626 #[simd_test(enable = "avx512f")]
10627 const unsafe fn test_mm512_zextsi256_si512() {
10628 let a = _mm256_setr_epi64x(17, 18, 19, 20);
10629 let r = _mm512_zextsi256_si512(a);
10630 let e = _mm512_setr_epi64(17, 18, 19, 20, 0, 0, 0, 0);
10631 assert_eq_m512i(r, e);
10632 }
10633
10634 #[simd_test(enable = "avx512f")]
10635 const unsafe fn test_mm512_castsi512_si128() {
10636 let a = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
10637 let r = _mm512_castsi512_si128(a);
10638 let e = _mm_setr_epi64x(17, 18);
10639 assert_eq_m128i(r, e);
10640 }
10641
10642 #[simd_test(enable = "avx512f")]
10643 const unsafe fn test_mm512_castsi512_si256() {
10644 let a = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
10645 let r = _mm512_castsi512_si256(a);
10646 let e = _mm256_setr_epi64x(17, 18, 19, 20);
10647 assert_eq_m256i(r, e);
10648 }
10649
10650 #[simd_test(enable = "avx512f")]
10651 const unsafe fn test_mm512_castsi512_ps() {
10652 let a = _mm512_set1_epi64(1 << 62);
10653 let r = _mm512_castsi512_ps(a);
10654 let e = _mm512_set_ps(
10655 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0.,
10656 );
10657 assert_eq_m512(r, e);
10658 }
10659
10660 #[simd_test(enable = "avx512f")]
10661 const unsafe fn test_mm512_castsi512_pd() {
10662 let a = _mm512_set1_epi64(1 << 62);
10663 let r = _mm512_castsi512_pd(a);
10664 let e = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
10665 assert_eq_m512d(r, e);
10666 }
10667
10668 #[simd_test(enable = "avx512f")]
10669 const unsafe fn test_mm512_broadcastq_epi64() {
10670 let a = _mm_setr_epi64x(17, 18);
10671 let r = _mm512_broadcastq_epi64(a);
10672 let e = _mm512_set1_epi64(17);
10673 assert_eq_m512i(r, e);
10674 }
10675
10676 #[simd_test(enable = "avx512f")]
10677 const unsafe fn test_mm512_mask_broadcastq_epi64() {
10678 let src = _mm512_set1_epi64(18);
10679 let a = _mm_setr_epi64x(17, 18);
10680 let r = _mm512_mask_broadcastq_epi64(src, 0, a);
10681 assert_eq_m512i(r, src);
10682 let r = _mm512_mask_broadcastq_epi64(src, 0b11111111, a);
10683 let e = _mm512_set1_epi64(17);
10684 assert_eq_m512i(r, e);
10685 }
10686
10687 #[simd_test(enable = "avx512f")]
10688 const unsafe fn test_mm512_maskz_broadcastq_epi64() {
10689 let a = _mm_setr_epi64x(17, 18);
10690 let r = _mm512_maskz_broadcastq_epi64(0, a);
10691 assert_eq_m512i(r, _mm512_setzero_si512());
10692 let r = _mm512_maskz_broadcastq_epi64(0b00001111, a);
10693 let e = _mm512_set_epi64(0, 0, 0, 0, 17, 17, 17, 17);
10694 assert_eq_m512i(r, e);
10695 }
10696
10697 #[simd_test(enable = "avx512f,avx512vl")]
10698 const unsafe fn test_mm256_mask_broadcastq_epi64() {
10699 let src = _mm256_set1_epi64x(18);
10700 let a = _mm_set_epi64x(17, 18);
10701 let r = _mm256_mask_broadcastq_epi64(src, 0, a);
10702 assert_eq_m256i(r, src);
10703 let r = _mm256_mask_broadcastq_epi64(src, 0b00001111, a);
10704 let e = _mm256_set1_epi64x(18);
10705 assert_eq_m256i(r, e);
10706 }
10707
10708 #[simd_test(enable = "avx512f,avx512vl")]
10709 const unsafe fn test_mm256_maskz_broadcastq_epi64() {
10710 let a = _mm_set_epi64x(17, 18);
10711 let r = _mm256_maskz_broadcastq_epi64(0, a);
10712 assert_eq_m256i(r, _mm256_setzero_si256());
10713 let r = _mm256_maskz_broadcastq_epi64(0b00001111, a);
10714 let e = _mm256_set1_epi64x(18);
10715 assert_eq_m256i(r, e);
10716 }
10717
10718 #[simd_test(enable = "avx512f,avx512vl")]
10719 const unsafe fn test_mm_mask_broadcastq_epi64() {
10720 let src = _mm_set1_epi64x(18);
10721 let a = _mm_set_epi64x(17, 18);
10722 let r = _mm_mask_broadcastq_epi64(src, 0, a);
10723 assert_eq_m128i(r, src);
10724 let r = _mm_mask_broadcastq_epi64(src, 0b00000011, a);
10725 let e = _mm_set1_epi64x(18);
10726 assert_eq_m128i(r, e);
10727 }
10728
10729 #[simd_test(enable = "avx512f,avx512vl")]
10730 const unsafe fn test_mm_maskz_broadcastq_epi64() {
10731 let a = _mm_set_epi64x(17, 18);
10732 let r = _mm_maskz_broadcastq_epi64(0, a);
10733 assert_eq_m128i(r, _mm_setzero_si128());
10734 let r = _mm_maskz_broadcastq_epi64(0b00000011, a);
10735 let e = _mm_set1_epi64x(18);
10736 assert_eq_m128i(r, e);
10737 }
10738
10739 #[simd_test(enable = "avx512f")]
10740 const unsafe fn test_mm512_broadcastsd_pd() {
10741 let a = _mm_set_pd(17., 18.);
10742 let r = _mm512_broadcastsd_pd(a);
10743 let e = _mm512_set1_pd(18.);
10744 assert_eq_m512d(r, e);
10745 }
10746
10747 #[simd_test(enable = "avx512f")]
10748 const unsafe fn test_mm512_mask_broadcastsd_pd() {
10749 let src = _mm512_set1_pd(18.);
10750 let a = _mm_set_pd(17., 18.);
10751 let r = _mm512_mask_broadcastsd_pd(src, 0, a);
10752 assert_eq_m512d(r, src);
10753 let r = _mm512_mask_broadcastsd_pd(src, 0b11111111, a);
10754 let e = _mm512_set1_pd(18.);
10755 assert_eq_m512d(r, e);
10756 }
10757
10758 #[simd_test(enable = "avx512f")]
10759 const unsafe fn test_mm512_maskz_broadcastsd_pd() {
10760 let a = _mm_set_pd(17., 18.);
10761 let r = _mm512_maskz_broadcastsd_pd(0, a);
10762 assert_eq_m512d(r, _mm512_setzero_pd());
10763 let r = _mm512_maskz_broadcastsd_pd(0b00001111, a);
10764 let e = _mm512_set_pd(0., 0., 0., 0., 18., 18., 18., 18.);
10765 assert_eq_m512d(r, e);
10766 }
10767
10768 #[simd_test(enable = "avx512f,avx512vl")]
10769 const unsafe fn test_mm256_mask_broadcastsd_pd() {
10770 let src = _mm256_set1_pd(18.);
10771 let a = _mm_set_pd(17., 18.);
10772 let r = _mm256_mask_broadcastsd_pd(src, 0, a);
10773 assert_eq_m256d(r, src);
10774 let r = _mm256_mask_broadcastsd_pd(src, 0b00001111, a);
10775 let e = _mm256_set1_pd(18.);
10776 assert_eq_m256d(r, e);
10777 }
10778
10779 #[simd_test(enable = "avx512f,avx512vl")]
10780 const unsafe fn test_mm256_maskz_broadcastsd_pd() {
10781 let a = _mm_set_pd(17., 18.);
10782 let r = _mm256_maskz_broadcastsd_pd(0, a);
10783 assert_eq_m256d(r, _mm256_setzero_pd());
10784 let r = _mm256_maskz_broadcastsd_pd(0b00001111, a);
10785 let e = _mm256_set1_pd(18.);
10786 assert_eq_m256d(r, e);
10787 }
10788
10789 #[simd_test(enable = "avx512f")]
10790 const unsafe fn test_mm512_broadcast_i64x4() {
10791 let a = _mm256_set_epi64x(17, 18, 19, 20);
10792 let r = _mm512_broadcast_i64x4(a);
10793 let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10794 assert_eq_m512i(r, e);
10795 }
10796
10797 #[simd_test(enable = "avx512f")]
10798 const unsafe fn test_mm512_mask_broadcast_i64x4() {
10799 let src = _mm512_set1_epi64(18);
10800 let a = _mm256_set_epi64x(17, 18, 19, 20);
10801 let r = _mm512_mask_broadcast_i64x4(src, 0, a);
10802 assert_eq_m512i(r, src);
10803 let r = _mm512_mask_broadcast_i64x4(src, 0b11111111, a);
10804 let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10805 assert_eq_m512i(r, e);
10806 }
10807
10808 #[simd_test(enable = "avx512f")]
10809 const unsafe fn test_mm512_maskz_broadcast_i64x4() {
10810 let a = _mm256_set_epi64x(17, 18, 19, 20);
10811 let r = _mm512_maskz_broadcast_i64x4(0, a);
10812 assert_eq_m512i(r, _mm512_setzero_si512());
10813 let r = _mm512_maskz_broadcast_i64x4(0b00001111, a);
10814 let e = _mm512_set_epi64(0, 0, 0, 0, 17, 18, 19, 20);
10815 assert_eq_m512i(r, e);
10816 }
10817
10818 #[simd_test(enable = "avx512f")]
10819 const unsafe fn test_mm512_broadcast_f64x4() {
10820 let a = _mm256_set_pd(17., 18., 19., 20.);
10821 let r = _mm512_broadcast_f64x4(a);
10822 let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10823 assert_eq_m512d(r, e);
10824 }
10825
10826 #[simd_test(enable = "avx512f")]
10827 const unsafe fn test_mm512_mask_broadcast_f64x4() {
10828 let src = _mm512_set1_pd(18.);
10829 let a = _mm256_set_pd(17., 18., 19., 20.);
10830 let r = _mm512_mask_broadcast_f64x4(src, 0, a);
10831 assert_eq_m512d(r, src);
10832 let r = _mm512_mask_broadcast_f64x4(src, 0b11111111, a);
10833 let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10834 assert_eq_m512d(r, e);
10835 }
10836
10837 #[simd_test(enable = "avx512f")]
10838 const unsafe fn test_mm512_maskz_broadcast_f64x4() {
10839 let a = _mm256_set_pd(17., 18., 19., 20.);
10840 let r = _mm512_maskz_broadcast_f64x4(0, a);
10841 assert_eq_m512d(r, _mm512_setzero_pd());
10842 let r = _mm512_maskz_broadcast_f64x4(0b00001111, a);
10843 let e = _mm512_set_pd(0., 0., 0., 0., 17., 18., 19., 20.);
10844 assert_eq_m512d(r, e);
10845 }
10846
10847 #[simd_test(enable = "avx512f")]
10848 const unsafe fn test_mm512_mask_blend_epi64() {
10849 let a = _mm512_set1_epi64(1);
10850 let b = _mm512_set1_epi64(2);
10851 let r = _mm512_mask_blend_epi64(0b11110000, a, b);
10852 let e = _mm512_set_epi64(2, 2, 2, 2, 1, 1, 1, 1);
10853 assert_eq_m512i(r, e);
10854 }
10855
10856 #[simd_test(enable = "avx512f,avx512vl")]
10857 const unsafe fn test_mm256_mask_blend_epi64() {
10858 let a = _mm256_set1_epi64x(1);
10859 let b = _mm256_set1_epi64x(2);
10860 let r = _mm256_mask_blend_epi64(0b00001111, a, b);
10861 let e = _mm256_set1_epi64x(2);
10862 assert_eq_m256i(r, e);
10863 }
10864
10865 #[simd_test(enable = "avx512f,avx512vl")]
10866 const unsafe fn test_mm_mask_blend_epi64() {
10867 let a = _mm_set1_epi64x(1);
10868 let b = _mm_set1_epi64x(2);
10869 let r = _mm_mask_blend_epi64(0b00000011, a, b);
10870 let e = _mm_set1_epi64x(2);
10871 assert_eq_m128i(r, e);
10872 }
10873
10874 #[simd_test(enable = "avx512f")]
10875 const unsafe fn test_mm512_mask_blend_pd() {
10876 let a = _mm512_set1_pd(1.);
10877 let b = _mm512_set1_pd(2.);
10878 let r = _mm512_mask_blend_pd(0b11110000, a, b);
10879 let e = _mm512_set_pd(2., 2., 2., 2., 1., 1., 1., 1.);
10880 assert_eq_m512d(r, e);
10881 }
10882
10883 #[simd_test(enable = "avx512f,avx512vl")]
10884 const unsafe fn test_mm256_mask_blend_pd() {
10885 let a = _mm256_set1_pd(1.);
10886 let b = _mm256_set1_pd(2.);
10887 let r = _mm256_mask_blend_pd(0b00001111, a, b);
10888 let e = _mm256_set1_pd(2.);
10889 assert_eq_m256d(r, e);
10890 }
10891
10892 #[simd_test(enable = "avx512f,avx512vl")]
10893 const unsafe fn test_mm_mask_blend_pd() {
10894 let a = _mm_set1_pd(1.);
10895 let b = _mm_set1_pd(2.);
10896 let r = _mm_mask_blend_pd(0b00000011, a, b);
10897 let e = _mm_set1_pd(2.);
10898 assert_eq_m128d(r, e);
10899 }
10900
10901 #[simd_test(enable = "avx512f")]
10902 const unsafe fn test_mm512_unpackhi_epi64() {
10903 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10904 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10905 let r = _mm512_unpackhi_epi64(a, b);
10906 let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10907 assert_eq_m512i(r, e);
10908 }
10909
10910 #[simd_test(enable = "avx512f")]
10911 const unsafe fn test_mm512_mask_unpackhi_epi64() {
10912 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10913 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10914 let r = _mm512_mask_unpackhi_epi64(a, 0, a, b);
10915 assert_eq_m512i(r, a);
10916 let r = _mm512_mask_unpackhi_epi64(a, 0b11111111, a, b);
10917 let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
10918 assert_eq_m512i(r, e);
10919 }
10920
10921 #[simd_test(enable = "avx512f")]
10922 const unsafe fn test_mm512_maskz_unpackhi_epi64() {
10923 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10924 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
10925 let r = _mm512_maskz_unpackhi_epi64(0, a, b);
10926 assert_eq_m512i(r, _mm512_setzero_si512());
10927 let r = _mm512_maskz_unpackhi_epi64(0b00001111, a, b);
10928 let e = _mm512_set_epi64(0, 0, 0, 0, 21, 5, 23, 7);
10929 assert_eq_m512i(r, e);
10930 }
10931
10932 #[simd_test(enable = "avx512f,avx512vl")]
10933 const unsafe fn test_mm256_mask_unpackhi_epi64() {
10934 let a = _mm256_set_epi64x(1, 2, 3, 4);
10935 let b = _mm256_set_epi64x(17, 18, 19, 20);
10936 let r = _mm256_mask_unpackhi_epi64(a, 0, a, b);
10937 assert_eq_m256i(r, a);
10938 let r = _mm256_mask_unpackhi_epi64(a, 0b00001111, a, b);
10939 let e = _mm256_set_epi64x(17, 1, 19, 3);
10940 assert_eq_m256i(r, e);
10941 }
10942
10943 #[simd_test(enable = "avx512f,avx512vl")]
10944 const unsafe fn test_mm256_maskz_unpackhi_epi64() {
10945 let a = _mm256_set_epi64x(1, 2, 3, 4);
10946 let b = _mm256_set_epi64x(17, 18, 19, 20);
10947 let r = _mm256_maskz_unpackhi_epi64(0, a, b);
10948 assert_eq_m256i(r, _mm256_setzero_si256());
10949 let r = _mm256_maskz_unpackhi_epi64(0b00001111, a, b);
10950 let e = _mm256_set_epi64x(17, 1, 19, 3);
10951 assert_eq_m256i(r, e);
10952 }
10953
10954 #[simd_test(enable = "avx512f,avx512vl")]
10955 const unsafe fn test_mm_mask_unpackhi_epi64() {
10956 let a = _mm_set_epi64x(1, 2);
10957 let b = _mm_set_epi64x(17, 18);
10958 let r = _mm_mask_unpackhi_epi64(a, 0, a, b);
10959 assert_eq_m128i(r, a);
10960 let r = _mm_mask_unpackhi_epi64(a, 0b00000011, a, b);
10961 let e = _mm_set_epi64x(17, 1);
10962 assert_eq_m128i(r, e);
10963 }
10964
10965 #[simd_test(enable = "avx512f,avx512vl")]
10966 const unsafe fn test_mm_maskz_unpackhi_epi64() {
10967 let a = _mm_set_epi64x(1, 2);
10968 let b = _mm_set_epi64x(17, 18);
10969 let r = _mm_maskz_unpackhi_epi64(0, a, b);
10970 assert_eq_m128i(r, _mm_setzero_si128());
10971 let r = _mm_maskz_unpackhi_epi64(0b00000011, a, b);
10972 let e = _mm_set_epi64x(17, 1);
10973 assert_eq_m128i(r, e);
10974 }
10975
10976 #[simd_test(enable = "avx512f")]
10977 const unsafe fn test_mm512_unpackhi_pd() {
10978 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10979 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10980 let r = _mm512_unpackhi_pd(a, b);
10981 let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10982 assert_eq_m512d(r, e);
10983 }
10984
10985 #[simd_test(enable = "avx512f")]
10986 const unsafe fn test_mm512_mask_unpackhi_pd() {
10987 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10988 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
10989 let r = _mm512_mask_unpackhi_pd(a, 0, a, b);
10990 assert_eq_m512d(r, a);
10991 let r = _mm512_mask_unpackhi_pd(a, 0b11111111, a, b);
10992 let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
10993 assert_eq_m512d(r, e);
10994 }
10995
10996 #[simd_test(enable = "avx512f")]
10997 const unsafe fn test_mm512_maskz_unpackhi_pd() {
10998 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10999 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11000 let r = _mm512_maskz_unpackhi_pd(0, a, b);
11001 assert_eq_m512d(r, _mm512_setzero_pd());
11002 let r = _mm512_maskz_unpackhi_pd(0b00001111, a, b);
11003 let e = _mm512_set_pd(0., 0., 0., 0., 21., 5., 23., 7.);
11004 assert_eq_m512d(r, e);
11005 }
11006
11007 #[simd_test(enable = "avx512f,avx512vl")]
11008 const unsafe fn test_mm256_mask_unpackhi_pd() {
11009 let a = _mm256_set_pd(1., 2., 3., 4.);
11010 let b = _mm256_set_pd(17., 18., 19., 20.);
11011 let r = _mm256_mask_unpackhi_pd(a, 0, a, b);
11012 assert_eq_m256d(r, a);
11013 let r = _mm256_mask_unpackhi_pd(a, 0b00001111, a, b);
11014 let e = _mm256_set_pd(17., 1., 19., 3.);
11015 assert_eq_m256d(r, e);
11016 }
11017
11018 #[simd_test(enable = "avx512f,avx512vl")]
11019 const unsafe fn test_mm256_maskz_unpackhi_pd() {
11020 let a = _mm256_set_pd(1., 2., 3., 4.);
11021 let b = _mm256_set_pd(17., 18., 19., 20.);
11022 let r = _mm256_maskz_unpackhi_pd(0, a, b);
11023 assert_eq_m256d(r, _mm256_setzero_pd());
11024 let r = _mm256_maskz_unpackhi_pd(0b00001111, a, b);
11025 let e = _mm256_set_pd(17., 1., 19., 3.);
11026 assert_eq_m256d(r, e);
11027 }
11028
11029 #[simd_test(enable = "avx512f,avx512vl")]
11030 const unsafe fn test_mm_mask_unpackhi_pd() {
11031 let a = _mm_set_pd(1., 2.);
11032 let b = _mm_set_pd(17., 18.);
11033 let r = _mm_mask_unpackhi_pd(a, 0, a, b);
11034 assert_eq_m128d(r, a);
11035 let r = _mm_mask_unpackhi_pd(a, 0b00000011, a, b);
11036 let e = _mm_set_pd(17., 1.);
11037 assert_eq_m128d(r, e);
11038 }
11039
11040 #[simd_test(enable = "avx512f,avx512vl")]
11041 const unsafe fn test_mm_maskz_unpackhi_pd() {
11042 let a = _mm_set_pd(1., 2.);
11043 let b = _mm_set_pd(17., 18.);
11044 let r = _mm_maskz_unpackhi_pd(0, a, b);
11045 assert_eq_m128d(r, _mm_setzero_pd());
11046 let r = _mm_maskz_unpackhi_pd(0b00000011, a, b);
11047 let e = _mm_set_pd(17., 1.);
11048 assert_eq_m128d(r, e);
11049 }
11050
11051 #[simd_test(enable = "avx512f")]
11052 const unsafe fn test_mm512_unpacklo_epi64() {
11053 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11054 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11055 let r = _mm512_unpacklo_epi64(a, b);
11056 let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11057 assert_eq_m512i(r, e);
11058 }
11059
11060 #[simd_test(enable = "avx512f")]
11061 const unsafe fn test_mm512_mask_unpacklo_epi64() {
11062 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11063 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11064 let r = _mm512_mask_unpacklo_epi64(a, 0, a, b);
11065 assert_eq_m512i(r, a);
11066 let r = _mm512_mask_unpacklo_epi64(a, 0b11111111, a, b);
11067 let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11068 assert_eq_m512i(r, e);
11069 }
11070
11071 #[simd_test(enable = "avx512f")]
11072 const unsafe fn test_mm512_maskz_unpacklo_epi64() {
11073 let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11074 let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11075 let r = _mm512_maskz_unpacklo_epi64(0, a, b);
11076 assert_eq_m512i(r, _mm512_setzero_si512());
11077 let r = _mm512_maskz_unpacklo_epi64(0b00001111, a, b);
11078 let e = _mm512_set_epi64(0, 0, 0, 0, 22, 6, 24, 8);
11079 assert_eq_m512i(r, e);
11080 }
11081
11082 #[simd_test(enable = "avx512f,avx512vl")]
11083 const unsafe fn test_mm256_mask_unpacklo_epi64() {
11084 let a = _mm256_set_epi64x(1, 2, 3, 4);
11085 let b = _mm256_set_epi64x(17, 18, 19, 20);
11086 let r = _mm256_mask_unpacklo_epi64(a, 0, a, b);
11087 assert_eq_m256i(r, a);
11088 let r = _mm256_mask_unpacklo_epi64(a, 0b00001111, a, b);
11089 let e = _mm256_set_epi64x(18, 2, 20, 4);
11090 assert_eq_m256i(r, e);
11091 }
11092
11093 #[simd_test(enable = "avx512f,avx512vl")]
11094 const unsafe fn test_mm256_maskz_unpacklo_epi64() {
11095 let a = _mm256_set_epi64x(1, 2, 3, 4);
11096 let b = _mm256_set_epi64x(17, 18, 19, 20);
11097 let r = _mm256_maskz_unpacklo_epi64(0, a, b);
11098 assert_eq_m256i(r, _mm256_setzero_si256());
11099 let r = _mm256_maskz_unpacklo_epi64(0b00001111, a, b);
11100 let e = _mm256_set_epi64x(18, 2, 20, 4);
11101 assert_eq_m256i(r, e);
11102 }
11103
11104 #[simd_test(enable = "avx512f,avx512vl")]
11105 const unsafe fn test_mm_mask_unpacklo_epi64() {
11106 let a = _mm_set_epi64x(1, 2);
11107 let b = _mm_set_epi64x(17, 18);
11108 let r = _mm_mask_unpacklo_epi64(a, 0, a, b);
11109 assert_eq_m128i(r, a);
11110 let r = _mm_mask_unpacklo_epi64(a, 0b00000011, a, b);
11111 let e = _mm_set_epi64x(18, 2);
11112 assert_eq_m128i(r, e);
11113 }
11114
11115 #[simd_test(enable = "avx512f,avx512vl")]
11116 const unsafe fn test_mm_maskz_unpacklo_epi64() {
11117 let a = _mm_set_epi64x(1, 2);
11118 let b = _mm_set_epi64x(17, 18);
11119 let r = _mm_maskz_unpacklo_epi64(0, a, b);
11120 assert_eq_m128i(r, _mm_setzero_si128());
11121 let r = _mm_maskz_unpacklo_epi64(0b00000011, a, b);
11122 let e = _mm_set_epi64x(18, 2);
11123 assert_eq_m128i(r, e);
11124 }
11125
11126 #[simd_test(enable = "avx512f")]
11127 const unsafe fn test_mm512_unpacklo_pd() {
11128 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11129 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11130 let r = _mm512_unpacklo_pd(a, b);
11131 let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11132 assert_eq_m512d(r, e);
11133 }
11134
11135 #[simd_test(enable = "avx512f")]
11136 const unsafe fn test_mm512_mask_unpacklo_pd() {
11137 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11138 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11139 let r = _mm512_mask_unpacklo_pd(a, 0, a, b);
11140 assert_eq_m512d(r, a);
11141 let r = _mm512_mask_unpacklo_pd(a, 0b11111111, a, b);
11142 let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11143 assert_eq_m512d(r, e);
11144 }
11145
11146 #[simd_test(enable = "avx512f")]
11147 const unsafe fn test_mm512_maskz_unpacklo_pd() {
11148 let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11149 let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11150 let r = _mm512_maskz_unpacklo_pd(0, a, b);
11151 assert_eq_m512d(r, _mm512_setzero_pd());
11152 let r = _mm512_maskz_unpacklo_pd(0b00001111, a, b);
11153 let e = _mm512_set_pd(0., 0., 0., 0., 22., 6., 24., 8.);
11154 assert_eq_m512d(r, e);
11155 }
11156
11157 #[simd_test(enable = "avx512f,avx512vl")]
11158 const unsafe fn test_mm256_mask_unpacklo_pd() {
11159 let a = _mm256_set_pd(1., 2., 3., 4.);
11160 let b = _mm256_set_pd(17., 18., 19., 20.);
11161 let r = _mm256_mask_unpacklo_pd(a, 0, a, b);
11162 assert_eq_m256d(r, a);
11163 let r = _mm256_mask_unpacklo_pd(a, 0b00001111, a, b);
11164 let e = _mm256_set_pd(18., 2., 20., 4.);
11165 assert_eq_m256d(r, e);
11166 }
11167
11168 #[simd_test(enable = "avx512f,avx512vl")]
11169 const unsafe fn test_mm256_maskz_unpacklo_pd() {
11170 let a = _mm256_set_pd(1., 2., 3., 4.);
11171 let b = _mm256_set_pd(17., 18., 19., 20.);
11172 let r = _mm256_maskz_unpacklo_pd(0, a, b);
11173 assert_eq_m256d(r, _mm256_setzero_pd());
11174 let r = _mm256_maskz_unpacklo_pd(0b00001111, a, b);
11175 let e = _mm256_set_pd(18., 2., 20., 4.);
11176 assert_eq_m256d(r, e);
11177 }
11178
11179 #[simd_test(enable = "avx512f,avx512vl")]
11180 const unsafe fn test_mm_mask_unpacklo_pd() {
11181 let a = _mm_set_pd(1., 2.);
11182 let b = _mm_set_pd(17., 18.);
11183 let r = _mm_mask_unpacklo_pd(a, 0, a, b);
11184 assert_eq_m128d(r, a);
11185 let r = _mm_mask_unpacklo_pd(a, 0b00000011, a, b);
11186 let e = _mm_set_pd(18., 2.);
11187 assert_eq_m128d(r, e);
11188 }
11189
11190 #[simd_test(enable = "avx512f,avx512vl")]
11191 const unsafe fn test_mm_maskz_unpacklo_pd() {
11192 let a = _mm_set_pd(1., 2.);
11193 let b = _mm_set_pd(17., 18.);
11194 let r = _mm_maskz_unpacklo_pd(0, a, b);
11195 assert_eq_m128d(r, _mm_setzero_pd());
11196 let r = _mm_maskz_unpacklo_pd(0b00000011, a, b);
11197 let e = _mm_set_pd(18., 2.);
11198 assert_eq_m128d(r, e);
11199 }
11200
11201 #[simd_test(enable = "avx512f")]
11202 const unsafe fn test_mm512_alignr_epi64() {
11203 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11204 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11205 let r = _mm512_alignr_epi64::<0>(a, b);
11206 assert_eq_m512i(r, b);
11207 let r = _mm512_alignr_epi64::<8>(a, b);
11208 assert_eq_m512i(r, b);
11209 let r = _mm512_alignr_epi64::<1>(a, b);
11210 let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11211 assert_eq_m512i(r, e);
11212 }
11213
11214 #[simd_test(enable = "avx512f")]
11215 const unsafe fn test_mm512_mask_alignr_epi64() {
11216 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11217 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11218 let r = _mm512_mask_alignr_epi64::<1>(a, 0, a, b);
11219 assert_eq_m512i(r, a);
11220 let r = _mm512_mask_alignr_epi64::<1>(a, 0b11111111, a, b);
11221 let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11222 assert_eq_m512i(r, e);
11223 }
11224
11225 #[simd_test(enable = "avx512f")]
11226 const unsafe fn test_mm512_maskz_alignr_epi64() {
11227 let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11228 let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11229 let r = _mm512_maskz_alignr_epi64::<1>(0, a, b);
11230 assert_eq_m512i(r, _mm512_setzero_si512());
11231 let r = _mm512_maskz_alignr_epi64::<1>(0b00001111, a, b);
11232 let e = _mm512_set_epi64(0, 0, 0, 0, 13, 12, 11, 10);
11233 assert_eq_m512i(r, e);
11234 }
11235
11236 #[simd_test(enable = "avx512f,avx512vl")]
11237 const unsafe fn test_mm256_alignr_epi64() {
11238 let a = _mm256_set_epi64x(4, 3, 2, 1);
11239 let b = _mm256_set_epi64x(8, 7, 6, 5);
11240 let r = _mm256_alignr_epi64::<0>(a, b);
11241 let e = _mm256_set_epi64x(8, 7, 6, 5);
11242 assert_eq_m256i(r, e);
11243 let r = _mm256_alignr_epi64::<1>(a, b);
11244 let e = _mm256_set_epi64x(1, 8, 7, 6);
11245 assert_eq_m256i(r, e);
11246 let r = _mm256_alignr_epi64::<6>(a, b);
11247 let e = _mm256_set_epi64x(2, 1, 8, 7);
11248 assert_eq_m256i(r, e);
11249 }
11250
11251 #[simd_test(enable = "avx512f,avx512vl")]
11252 const unsafe fn test_mm256_mask_alignr_epi64() {
11253 let a = _mm256_set_epi64x(4, 3, 2, 1);
11254 let b = _mm256_set_epi64x(8, 7, 6, 5);
11255 let r = _mm256_mask_alignr_epi64::<1>(a, 0, a, b);
11256 assert_eq_m256i(r, a);
11257 let r = _mm256_mask_alignr_epi64::<0>(a, 0b00001111, a, b);
11258 let e = _mm256_set_epi64x(8, 7, 6, 5);
11259 assert_eq_m256i(r, e);
11260 }
11261
11262 #[simd_test(enable = "avx512f,avx512vl")]
11263 const unsafe fn test_mm256_maskz_alignr_epi64() {
11264 let a = _mm256_set_epi64x(4, 3, 2, 1);
11265 let b = _mm256_set_epi64x(8, 7, 6, 5);
11266 let r = _mm256_maskz_alignr_epi64::<1>(0, a, b);
11267 assert_eq_m256i(r, _mm256_setzero_si256());
11268 let r = _mm256_maskz_alignr_epi64::<0>(0b00001111, a, b);
11269 let e = _mm256_set_epi64x(8, 7, 6, 5);
11270 assert_eq_m256i(r, e);
11271 }
11272
11273 #[simd_test(enable = "avx512f,avx512vl")]
11274 const unsafe fn test_mm_alignr_epi64() {
11275 let a = _mm_set_epi64x(2, 1);
11276 let b = _mm_set_epi64x(4, 3);
11277 let r = _mm_alignr_epi64::<0>(a, b);
11278 let e = _mm_set_epi64x(4, 3);
11279 assert_eq_m128i(r, e);
11280 }
11281
11282 #[simd_test(enable = "avx512f,avx512vl")]
11283 const unsafe fn test_mm_mask_alignr_epi64() {
11284 let a = _mm_set_epi64x(2, 1);
11285 let b = _mm_set_epi64x(4, 3);
11286 let r = _mm_mask_alignr_epi64::<1>(a, 0, a, b);
11287 assert_eq_m128i(r, a);
11288 let r = _mm_mask_alignr_epi64::<0>(a, 0b00000011, a, b);
11289 let e = _mm_set_epi64x(4, 3);
11290 assert_eq_m128i(r, e);
11291 }
11292
11293 #[simd_test(enable = "avx512f,avx512vl")]
11294 const unsafe fn test_mm_maskz_alignr_epi64() {
11295 let a = _mm_set_epi64x(2, 1);
11296 let b = _mm_set_epi64x(4, 3);
11297 let r = _mm_maskz_alignr_epi64::<1>(0, a, b);
11298 assert_eq_m128i(r, _mm_setzero_si128());
11299 let r = _mm_maskz_alignr_epi64::<0>(0b00000011, a, b);
11300 let e = _mm_set_epi64x(4, 3);
11301 assert_eq_m128i(r, e);
11302 }
11303
11304 #[simd_test(enable = "avx512f")]
11305 const unsafe fn test_mm512_and_epi64() {
11306 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11307 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11308 let r = _mm512_and_epi64(a, b);
11309 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11310 assert_eq_m512i(r, e);
11311 }
11312
11313 #[simd_test(enable = "avx512f")]
11314 const unsafe fn test_mm512_mask_and_epi64() {
11315 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11316 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11317 let r = _mm512_mask_and_epi64(a, 0, a, b);
11318 assert_eq_m512i(r, a);
11319 let r = _mm512_mask_and_epi64(a, 0b01111111, a, b);
11320 let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11321 assert_eq_m512i(r, e);
11322 }
11323
11324 #[simd_test(enable = "avx512f")]
11325 const unsafe fn test_mm512_maskz_and_epi64() {
11326 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11327 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11328 let r = _mm512_maskz_and_epi64(0, a, b);
11329 assert_eq_m512i(r, _mm512_setzero_si512());
11330 let r = _mm512_maskz_and_epi64(0b00001111, a, b);
11331 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11332 assert_eq_m512i(r, e);
11333 }
11334
11335 #[simd_test(enable = "avx512f,avx512vl")]
11336 const unsafe fn test_mm256_mask_and_epi64() {
11337 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11338 let b = _mm256_set1_epi64x(1 << 0);
11339 let r = _mm256_mask_and_epi64(a, 0, a, b);
11340 assert_eq_m256i(r, a);
11341 let r = _mm256_mask_and_epi64(a, 0b00001111, a, b);
11342 let e = _mm256_set1_epi64x(1 << 0);
11343 assert_eq_m256i(r, e);
11344 }
11345
11346 #[simd_test(enable = "avx512f,avx512vl")]
11347 const unsafe fn test_mm256_maskz_and_epi64() {
11348 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11349 let b = _mm256_set1_epi64x(1 << 0);
11350 let r = _mm256_maskz_and_epi64(0, a, b);
11351 assert_eq_m256i(r, _mm256_setzero_si256());
11352 let r = _mm256_maskz_and_epi64(0b00001111, a, b);
11353 let e = _mm256_set1_epi64x(1 << 0);
11354 assert_eq_m256i(r, e);
11355 }
11356
11357 #[simd_test(enable = "avx512f,avx512vl")]
11358 const unsafe fn test_mm_mask_and_epi64() {
11359 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11360 let b = _mm_set1_epi64x(1 << 0);
11361 let r = _mm_mask_and_epi64(a, 0, a, b);
11362 assert_eq_m128i(r, a);
11363 let r = _mm_mask_and_epi64(a, 0b00000011, a, b);
11364 let e = _mm_set1_epi64x(1 << 0);
11365 assert_eq_m128i(r, e);
11366 }
11367
11368 #[simd_test(enable = "avx512f,avx512vl")]
11369 const unsafe fn test_mm_maskz_and_epi64() {
11370 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11371 let b = _mm_set1_epi64x(1 << 0);
11372 let r = _mm_maskz_and_epi64(0, a, b);
11373 assert_eq_m128i(r, _mm_setzero_si128());
11374 let r = _mm_maskz_and_epi64(0b00000011, a, b);
11375 let e = _mm_set1_epi64x(1 << 0);
11376 assert_eq_m128i(r, e);
11377 }
11378
11379 #[simd_test(enable = "avx512f")]
11380 const unsafe fn test_mm512_and_si512() {
11381 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11382 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11383 let r = _mm512_and_epi64(a, b);
11384 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11385 assert_eq_m512i(r, e);
11386 }
11387
11388 #[simd_test(enable = "avx512f")]
11389 const unsafe fn test_mm512_or_epi64() {
11390 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11391 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11392 let r = _mm512_or_epi64(a, b);
11393 #[rustfmt::skip]
11394 let e = _mm512_set_epi64(
11395 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11396 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11397 );
11398 assert_eq_m512i(r, e);
11399 }
11400
11401 #[simd_test(enable = "avx512f")]
11402 const unsafe fn test_mm512_mask_or_epi64() {
11403 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11404 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11405 let r = _mm512_mask_or_epi64(a, 0, a, b);
11406 assert_eq_m512i(r, a);
11407 let r = _mm512_mask_or_epi64(a, 0b11111111, a, b);
11408 #[rustfmt::skip]
11409 let e = _mm512_set_epi64(
11410 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11411 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11412 );
11413 assert_eq_m512i(r, e);
11414 }
11415
11416 #[simd_test(enable = "avx512f")]
11417 const unsafe fn test_mm512_maskz_or_epi64() {
11418 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11419 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11420 let r = _mm512_maskz_or_epi64(0, a, b);
11421 assert_eq_m512i(r, _mm512_setzero_si512());
11422 let r = _mm512_maskz_or_epi64(0b00001111, a, b);
11423 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11424 assert_eq_m512i(r, e);
11425 }
11426
11427 #[simd_test(enable = "avx512f,avx512vl")]
11428 const unsafe fn test_mm256_or_epi64() {
11429 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11430 let b = _mm256_set1_epi64x(1 << 13);
11431 let r = _mm256_or_epi64(a, b);
11432 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11433 assert_eq_m256i(r, e);
11434 }
11435
11436 #[simd_test(enable = "avx512f,avx512vl")]
11437 const unsafe fn test_mm256_mask_or_epi64() {
11438 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11439 let b = _mm256_set1_epi64x(1 << 13);
11440 let r = _mm256_mask_or_epi64(a, 0, a, b);
11441 assert_eq_m256i(r, a);
11442 let r = _mm256_mask_or_epi64(a, 0b00001111, a, b);
11443 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11444 assert_eq_m256i(r, e);
11445 }
11446
11447 #[simd_test(enable = "avx512f,avx512vl")]
11448 const unsafe fn test_mm256_maskz_or_epi64() {
11449 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11450 let b = _mm256_set1_epi64x(1 << 13);
11451 let r = _mm256_maskz_or_epi64(0, a, b);
11452 assert_eq_m256i(r, _mm256_setzero_si256());
11453 let r = _mm256_maskz_or_epi64(0b00001111, a, b);
11454 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11455 assert_eq_m256i(r, e);
11456 }
11457
11458 #[simd_test(enable = "avx512f,avx512vl")]
11459 const unsafe fn test_mm_or_epi64() {
11460 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11461 let b = _mm_set1_epi64x(1 << 13);
11462 let r = _mm_or_epi64(a, b);
11463 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11464 assert_eq_m128i(r, e);
11465 }
11466
11467 #[simd_test(enable = "avx512f,avx512vl")]
11468 const unsafe fn test_mm_mask_or_epi64() {
11469 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11470 let b = _mm_set1_epi64x(1 << 13);
11471 let r = _mm_mask_or_epi64(a, 0, a, b);
11472 assert_eq_m128i(r, a);
11473 let r = _mm_mask_or_epi64(a, 0b00000011, a, b);
11474 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11475 assert_eq_m128i(r, e);
11476 }
11477
11478 #[simd_test(enable = "avx512f,avx512vl")]
11479 const unsafe fn test_mm_maskz_or_epi64() {
11480 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11481 let b = _mm_set1_epi64x(1 << 13);
11482 let r = _mm_maskz_or_epi64(0, a, b);
11483 assert_eq_m128i(r, _mm_setzero_si128());
11484 let r = _mm_maskz_or_epi64(0b00000011, a, b);
11485 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11486 assert_eq_m128i(r, e);
11487 }
11488
11489 #[simd_test(enable = "avx512f")]
11490 const unsafe fn test_mm512_or_si512() {
11491 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11492 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11493 let r = _mm512_or_epi64(a, b);
11494 #[rustfmt::skip]
11495 let e = _mm512_set_epi64(
11496 1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11497 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11498 );
11499 assert_eq_m512i(r, e);
11500 }
11501
11502 #[simd_test(enable = "avx512f")]
11503 const unsafe fn test_mm512_xor_epi64() {
11504 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11505 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11506 let r = _mm512_xor_epi64(a, b);
11507 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11508 assert_eq_m512i(r, e);
11509 }
11510
11511 #[simd_test(enable = "avx512f")]
11512 const unsafe fn test_mm512_mask_xor_epi64() {
11513 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11514 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11515 let r = _mm512_mask_xor_epi64(a, 0, a, b);
11516 assert_eq_m512i(r, a);
11517 let r = _mm512_mask_xor_epi64(a, 0b11111111, a, b);
11518 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11519 assert_eq_m512i(r, e);
11520 }
11521
11522 #[simd_test(enable = "avx512f")]
11523 const unsafe fn test_mm512_maskz_xor_epi64() {
11524 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11525 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11526 let r = _mm512_maskz_xor_epi64(0, a, b);
11527 assert_eq_m512i(r, _mm512_setzero_si512());
11528 let r = _mm512_maskz_xor_epi64(0b00001111, a, b);
11529 let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
11530 assert_eq_m512i(r, e);
11531 }
11532
11533 #[simd_test(enable = "avx512f,avx512vl")]
11534 const unsafe fn test_mm256_xor_epi64() {
11535 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11536 let b = _mm256_set1_epi64x(1 << 13);
11537 let r = _mm256_xor_epi64(a, b);
11538 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11539 assert_eq_m256i(r, e);
11540 }
11541
11542 #[simd_test(enable = "avx512f,avx512vl")]
11543 const unsafe fn test_mm256_mask_xor_epi64() {
11544 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11545 let b = _mm256_set1_epi64x(1 << 13);
11546 let r = _mm256_mask_xor_epi64(a, 0, a, b);
11547 assert_eq_m256i(r, a);
11548 let r = _mm256_mask_xor_epi64(a, 0b00001111, a, b);
11549 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11550 assert_eq_m256i(r, e);
11551 }
11552
11553 #[simd_test(enable = "avx512f,avx512vl")]
11554 const unsafe fn test_mm256_maskz_xor_epi64() {
11555 let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11556 let b = _mm256_set1_epi64x(1 << 13);
11557 let r = _mm256_maskz_xor_epi64(0, a, b);
11558 assert_eq_m256i(r, _mm256_setzero_si256());
11559 let r = _mm256_maskz_xor_epi64(0b00001111, a, b);
11560 let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11561 assert_eq_m256i(r, e);
11562 }
11563
11564 #[simd_test(enable = "avx512f,avx512vl")]
11565 const unsafe fn test_mm_xor_epi64() {
11566 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11567 let b = _mm_set1_epi64x(1 << 13);
11568 let r = _mm_xor_epi64(a, b);
11569 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11570 assert_eq_m128i(r, e);
11571 }
11572
11573 #[simd_test(enable = "avx512f,avx512vl")]
11574 const unsafe fn test_mm_mask_xor_epi64() {
11575 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11576 let b = _mm_set1_epi64x(1 << 13);
11577 let r = _mm_mask_xor_epi64(a, 0, a, b);
11578 assert_eq_m128i(r, a);
11579 let r = _mm_mask_xor_epi64(a, 0b00000011, a, b);
11580 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11581 assert_eq_m128i(r, e);
11582 }
11583
11584 #[simd_test(enable = "avx512f,avx512vl")]
11585 const unsafe fn test_mm_maskz_xor_epi64() {
11586 let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11587 let b = _mm_set1_epi64x(1 << 13);
11588 let r = _mm_maskz_xor_epi64(0, a, b);
11589 assert_eq_m128i(r, _mm_setzero_si128());
11590 let r = _mm_maskz_xor_epi64(0b00000011, a, b);
11591 let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11592 assert_eq_m128i(r, e);
11593 }
11594
11595 #[simd_test(enable = "avx512f")]
11596 const unsafe fn test_mm512_xor_si512() {
11597 let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11598 let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11599 let r = _mm512_xor_epi64(a, b);
11600 let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11601 assert_eq_m512i(r, e);
11602 }
11603
11604 #[simd_test(enable = "avx512f")]
11605 const unsafe fn test_mm512_andnot_epi64() {
11606 let a = _mm512_set1_epi64(0);
11607 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11608 let r = _mm512_andnot_epi64(a, b);
11609 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11610 assert_eq_m512i(r, e);
11611 }
11612
11613 #[simd_test(enable = "avx512f")]
11614 const unsafe fn test_mm512_mask_andnot_epi64() {
11615 let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11616 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11617 let r = _mm512_mask_andnot_epi64(a, 0, a, b);
11618 assert_eq_m512i(r, a);
11619 let r = _mm512_mask_andnot_epi64(a, 0b11111111, a, b);
11620 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11621 assert_eq_m512i(r, e);
11622 }
11623
11624 #[simd_test(enable = "avx512f")]
11625 const unsafe fn test_mm512_maskz_andnot_epi64() {
11626 let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11627 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11628 let r = _mm512_maskz_andnot_epi64(0, a, b);
11629 assert_eq_m512i(r, _mm512_setzero_si512());
11630 let r = _mm512_maskz_andnot_epi64(0b00001111, a, b);
11631 #[rustfmt::skip]
11632 let e = _mm512_set_epi64(
11633 0, 0, 0, 0,
11634 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4,
11635 );
11636 assert_eq_m512i(r, e);
11637 }
11638
11639 #[simd_test(enable = "avx512f,avx512vl")]
11640 const unsafe fn test_mm256_mask_andnot_epi64() {
11641 let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11642 let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11643 let r = _mm256_mask_andnot_epi64(a, 0, a, b);
11644 assert_eq_m256i(r, a);
11645 let r = _mm256_mask_andnot_epi64(a, 0b00001111, a, b);
11646 let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11647 assert_eq_m256i(r, e);
11648 }
11649
11650 #[simd_test(enable = "avx512f,avx512vl")]
11651 const unsafe fn test_mm256_maskz_andnot_epi64() {
11652 let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11653 let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11654 let r = _mm256_maskz_andnot_epi64(0, a, b);
11655 assert_eq_m256i(r, _mm256_setzero_si256());
11656 let r = _mm256_maskz_andnot_epi64(0b00001111, a, b);
11657 let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11658 assert_eq_m256i(r, e);
11659 }
11660
11661 #[simd_test(enable = "avx512f,avx512vl")]
11662 const unsafe fn test_mm_mask_andnot_epi64() {
11663 let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11664 let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11665 let r = _mm_mask_andnot_epi64(a, 0, a, b);
11666 assert_eq_m128i(r, a);
11667 let r = _mm_mask_andnot_epi64(a, 0b00000011, a, b);
11668 let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11669 assert_eq_m128i(r, e);
11670 }
11671
11672 #[simd_test(enable = "avx512f,avx512vl")]
11673 const unsafe fn test_mm_maskz_andnot_epi64() {
11674 let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11675 let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11676 let r = _mm_maskz_andnot_epi64(0, a, b);
11677 assert_eq_m128i(r, _mm_setzero_si128());
11678 let r = _mm_maskz_andnot_epi64(0b00000011, a, b);
11679 let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11680 assert_eq_m128i(r, e);
11681 }
11682
11683 #[simd_test(enable = "avx512f")]
11684 const unsafe fn test_mm512_andnot_si512() {
11685 let a = _mm512_set1_epi64(0);
11686 let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11687 let r = _mm512_andnot_si512(a, b);
11688 let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11689 assert_eq_m512i(r, e);
11690 }
11691
11692 #[simd_test(enable = "avx512f")]
11693 const unsafe fn test_mm512_reduce_add_epi64() {
11694 let a = _mm512_set1_epi64(1);
11695 let e: i64 = _mm512_reduce_add_epi64(a);
11696 assert_eq!(8, e);
11697 }
11698
11699 #[simd_test(enable = "avx512f")]
11700 const unsafe fn test_mm512_mask_reduce_add_epi64() {
11701 let a = _mm512_set1_epi64(1);
11702 let e: i64 = _mm512_mask_reduce_add_epi64(0b11110000, a);
11703 assert_eq!(4, e);
11704 }
11705
11706 #[simd_test(enable = "avx512f")]
11707 const unsafe fn test_mm512_reduce_add_pd() {
11708 let a = _mm512_set1_pd(1.);
11709 let e: f64 = _mm512_reduce_add_pd(a);
11710 assert_eq!(8., e);
11711 }
11712
11713 #[simd_test(enable = "avx512f")]
11714 const unsafe fn test_mm512_mask_reduce_add_pd() {
11715 let a = _mm512_set1_pd(1.);
11716 let e: f64 = _mm512_mask_reduce_add_pd(0b11110000, a);
11717 assert_eq!(4., e);
11718 }
11719
11720 #[simd_test(enable = "avx512f")]
11721 const unsafe fn test_mm512_reduce_mul_epi64() {
11722 let a = _mm512_set1_epi64(2);
11723 let e: i64 = _mm512_reduce_mul_epi64(a);
11724 assert_eq!(256, e);
11725 }
11726
11727 #[simd_test(enable = "avx512f")]
11728 const unsafe fn test_mm512_mask_reduce_mul_epi64() {
11729 let a = _mm512_set1_epi64(2);
11730 let e: i64 = _mm512_mask_reduce_mul_epi64(0b11110000, a);
11731 assert_eq!(16, e);
11732 }
11733
11734 #[simd_test(enable = "avx512f")]
11735 const unsafe fn test_mm512_reduce_mul_pd() {
11736 let a = _mm512_set1_pd(2.);
11737 let e: f64 = _mm512_reduce_mul_pd(a);
11738 assert_eq!(256., e);
11739 }
11740
11741 #[simd_test(enable = "avx512f")]
11742 const unsafe fn test_mm512_mask_reduce_mul_pd() {
11743 let a = _mm512_set1_pd(2.);
11744 let e: f64 = _mm512_mask_reduce_mul_pd(0b11110000, a);
11745 assert_eq!(16., e);
11746 }
11747
11748 #[simd_test(enable = "avx512f")]
11749 const unsafe fn test_mm512_reduce_max_epi64() {
11750 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11751 let e: i64 = _mm512_reduce_max_epi64(a);
11752 assert_eq!(7, e);
11753 }
11754
11755 #[simd_test(enable = "avx512f")]
11756 const unsafe fn test_mm512_mask_reduce_max_epi64() {
11757 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11758 let e: i64 = _mm512_mask_reduce_max_epi64(0b11110000, a);
11759 assert_eq!(3, e);
11760 }
11761
11762 #[simd_test(enable = "avx512f")]
11763 const unsafe fn test_mm512_reduce_max_epu64() {
11764 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11765 let e: u64 = _mm512_reduce_max_epu64(a);
11766 assert_eq!(7, e);
11767 }
11768
11769 #[simd_test(enable = "avx512f")]
11770 const unsafe fn test_mm512_mask_reduce_max_epu64() {
11771 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11772 let e: u64 = _mm512_mask_reduce_max_epu64(0b11110000, a);
11773 assert_eq!(3, e);
11774 }
11775
11776 #[simd_test(enable = "avx512f")]
11777 unsafe fn test_mm512_reduce_max_pd() {
11778 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11779 let e: f64 = _mm512_reduce_max_pd(a);
11780 assert_eq!(7., e);
11781 }
11782
11783 #[simd_test(enable = "avx512f")]
11784 unsafe fn test_mm512_mask_reduce_max_pd() {
11785 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11786 let e: f64 = _mm512_mask_reduce_max_pd(0b11110000, a);
11787 assert_eq!(3., e);
11788 }
11789
11790 #[simd_test(enable = "avx512f")]
11791 const unsafe fn test_mm512_reduce_min_epi64() {
11792 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11793 let e: i64 = _mm512_reduce_min_epi64(a);
11794 assert_eq!(0, e);
11795 }
11796
11797 #[simd_test(enable = "avx512f")]
11798 const unsafe fn test_mm512_mask_reduce_min_epi64() {
11799 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11800 let e: i64 = _mm512_mask_reduce_min_epi64(0b11110000, a);
11801 assert_eq!(0, e);
11802 }
11803
11804 #[simd_test(enable = "avx512f")]
11805 const unsafe fn test_mm512_reduce_min_epu64() {
11806 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11807 let e: u64 = _mm512_reduce_min_epu64(a);
11808 assert_eq!(0, e);
11809 }
11810
11811 #[simd_test(enable = "avx512f")]
11812 const unsafe fn test_mm512_mask_reduce_min_epu64() {
11813 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11814 let e: u64 = _mm512_mask_reduce_min_epu64(0b11110000, a);
11815 assert_eq!(0, e);
11816 }
11817
11818 #[simd_test(enable = "avx512f")]
11819 unsafe fn test_mm512_reduce_min_pd() {
11820 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11821 let e: f64 = _mm512_reduce_min_pd(a);
11822 assert_eq!(0., e);
11823 }
11824
11825 #[simd_test(enable = "avx512f")]
11826 unsafe fn test_mm512_mask_reduce_min_pd() {
11827 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11828 let e: f64 = _mm512_mask_reduce_min_pd(0b11110000, a);
11829 assert_eq!(0., e);
11830 }
11831
11832 #[simd_test(enable = "avx512f")]
11833 const unsafe fn test_mm512_reduce_and_epi64() {
11834 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11835 let e: i64 = _mm512_reduce_and_epi64(a);
11836 assert_eq!(0, e);
11837 }
11838
11839 #[simd_test(enable = "avx512f")]
11840 const unsafe fn test_mm512_mask_reduce_and_epi64() {
11841 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11842 let e: i64 = _mm512_mask_reduce_and_epi64(0b11110000, a);
11843 assert_eq!(1, e);
11844 }
11845
11846 #[simd_test(enable = "avx512f")]
11847 const unsafe fn test_mm512_reduce_or_epi64() {
11848 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11849 let e: i64 = _mm512_reduce_or_epi64(a);
11850 assert_eq!(3, e);
11851 }
11852
11853 #[simd_test(enable = "avx512f")]
11854 const unsafe fn test_mm512_mask_reduce_or_epi64() {
11855 let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11856 let e: i64 = _mm512_mask_reduce_or_epi64(0b11110000, a);
11857 assert_eq!(1, e);
11858 }
11859
11860 #[simd_test(enable = "avx512f")]
11861 const unsafe fn test_mm512_extractf64x4_pd() {
11862 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11863 let r = _mm512_extractf64x4_pd::<1>(a);
11864 let e = _mm256_setr_pd(5., 6., 7., 8.);
11865 assert_eq_m256d(r, e);
11866 }
11867
11868 #[simd_test(enable = "avx512f")]
11869 const unsafe fn test_mm512_mask_extractf64x4_pd() {
11870 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11871 let src = _mm256_set1_pd(100.);
11872 let r = _mm512_mask_extractf64x4_pd::<1>(src, 0, a);
11873 assert_eq_m256d(r, src);
11874 let r = _mm512_mask_extractf64x4_pd::<1>(src, 0b11111111, a);
11875 let e = _mm256_setr_pd(5., 6., 7., 8.);
11876 assert_eq_m256d(r, e);
11877 }
11878
11879 #[simd_test(enable = "avx512f")]
11880 const unsafe fn test_mm512_maskz_extractf64x4_pd() {
11881 let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11882 let r = _mm512_maskz_extractf64x4_pd::<1>(0, a);
11883 assert_eq_m256d(r, _mm256_setzero_pd());
11884 let r = _mm512_maskz_extractf64x4_pd::<1>(0b00000001, a);
11885 let e = _mm256_setr_pd(5., 0., 0., 0.);
11886 assert_eq_m256d(r, e);
11887 }
11888
11889 #[simd_test(enable = "avx512f")]
11890 const unsafe fn test_mm512_extracti64x4_epi64() {
11891 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11892 let r = _mm512_extracti64x4_epi64::<0x1>(a);
11893 let e = _mm256_setr_epi64x(5, 6, 7, 8);
11894 assert_eq_m256i(r, e);
11895 }
11896
11897 #[simd_test(enable = "avx512f")]
11898 const unsafe fn test_mm512_mask_extracti64x4_epi64() {
11899 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11900 let src = _mm256_set1_epi64x(100);
11901 let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0, a);
11902 assert_eq_m256i(r, src);
11903 let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0b11111111, a);
11904 let e = _mm256_setr_epi64x(5, 6, 7, 8);
11905 assert_eq_m256i(r, e);
11906 }
11907
11908 #[simd_test(enable = "avx512f")]
11909 const unsafe fn test_mm512_maskz_extracti64x4_epi64() {
11910 let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11911 let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0, a);
11912 assert_eq_m256i(r, _mm256_setzero_si256());
11913 let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0b00000001, a);
11914 let e = _mm256_setr_epi64x(5, 0, 0, 0);
11915 assert_eq_m256i(r, e);
11916 }
11917
11918 #[simd_test(enable = "avx512f")]
11919 unsafe fn test_mm512_mask_compress_epi64() {
11920 let src = _mm512_set1_epi64(200);
11921 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11922 let r = _mm512_mask_compress_epi64(src, 0, a);
11923 assert_eq_m512i(r, src);
11924 let r = _mm512_mask_compress_epi64(src, 0b01010101, a);
11925 let e = _mm512_set_epi64(200, 200, 200, 200, 1, 3, 5, 7);
11926 assert_eq_m512i(r, e);
11927 }
11928
11929 #[simd_test(enable = "avx512f")]
11930 unsafe fn test_mm512_maskz_compress_epi64() {
11931 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11932 let r = _mm512_maskz_compress_epi64(0, a);
11933 assert_eq_m512i(r, _mm512_setzero_si512());
11934 let r = _mm512_maskz_compress_epi64(0b01010101, a);
11935 let e = _mm512_set_epi64(0, 0, 0, 0, 1, 3, 5, 7);
11936 assert_eq_m512i(r, e);
11937 }
11938
11939 #[simd_test(enable = "avx512f,avx512vl")]
11940 unsafe fn test_mm256_mask_compress_epi64() {
11941 let src = _mm256_set1_epi64x(200);
11942 let a = _mm256_set_epi64x(0, 1, 2, 3);
11943 let r = _mm256_mask_compress_epi64(src, 0, a);
11944 assert_eq_m256i(r, src);
11945 let r = _mm256_mask_compress_epi64(src, 0b00000101, a);
11946 let e = _mm256_set_epi64x(200, 200, 1, 3);
11947 assert_eq_m256i(r, e);
11948 }
11949
11950 #[simd_test(enable = "avx512f,avx512vl")]
11951 unsafe fn test_mm256_maskz_compress_epi64() {
11952 let a = _mm256_set_epi64x(0, 1, 2, 3);
11953 let r = _mm256_maskz_compress_epi64(0, a);
11954 assert_eq_m256i(r, _mm256_setzero_si256());
11955 let r = _mm256_maskz_compress_epi64(0b00000101, a);
11956 let e = _mm256_set_epi64x(0, 0, 1, 3);
11957 assert_eq_m256i(r, e);
11958 }
11959
11960 #[simd_test(enable = "avx512f,avx512vl")]
11961 unsafe fn test_mm_mask_compress_epi64() {
11962 let src = _mm_set1_epi64x(200);
11963 let a = _mm_set_epi64x(0, 1);
11964 let r = _mm_mask_compress_epi64(src, 0, a);
11965 assert_eq_m128i(r, src);
11966 let r = _mm_mask_compress_epi64(src, 0b00000001, a);
11967 let e = _mm_set_epi64x(200, 1);
11968 assert_eq_m128i(r, e);
11969 }
11970
11971 #[simd_test(enable = "avx512f,avx512vl")]
11972 unsafe fn test_mm_maskz_compress_epi64() {
11973 let a = _mm_set_epi64x(0, 1);
11974 let r = _mm_maskz_compress_epi64(0, a);
11975 assert_eq_m128i(r, _mm_setzero_si128());
11976 let r = _mm_maskz_compress_epi64(0b00000001, a);
11977 let e = _mm_set_epi64x(0, 1);
11978 assert_eq_m128i(r, e);
11979 }
11980
11981 #[simd_test(enable = "avx512f")]
11982 unsafe fn test_mm512_mask_compress_pd() {
11983 let src = _mm512_set1_pd(200.);
11984 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11985 let r = _mm512_mask_compress_pd(src, 0, a);
11986 assert_eq_m512d(r, src);
11987 let r = _mm512_mask_compress_pd(src, 0b01010101, a);
11988 let e = _mm512_set_pd(200., 200., 200., 200., 1., 3., 5., 7.);
11989 assert_eq_m512d(r, e);
11990 }
11991
11992 #[simd_test(enable = "avx512f")]
11993 unsafe fn test_mm512_maskz_compress_pd() {
11994 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11995 let r = _mm512_maskz_compress_pd(0, a);
11996 assert_eq_m512d(r, _mm512_setzero_pd());
11997 let r = _mm512_maskz_compress_pd(0b01010101, a);
11998 let e = _mm512_set_pd(0., 0., 0., 0., 1., 3., 5., 7.);
11999 assert_eq_m512d(r, e);
12000 }
12001
12002 #[simd_test(enable = "avx512f,avx512vl")]
12003 unsafe fn test_mm256_mask_compress_pd() {
12004 let src = _mm256_set1_pd(200.);
12005 let a = _mm256_set_pd(0., 1., 2., 3.);
12006 let r = _mm256_mask_compress_pd(src, 0, a);
12007 assert_eq_m256d(r, src);
12008 let r = _mm256_mask_compress_pd(src, 0b00000101, a);
12009 let e = _mm256_set_pd(200., 200., 1., 3.);
12010 assert_eq_m256d(r, e);
12011 }
12012
12013 #[simd_test(enable = "avx512f,avx512vl")]
12014 unsafe fn test_mm256_maskz_compress_pd() {
12015 let a = _mm256_set_pd(0., 1., 2., 3.);
12016 let r = _mm256_maskz_compress_pd(0, a);
12017 assert_eq_m256d(r, _mm256_setzero_pd());
12018 let r = _mm256_maskz_compress_pd(0b00000101, a);
12019 let e = _mm256_set_pd(0., 0., 1., 3.);
12020 assert_eq_m256d(r, e);
12021 }
12022
12023 #[simd_test(enable = "avx512f,avx512vl")]
12024 unsafe fn test_mm_mask_compress_pd() {
12025 let src = _mm_set1_pd(200.);
12026 let a = _mm_set_pd(0., 1.);
12027 let r = _mm_mask_compress_pd(src, 0, a);
12028 assert_eq_m128d(r, src);
12029 let r = _mm_mask_compress_pd(src, 0b00000001, a);
12030 let e = _mm_set_pd(200., 1.);
12031 assert_eq_m128d(r, e);
12032 }
12033
12034 #[simd_test(enable = "avx512f,avx512vl")]
12035 unsafe fn test_mm_maskz_compress_pd() {
12036 let a = _mm_set_pd(0., 1.);
12037 let r = _mm_maskz_compress_pd(0, a);
12038 assert_eq_m128d(r, _mm_setzero_pd());
12039 let r = _mm_maskz_compress_pd(0b00000001, a);
12040 let e = _mm_set_pd(0., 1.);
12041 assert_eq_m128d(r, e);
12042 }
12043
12044 #[simd_test(enable = "avx512f")]
12045 unsafe fn test_mm512_mask_expand_epi64() {
12046 let src = _mm512_set1_epi64(200);
12047 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12048 let r = _mm512_mask_expand_epi64(src, 0, a);
12049 assert_eq_m512i(r, src);
12050 let r = _mm512_mask_expand_epi64(src, 0b01010101, a);
12051 let e = _mm512_set_epi64(200, 4, 200, 5, 200, 6, 200, 7);
12052 assert_eq_m512i(r, e);
12053 }
12054
12055 #[simd_test(enable = "avx512f")]
12056 unsafe fn test_mm512_maskz_expand_epi64() {
12057 let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12058 let r = _mm512_maskz_expand_epi64(0, a);
12059 assert_eq_m512i(r, _mm512_setzero_si512());
12060 let r = _mm512_maskz_expand_epi64(0b01010101, a);
12061 let e = _mm512_set_epi64(0, 4, 0, 5, 0, 6, 0, 7);
12062 assert_eq_m512i(r, e);
12063 }
12064
12065 #[simd_test(enable = "avx512f,avx512vl")]
12066 unsafe fn test_mm256_mask_expand_epi64() {
12067 let src = _mm256_set1_epi64x(200);
12068 let a = _mm256_set_epi64x(0, 1, 2, 3);
12069 let r = _mm256_mask_expand_epi64(src, 0, a);
12070 assert_eq_m256i(r, src);
12071 let r = _mm256_mask_expand_epi64(src, 0b00000101, a);
12072 let e = _mm256_set_epi64x(200, 2, 200, 3);
12073 assert_eq_m256i(r, e);
12074 }
12075
12076 #[simd_test(enable = "avx512f,avx512vl")]
12077 unsafe fn test_mm256_maskz_expand_epi64() {
12078 let a = _mm256_set_epi64x(0, 1, 2, 3);
12079 let r = _mm256_maskz_expand_epi64(0, a);
12080 assert_eq_m256i(r, _mm256_setzero_si256());
12081 let r = _mm256_maskz_expand_epi64(0b00000101, a);
12082 let e = _mm256_set_epi64x(0, 2, 0, 3);
12083 assert_eq_m256i(r, e);
12084 }
12085
12086 #[simd_test(enable = "avx512f,avx512vl")]
12087 unsafe fn test_mm_mask_expand_epi64() {
12088 let src = _mm_set1_epi64x(200);
12089 let a = _mm_set_epi64x(0, 1);
12090 let r = _mm_mask_expand_epi64(src, 0, a);
12091 assert_eq_m128i(r, src);
12092 let r = _mm_mask_expand_epi64(src, 0b00000001, a);
12093 let e = _mm_set_epi64x(200, 1);
12094 assert_eq_m128i(r, e);
12095 }
12096
12097 #[simd_test(enable = "avx512f,avx512vl")]
12098 unsafe fn test_mm_maskz_expand_epi64() {
12099 let a = _mm_set_epi64x(0, 1);
12100 let r = _mm_maskz_expand_epi64(0, a);
12101 assert_eq_m128i(r, _mm_setzero_si128());
12102 let r = _mm_maskz_expand_epi64(0b00000001, a);
12103 let e = _mm_set_epi64x(0, 1);
12104 assert_eq_m128i(r, e);
12105 }
12106
12107 #[simd_test(enable = "avx512f")]
12108 unsafe fn test_mm512_mask_expand_pd() {
12109 let src = _mm512_set1_pd(200.);
12110 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12111 let r = _mm512_mask_expand_pd(src, 0, a);
12112 assert_eq_m512d(r, src);
12113 let r = _mm512_mask_expand_pd(src, 0b01010101, a);
12114 let e = _mm512_set_pd(200., 4., 200., 5., 200., 6., 200., 7.);
12115 assert_eq_m512d(r, e);
12116 }
12117
12118 #[simd_test(enable = "avx512f")]
12119 unsafe fn test_mm512_maskz_expand_pd() {
12120 let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12121 let r = _mm512_maskz_expand_pd(0, a);
12122 assert_eq_m512d(r, _mm512_setzero_pd());
12123 let r = _mm512_maskz_expand_pd(0b01010101, a);
12124 let e = _mm512_set_pd(0., 4., 0., 5., 0., 6., 0., 7.);
12125 assert_eq_m512d(r, e);
12126 }
12127
12128 #[simd_test(enable = "avx512f,avx512vl")]
12129 unsafe fn test_mm256_mask_expand_pd() {
12130 let src = _mm256_set1_pd(200.);
12131 let a = _mm256_set_pd(0., 1., 2., 3.);
12132 let r = _mm256_mask_expand_pd(src, 0, a);
12133 assert_eq_m256d(r, src);
12134 let r = _mm256_mask_expand_pd(src, 0b00000101, a);
12135 let e = _mm256_set_pd(200., 2., 200., 3.);
12136 assert_eq_m256d(r, e);
12137 }
12138
12139 #[simd_test(enable = "avx512f,avx512vl")]
12140 unsafe fn test_mm256_maskz_expand_pd() {
12141 let a = _mm256_set_pd(0., 1., 2., 3.);
12142 let r = _mm256_maskz_expand_pd(0, a);
12143 assert_eq_m256d(r, _mm256_setzero_pd());
12144 let r = _mm256_maskz_expand_pd(0b00000101, a);
12145 let e = _mm256_set_pd(0., 2., 0., 3.);
12146 assert_eq_m256d(r, e);
12147 }
12148
12149 #[simd_test(enable = "avx512f,avx512vl")]
12150 unsafe fn test_mm_mask_expand_pd() {
12151 let src = _mm_set1_pd(200.);
12152 let a = _mm_set_pd(0., 1.);
12153 let r = _mm_mask_expand_pd(src, 0, a);
12154 assert_eq_m128d(r, src);
12155 let r = _mm_mask_expand_pd(src, 0b00000001, a);
12156 let e = _mm_set_pd(200., 1.);
12157 assert_eq_m128d(r, e);
12158 }
12159
12160 #[simd_test(enable = "avx512f,avx512vl")]
12161 unsafe fn test_mm_maskz_expand_pd() {
12162 let a = _mm_set_pd(0., 1.);
12163 let r = _mm_maskz_expand_pd(0, a);
12164 assert_eq_m128d(r, _mm_setzero_pd());
12165 let r = _mm_maskz_expand_pd(0b00000001, a);
12166 let e = _mm_set_pd(0., 1.);
12167 assert_eq_m128d(r, e);
12168 }
12169
12170 #[simd_test(enable = "avx512f")]
12171 const unsafe fn test_mm512_loadu_epi64() {
12172 let a = &[4, 3, 2, 5, -8, -9, -64, -50];
12173 let p = a.as_ptr();
12174 let r = _mm512_loadu_epi64(black_box(p));
12175 let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12176 assert_eq_m512i(r, e);
12177 }
12178
12179 #[simd_test(enable = "avx512f,avx512vl")]
12180 const unsafe fn test_mm256_loadu_epi64() {
12181 let a = &[4, 3, 2, 5];
12182 let p = a.as_ptr();
12183 let r = _mm256_loadu_epi64(black_box(p));
12184 let e = _mm256_setr_epi64x(4, 3, 2, 5);
12185 assert_eq_m256i(r, e);
12186 }
12187
12188 #[simd_test(enable = "avx512f,avx512vl")]
12189 const unsafe fn test_mm_loadu_epi64() {
12190 let a = &[4, 3];
12191 let p = a.as_ptr();
12192 let r = _mm_loadu_epi64(black_box(p));
12193 let e = _mm_setr_epi64x(4, 3);
12194 assert_eq_m128i(r, e);
12195 }
12196
12197 #[simd_test(enable = "avx512f")]
12198 unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() {
12199 let a = _mm512_set1_epi64(9);
12200 let mut r = _mm_undefined_si128();
12201 _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12202 let e = _mm_set1_epi16(9);
12203 assert_eq_m128i(r, e);
12204 }
12205
12206 #[simd_test(enable = "avx512f,avx512vl")]
12207 unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() {
12208 let a = _mm256_set1_epi64x(9);
12209 let mut r = _mm_set1_epi16(0);
12210 _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12211 let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
12212 assert_eq_m128i(r, e);
12213 }
12214
12215 #[simd_test(enable = "avx512f,avx512vl")]
12216 unsafe fn test_mm_mask_cvtepi64_storeu_epi16() {
12217 let a = _mm_set1_epi64x(9);
12218 let mut r = _mm_set1_epi16(0);
12219 _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12220 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9);
12221 assert_eq_m128i(r, e);
12222 }
12223
12224 #[simd_test(enable = "avx512f")]
12225 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi16() {
12226 let a = _mm512_set1_epi64(i64::MAX);
12227 let mut r = _mm_undefined_si128();
12228 _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12229 let e = _mm_set1_epi16(i16::MAX);
12230 assert_eq_m128i(r, e);
12231 }
12232
12233 #[simd_test(enable = "avx512f,avx512vl")]
12234 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi16() {
12235 let a = _mm256_set1_epi64x(i64::MAX);
12236 let mut r = _mm_set1_epi16(0);
12237 _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12238 let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
12239 assert_eq_m128i(r, e);
12240 }
12241
12242 #[simd_test(enable = "avx512f,avx512vl")]
12243 unsafe fn test_mm_mask_cvtsepi64_storeu_epi16() {
12244 let a = _mm_set1_epi64x(i64::MAX);
12245 let mut r = _mm_set1_epi16(0);
12246 _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12247 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX);
12248 assert_eq_m128i(r, e);
12249 }
12250
12251 #[simd_test(enable = "avx512f")]
12252 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi16() {
12253 let a = _mm512_set1_epi64(i64::MAX);
12254 let mut r = _mm_undefined_si128();
12255 _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12256 let e = _mm_set1_epi16(u16::MAX as i16);
12257 assert_eq_m128i(r, e);
12258 }
12259
12260 #[simd_test(enable = "avx512f,avx512vl")]
12261 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi16() {
12262 let a = _mm256_set1_epi64x(i64::MAX);
12263 let mut r = _mm_set1_epi16(0);
12264 _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12265 let e = _mm_set_epi16(
12266 0,
12267 0,
12268 0,
12269 0,
12270 u16::MAX as i16,
12271 u16::MAX as i16,
12272 u16::MAX as i16,
12273 u16::MAX as i16,
12274 );
12275 assert_eq_m128i(r, e);
12276 }
12277
12278 #[simd_test(enable = "avx512f,avx512vl")]
12279 unsafe fn test_mm_mask_cvtusepi64_storeu_epi16() {
12280 let a = _mm_set1_epi64x(i64::MAX);
12281 let mut r = _mm_set1_epi16(0);
12282 _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12283 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16);
12284 assert_eq_m128i(r, e);
12285 }
12286
12287 #[simd_test(enable = "avx512f")]
12288 unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() {
12289 let a = _mm512_set1_epi64(9);
12290 let mut r = _mm_set1_epi8(0);
12291 _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12292 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
12293 assert_eq_m128i(r, e);
12294 }
12295
12296 #[simd_test(enable = "avx512f,avx512vl")]
12297 unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() {
12298 let a = _mm256_set1_epi64x(9);
12299 let mut r = _mm_set1_epi8(0);
12300 _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12301 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
12302 assert_eq_m128i(r, e);
12303 }
12304
12305 #[simd_test(enable = "avx512f,avx512vl")]
12306 unsafe fn test_mm_mask_cvtepi64_storeu_epi8() {
12307 let a = _mm_set1_epi64x(9);
12308 let mut r = _mm_set1_epi8(0);
12309 _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12310 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9);
12311 assert_eq_m128i(r, e);
12312 }
12313
12314 #[simd_test(enable = "avx512f")]
12315 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi8() {
12316 let a = _mm512_set1_epi64(i64::MAX);
12317 let mut r = _mm_set1_epi8(0);
12318 _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12319 #[rustfmt::skip]
12320 let e = _mm_set_epi8(
12321 0, 0, 0, 0,
12322 0, 0, 0, 0,
12323 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12324 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12325 );
12326 assert_eq_m128i(r, e);
12327 }
12328
12329 #[simd_test(enable = "avx512f,avx512vl")]
12330 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi8() {
12331 let a = _mm256_set1_epi64x(i64::MAX);
12332 let mut r = _mm_set1_epi8(0);
12333 _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12334 #[rustfmt::skip]
12335 let e = _mm_set_epi8(
12336 0, 0, 0, 0,
12337 0, 0, 0, 0,
12338 0, 0, 0, 0,
12339 i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12340 );
12341 assert_eq_m128i(r, e);
12342 }
12343
12344 #[simd_test(enable = "avx512f,avx512vl")]
12345 unsafe fn test_mm_mask_cvtsepi64_storeu_epi8() {
12346 let a = _mm_set1_epi64x(i64::MAX);
12347 let mut r = _mm_set1_epi8(0);
12348 _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12349 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX);
12350 assert_eq_m128i(r, e);
12351 }
12352
12353 #[simd_test(enable = "avx512f")]
12354 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi8() {
12355 let a = _mm512_set1_epi64(i64::MAX);
12356 let mut r = _mm_set1_epi8(0);
12357 _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12358 #[rustfmt::skip]
12359 let e = _mm_set_epi8(
12360 0, 0, 0, 0,
12361 0, 0, 0, 0,
12362 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12363 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12364 );
12365 assert_eq_m128i(r, e);
12366 }
12367
12368 #[simd_test(enable = "avx512f,avx512vl")]
12369 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi8() {
12370 let a = _mm256_set1_epi64x(i64::MAX);
12371 let mut r = _mm_set1_epi8(0);
12372 _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12373 #[rustfmt::skip]
12374 let e = _mm_set_epi8(
12375 0, 0, 0, 0,
12376 0, 0, 0, 0,
12377 0, 0, 0, 0,
12378 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12379 );
12380 assert_eq_m128i(r, e);
12381 }
12382
12383 #[simd_test(enable = "avx512f,avx512vl")]
12384 unsafe fn test_mm_mask_cvtusepi64_storeu_epi8() {
12385 let a = _mm_set1_epi64x(i64::MAX);
12386 let mut r = _mm_set1_epi8(0);
12387 _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12388 #[rustfmt::skip]
12389 let e = _mm_set_epi8(
12390 0, 0, 0, 0,
12391 0, 0, 0, 0,
12392 0, 0, 0, 0,
12393 0, 0, u8::MAX as i8, u8::MAX as i8,
12394 );
12395 assert_eq_m128i(r, e);
12396 }
12397
12398 #[simd_test(enable = "avx512f")]
12399 unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() {
12400 let a = _mm512_set1_epi64(9);
12401 let mut r = _mm256_undefined_si256();
12402 _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12403 let e = _mm256_set1_epi32(9);
12404 assert_eq_m256i(r, e);
12405 }
12406
12407 #[simd_test(enable = "avx512f,avx512vl")]
12408 unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() {
12409 let a = _mm256_set1_epi64x(9);
12410 let mut r = _mm_set1_epi32(0);
12411 _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12412 let e = _mm_set_epi32(9, 9, 9, 9);
12413 assert_eq_m128i(r, e);
12414 }
12415
12416 #[simd_test(enable = "avx512f,avx512vl")]
12417 unsafe fn test_mm_mask_cvtepi64_storeu_epi32() {
12418 let a = _mm_set1_epi64x(9);
12419 let mut r = _mm_set1_epi16(0);
12420 _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12421 let e = _mm_set_epi32(0, 0, 9, 9);
12422 assert_eq_m128i(r, e);
12423 }
12424
12425 #[simd_test(enable = "avx512f")]
12426 unsafe fn test_mm512_mask_cvtsepi64_storeu_epi32() {
12427 let a = _mm512_set1_epi64(i64::MAX);
12428 let mut r = _mm256_undefined_si256();
12429 _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12430 let e = _mm256_set1_epi32(i32::MAX);
12431 assert_eq_m256i(r, e);
12432 }
12433
12434 #[simd_test(enable = "avx512f,avx512vl")]
12435 unsafe fn test_mm256_mask_cvtsepi64_storeu_epi32() {
12436 let a = _mm256_set1_epi64x(i64::MAX);
12437 let mut r = _mm_set1_epi32(0);
12438 _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
12439 let e = _mm_set1_epi32(i32::MAX);
12440 assert_eq_m128i(r, e);
12441 }
12442
12443 #[simd_test(enable = "avx512f,avx512vl")]
12444 unsafe fn test_mm_mask_cvtsepi64_storeu_epi32() {
12445 let a = _mm_set1_epi64x(i64::MAX);
12446 let mut r = _mm_set1_epi16(0);
12447 _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
12448 let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX);
12449 assert_eq_m128i(r, e);
12450 }
12451
12452 #[simd_test(enable = "avx512f")]
12453 unsafe fn test_mm512_mask_cvtusepi64_storeu_epi32() {
12454 let a = _mm512_set1_epi64(i64::MAX);
12455 let mut r = _mm256_undefined_si256();
12456 _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12457 let e = _mm256_set1_epi32(u32::MAX as i32);
12458 assert_eq_m256i(r, e);
12459 }
12460
12461 #[simd_test(enable = "avx512f,avx512vl")]
12462 unsafe fn test_mm256_mask_cvtusepi64_storeu_epi32() {
12463 let a = _mm256_set1_epi64x(i64::MAX);
12464 let mut r = _mm_set1_epi32(0);
12465 _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
12466 let e = _mm_set1_epi32(u32::MAX as i32);
12467 assert_eq_m128i(r, e);
12468 }
12469
12470 #[simd_test(enable = "avx512f,avx512vl")]
12471 unsafe fn test_mm_mask_cvtusepi64_storeu_epi32() {
12472 let a = _mm_set1_epi64x(i64::MAX);
12473 let mut r = _mm_set1_epi16(0);
12474 _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
12475 let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32);
12476 assert_eq_m128i(r, e);
12477 }
12478
12479 #[simd_test(enable = "avx512f")]
12480 const unsafe fn test_mm512_storeu_epi64() {
12481 let a = _mm512_set1_epi64(9);
12482 let mut r = _mm512_set1_epi64(0);
12483 _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12484 assert_eq_m512i(r, a);
12485 }
12486
12487 #[simd_test(enable = "avx512f,avx512vl")]
12488 const unsafe fn test_mm256_storeu_epi64() {
12489 let a = _mm256_set1_epi64x(9);
12490 let mut r = _mm256_set1_epi64x(0);
12491 _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12492 assert_eq_m256i(r, a);
12493 }
12494
12495 #[simd_test(enable = "avx512f,avx512vl")]
12496 const unsafe fn test_mm_storeu_epi64() {
12497 let a = _mm_set1_epi64x(9);
12498 let mut r = _mm_set1_epi64x(0);
12499 _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12500 assert_eq_m128i(r, a);
12501 }
12502
12503 #[simd_test(enable = "avx512f")]
12504 const unsafe fn test_mm512_load_epi64() {
12505 #[repr(align(64))]
12506 struct Align {
12507 data: [i64; 8], }
12509 let a = Align {
12510 data: [4, 3, 2, 5, -8, -9, -64, -50],
12511 };
12512 let p = (a.data).as_ptr();
12513 let r = _mm512_load_epi64(black_box(p));
12514 let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12515 assert_eq_m512i(r, e);
12516 }
12517
12518 #[simd_test(enable = "avx512f,avx512vl")]
12519 const unsafe fn test_mm256_load_epi64() {
12520 #[repr(align(64))]
12521 struct Align {
12522 data: [i64; 4],
12523 }
12524 let a = Align { data: [4, 3, 2, 5] };
12525 let p = (a.data).as_ptr();
12526 let r = _mm256_load_epi64(black_box(p));
12527 let e = _mm256_set_epi64x(5, 2, 3, 4);
12528 assert_eq_m256i(r, e);
12529 }
12530
12531 #[simd_test(enable = "avx512f,avx512vl")]
12532 const unsafe fn test_mm_load_epi64() {
12533 #[repr(align(64))]
12534 struct Align {
12535 data: [i64; 2],
12536 }
12537 let a = Align { data: [4, 3] };
12538 let p = (a.data).as_ptr();
12539 let r = _mm_load_epi64(black_box(p));
12540 let e = _mm_set_epi64x(3, 4);
12541 assert_eq_m128i(r, e);
12542 }
12543
12544 #[simd_test(enable = "avx512f")]
12545 const unsafe fn test_mm512_store_epi64() {
12546 let a = _mm512_set1_epi64(9);
12547 let mut r = _mm512_set1_epi64(0);
12548 _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
12549 assert_eq_m512i(r, a);
12550 }
12551
12552 #[simd_test(enable = "avx512f,avx512vl")]
12553 const unsafe fn test_mm256_store_epi64() {
12554 let a = _mm256_set1_epi64x(9);
12555 let mut r = _mm256_set1_epi64x(0);
12556 _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
12557 assert_eq_m256i(r, a);
12558 }
12559
12560 #[simd_test(enable = "avx512f,avx512vl")]
12561 const unsafe fn test_mm_store_epi64() {
12562 let a = _mm_set1_epi64x(9);
12563 let mut r = _mm_set1_epi64x(0);
12564 _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
12565 assert_eq_m128i(r, a);
12566 }
12567
12568 #[simd_test(enable = "avx512f")]
12569 const unsafe fn test_mm512_load_pd() {
12570 #[repr(align(64))]
12571 struct Align {
12572 data: [f64; 8], }
12574 let a = Align {
12575 data: [4., 3., 2., 5., -8., -9., -64., -50.],
12576 };
12577 let p = (a.data).as_ptr();
12578 let r = _mm512_load_pd(black_box(p));
12579 let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.);
12580 assert_eq_m512d(r, e);
12581 }
12582
12583 #[simd_test(enable = "avx512f")]
12584 const unsafe fn test_mm512_store_pd() {
12585 let a = _mm512_set1_pd(9.);
12586 let mut r = _mm512_undefined_pd();
12587 _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
12588 assert_eq_m512d(r, a);
12589 }
12590
12591 #[simd_test(enable = "avx512f")]
12592 const unsafe fn test_mm512_test_epi64_mask() {
12593 let a = _mm512_set1_epi64(1 << 0);
12594 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12595 let r = _mm512_test_epi64_mask(a, b);
12596 let e: __mmask8 = 0b11111111;
12597 assert_eq!(r, e);
12598 }
12599
12600 #[simd_test(enable = "avx512f")]
12601 const unsafe fn test_mm512_mask_test_epi64_mask() {
12602 let a = _mm512_set1_epi64(1 << 0);
12603 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12604 let r = _mm512_mask_test_epi64_mask(0, a, b);
12605 assert_eq!(r, 0);
12606 let r = _mm512_mask_test_epi64_mask(0b11111111, a, b);
12607 let e: __mmask8 = 0b11111111;
12608 assert_eq!(r, e);
12609 }
12610
12611 #[simd_test(enable = "avx512f,avx512vl")]
12612 const unsafe fn test_mm256_test_epi64_mask() {
12613 let a = _mm256_set1_epi64x(1 << 0);
12614 let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12615 let r = _mm256_test_epi64_mask(a, b);
12616 let e: __mmask8 = 0b00001111;
12617 assert_eq!(r, e);
12618 }
12619
12620 #[simd_test(enable = "avx512f,avx512vl")]
12621 const unsafe fn test_mm256_mask_test_epi64_mask() {
12622 let a = _mm256_set1_epi64x(1 << 0);
12623 let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12624 let r = _mm256_mask_test_epi64_mask(0, a, b);
12625 assert_eq!(r, 0);
12626 let r = _mm256_mask_test_epi64_mask(0b00001111, a, b);
12627 let e: __mmask8 = 0b00001111;
12628 assert_eq!(r, e);
12629 }
12630
12631 #[simd_test(enable = "avx512f,avx512vl")]
12632 const unsafe fn test_mm_test_epi64_mask() {
12633 let a = _mm_set1_epi64x(1 << 0);
12634 let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12635 let r = _mm_test_epi64_mask(a, b);
12636 let e: __mmask8 = 0b00000011;
12637 assert_eq!(r, e);
12638 }
12639
12640 #[simd_test(enable = "avx512f,avx512vl")]
12641 const unsafe fn test_mm_mask_test_epi64_mask() {
12642 let a = _mm_set1_epi64x(1 << 0);
12643 let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12644 let r = _mm_mask_test_epi64_mask(0, a, b);
12645 assert_eq!(r, 0);
12646 let r = _mm_mask_test_epi64_mask(0b00000011, a, b);
12647 let e: __mmask8 = 0b00000011;
12648 assert_eq!(r, e);
12649 }
12650
12651 #[simd_test(enable = "avx512f")]
12652 const unsafe fn test_mm512_testn_epi64_mask() {
12653 let a = _mm512_set1_epi64(1 << 0);
12654 let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12655 let r = _mm512_testn_epi64_mask(a, b);
12656 let e: __mmask8 = 0b00000000;
12657 assert_eq!(r, e);
12658 }
12659
12660 #[simd_test(enable = "avx512f")]
12661 const unsafe fn test_mm512_mask_testn_epi64_mask() {
12662 let a = _mm512_set1_epi64(1 << 0);
12663 let b = _mm512_set1_epi64(1 << 1);
12664 let r = _mm512_mask_testn_epi64_mask(0, a, b);
12665 assert_eq!(r, 0);
12666 let r = _mm512_mask_testn_epi64_mask(0b11111111, a, b);
12667 let e: __mmask8 = 0b11111111;
12668 assert_eq!(r, e);
12669 }
12670
12671 #[simd_test(enable = "avx512f,avx512vl")]
12672 const unsafe fn test_mm256_testn_epi64_mask() {
12673 let a = _mm256_set1_epi64x(1 << 0);
12674 let b = _mm256_set1_epi64x(1 << 1);
12675 let r = _mm256_testn_epi64_mask(a, b);
12676 let e: __mmask8 = 0b00001111;
12677 assert_eq!(r, e);
12678 }
12679
12680 #[simd_test(enable = "avx512f,avx512vl")]
12681 const unsafe fn test_mm256_mask_testn_epi64_mask() {
12682 let a = _mm256_set1_epi64x(1 << 0);
12683 let b = _mm256_set1_epi64x(1 << 1);
12684 let r = _mm256_mask_testn_epi64_mask(0, a, b);
12685 assert_eq!(r, 0);
12686 let r = _mm256_mask_testn_epi64_mask(0b11111111, a, b);
12687 let e: __mmask8 = 0b00001111;
12688 assert_eq!(r, e);
12689 }
12690
12691 #[simd_test(enable = "avx512f,avx512vl")]
12692 const unsafe fn test_mm_testn_epi64_mask() {
12693 let a = _mm_set1_epi64x(1 << 0);
12694 let b = _mm_set1_epi64x(1 << 1);
12695 let r = _mm_testn_epi64_mask(a, b);
12696 let e: __mmask8 = 0b00000011;
12697 assert_eq!(r, e);
12698 }
12699
12700 #[simd_test(enable = "avx512f,avx512vl")]
12701 const unsafe fn test_mm_mask_testn_epi64_mask() {
12702 let a = _mm_set1_epi64x(1 << 0);
12703 let b = _mm_set1_epi64x(1 << 1);
12704 let r = _mm_mask_testn_epi64_mask(0, a, b);
12705 assert_eq!(r, 0);
12706 let r = _mm_mask_testn_epi64_mask(0b11111111, a, b);
12707 let e: __mmask8 = 0b00000011;
12708 assert_eq!(r, e);
12709 }
12710
12711 #[simd_test(enable = "avx512f")]
12712 const unsafe fn test_mm512_mask_set1_epi64() {
12713 let src = _mm512_set1_epi64(2);
12714 let a: i64 = 11;
12715 let r = _mm512_mask_set1_epi64(src, 0, a);
12716 assert_eq_m512i(r, src);
12717 let r = _mm512_mask_set1_epi64(src, 0b11111111, a);
12718 let e = _mm512_set1_epi64(11);
12719 assert_eq_m512i(r, e);
12720 }
12721
12722 #[simd_test(enable = "avx512f")]
12723 const unsafe fn test_mm512_maskz_set1_epi64() {
12724 let a: i64 = 11;
12725 let r = _mm512_maskz_set1_epi64(0, a);
12726 assert_eq_m512i(r, _mm512_setzero_si512());
12727 let r = _mm512_maskz_set1_epi64(0b11111111, a);
12728 let e = _mm512_set1_epi64(11);
12729 assert_eq_m512i(r, e);
12730 }
12731
12732 #[simd_test(enable = "avx512f,avx512vl")]
12733 const unsafe fn test_mm256_mask_set1_epi64() {
12734 let src = _mm256_set1_epi64x(2);
12735 let a: i64 = 11;
12736 let r = _mm256_mask_set1_epi64(src, 0, a);
12737 assert_eq_m256i(r, src);
12738 let r = _mm256_mask_set1_epi64(src, 0b00001111, a);
12739 let e = _mm256_set1_epi64x(11);
12740 assert_eq_m256i(r, e);
12741 }
12742
12743 #[simd_test(enable = "avx512f,avx512vl")]
12744 const unsafe fn test_mm256_maskz_set1_epi64() {
12745 let a: i64 = 11;
12746 let r = _mm256_maskz_set1_epi64(0, a);
12747 assert_eq_m256i(r, _mm256_setzero_si256());
12748 let r = _mm256_maskz_set1_epi64(0b00001111, a);
12749 let e = _mm256_set1_epi64x(11);
12750 assert_eq_m256i(r, e);
12751 }
12752
12753 #[simd_test(enable = "avx512f,avx512vl")]
12754 const unsafe fn test_mm_mask_set1_epi64() {
12755 let src = _mm_set1_epi64x(2);
12756 let a: i64 = 11;
12757 let r = _mm_mask_set1_epi64(src, 0, a);
12758 assert_eq_m128i(r, src);
12759 let r = _mm_mask_set1_epi64(src, 0b00000011, a);
12760 let e = _mm_set1_epi64x(11);
12761 assert_eq_m128i(r, e);
12762 }
12763
12764 #[simd_test(enable = "avx512f,avx512vl")]
12765 const unsafe fn test_mm_maskz_set1_epi64() {
12766 let a: i64 = 11;
12767 let r = _mm_maskz_set1_epi64(0, a);
12768 assert_eq_m128i(r, _mm_setzero_si128());
12769 let r = _mm_maskz_set1_epi64(0b00000011, a);
12770 let e = _mm_set1_epi64x(11);
12771 assert_eq_m128i(r, e);
12772 }
12773
12774 #[simd_test(enable = "avx512f")]
12775 unsafe fn test_mm_cvtsd_i64() {
12776 let a = _mm_set_pd(1., -1.5);
12777 let r = _mm_cvtsd_i64(a);
12778 let e: i64 = -2;
12779 assert_eq!(r, e);
12780 }
12781
12782 #[simd_test(enable = "avx512f")]
12783 unsafe fn test_mm_cvtss_i64() {
12784 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12785 let r = _mm_cvtss_i64(a);
12786 let e: i64 = -2;
12787 assert_eq!(r, e);
12788 }
12789
12790 #[simd_test(enable = "avx512f")]
12791 unsafe fn test_mm_cvt_roundi64_ss() {
12792 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12793 let b: i64 = 9;
12794 let r = _mm_cvt_roundi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12795 let e = _mm_set_ps(0., -0.5, 1., 9.);
12796 assert_eq_m128(r, e);
12797 }
12798
12799 #[simd_test(enable = "avx512f")]
12800 unsafe fn test_mm_cvt_roundsi64_ss() {
12801 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12802 let b: i64 = 9;
12803 let r = _mm_cvt_roundsi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12804 let e = _mm_set_ps(0., -0.5, 1., 9.);
12805 assert_eq_m128(r, e);
12806 }
12807
12808 #[simd_test(enable = "avx512f")]
12809 const unsafe fn test_mm_cvti64_ss() {
12810 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12811 let b: i64 = 9;
12812 let r = _mm_cvti64_ss(a, b);
12813 let e = _mm_set_ps(0., -0.5, 1., 9.);
12814 assert_eq_m128(r, e);
12815 }
12816
12817 #[simd_test(enable = "avx512f")]
12818 const unsafe fn test_mm_cvti64_sd() {
12819 let a = _mm_set_pd(1., -1.5);
12820 let b: i64 = 9;
12821 let r = _mm_cvti64_sd(a, b);
12822 let e = _mm_set_pd(1., 9.);
12823 assert_eq_m128d(r, e);
12824 }
12825
12826 #[simd_test(enable = "avx512f")]
12827 unsafe fn test_mm_cvt_roundsd_si64() {
12828 let a = _mm_set_pd(1., -1.5);
12829 let r = _mm_cvt_roundsd_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12830 let e: i64 = -1;
12831 assert_eq!(r, e);
12832 }
12833
12834 #[simd_test(enable = "avx512f")]
12835 unsafe fn test_mm_cvt_roundsd_i64() {
12836 let a = _mm_set_pd(1., -1.5);
12837 let r = _mm_cvt_roundsd_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12838 let e: i64 = -1;
12839 assert_eq!(r, e);
12840 }
12841
12842 #[simd_test(enable = "avx512f")]
12843 unsafe fn test_mm_cvt_roundsd_u64() {
12844 let a = _mm_set_pd(1., f64::MAX);
12845 let r = _mm_cvt_roundsd_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12846 let e: u64 = u64::MAX;
12847 assert_eq!(r, e);
12848 }
12849
12850 #[simd_test(enable = "avx512f")]
12851 unsafe fn test_mm_cvtsd_u64() {
12852 let a = _mm_set_pd(1., -1.5);
12853 let r = _mm_cvtsd_u64(a);
12854 let e: u64 = u64::MAX;
12855 assert_eq!(r, e);
12856 }
12857
12858 #[simd_test(enable = "avx512f")]
12859 unsafe fn test_mm_cvt_roundss_i64() {
12860 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12861 let r = _mm_cvt_roundss_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12862 let e: i64 = -1;
12863 assert_eq!(r, e);
12864 }
12865
12866 #[simd_test(enable = "avx512f")]
12867 unsafe fn test_mm_cvt_roundss_si64() {
12868 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12869 let r = _mm_cvt_roundss_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12870 let e: i64 = -1;
12871 assert_eq!(r, e);
12872 }
12873
12874 #[simd_test(enable = "avx512f")]
12875 unsafe fn test_mm_cvt_roundss_u64() {
12876 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12877 let r = _mm_cvt_roundss_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
12878 let e: u64 = u64::MAX;
12879 assert_eq!(r, e);
12880 }
12881
12882 #[simd_test(enable = "avx512f")]
12883 unsafe fn test_mm_cvtss_u64() {
12884 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12885 let r = _mm_cvtss_u64(a);
12886 let e: u64 = u64::MAX;
12887 assert_eq!(r, e);
12888 }
12889
12890 #[simd_test(enable = "avx512f")]
12891 unsafe fn test_mm_cvttsd_i64() {
12892 let a = _mm_set_pd(1., -1.5);
12893 let r = _mm_cvttsd_i64(a);
12894 let e: i64 = -1;
12895 assert_eq!(r, e);
12896 }
12897
12898 #[simd_test(enable = "avx512f")]
12899 unsafe fn test_mm_cvtt_roundsd_i64() {
12900 let a = _mm_set_pd(1., -1.5);
12901 let r = _mm_cvtt_roundsd_i64::<_MM_FROUND_NO_EXC>(a);
12902 let e: i64 = -1;
12903 assert_eq!(r, e);
12904 }
12905
12906 #[simd_test(enable = "avx512f")]
12907 unsafe fn test_mm_cvtt_roundsd_si64() {
12908 let a = _mm_set_pd(1., -1.5);
12909 let r = _mm_cvtt_roundsd_si64::<_MM_FROUND_NO_EXC>(a);
12910 let e: i64 = -1;
12911 assert_eq!(r, e);
12912 }
12913
12914 #[simd_test(enable = "avx512f")]
12915 unsafe fn test_mm_cvtt_roundsd_u64() {
12916 let a = _mm_set_pd(1., -1.5);
12917 let r = _mm_cvtt_roundsd_u64::<_MM_FROUND_NO_EXC>(a);
12918 let e: u64 = u64::MAX;
12919 assert_eq!(r, e);
12920 }
12921
12922 #[simd_test(enable = "avx512f")]
12923 unsafe fn test_mm_cvttsd_u64() {
12924 let a = _mm_set_pd(1., -1.5);
12925 let r = _mm_cvttsd_u64(a);
12926 let e: u64 = u64::MAX;
12927 assert_eq!(r, e);
12928 }
12929
12930 #[simd_test(enable = "avx512f")]
12931 unsafe fn test_mm_cvttss_i64() {
12932 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12933 let r = _mm_cvttss_i64(a);
12934 let e: i64 = -1;
12935 assert_eq!(r, e);
12936 }
12937
12938 #[simd_test(enable = "avx512f")]
12939 unsafe fn test_mm_cvtt_roundss_i64() {
12940 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12941 let r = _mm_cvtt_roundss_i64::<_MM_FROUND_NO_EXC>(a);
12942 let e: i64 = -1;
12943 assert_eq!(r, e);
12944 }
12945
12946 #[simd_test(enable = "avx512f")]
12947 unsafe fn test_mm_cvtt_roundss_si64() {
12948 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12949 let r = _mm_cvtt_roundss_si64::<_MM_FROUND_NO_EXC>(a);
12950 let e: i64 = -1;
12951 assert_eq!(r, e);
12952 }
12953
12954 #[simd_test(enable = "avx512f")]
12955 unsafe fn test_mm_cvtt_roundss_u64() {
12956 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12957 let r = _mm_cvtt_roundss_u64::<_MM_FROUND_NO_EXC>(a);
12958 let e: u64 = u64::MAX;
12959 assert_eq!(r, e);
12960 }
12961
12962 #[simd_test(enable = "avx512f")]
12963 unsafe fn test_mm_cvttss_u64() {
12964 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12965 let r = _mm_cvttss_u64(a);
12966 let e: u64 = u64::MAX;
12967 assert_eq!(r, e);
12968 }
12969
12970 #[simd_test(enable = "avx512f")]
12971 const unsafe fn test_mm_cvtu64_ss() {
12972 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12973 let b: u64 = 9;
12974 let r = _mm_cvtu64_ss(a, b);
12975 let e = _mm_set_ps(0., -0.5, 1., 9.);
12976 assert_eq_m128(r, e);
12977 }
12978
12979 #[simd_test(enable = "avx512f")]
12980 const unsafe fn test_mm_cvtu64_sd() {
12981 let a = _mm_set_pd(1., -1.5);
12982 let b: u64 = 9;
12983 let r = _mm_cvtu64_sd(a, b);
12984 let e = _mm_set_pd(1., 9.);
12985 assert_eq_m128d(r, e);
12986 }
12987
12988 #[simd_test(enable = "avx512f")]
12989 unsafe fn test_mm_cvt_roundu64_ss() {
12990 let a = _mm_set_ps(0., -0.5, 1., -1.5);
12991 let b: u64 = 9;
12992 let r = _mm_cvt_roundu64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12993 let e = _mm_set_ps(0., -0.5, 1., 9.);
12994 assert_eq_m128(r, e);
12995 }
12996
12997 #[simd_test(enable = "avx512f")]
12998 unsafe fn test_mm_cvt_roundu64_sd() {
12999 let a = _mm_set_pd(1., -1.5);
13000 let b: u64 = 9;
13001 let r = _mm_cvt_roundu64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13002 let e = _mm_set_pd(1., 9.);
13003 assert_eq_m128d(r, e);
13004 }
13005
13006 #[simd_test(enable = "avx512f")]
13007 unsafe fn test_mm_cvt_roundi64_sd() {
13008 let a = _mm_set_pd(1., -1.5);
13009 let b: i64 = 9;
13010 let r = _mm_cvt_roundi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13011 let e = _mm_set_pd(1., 9.);
13012 assert_eq_m128d(r, e);
13013 }
13014
13015 #[simd_test(enable = "avx512f")]
13016 unsafe fn test_mm_cvt_roundsi64_sd() {
13017 let a = _mm_set_pd(1., -1.5);
13018 let b: i64 = 9;
13019 let r = _mm_cvt_roundsi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13020 let e = _mm_set_pd(1., 9.);
13021 assert_eq_m128d(r, e);
13022 }
13023}