Module aarch64 

Available on AArch64 or ARM64EC only.

Platform-specific intrinsics for the aarch64 platform.

See the module documentation for more details.

Structs

float16x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of four packed f16.

float16x4x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two float16x4_t vectors.

float16x4x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three float16x4_t vectors.

float16x4x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four float16x4_t vectors.

float16x8_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of eight packed f16.

float16x8x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two float16x8_t vectors.

float16x8x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three float16x8_t vectors.

float16x8x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four float16x8_t vectors.

float32x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of two packed f32.

float32x2x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two float32x2_t vectors.

float32x2x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three float32x2_t vectors.

float32x2x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four float32x2_t vectors.

float32x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of four packed f32.

float32x4x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two float32x4_t vectors.

float32x4x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three float32x4_t vectors.

float32x4x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four float32x4_t vectors.

float64x1_t

ARM-specific 64-bit wide vector of one packed f64.

float64x1x2_t

ARM-specific type containing two float64x1_t vectors.

float64x1x3_t

ARM-specific type containing three float64x1_t vectors.

float64x1x4_t

ARM-specific type containing four float64x1_t vectors.

float64x2_t

ARM-specific 128-bit wide vector of two packed f64.

float64x2x2_t

ARM-specific type containing two float64x2_t vectors.

float64x2x3_t

ARM-specific type containing three float64x2_t vectors.

float64x2x4_t

ARM-specific type containing four float64x2_t vectors.

int8x8_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of eight packed i8.

int8x8x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two int8x8_t vectors.

int8x8x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three int8x8_t vectors.

int8x8x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four int8x8_t vectors.

int8x16_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of sixteen packed i8.

int8x16x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two int8x16_t vectors.

int8x16x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three int8x16_t vectors.

int8x16x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four int8x16_t vectors.

int16x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of four packed i16.

int16x4x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two int16x4_t vectors.

int16x4x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three int16x4_t vectors.

int16x4x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four int16x4_t vectors.

int16x8_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of eight packed i16.

int16x8x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two int16x8_t vectors.

int16x8x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three int16x8_t vectors.

int16x8x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four int16x8_t vectors.

int32x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of two packed i32.

int32x2x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two int32x2_t vectors.

int32x2x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three int32x2_t vectors.

int32x2x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four int32x2_t vectors.

int32x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of four packed i32.

int32x4x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two int32x4_t vectors.

int32x4x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three int32x4_t vectors.

int32x4x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four int32x4_t vectors.

int64x1_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of one packed i64.

int64x1x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two int64x1_t vectors.

int64x1x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three int64x1_t vectors.

int64x1x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four int64x1_t vectors.

int64x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of two packed i64.

int64x2x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two int64x2_t vectors.

int64x2x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three int64x2_t vectors.

int64x2x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four int64x2_t vectors.

poly8x8_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide polynomial vector of eight packed p8.

poly8x8x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two poly8x8_t vectors.

poly8x8x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three poly8x8_t vectors.

poly8x8x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four poly8x8_t vectors.

poly8x16_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of sixteen packed p8.

poly8x16x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two poly8x16_t vectors.

poly8x16x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three poly8x16_t vectors.

poly8x16x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four poly8x16_t vectors.

poly16x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of four packed p16.

poly16x4x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two poly16x4_t vectors.

poly16x4x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three poly16x4_t vectors.

poly16x4x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four poly16x4_t vectors.

poly16x8_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of eight packed p16.

poly16x8x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two poly16x8_t vectors.

poly16x8x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three poly16x8_t vectors.

poly16x8x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four poly16x8_t vectors.

poly64x1_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of one packed p64.

poly64x1x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two poly64x1_t vectors.

poly64x1x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three poly64x1_t vectors.

poly64x1x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four poly64x1_t vectors.

poly64x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of two packed p64.

poly64x2x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two poly64x2_t vectors.

poly64x2x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three poly64x2_t vectors.

poly64x2x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four poly64x2_t vectors.

uint8x8_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of eight packed u8.

uint8x8x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two uint8x8_t vectors.

uint8x8x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three uint8x8_t vectors.

uint8x8x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four uint8x8_t vectors.

uint8x16_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of sixteen packed u8.

uint8x16x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two uint8x16_t vectors.

uint8x16x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three uint8x16_t vectors.

uint8x16x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four uint8x16_t vectors.

uint16x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of four packed u16.

uint16x4x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two uint16x4_t vectors.

uint16x4x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three uint16x4_t vectors.

uint16x4x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four uint16x4_t vectors.

uint16x8_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of eight packed u16.

uint16x8x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two uint16x8_t vectors.

uint16x8x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three uint16x8_t vectors.

uint16x8x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four uint16x8_t vectors.

uint32x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of two packed u32.

uint32x2x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two uint32x2_t vectors.

uint32x2x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three uint32x2_t vectors.

uint32x2x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four uint32x2_t vectors.

uint32x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of four packed u32.

uint32x4x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two uint32x4_t vectors.

uint32x4x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three uint32x4_t vectors.

uint32x4x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four uint32x4_t vectors.

uint64x1_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 64-bit wide vector of one packed u64.

uint64x1x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two uint64x1_t vectors.

uint64x1x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three uint64x1_t vectors.

uint64x1x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four uint64x1_t vectors.

uint64x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific 128-bit wide vector of two packed u64.

uint64x2x2_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing two uint64x2_t vectors.

uint64x2x3_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing three uint64x2_t vectors.

uint64x2x4_t(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC)

Arm-specific type containing four uint64x2_t vectors.

SYExperimentalNeither AArch64 nor ARM64EC nor v7 nor mclass and (ARM or AArch64 or ARM64EC)

Full system is the required shareability domain, reads and writes are the required access types

svbool_tExperimental

Scalable vector of type bool

svfloat32_tExperimental

Scalable vector of type f32

svfloat32x2_tExperimental

Two-element tuple of scalable vectors of type svfloat32_t

svfloat32x3_tExperimental

Three-element tuple of scalable vectors of type svfloat32_t

svfloat32x4_tExperimental

Four-element tuple of scalable vectors of type svfloat32_t

svfloat64_tExperimental

Scalable vector of type f64

svfloat64x2_tExperimental

Two-element tuple of scalable vectors of type svfloat64_t

svfloat64x3_tExperimental

Three-element tuple of scalable vectors of type svfloat64_t

svfloat64x4_tExperimental

Four-element tuple of scalable vectors of type svfloat64_t

svint8_tExperimental

Scalable vector of type i8

svint8x2_tExperimental

Two-element tuple of scalable vectors of type svint8_t

svint8x3_tExperimental

Three-element tuple of scalable vectors of type svint8_t

svint8x4_tExperimental

Four-element tuple of scalable vectors of type svint8_t

svint16_tExperimental

Scalable vector of type i16

svint16x2_tExperimental

Two-element tuple of scalable vectors of type svint16_t

svint16x3_tExperimental

Three-element tuple of scalable vectors of type svint16_t

svint16x4_tExperimental

Four-element tuple of scalable vectors of type svint16_t

svint32_tExperimental

Scalable vector of type i32

svint32x2_tExperimental

Two-element tuple of scalable vectors of type svint32_t

svint32x3_tExperimental

Three-element tuple of scalable vectors of type svint32_t

svint32x4_tExperimental

Four-element tuple of scalable vectors of type svint32_t

svint64_tExperimental

Scalable vector of type i64

svint64x2_tExperimental

Two-element tuple of scalable vectors of type svint64_t

svint64x3_tExperimental

Three-element tuple of scalable vectors of type svint64_t

svint64x4_tExperimental

Four-element tuple of scalable vectors of type svint64_t

svuint8_tExperimental

Scalable vector of type u8

svuint8x2_tExperimental

Two-element tuple of scalable vectors of type svuint8_t

svuint8x3_tExperimental

Three-element tuple of scalable vectors of type svuint8_t

svuint8x4_tExperimental

Four-element tuple of scalable vectors of type svuint8_t

svuint16_tExperimental

Scalable vector of type u16

svuint16x2_tExperimental

Two-element tuple of scalable vectors of type svuint16_t

svuint16x3_tExperimental

Three-element tuple of scalable vectors of type svuint16_t

svuint16x4_tExperimental

Four-element tuple of scalable vectors of type svuint16_t

svuint32_tExperimental

Scalable vector of type u32

svuint32x2_tExperimental

Two-element tuple of scalable vectors of type svuint32_t

svuint32x3_tExperimental

Three-element tuple of scalable vectors of type svuint32_t

svuint32x4_tExperimental

Four-element tuple of scalable vectors of type svuint32_t

svuint64_tExperimental

Scalable vector of type u64

svuint64x2_tExperimental

Two-element tuple of scalable vectors of type svuint64_t

svuint64x3_tExperimental

Three-element tuple of scalable vectors of type svuint64_t

svuint64x4_tExperimental

Four-element tuple of scalable vectors of type svuint64_t

Enums

svpatternExperimental

Patterns returned by a PTRUE

svprfopExperimental

Addressing mode for prefetch intrinsics - allows the specification of the expected access kind (read or write), the cache level to load the data, the data retention policy (temporal or streaming)

Constants

_PREFETCH_LOCALITY0Experimental

See prefetch.

_PREFETCH_LOCALITY1Experimental

See prefetch.

_PREFETCH_LOCALITY2Experimental

See prefetch.

_PREFETCH_LOCALITY3Experimental

See prefetch.

_PREFETCH_READExperimental

See prefetch.

_PREFETCH_WRITEExperimental

See prefetch.

Functions

__crc32b(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and crc

CRC32 single round checksum for bytes (8 bits). Arm’s documentation

__crc32cb(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and crc

CRC32-C single round checksum for bytes (8 bits). Arm’s documentation

__crc32cdcrc

CRC32-C single round checksum for quad words (64 bits). Arm’s documentation

__crc32ch(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and crc

CRC32-C single round checksum for bytes (16 bits). Arm’s documentation

__crc32cw(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and crc

CRC32-C single round checksum for bytes (32 bits). Arm’s documentation

__crc32dcrc

CRC32 single round checksum for quad words (64 bits). Arm’s documentation

__crc32h(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and crc

CRC32 single round checksum for bytes (16 bits). Arm’s documentation

__crc32w(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and crc

CRC32 single round checksum for bytes (32 bits). Arm’s documentation

__jcvtjsconv

Floating-point JavaScript convert to signed fixed-point, rounding toward zero Arm’s documentation

vaba_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (64-bit) Arm’s documentation

vaba_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (64-bit) Arm’s documentation

vaba_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (64-bit) Arm’s documentation

vaba_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (64-bit) Arm’s documentation

vaba_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (64-bit) Arm’s documentation

vaba_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (64-bit) Arm’s documentation

vabal_high_s8neon

Signed Absolute difference and Accumulate Long Arm’s documentation

vabal_high_s16neon

Signed Absolute difference and Accumulate Long Arm’s documentation

vabal_high_s32neon

Signed Absolute difference and Accumulate Long Arm’s documentation

vabal_high_u8neon

Unsigned Absolute difference and Accumulate Long Arm’s documentation

vabal_high_u16neon

Unsigned Absolute difference and Accumulate Long Arm’s documentation

vabal_high_u32neon

Unsigned Absolute difference and Accumulate Long Arm’s documentation

vabal_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Absolute difference and Accumulate Long Arm’s documentation

vabal_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Absolute difference and Accumulate Long Arm’s documentation

vabal_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Absolute difference and Accumulate Long Arm’s documentation

vabal_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Absolute difference and Accumulate Long Arm’s documentation

vabal_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Absolute difference and Accumulate Long Arm’s documentation

vabal_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Absolute difference and Accumulate Long Arm’s documentation

vabaq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (128-bit) Arm’s documentation

vabaq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (128-bit) Arm’s documentation

vabaq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (128-bit) Arm’s documentation

vabaq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (128-bit) Arm’s documentation

vabaq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (128-bit) Arm’s documentation

vabaq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference and accumulate (128-bit) Arm’s documentation

vabd_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Absolute difference between the arguments of Floating Arm’s documentation

vabd_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments of Floating Arm’s documentation

vabd_f64neon

Absolute difference between the arguments of Floating Arm’s documentation

vabd_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabd_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabd_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabd_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabd_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabd_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabdd_f64neon

Floating-point absolute difference Arm’s documentation

vabdl_high_s8neon

Signed Absolute difference Long Arm’s documentation

vabdl_high_s16neon

Signed Absolute difference Long Arm’s documentation

vabdl_high_s32neon

Signed Absolute difference Long Arm’s documentation

vabdl_high_u8neon

Unsigned Absolute difference Long Arm’s documentation

vabdl_high_u16neon

Unsigned Absolute difference Long Arm’s documentation

vabdl_high_u32neon

Unsigned Absolute difference Long Arm’s documentation

vabdl_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Absolute difference Long Arm’s documentation

vabdl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Absolute difference Long Arm’s documentation

vabdl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Absolute difference Long Arm’s documentation

vabdl_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Absolute difference Long Arm’s documentation

vabdl_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Absolute difference Long Arm’s documentation

vabdl_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Absolute difference Long Arm’s documentation

vabdq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Absolute difference between the arguments of Floating Arm’s documentation

vabdq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments of Floating Arm’s documentation

vabdq_f64neon

Absolute difference between the arguments of Floating Arm’s documentation

vabdq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabdq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabdq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabdq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabdq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabdq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute difference between the arguments Arm’s documentation

vabds_f32neon

Floating-point absolute difference Arm’s documentation

vabs_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point absolute value Arm’s documentation

vabs_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point absolute value Arm’s documentation

vabs_f64neon

Floating-point absolute value Arm’s documentation

vabs_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute value (wrapping). Arm’s documentation

vabs_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute value (wrapping). Arm’s documentation

vabs_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute value (wrapping). Arm’s documentation

vabs_s64neon

Absolute Value (wrapping). Arm’s documentation

vabsd_s64neon

Absolute Value (wrapping). Arm’s documentation

vabsq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point absolute value Arm’s documentation

vabsq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point absolute value Arm’s documentation

vabsq_f64neon

Floating-point absolute value Arm’s documentation

vabsq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute value (wrapping). Arm’s documentation

vabsq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute value (wrapping). Arm’s documentation

vabsq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Absolute value (wrapping). Arm’s documentation

vabsq_s64neon

Absolute Value (wrapping). Arm’s documentation

vadd_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point Add (vector). Arm’s documentation

vadd_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vadd_f64neon

Vector add.

vadd_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise exclusive OR Arm’s documentation

vadd_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise exclusive OR Arm’s documentation

vadd_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise exclusive OR Arm’s documentation

vadd_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vadd_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vadd_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vadd_s64neon

Vector add.

vadd_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vadd_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vadd_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vadd_u64neon

Vector add.

vaddd_s64neon

Vector add.

vaddd_u64neon

Vector add.

vaddhn_high_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow (high half). Arm’s documentation

vaddhn_high_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow (high half). Arm’s documentation

vaddhn_high_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow (high half). Arm’s documentation

vaddhn_high_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow (high half). Arm’s documentation

vaddhn_high_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow (high half). Arm’s documentation

vaddhn_high_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow (high half). Arm’s documentation

vaddhn_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow. Arm’s documentation

vaddhn_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow. Arm’s documentation

vaddhn_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow. Arm’s documentation

vaddhn_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow. Arm’s documentation

vaddhn_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow. Arm’s documentation

vaddhn_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add returning High Narrow. Arm’s documentation

vaddl_high_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add Long (vector, high half). Arm’s documentation

vaddl_high_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add Long (vector, high half). Arm’s documentation

vaddl_high_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add Long (vector, high half). Arm’s documentation

vaddl_high_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add Long (vector, high half). Arm’s documentation

vaddl_high_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add Long (vector, high half). Arm’s documentation

vaddl_high_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add Long (vector, high half). Arm’s documentation

vaddl_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Long (vector). Arm’s documentation

vaddl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Long (vector). Arm’s documentation

vaddl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Long (vector). Arm’s documentation

vaddl_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Long (vector). Arm’s documentation

vaddl_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Long (vector). Arm’s documentation

vaddl_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Long (vector). Arm’s documentation

vaddlv_s8neon

Signed Add Long across Vector Arm’s documentation

vaddlv_s16neon

Signed Add Long across Vector Arm’s documentation

vaddlv_s32neon

Signed Add Long across Vector Arm’s documentation

vaddlv_u8neon

Unsigned Add Long across Vector Arm’s documentation

vaddlv_u16neon

Unsigned Add Long across Vector Arm’s documentation

vaddlv_u32neon

Unsigned Add Long across Vector Arm’s documentation

vaddlvq_s8neon

Signed Add Long across Vector Arm’s documentation

vaddlvq_s16neon

Signed Add Long across Vector Arm’s documentation

vaddlvq_s32neon

Signed Add Long across Vector Arm’s documentation

vaddlvq_u8neon

Unsigned Add Long across Vector Arm’s documentation

vaddlvq_u16neon

Unsigned Add Long across Vector Arm’s documentation

vaddlvq_u32neon

Unsigned Add Long across Vector Arm’s documentation

vaddq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point Add (vector). Arm’s documentation

vaddq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vaddq_f64neon

Vector add.

vaddq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise exclusive OR Arm’s documentation

vaddq_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise exclusive OR Arm’s documentation

vaddq_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise exclusive OR Arm’s documentation

vaddq_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise exclusive OR Arm’s documentation

vaddq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vaddq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vaddq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vaddq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vaddq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vaddq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vaddq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vaddq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector add. Arm’s documentation

vaddv_f32neon

Floating-point add across vector Arm’s documentation

vaddv_s8neon

Add across vector Arm’s documentation

vaddv_s16neon

Add across vector Arm’s documentation

vaddv_s32neon

Add across vector Arm’s documentation

vaddv_u8neon

Add across vector Arm’s documentation

vaddv_u16neon

Add across vector Arm’s documentation

vaddv_u32neon

Add across vector Arm’s documentation

vaddvq_f32neon

Floating-point add across vector Arm’s documentation

vaddvq_f64neon

Floating-point add across vector Arm’s documentation

vaddvq_s8neon

Add across vector Arm’s documentation

vaddvq_s16neon

Add across vector Arm’s documentation

vaddvq_s32neon

Add across vector Arm’s documentation

vaddvq_s64neon

Add across vector Arm’s documentation

vaddvq_u8neon

Add across vector Arm’s documentation

vaddvq_u16neon

Add across vector Arm’s documentation

vaddvq_u32neon

Add across vector Arm’s documentation

vaddvq_u64neon

Add across vector Arm’s documentation

vaddw_high_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide (high half). Arm’s documentation

vaddw_high_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide (high half). Arm’s documentation

vaddw_high_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide (high half). Arm’s documentation

vaddw_high_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide (high half). Arm’s documentation

vaddw_high_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide (high half). Arm’s documentation

vaddw_high_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide (high half). Arm’s documentation

vaddw_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide Arm’s documentation

vaddw_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide Arm’s documentation

vaddw_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide Arm’s documentation

vaddw_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide Arm’s documentation

vaddw_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide Arm’s documentation

vaddw_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add Wide Arm’s documentation

vaesdq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and aes

AES single round encryption. Arm’s documentation

vaeseq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and aes

AES single round encryption. Arm’s documentation

vaesimcq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and aes

AES inverse mix columns. Arm’s documentation

vaesmcq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and aes

AES mix columns. Arm’s documentation

vand_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vand_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vand_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vand_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vand_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vand_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vand_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vand_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vandq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vandq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vandq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vandq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vandq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vandq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vandq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vandq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise and Arm’s documentation

vbcaxq_s8neon and sha3

Bit clear and exclusive OR Arm’s documentation

vbcaxq_s16neon and sha3

Bit clear and exclusive OR Arm’s documentation

vbcaxq_s32neon and sha3

Bit clear and exclusive OR Arm’s documentation

vbcaxq_s64neon and sha3

Bit clear and exclusive OR Arm’s documentation

vbcaxq_u8neon and sha3

Bit clear and exclusive OR Arm’s documentation

vbcaxq_u16neon and sha3

Bit clear and exclusive OR Arm’s documentation

vbcaxq_u32neon and sha3

Bit clear and exclusive OR Arm’s documentation

vbcaxq_u64neon and sha3

Bit clear and exclusive OR Arm’s documentation

vbic_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbic_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbic_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbic_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbic_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbic_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbic_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbic_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbicq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbicq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbicq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbicq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbicq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbicq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbicq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbicq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise bit clear. Arm’s documentation

vbsl_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Bitwise Select. Arm’s documentation

vbsl_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbsl_f64neon

Bitwise Select instructions. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

vbsl_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbsl_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbsl_p64neon

Bitwise Select.

vbsl_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbsl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbsl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbsl_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbsl_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbsl_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbsl_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbsl_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbslq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Bitwise Select. Arm’s documentation

vbslq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbslq_f64neon

Bitwise Select. (128-bit)

vbslq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbslq_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbslq_p64neon

Bitwise Select. (128-bit)

vbslq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbslq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbslq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbslq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbslq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbslq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbslq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vbslq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Bitwise Select. Arm’s documentation

vcage_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point absolute compare greater than or equal Arm’s documentation

vcage_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point absolute compare greater than or equal Arm’s documentation

vcage_f64neon

Floating-point absolute compare greater than or equal Arm’s documentation

vcaged_f64neon

Floating-point absolute compare greater than or equal Arm’s documentation

vcageq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point absolute compare greater than or equal Arm’s documentation

vcageq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point absolute compare greater than or equal Arm’s documentation

vcageq_f64neon

Floating-point absolute compare greater than or equal Arm’s documentation

vcages_f32neon

Floating-point absolute compare greater than or equal Arm’s documentation

vcagt_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point absolute compare greater than Arm’s documentation

vcagt_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point absolute compare greater than Arm’s documentation

vcagt_f64neon

Floating-point absolute compare greater than Arm’s documentation

vcagtd_f64neon

Floating-point absolute compare greater than Arm’s documentation

vcagtq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point absolute compare greater than Arm’s documentation

vcagtq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point absolute compare greater than Arm’s documentation

vcagtq_f64neon

Floating-point absolute compare greater than Arm’s documentation

vcagts_f32neon

Floating-point absolute compare greater than Arm’s documentation

vcale_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point absolute compare less than or equal Arm’s documentation

vcale_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point absolute compare less than or equal Arm’s documentation

vcale_f64neon

Floating-point absolute compare less than or equal Arm’s documentation

vcaled_f64neon

Floating-point absolute compare less than or equal Arm’s documentation

vcaleq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point absolute compare less than or equal Arm’s documentation

vcaleq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point absolute compare less than or equal Arm’s documentation

vcaleq_f64neon

Floating-point absolute compare less than or equal Arm’s documentation

vcales_f32neon

Floating-point absolute compare less than or equal Arm’s documentation

vcalt_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point absolute compare less than Arm’s documentation

vcalt_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point absolute compare less than Arm’s documentation

vcalt_f64neon

Floating-point absolute compare less than Arm’s documentation

vcaltd_f64neon

Floating-point absolute compare less than Arm’s documentation

vcaltq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point absolute compare less than Arm’s documentation

vcaltq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point absolute compare less than Arm’s documentation

vcaltq_f64neon

Floating-point absolute compare less than Arm’s documentation

vcalts_f32neon

Floating-point absolute compare less than Arm’s documentation

vceq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare equal Arm’s documentation

vceq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point compare equal Arm’s documentation

vceq_f64neon

Floating-point compare equal Arm’s documentation

vceq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceq_p64neon

Compare bitwise Equal (vector) Arm’s documentation

vceq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceq_s64neon

Compare bitwise Equal (vector) Arm’s documentation

vceq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceq_u64neon

Compare bitwise Equal (vector) Arm’s documentation

vceqd_f64neon

Floating-point compare equal Arm’s documentation

vceqd_s64neon

Compare bitwise equal Arm’s documentation

vceqd_u64neon

Compare bitwise equal Arm’s documentation

vceqq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare equal Arm’s documentation

vceqq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point compare equal Arm’s documentation

vceqq_f64neon

Floating-point compare equal Arm’s documentation

vceqq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceqq_p64neon

Compare bitwise Equal (vector) Arm’s documentation

vceqq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceqq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceqq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceqq_s64neon

Compare bitwise Equal (vector) Arm’s documentation

vceqq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceqq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceqq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare bitwise Equal (vector) Arm’s documentation

vceqq_u64neon

Compare bitwise Equal (vector) Arm’s documentation

vceqs_f32neon

Floating-point compare equal Arm’s documentation

vceqz_f16neon and fp16

Floating-point compare bitwise equal to zero Arm’s documentation

vceqz_f32neon

Floating-point compare bitwise equal to zero Arm’s documentation

vceqz_f64neon

Floating-point compare bitwise equal to zero Arm’s documentation

vceqz_p8neon

Signed compare bitwise equal to zero Arm’s documentation

vceqz_p64neon

Signed compare bitwise equal to zero Arm’s documentation

vceqz_s8neon

Signed compare bitwise equal to zero Arm’s documentation

vceqz_s16neon

Signed compare bitwise equal to zero Arm’s documentation

vceqz_s32neon

Signed compare bitwise equal to zero Arm’s documentation

vceqz_s64neon

Signed compare bitwise equal to zero Arm’s documentation

vceqz_u8neon

Unsigned compare bitwise equal to zero Arm’s documentation

vceqz_u16neon

Unsigned compare bitwise equal to zero Arm’s documentation

vceqz_u32neon

Unsigned compare bitwise equal to zero Arm’s documentation

vceqz_u64neon

Unsigned compare bitwise equal to zero Arm’s documentation

vceqzd_f64neon

Floating-point compare bitwise equal to zero Arm’s documentation

vceqzd_s64neon

Compare bitwise equal to zero Arm’s documentation

vceqzd_u64neon

Compare bitwise equal to zero Arm’s documentation

vceqzq_f16neon and fp16

Floating-point compare bitwise equal to zero Arm’s documentation

vceqzq_f32neon

Floating-point compare bitwise equal to zero Arm’s documentation

vceqzq_f64neon

Floating-point compare bitwise equal to zero Arm’s documentation

vceqzq_p8neon

Signed compare bitwise equal to zero Arm’s documentation

vceqzq_p64neon

Signed compare bitwise equal to zero Arm’s documentation

vceqzq_s8neon

Signed compare bitwise equal to zero Arm’s documentation

vceqzq_s16neon

Signed compare bitwise equal to zero Arm’s documentation

vceqzq_s32neon

Signed compare bitwise equal to zero Arm’s documentation

vceqzq_s64neon

Signed compare bitwise equal to zero Arm’s documentation

vceqzq_u8neon

Unsigned compare bitwise equal to zero Arm’s documentation

vceqzq_u16neon

Unsigned compare bitwise equal to zero Arm’s documentation

vceqzq_u32neon

Unsigned compare bitwise equal to zero Arm’s documentation

vceqzq_u64neon

Unsigned compare bitwise equal to zero Arm’s documentation

vceqzs_f32neon

Floating-point compare bitwise equal to zero Arm’s documentation

vcge_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare greater than or equal Arm’s documentation

vcge_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point compare greater than or equal Arm’s documentation

vcge_f64neon

Floating-point compare greater than or equal Arm’s documentation

vcge_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than or equal Arm’s documentation

vcge_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than or equal Arm’s documentation

vcge_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than or equal Arm’s documentation

vcge_s64neon

Compare signed greater than or equal Arm’s documentation

vcge_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than or equal Arm’s documentation

vcge_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than or equal Arm’s documentation

vcge_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than or equal Arm’s documentation

vcge_u64neon

Compare unsigned greater than or equal Arm’s documentation

vcged_f64neon

Floating-point compare greater than or equal Arm’s documentation

vcged_s64neon

Compare greater than or equal Arm’s documentation

vcged_u64neon

Compare greater than or equal Arm’s documentation

vcgeq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare greater than or equal Arm’s documentation

vcgeq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point compare greater than or equal Arm’s documentation

vcgeq_f64neon

Floating-point compare greater than or equal Arm’s documentation

vcgeq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than or equal Arm’s documentation

vcgeq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than or equal Arm’s documentation

vcgeq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than or equal Arm’s documentation

vcgeq_s64neon

Compare signed greater than or equal Arm’s documentation

vcgeq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than or equal Arm’s documentation

vcgeq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than or equal Arm’s documentation

vcgeq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than or equal Arm’s documentation

vcgeq_u64neon

Compare unsigned greater than or equal Arm’s documentation

vcges_f32neon

Floating-point compare greater than or equal Arm’s documentation

vcgez_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare greater than or equal to zero Arm’s documentation

vcgez_f32neon

Floating-point compare greater than or equal to zero Arm’s documentation

vcgez_f64neon

Floating-point compare greater than or equal to zero Arm’s documentation

vcgez_s8neon

Compare signed greater than or equal to zero Arm’s documentation

vcgez_s16neon

Compare signed greater than or equal to zero Arm’s documentation

vcgez_s32neon

Compare signed greater than or equal to zero Arm’s documentation

vcgez_s64neon

Compare signed greater than or equal to zero Arm’s documentation

vcgezd_f64neon

Floating-point compare greater than or equal to zero Arm’s documentation

vcgezd_s64neon

Compare signed greater than or equal to zero Arm’s documentation

vcgezq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare greater than or equal to zero Arm’s documentation

vcgezq_f32neon

Floating-point compare greater than or equal to zero Arm’s documentation

vcgezq_f64neon

Floating-point compare greater than or equal to zero Arm’s documentation

vcgezq_s8neon

Compare signed greater than or equal to zero Arm’s documentation

vcgezq_s16neon

Compare signed greater than or equal to zero Arm’s documentation

vcgezq_s32neon

Compare signed greater than or equal to zero Arm’s documentation

vcgezq_s64neon

Compare signed greater than or equal to zero Arm’s documentation

vcgezs_f32neon

Floating-point compare greater than or equal to zero Arm’s documentation

vcgt_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare greater than Arm’s documentation

vcgt_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point compare greater than Arm’s documentation

vcgt_f64neon

Floating-point compare greater than Arm’s documentation

vcgt_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than Arm’s documentation

vcgt_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than Arm’s documentation

vcgt_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than Arm’s documentation

vcgt_s64neon

Compare signed greater than Arm’s documentation

vcgt_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than Arm’s documentation

vcgt_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than Arm’s documentation

vcgt_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than Arm’s documentation

vcgt_u64neon

Compare unsigned greater than Arm’s documentation

vcgtd_f64neon

Floating-point compare greater than Arm’s documentation

vcgtd_s64neon

Compare greater than Arm’s documentation

vcgtd_u64neon

Compare greater than Arm’s documentation

vcgtq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare greater than Arm’s documentation

vcgtq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point compare greater than Arm’s documentation

vcgtq_f64neon

Floating-point compare greater than Arm’s documentation

vcgtq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than Arm’s documentation

vcgtq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than Arm’s documentation

vcgtq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed greater than Arm’s documentation

vcgtq_s64neon

Compare signed greater than Arm’s documentation

vcgtq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than Arm’s documentation

vcgtq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than Arm’s documentation

vcgtq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned greater than Arm’s documentation

vcgtq_u64neon

Compare unsigned greater than Arm’s documentation

vcgts_f32neon

Floating-point compare greater than Arm’s documentation

vcgtz_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare greater than zero Arm’s documentation

vcgtz_f32neon

Floating-point compare greater than zero Arm’s documentation

vcgtz_f64neon

Floating-point compare greater than zero Arm’s documentation

vcgtz_s8neon

Compare signed greater than zero Arm’s documentation

vcgtz_s16neon

Compare signed greater than zero Arm’s documentation

vcgtz_s32neon

Compare signed greater than zero Arm’s documentation

vcgtz_s64neon

Compare signed greater than zero Arm’s documentation

vcgtzd_f64neon

Floating-point compare greater than zero Arm’s documentation

vcgtzd_s64neon

Compare signed greater than zero Arm’s documentation

vcgtzq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare greater than zero Arm’s documentation

vcgtzq_f32neon

Floating-point compare greater than zero Arm’s documentation

vcgtzq_f64neon

Floating-point compare greater than zero Arm’s documentation

vcgtzq_s8neon

Compare signed greater than zero Arm’s documentation

vcgtzq_s16neon

Compare signed greater than zero Arm’s documentation

vcgtzq_s32neon

Compare signed greater than zero Arm’s documentation

vcgtzq_s64neon

Compare signed greater than zero Arm’s documentation

vcgtzs_f32neon

Floating-point compare greater than zero Arm’s documentation

vcle_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare less than or equal Arm’s documentation

vcle_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point compare less than or equal Arm’s documentation

vcle_f64neon

Floating-point compare less than or equal Arm’s documentation

vcle_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than or equal Arm’s documentation

vcle_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than or equal Arm’s documentation

vcle_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than or equal Arm’s documentation

vcle_s64neon

Compare signed less than or equal Arm’s documentation

vcle_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than or equal Arm’s documentation

vcle_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than or equal Arm’s documentation

vcle_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than or equal Arm’s documentation

vcle_u64neon

Compare unsigned less than or equal Arm’s documentation

vcled_f64neon

Floating-point compare less than or equal Arm’s documentation

vcled_s64neon

Compare less than or equal Arm’s documentation

vcled_u64neon

Compare less than or equal Arm’s documentation

vcleq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare less than or equal Arm’s documentation

vcleq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point compare less than or equal Arm’s documentation

vcleq_f64neon

Floating-point compare less than or equal Arm’s documentation

vcleq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than or equal Arm’s documentation

vcleq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than or equal Arm’s documentation

vcleq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than or equal Arm’s documentation

vcleq_s64neon

Compare signed less than or equal Arm’s documentation

vcleq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than or equal Arm’s documentation

vcleq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than or equal Arm’s documentation

vcleq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than or equal Arm’s documentation

vcleq_u64neon

Compare unsigned less than or equal Arm’s documentation

vcles_f32neon

Floating-point compare less than or equal Arm’s documentation

vclez_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare less than or equal to zero Arm’s documentation

vclez_f32neon

Floating-point compare less than or equal to zero Arm’s documentation

vclez_f64neon

Floating-point compare less than or equal to zero Arm’s documentation

vclez_s8neon

Compare signed less than or equal to zero Arm’s documentation

vclez_s16neon

Compare signed less than or equal to zero Arm’s documentation

vclez_s32neon

Compare signed less than or equal to zero Arm’s documentation

vclez_s64neon

Compare signed less than or equal to zero Arm’s documentation

vclezd_f64neon

Floating-point compare less than or equal to zero Arm’s documentation

vclezd_s64neon

Compare less than or equal to zero Arm’s documentation

vclezq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare less than or equal to zero Arm’s documentation

vclezq_f32neon

Floating-point compare less than or equal to zero Arm’s documentation

vclezq_f64neon

Floating-point compare less than or equal to zero Arm’s documentation

vclezq_s8neon

Compare signed less than or equal to zero Arm’s documentation

vclezq_s16neon

Compare signed less than or equal to zero Arm’s documentation

vclezq_s32neon

Compare signed less than or equal to zero Arm’s documentation

vclezq_s64neon

Compare signed less than or equal to zero Arm’s documentation

vclezs_f32neon

Floating-point compare less than or equal to zero Arm’s documentation

vcls_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vcls_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vcls_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vcls_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vcls_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vcls_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vclsq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vclsq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vclsq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vclsq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vclsq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vclsq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading sign bits Arm’s documentation

vclt_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare less than Arm’s documentation

vclt_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point compare less than Arm’s documentation

vclt_f64neon

Floating-point compare less than Arm’s documentation

vclt_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than Arm’s documentation

vclt_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than Arm’s documentation

vclt_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than Arm’s documentation

vclt_s64neon

Compare signed less than Arm’s documentation

vclt_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than Arm’s documentation

vclt_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than Arm’s documentation

vclt_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than Arm’s documentation

vclt_u64neon

Compare unsigned less than Arm’s documentation

vcltd_f64neon

Floating-point compare less than Arm’s documentation

vcltd_s64neon

Compare less than Arm’s documentation

vcltd_u64neon

Compare less than Arm’s documentation

vcltq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare less than Arm’s documentation

vcltq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point compare less than Arm’s documentation

vcltq_f64neon

Floating-point compare less than Arm’s documentation

vcltq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than Arm’s documentation

vcltq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than Arm’s documentation

vcltq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare signed less than Arm’s documentation

vcltq_s64neon

Compare signed less than Arm’s documentation

vcltq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than Arm’s documentation

vcltq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than Arm’s documentation

vcltq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Compare unsigned less than Arm’s documentation

vcltq_u64neon

Compare unsigned less than Arm’s documentation

vclts_f32neon

Floating-point compare less than Arm’s documentation

vcltz_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare less than Arm’s documentation

vcltz_f32neon

Floating-point compare less than zero Arm’s documentation

vcltz_f64neon

Floating-point compare less than zero Arm’s documentation

vcltz_s8neon

Compare signed less than zero Arm’s documentation

vcltz_s16neon

Compare signed less than zero Arm’s documentation

vcltz_s32neon

Compare signed less than zero Arm’s documentation

vcltz_s64neon

Compare signed less than zero Arm’s documentation

vcltzd_f64neon

Floating-point compare less than zero Arm’s documentation

vcltzd_s64neon

Compare less than zero Arm’s documentation

vcltzq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point compare less than Arm’s documentation

vcltzq_f32neon

Floating-point compare less than zero Arm’s documentation

vcltzq_f64neon

Floating-point compare less than zero Arm’s documentation

vcltzq_s8neon

Compare signed less than zero Arm’s documentation

vcltzq_s16neon

Compare signed less than zero Arm’s documentation

vcltzq_s32neon

Compare signed less than zero Arm’s documentation

vcltzq_s64neon

Compare signed less than zero Arm’s documentation

vcltzs_f32neon

Floating-point compare less than zero Arm’s documentation

vclz_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading zero bits Arm’s documentation

vclz_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading zero bits Arm’s documentation

vclz_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading zero bits Arm’s documentation

vclz_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Count leading zero bits Arm’s documentation

vclz_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Count leading zero bits Arm’s documentation

vclz_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Count leading zero bits Arm’s documentation

vclzq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading zero bits Arm’s documentation

vclzq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading zero bits Arm’s documentation

vclzq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Count leading zero bits Arm’s documentation

vclzq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Count leading zero bits Arm’s documentation

vclzq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Count leading zero bits Arm’s documentation

vclzq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Count leading zero bits Arm’s documentation

vcnt_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Population count per byte. Arm’s documentation

vcnt_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Population count per byte. Arm’s documentation

vcnt_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Population count per byte. Arm’s documentation

vcntq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Population count per byte. Arm’s documentation

vcntq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Population count per byte. Arm’s documentation

vcntq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Population count per byte. Arm’s documentation

vcombine_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_f64neon

Vector combine

vcombine_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcombine_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Join two smaller vectors into a single larger vector Arm’s documentation

vcopy_lane_f32neon

Insert vector element from another vector element Arm’s documentation

vcopy_lane_f64neon

Duplicate vector element to vector or scalar

vcopy_lane_p8neon

Insert vector element from another vector element Arm’s documentation

vcopy_lane_p16neon

Insert vector element from another vector element Arm’s documentation

vcopy_lane_p64neon

Duplicate vector element to vector or scalar

vcopy_lane_s8neon

Insert vector element from another vector element Arm’s documentation

vcopy_lane_s16neon

Insert vector element from another vector element Arm’s documentation

vcopy_lane_s32neon

Insert vector element from another vector element Arm’s documentation

vcopy_lane_s64neon

Duplicate vector element to vector or scalar

vcopy_lane_u8neon

Insert vector element from another vector element Arm’s documentation

vcopy_lane_u16neon

Insert vector element from another vector element Arm’s documentation

vcopy_lane_u32neon

Insert vector element from another vector element Arm’s documentation

vcopy_lane_u64neon

Duplicate vector element to vector or scalar

vcopy_laneq_f32neon

Insert vector element from another vector element Arm’s documentation

vcopy_laneq_f64neon

Duplicate vector element to vector or scalar

vcopy_laneq_p8neon

Insert vector element from another vector element Arm’s documentation

vcopy_laneq_p16neon

Insert vector element from another vector element Arm’s documentation

vcopy_laneq_p64neon

Duplicate vector element to vector or scalar

vcopy_laneq_s8neon

Insert vector element from another vector element Arm’s documentation

vcopy_laneq_s16neon

Insert vector element from another vector element Arm’s documentation

vcopy_laneq_s32neon

Insert vector element from another vector element Arm’s documentation

vcopy_laneq_s64neon

Duplicate vector element to vector or scalar

vcopy_laneq_u8neon

Insert vector element from another vector element Arm’s documentation

vcopy_laneq_u16neon

Insert vector element from another vector element Arm’s documentation

vcopy_laneq_u32neon

Insert vector element from another vector element Arm’s documentation

vcopy_laneq_u64neon

Duplicate vector element to vector or scalar

vcopyq_lane_f32neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_f64neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_p8neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_p16neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_p64neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_s8neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_s16neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_s32neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_s64neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_u8neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_u16neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_u32neon

Insert vector element from another vector element Arm’s documentation

vcopyq_lane_u64neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_f32neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_f64neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_p8neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_p16neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_p64neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_s8neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_s16neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_s32neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_s64neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_u8neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_u16neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_u32neon

Insert vector element from another vector element Arm’s documentation

vcopyq_laneq_u64neon

Insert vector element from another vector element Arm’s documentation

vcreate_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Insert vector element from another vector element Arm’s documentation

vcreate_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Insert vector element from another vector element Arm’s documentation

vcreate_f64neon

Insert vector element from another vector element Arm’s documentation

vcreate_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Insert vector element from another vector element Arm’s documentation

vcreate_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Insert vector element from another vector element Arm’s documentation

vcreate_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Insert vector element from another vector element Arm’s documentation

vcreate_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Insert vector element from another vector element Arm’s documentation

vcreate_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Insert vector element from another vector element Arm’s documentation

vcreate_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Insert vector element from another vector element Arm’s documentation

vcreate_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vcreate_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Insert vector element from another vector element Arm’s documentation

vcreate_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Insert vector element from another vector element Arm’s documentation

vcreate_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Insert vector element from another vector element Arm’s documentation

vcreate_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vcvt_f16_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Floating-point convert to lower precision narrow Arm’s documentation

vcvt_f16_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvt_f16_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvt_f32_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Floating-point convert to higher precision long Arm’s documentation

vcvt_f32_f64neon

Floating-point convert Arm’s documentation

vcvt_f32_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Fixed-point convert to floating-point Arm’s documentation

vcvt_f32_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Fixed-point convert to floating-point Arm’s documentation

vcvt_f64_f32neon

Floating-point convert to higher precision long Arm’s documentation

vcvt_f64_s64neon

Fixed-point convert to floating-point Arm’s documentation

vcvt_f64_u64neon

Fixed-point convert to floating-point Arm’s documentation

vcvt_high_f16_f32neon

Floating-point convert to lower precision Arm’s documentation

vcvt_high_f32_f16neon

Floating-point convert to higher precision Arm’s documentation

vcvt_high_f32_f64neon

Floating-point convert to lower precision narrow Arm’s documentation

vcvt_high_f64_f32neon

Floating-point convert to higher precision long Arm’s documentation

vcvt_n_f16_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvt_n_f16_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvt_n_f32_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Fixed-point convert to floating-point Arm’s documentation

vcvt_n_f32_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Fixed-point convert to floating-point Arm’s documentation

vcvt_n_f64_s64neon

Fixed-point convert to floating-point Arm’s documentation

vcvt_n_f64_u64neon

Fixed-point convert to floating-point Arm’s documentation

vcvt_n_s16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point convert to signed fixed-point Arm’s documentation

vcvt_n_s32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvt_n_s64_f64neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvt_n_u16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Fixed-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation

vcvt_n_u32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvt_n_u64_f64neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvt_s16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation

vcvt_s32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation

vcvt_s64_f64neon

Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation

vcvt_u16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation

vcvt_u32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation

vcvt_u64_f64neon

Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation

vcvta_s16_f16neon and fp16

Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation

vcvta_s32_f32neon

Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation

vcvta_s64_f64neon

Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation

vcvta_u16_f16neon and fp16

Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation

vcvta_u32_f32neon

Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation

vcvta_u64_f64neon

Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation

vcvtad_s64_f64neon

Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation

vcvtad_u64_f64neon

Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation

vcvtaq_s16_f16neon and fp16

Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation

vcvtaq_s32_f32neon

Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation

vcvtaq_s64_f64neon

Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation

vcvtaq_u16_f16neon and fp16

Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation

vcvtaq_u32_f32neon

Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation

vcvtaq_u64_f64neon

Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation

vcvtas_s32_f32neon

Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation

vcvtas_u32_f32neon

Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation

vcvtd_f64_s64neon

Fixed-point convert to floating-point Arm’s documentation

vcvtd_f64_u64neon

Fixed-point convert to floating-point Arm’s documentation

vcvtd_n_f64_s64neon

Fixed-point convert to floating-point Arm’s documentation

vcvtd_n_f64_u64neon

Fixed-point convert to floating-point Arm’s documentation

vcvtd_n_s64_f64neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvtd_n_u64_f64neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvtd_s64_f64neon

Fixed-point convert to floating-point Arm’s documentation

vcvtd_u64_f64neon

Fixed-point convert to floating-point Arm’s documentation

vcvtm_s16_f16neon and fp16

Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation

vcvtm_s32_f32neon

Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation

vcvtm_s64_f64neon

Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation

vcvtm_u16_f16neon and fp16

Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation

vcvtm_u32_f32neon

Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation

vcvtm_u64_f64neon

Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation

vcvtmd_s64_f64neon

Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation

vcvtmd_u64_f64neon

Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation

vcvtmq_s16_f16neon and fp16

Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation

vcvtmq_s32_f32neon

Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation

vcvtmq_s64_f64neon

Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation

vcvtmq_u16_f16neon and fp16

Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation

vcvtmq_u32_f32neon

Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation

vcvtmq_u64_f64neon

Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation

vcvtms_s32_f32neon

Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation

vcvtms_u32_f32neon

Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation

vcvtn_s16_f16neon and fp16

Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation

vcvtn_s32_f32neon

Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation

vcvtn_s64_f64neon

Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation

vcvtn_u16_f16neon and fp16

Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation

vcvtn_u32_f32neon

Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation

vcvtn_u64_f64neon

Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation

vcvtnd_s64_f64neon

Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation

vcvtnd_u64_f64neon

Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation

vcvtnq_s16_f16neon and fp16

Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation

vcvtnq_s32_f32neon

Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation

vcvtnq_s64_f64neon

Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation

vcvtnq_u16_f16neon and fp16

Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation

vcvtnq_u32_f32neon

Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation

vcvtnq_u64_f64neon

Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation

vcvtns_s32_f32neon

Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation

vcvtns_u32_f32neon

Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation

vcvtp_s16_f16neon and fp16

Floating-point convert to signed integer, rounding to plus infinity Arm’s documentation

vcvtp_s32_f32neon

Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation

vcvtp_s64_f64neon

Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation

vcvtp_u16_f16neon and fp16

Floating-point convert to unsigned integer, rounding to plus infinity Arm’s documentation

vcvtp_u32_f32neon

Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation

vcvtp_u64_f64neon

Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation

vcvtpd_s64_f64neon

Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation

vcvtpd_u64_f64neon

Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation

vcvtpq_s16_f16neon and fp16

Floating-point convert to signed integer, rounding to plus infinity Arm’s documentation

vcvtpq_s32_f32neon

Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation

vcvtpq_s64_f64neon

Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation

vcvtpq_u16_f16neon and fp16

Floating-point convert to unsigned integer, rounding to plus infinity Arm’s documentation

vcvtpq_u32_f32neon

Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation

vcvtpq_u64_f64neon

Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation

vcvtps_s32_f32neon

Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation

vcvtps_u32_f32neon

Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation

vcvtq_f16_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvtq_f16_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvtq_f32_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Fixed-point convert to floating-point Arm’s documentation

vcvtq_f32_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Fixed-point convert to floating-point Arm’s documentation

vcvtq_f64_s64neon

Fixed-point convert to floating-point Arm’s documentation

vcvtq_f64_u64neon

Fixed-point convert to floating-point Arm’s documentation

vcvtq_n_f16_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvtq_n_f16_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvtq_n_f32_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Fixed-point convert to floating-point Arm’s documentation

vcvtq_n_f32_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Fixed-point convert to floating-point Arm’s documentation

vcvtq_n_f64_s64neon

Fixed-point convert to floating-point Arm’s documentation

vcvtq_n_f64_u64neon

Fixed-point convert to floating-point Arm’s documentation

vcvtq_n_s16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point convert to signed fixed-point Arm’s documentation

vcvtq_n_s32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvtq_n_s64_f64neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvtq_n_u16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Fixed-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation

vcvtq_n_u32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvtq_n_u64_f64neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvtq_s16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation

vcvtq_s32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation

vcvtq_s64_f64neon

Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation

vcvtq_u16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation

vcvtq_u32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation

vcvtq_u64_f64neon

Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation

vcvts_f32_s32neon

Fixed-point convert to floating-point Arm’s documentation

vcvts_f32_u32neon

Fixed-point convert to floating-point Arm’s documentation

vcvts_n_f32_s32neon

Fixed-point convert to floating-point Arm’s documentation

vcvts_n_f32_u32neon

Fixed-point convert to floating-point Arm’s documentation

vcvts_n_s32_f32neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvts_n_u32_f32neon

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvts_s32_f32neon

Fixed-point convert to floating-point Arm’s documentation

vcvts_u32_f32neon

Fixed-point convert to floating-point Arm’s documentation

vcvtx_f32_f64neon

Floating-point convert to lower precision narrow, rounding to odd Arm’s documentation

vcvtx_high_f32_f64neon

Floating-point convert to lower precision narrow, rounding to odd Arm’s documentation

vcvtxd_f32_f64neon

Floating-point convert to lower precision narrow, rounding to odd Arm’s documentation

vdiv_f16neon and fp16

Divide Arm’s documentation

vdiv_f32neon

Divide Arm’s documentation

vdiv_f64neon

Divide Arm’s documentation

vdivq_f16neon and fp16

Divide Arm’s documentation

vdivq_f32neon

Divide Arm’s documentation

vdivq_f64neon

Divide Arm’s documentation

vdup_lane_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_f64neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_p64neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_lane_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_f64neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_p64neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_laneq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdup_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdup_n_f64neon

Duplicate vector element to vector or scalar

vdup_n_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdup_n_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdup_n_p64neon

Duplicate vector element to vector or scalar

vdup_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdup_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdup_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdup_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdup_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdup_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdup_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdup_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdupb_lane_p8neon

Set all vector lanes to the same value Arm’s documentation

vdupb_lane_s8neon

Set all vector lanes to the same value Arm’s documentation

vdupb_lane_u8neon

Set all vector lanes to the same value Arm’s documentation

vdupb_laneq_p8neon

Extract an element from a vector Arm’s documentation

vdupb_laneq_s8neon

Extract an element from a vector Arm’s documentation

vdupb_laneq_u8neon

Extract an element from a vector Arm’s documentation

vdupd_lane_f64neon

Set all vector lanes to the same value Arm’s documentation

vdupd_lane_s64neon

Set all vector lanes to the same value Arm’s documentation

vdupd_lane_u64neon

Set all vector lanes to the same value Arm’s documentation

vdupd_laneq_f64neon

Set all vector lanes to the same value Arm’s documentation

vdupd_laneq_s64neon

Set all vector lanes to the same value Arm’s documentation

vdupd_laneq_u64neon

Set all vector lanes to the same value Arm’s documentation

vduph_lane_p16neon

Set all vector lanes to the same value Arm’s documentation

vduph_lane_s16neon

Set all vector lanes to the same value Arm’s documentation

vduph_lane_u16neon

Set all vector lanes to the same value Arm’s documentation

vduph_laneq_p16neon

Set all vector lanes to the same value Arm’s documentation

vduph_laneq_s16neon

Set all vector lanes to the same value Arm’s documentation

vduph_laneq_u16neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_f64neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_p64neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_lane_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_f64neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_p64neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_laneq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Set all vector lanes to the same value Arm’s documentation

vdupq_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdupq_n_f64neon

Duplicate vector element to vector or scalar

vdupq_n_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdupq_n_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdupq_n_p64neon

Duplicate vector element to vector or scalar

vdupq_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdupq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdupq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdupq_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdupq_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdupq_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdupq_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdupq_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vdups_lane_f32neon

Set all vector lanes to the same value Arm’s documentation

vdups_lane_s32neon

Set all vector lanes to the same value Arm’s documentation

vdups_lane_u32neon

Set all vector lanes to the same value Arm’s documentation

vdups_laneq_f32neon

Set all vector lanes to the same value Arm’s documentation

vdups_laneq_s32neon

Set all vector lanes to the same value Arm’s documentation

vdups_laneq_u32neon

Set all vector lanes to the same value Arm’s documentation

veor3q_s8neon and sha3

Three-way exclusive OR Arm’s documentation

veor3q_s16neon and sha3

Three-way exclusive OR Arm’s documentation

veor3q_s32neon and sha3

Three-way exclusive OR Arm’s documentation

veor3q_s64neon and sha3

Three-way exclusive OR Arm’s documentation

veor3q_u8neon and sha3

Three-way exclusive OR Arm’s documentation

veor3q_u16neon and sha3

Three-way exclusive OR Arm’s documentation

veor3q_u32neon and sha3

Three-way exclusive OR Arm’s documentation

veor3q_u64neon and sha3

Three-way exclusive OR Arm’s documentation

veor_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veor_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veor_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veor_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veor_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veor_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veor_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veor_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veorq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veorq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veorq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veorq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veorq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veorq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veorq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

veorq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise exclusive or (vector) Arm’s documentation

vext_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Extract vector from pair of vectors Arm’s documentation

vext_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vext_f64neon

Extract vector from pair of vectors

vext_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vext_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vext_p64neon

Extract vector from pair of vectors

vext_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vext_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vext_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vext_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vext_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vext_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vext_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vext_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vextq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Extract vector from pair of vectors Arm’s documentation

vextq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vextq_f64neon

Extract vector from pair of vectors Arm’s documentation

vextq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vextq_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vextq_p64neon

Extract vector from pair of vectors Arm’s documentation

vextq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vextq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vextq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vextq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vextq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vextq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vextq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vextq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Extract vector from pair of vectors Arm’s documentation

vfma_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point fused Multiply-Add to accumulator (vector) Arm’s documentation

vfma_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation

vfma_f64neon

Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation

vfma_lane_f16neon and fp16

Floating-point fused multiply-add to accumulator Arm’s documentation

vfma_lane_f32neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfma_lane_f64neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfma_laneq_f16neon and fp16

Floating-point fused multiply-add to accumulator Arm’s documentation

vfma_laneq_f32neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfma_laneq_f64neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfma_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation

vfma_n_f64neon

Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation

vfmad_lane_f64neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmad_laneq_f64neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmaq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point fused Multiply-Add to accumulator (vector) Arm’s documentation

vfmaq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation

vfmaq_f64neon

Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation

vfmaq_lane_f16neon and fp16

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmaq_lane_f32neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmaq_lane_f64neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmaq_laneq_f16neon and fp16

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmaq_laneq_f32neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmaq_laneq_f64neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmaq_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation

vfmaq_n_f64neon

Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation

vfmas_lane_f32neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmas_laneq_f32neon

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmlal_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (vector). Arm’s documentation

vfmlal_lane_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation

vfmlal_lane_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation

vfmlal_laneq_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation

vfmlal_laneq_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation

vfmlal_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (vector). Arm’s documentation

vfmlalq_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (vector). Arm’s documentation

vfmlalq_lane_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation

vfmlalq_lane_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation

vfmlalq_laneq_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation

vfmlalq_laneq_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation

vfmlalq_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Add Long to accumulator (vector). Arm’s documentation

vfmlsl_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (vector). Arm’s documentation

vfmlsl_lane_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation

vfmlsl_lane_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation

vfmlsl_laneq_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation

vfmlsl_laneq_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation

vfmlsl_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (vector). Arm’s documentation

vfmlslq_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (vector). Arm’s documentation

vfmlslq_lane_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation

vfmlslq_lane_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation

vfmlslq_laneq_high_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation

vfmlslq_laneq_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation

vfmlslq_low_f16neon and fp16 and fhm

Floating-point fused Multiply-Subtract Long from accumulator (vector). Arm’s documentation

vfms_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfms_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfms_f64neon

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfms_lane_f16neon and fp16

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfms_lane_f32neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vfms_lane_f64neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vfms_laneq_f16neon and fp16

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfms_laneq_f32neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vfms_laneq_f64neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vfms_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point fused Multiply-subtract to accumulator(vector) Arm’s documentation

vfms_n_f64neon

Floating-point fused Multiply-subtract to accumulator(vector) Arm’s documentation

vfmsd_lane_f64neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vfmsd_laneq_f64neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vfmsq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfmsq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfmsq_f64neon

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfmsq_lane_f16neon and fp16

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfmsq_lane_f32neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vfmsq_lane_f64neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vfmsq_laneq_f16neon and fp16

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfmsq_laneq_f32neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vfmsq_laneq_f64neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vfmsq_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point fused Multiply-subtract to accumulator(vector) Arm’s documentation

vfmsq_n_f64neon

Floating-point fused Multiply-subtract to accumulator(vector) Arm’s documentation

vfmss_lane_f32neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vfmss_laneq_f32neon

Floating-point fused multiply-subtract to accumulator Arm’s documentation

vget_high_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Duplicate vector element to vector Arm’s documentation

vget_high_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_high_f64neon

Duplicate vector element to vector or scalar

vget_high_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_high_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_high_p64neon

Duplicate vector element to vector or scalar

vget_high_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_high_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_high_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_high_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_high_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_high_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_high_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_high_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_lane_f64neon

Duplicate vector element to vector or scalar

vget_lane_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_lane_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_lane_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_lane_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_lane_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_lane_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_lane_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vget_low_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Duplicate vector element to vector Arm’s documentation

vget_low_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_low_f64neon

Duplicate vector element to vector or scalar

vget_low_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_low_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_low_p64neon

Duplicate vector element to vector or scalar

vget_low_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_low_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_low_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_low_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_low_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_low_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_low_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vget_low_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vgetq_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vgetq_lane_f64neon

Duplicate vector element to vector or scalar

vgetq_lane_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vgetq_lane_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vgetq_lane_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vgetq_lane_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vgetq_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vgetq_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vgetq_lane_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vgetq_lane_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vgetq_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vgetq_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vgetq_lane_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Move vector element to general-purpose register Arm’s documentation

vhadd_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhadd_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhadd_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhadd_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhadd_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhadd_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhaddq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhaddq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhaddq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhaddq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhaddq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhaddq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Halving add Arm’s documentation

vhsub_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vhsub_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vhsub_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vhsub_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vhsub_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vhsub_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vhsubq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vhsubq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vhsubq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vhsubq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vhsubq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vhsubq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed halving subtract Arm’s documentation

vld1_dup_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_dup_f64^⚠neon

Load multiple single-element structures to one, two, three, or four registers

vld1_dup_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_dup_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_dup_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_dup_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_dup_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_dup_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_dup_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_dup_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_dup_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_dup_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_dup_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1_f32^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_f64^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_f32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_f32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_f32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_f64_x2^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_f64_x3^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_f64_x4^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_lane_f64^⚠neon

Load one single-element structure to one lane of one register.

vld1_lane_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_lane_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_lane_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_lane_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_lane_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_lane_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1_p8^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_p8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_p8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_p8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_p16^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_p64^⚠neon and aes

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_p16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_p16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_p16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_p64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_p64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_p64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s8^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s16^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s32^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s64^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_s64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u8^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u16^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u32^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u64^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_u64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_dup_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_dup_f64^⚠neon

Load multiple single-element structures to one, two, three, or four registers

vld1q_dup_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_dup_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_dup_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_dup_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_dup_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_dup_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_dup_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_dup_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_dup_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_dup_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_dup_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation

vld1q_f32^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_f64^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_f32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_f32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_f32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_f64_x2^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_f64_x3^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_f64_x4^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_lane_f64^⚠neon

Load one single-element structure to one lane of one register.

vld1q_lane_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_lane_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_lane_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_lane_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_lane_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_lane_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load one single-element structure to one lane of one register. Arm’s documentation

vld1q_p8^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_p8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_p8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_p8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_p16^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_p64^⚠neon and aes

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_p16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_p16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_p16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_p64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_p64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_p64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s8^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s16^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s32^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s64^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_s64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u8^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u16^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u32^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u64^⚠neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_u64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld2_dup_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_f64^⚠neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_dup_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_f64^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_f64^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_p64^⚠neon and aes

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_s64^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_lane_u64^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load multiple 2-element structures to two registers Arm’s documentation

vld2_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_dup_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_f64^⚠neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_p64^⚠neon and aes

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_s64^⚠neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_dup_u64^⚠neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_f64^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_f64^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_p8^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_p64^⚠neon and aes

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_s8^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_s64^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_u8^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_lane_u64^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_p64^⚠neon and aes

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_s64^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_u64^⚠neon

Load multiple 2-element structures to two registers Arm’s documentation

vld3_dup_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_f64^⚠neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_dup_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_f64^⚠neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_lane_f64^⚠neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_lane_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_lane_p64^⚠neon and aes

Load multiple 3-element structures to three registers Arm’s documentation

vld3_lane_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to two registers Arm’s documentation

vld3_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to two registers Arm’s documentation

vld3_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to two registers Arm’s documentation

vld3_lane_s64^⚠neon

Load multiple 3-element structures to two registers Arm’s documentation

vld3_lane_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_lane_u64^⚠neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load multiple 3-element structures to three registers Arm’s documentation

vld3_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_dup_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_f64^⚠neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_p64^⚠neon and aes

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_s64^⚠neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_dup_u64^⚠neon

Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation

vld3q_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_f64^⚠neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_lane_f64^⚠neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_lane_p8^⚠neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_lane_p64^⚠neon and aes

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_lane_s8^⚠neon

Load multiple 3-element structures to two registers Arm’s documentation

vld3q_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to two registers Arm’s documentation

vld3q_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to two registers Arm’s documentation

vld3q_lane_s64^⚠neon

Load multiple 3-element structures to two registers Arm’s documentation

vld3q_lane_u8^⚠neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_lane_u64^⚠neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_p64^⚠neon and aes

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_s64^⚠neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 3-element structures to three registers Arm’s documentation

vld3q_u64^⚠neon

Load multiple 3-element structures to three registers Arm’s documentation

vld4_dup_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_f64^⚠neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_dup_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_f64^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_f64^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_p64^⚠neon and aes

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_s64^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_lane_u64^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Load multiple 4-element structures to four registers Arm’s documentation

vld4_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_dup_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_f64^⚠neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_p64^⚠neon and aes

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_s64^⚠neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_dup_u64^⚠neon

Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation

vld4q_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_f64^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_f64^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_p8^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_p64^⚠neon and aes

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_s8^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_s64^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_u8^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_lane_u64^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_p64^⚠neon and aes

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_s64^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Load multiple 4-element structures to four registers Arm’s documentation

vld4q_u64^⚠neon

Load multiple 4-element structures to four registers Arm’s documentation

vldrq_p128^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store SIMD&FP register (immediate offset) Arm’s documentation

vmax_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Maximum (vector) Arm’s documentation

vmax_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmax_f64neon

Maximum (vector) Arm’s documentation

vmax_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmax_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmax_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmax_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmax_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmax_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmaxnm_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point Maximum Number (vector) Arm’s documentation

vmaxnm_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point Maximum Number (vector) Arm’s documentation

vmaxnm_f64neon

Floating-point Maximum Number (vector) Arm’s documentation

vmaxnmq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point Maximum Number (vector) Arm’s documentation

vmaxnmq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point Maximum Number (vector) Arm’s documentation

vmaxnmq_f64neon

Floating-point Maximum Number (vector) Arm’s documentation

vmaxnmv_f32neon

Floating-point maximum number across vector Arm’s documentation

vmaxnmvq_f32neon

Floating-point maximum number across vector Arm’s documentation

vmaxnmvq_f64neon

Floating-point maximum number across vector Arm’s documentation

vmaxq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Maximum (vector) Arm’s documentation

vmaxq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmaxq_f64neon

Maximum (vector) Arm’s documentation

vmaxq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmaxq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmaxq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmaxq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmaxq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmaxq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Maximum (vector) Arm’s documentation

vmaxv_f32neon

Horizontal vector max. Arm’s documentation

vmaxv_s8neon

Horizontal vector max. Arm’s documentation

vmaxv_s16neon

Horizontal vector max. Arm’s documentation

vmaxv_s32neon

Horizontal vector max. Arm’s documentation

vmaxv_u8neon

Horizontal vector max. Arm’s documentation

vmaxv_u16neon

Horizontal vector max. Arm’s documentation

vmaxv_u32neon

Horizontal vector max. Arm’s documentation

vmaxvq_f32neon

Horizontal vector max. Arm’s documentation

vmaxvq_f64neon

Horizontal vector max. Arm’s documentation

vmaxvq_s8neon

Horizontal vector max. Arm’s documentation

vmaxvq_s16neon

Horizontal vector max. Arm’s documentation

vmaxvq_s32neon

Horizontal vector max. Arm’s documentation

vmaxvq_u8neon

Horizontal vector max. Arm’s documentation

vmaxvq_u16neon

Horizontal vector max. Arm’s documentation

vmaxvq_u32neon

Horizontal vector max. Arm’s documentation

vmin_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Minimum (vector) Arm’s documentation

vmin_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vmin_f64neon

Minimum (vector) Arm’s documentation

vmin_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vmin_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vmin_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vmin_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vmin_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vmin_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vminnm_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point Minimum Number (vector) Arm’s documentation

vminnm_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point Minimum Number (vector) Arm’s documentation

vminnm_f64neon

Floating-point Minimum Number (vector) Arm’s documentation

vminnmq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point Minimum Number (vector) Arm’s documentation

vminnmq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point Minimum Number (vector) Arm’s documentation

vminnmq_f64neon

Floating-point Minimum Number (vector) Arm’s documentation

vminnmv_f32neon

Floating-point minimum number across vector Arm’s documentation

vminnmvq_f32neon

Floating-point minimum number across vector Arm’s documentation

vminnmvq_f64neon

Floating-point minimum number across vector Arm’s documentation

vminq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Minimum (vector) Arm’s documentation

vminq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vminq_f64neon

Minimum (vector) Arm’s documentation

vminq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vminq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vminq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vminq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vminq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vminq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Minimum (vector) Arm’s documentation

vminv_f32neon

Horizontal vector min. Arm’s documentation

vminv_s8neon

Horizontal vector min. Arm’s documentation

vminv_s16neon

Horizontal vector min. Arm’s documentation

vminv_s32neon

Horizontal vector min. Arm’s documentation

vminv_u8neon

Horizontal vector min. Arm’s documentation

vminv_u16neon

Horizontal vector min. Arm’s documentation

vminv_u32neon

Horizontal vector min. Arm’s documentation

vminvq_f32neon

Horizontal vector min. Arm’s documentation

vminvq_f64neon

Horizontal vector min. Arm’s documentation

vminvq_s8neon

Horizontal vector min. Arm’s documentation

vminvq_s16neon

Horizontal vector min. Arm’s documentation

vminvq_s32neon

Horizontal vector min. Arm’s documentation

vminvq_u8neon

Horizontal vector min. Arm’s documentation

vminvq_u16neon

Horizontal vector min. Arm’s documentation

vminvq_u32neon

Horizontal vector min. Arm’s documentation

vmla_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point multiply-add to accumulator Arm’s documentation

vmla_f64neon

Floating-point multiply-add to accumulator Arm’s documentation

vmla_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_laneq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_laneq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_laneq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmla_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmla_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmla_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmla_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmla_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmla_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmlal_high_lane_s16neon

Multiply-add long Arm’s documentation

vmlal_high_lane_s32neon

Multiply-add long Arm’s documentation

vmlal_high_lane_u16neon

Multiply-add long Arm’s documentation

vmlal_high_lane_u32neon

Multiply-add long Arm’s documentation

vmlal_high_laneq_s16neon

Multiply-add long Arm’s documentation

vmlal_high_laneq_s32neon

Multiply-add long Arm’s documentation

vmlal_high_laneq_u16neon

Multiply-add long Arm’s documentation

vmlal_high_laneq_u32neon

Multiply-add long Arm’s documentation

vmlal_high_n_s16neon

Multiply-add long Arm’s documentation

vmlal_high_n_s32neon

Multiply-add long Arm’s documentation

vmlal_high_n_u16neon

Multiply-add long Arm’s documentation

vmlal_high_n_u32neon

Multiply-add long Arm’s documentation

vmlal_high_s8neon

Signed multiply-add long Arm’s documentation

vmlal_high_s16neon

Signed multiply-add long Arm’s documentation

vmlal_high_s32neon

Signed multiply-add long Arm’s documentation

vmlal_high_u8neon

Unsigned multiply-add long Arm’s documentation

vmlal_high_u16neon

Unsigned multiply-add long Arm’s documentation

vmlal_high_u32neon

Unsigned multiply-add long Arm’s documentation

vmlal_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_laneq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_laneq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply accumulate with scalar Arm’s documentation

vmlal_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed multiply-add long Arm’s documentation

vmlal_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed multiply-add long Arm’s documentation

vmlal_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed multiply-add long Arm’s documentation

vmlal_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned multiply-add long Arm’s documentation

vmlal_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned multiply-add long Arm’s documentation

vmlal_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned multiply-add long Arm’s documentation

vmlaq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point multiply-add to accumulator Arm’s documentation

vmlaq_f64neon

Floating-point multiply-add to accumulator Arm’s documentation

vmlaq_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_laneq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_laneq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_laneq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply accumulate with scalar Arm’s documentation

vmlaq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmlaq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmlaq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmlaq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmlaq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmlaq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-add to accumulator Arm’s documentation

vmls_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point multiply-subtract from accumulator Arm’s documentation

vmls_f64neon

Floating-point multiply-subtract from accumulator Arm’s documentation

vmls_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_laneq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_laneq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_laneq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmls_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmls_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmls_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmls_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmls_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmls_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmlsl_high_lane_s16neon

Multiply-subtract long Arm’s documentation

vmlsl_high_lane_s32neon

Multiply-subtract long Arm’s documentation

vmlsl_high_lane_u16neon

Multiply-subtract long Arm’s documentation

vmlsl_high_lane_u32neon

Multiply-subtract long Arm’s documentation

vmlsl_high_laneq_s16neon

Multiply-subtract long Arm’s documentation

vmlsl_high_laneq_s32neon

Multiply-subtract long Arm’s documentation

vmlsl_high_laneq_u16neon

Multiply-subtract long Arm’s documentation

vmlsl_high_laneq_u32neon

Multiply-subtract long Arm’s documentation

vmlsl_high_n_s16neon

Multiply-subtract long Arm’s documentation

vmlsl_high_n_s32neon

Multiply-subtract long Arm’s documentation

vmlsl_high_n_u16neon

Multiply-subtract long Arm’s documentation

vmlsl_high_n_u32neon

Multiply-subtract long Arm’s documentation

vmlsl_high_s8neon

Signed multiply-subtract long Arm’s documentation

vmlsl_high_s16neon

Signed multiply-subtract long Arm’s documentation

vmlsl_high_s32neon

Signed multiply-subtract long Arm’s documentation

vmlsl_high_u8neon

Unsigned multiply-subtract long Arm’s documentation

vmlsl_high_u16neon

Unsigned multiply-subtract long Arm’s documentation

vmlsl_high_u32neon

Unsigned multiply-subtract long Arm’s documentation

vmlsl_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_laneq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_laneq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening multiply subtract with scalar Arm’s documentation

vmlsl_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed multiply-subtract long Arm’s documentation

vmlsl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed multiply-subtract long Arm’s documentation

vmlsl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed multiply-subtract long Arm’s documentation

vmlsl_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned multiply-subtract long Arm’s documentation

vmlsl_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned multiply-subtract long Arm’s documentation

vmlsl_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned multiply-subtract long Arm’s documentation

vmlsq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point multiply-subtract from accumulator Arm’s documentation

vmlsq_f64neon

Floating-point multiply-subtract from accumulator Arm’s documentation

vmlsq_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_laneq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_laneq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_laneq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply subtract with scalar Arm’s documentation

vmlsq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmlsq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmlsq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmlsq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmlsq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmlsq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply-subtract from accumulator Arm’s documentation

vmov_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmov_n_f64neon

Duplicate vector element to vector or scalar

vmov_n_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmov_n_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmov_n_p64neon

Duplicate vector element to vector or scalar

vmov_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmov_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmov_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmov_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmov_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmov_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmov_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmov_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmovl_high_s8neon

Vector move Arm’s documentation

vmovl_high_s16neon

Vector move Arm’s documentation

vmovl_high_s32neon

Vector move Arm’s documentation

vmovl_high_u8neon

Vector move Arm’s documentation

vmovl_high_u16neon

Vector move Arm’s documentation

vmovl_high_u32neon

Vector move Arm’s documentation

vmovl_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long move. Arm’s documentation

vmovl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long move. Arm’s documentation

vmovl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long move. Arm’s documentation

vmovl_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long move. Arm’s documentation

vmovl_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long move. Arm’s documentation

vmovl_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long move. Arm’s documentation

vmovn_high_s16neon

Extract narrow Arm’s documentation

vmovn_high_s32neon

Extract narrow Arm’s documentation

vmovn_high_s64neon

Extract narrow Arm’s documentation

vmovn_high_u16neon

Extract narrow Arm’s documentation

vmovn_high_u32neon

Extract narrow Arm’s documentation

vmovn_high_u64neon

Extract narrow Arm’s documentation

vmovn_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector narrow integer. Arm’s documentation

vmovn_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector narrow integer. Arm’s documentation

vmovn_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector narrow integer. Arm’s documentation

vmovn_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector narrow integer. Arm’s documentation

vmovn_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector narrow integer. Arm’s documentation

vmovn_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector narrow integer. Arm’s documentation

vmovq_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmovq_n_f64neon

Duplicate vector element to vector or scalar

vmovq_n_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmovq_n_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmovq_n_p64neon

Duplicate vector element to vector or scalar

vmovq_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmovq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmovq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmovq_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmovq_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmovq_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmovq_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmovq_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Duplicate vector element to vector or scalar Arm’s documentation

vmul_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Multiply Arm’s documentation

vmul_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_f64neon

Multiply Arm’s documentation

vmul_lane_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Multiply Arm’s documentation

vmul_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point multiply Arm’s documentation

vmul_lane_f64neon

Floating-point multiply Arm’s documentation

vmul_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_laneq_f16neon and fp16

Floating-point multiply Arm’s documentation

vmul_laneq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point multiply Arm’s documentation

vmul_laneq_f64neon

Floating-point multiply Arm’s documentation

vmul_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_laneq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_laneq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply by scalar Arm’s documentation

vmul_n_f64neon

Vector multiply by scalar Arm’s documentation

vmul_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply by scalar Arm’s documentation

vmul_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply by scalar Arm’s documentation

vmul_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply by scalar Arm’s documentation

vmul_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply by scalar Arm’s documentation

vmul_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Polynomial multiply Arm’s documentation

vmul_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmul_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmuld_lane_f64neon

Floating-point multiply Arm’s documentation

vmuld_laneq_f64neon

Floating-point multiply Arm’s documentation

vmull_high_lane_s16neon

Multiply long Arm’s documentation

vmull_high_lane_s32neon

Multiply long Arm’s documentation

vmull_high_lane_u16neon

Multiply long Arm’s documentation

vmull_high_lane_u32neon

Multiply long Arm’s documentation

vmull_high_laneq_s16neon

Multiply long Arm’s documentation

vmull_high_laneq_s32neon

Multiply long Arm’s documentation

vmull_high_laneq_u16neon

Multiply long Arm’s documentation

vmull_high_laneq_u32neon

Multiply long Arm’s documentation

vmull_high_n_s16neon

Multiply long Arm’s documentation

vmull_high_n_s32neon

Multiply long Arm’s documentation

vmull_high_n_u16neon

Multiply long Arm’s documentation

vmull_high_n_u32neon

Multiply long Arm’s documentation

vmull_high_p8neon

Polynomial multiply long Arm’s documentation

vmull_high_p64neon and aes

Polynomial multiply long Arm’s documentation

vmull_high_s8neon

Signed multiply long Arm’s documentation

vmull_high_s16neon

Signed multiply long Arm’s documentation

vmull_high_s32neon

Signed multiply long Arm’s documentation

vmull_high_u8neon

Unsigned multiply long Arm’s documentation

vmull_high_u16neon

Unsigned multiply long Arm’s documentation

vmull_high_u32neon

Unsigned multiply long Arm’s documentation

vmull_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply by scalar Arm’s documentation

vmull_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply by scalar Arm’s documentation

vmull_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply by scalar Arm’s documentation

vmull_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply by scalar Arm’s documentation

vmull_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply by scalar Arm’s documentation

vmull_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply by scalar Arm’s documentation

vmull_laneq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply by scalar Arm’s documentation

vmull_laneq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply by scalar Arm’s documentation

vmull_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply with scalar Arm’s documentation

vmull_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply with scalar Arm’s documentation

vmull_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply with scalar Arm’s documentation

vmull_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector long multiply with scalar Arm’s documentation

vmull_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Polynomial multiply long Arm’s documentation

vmull_p64neon and aes

Polynomial multiply long Arm’s documentation

vmull_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed multiply long Arm’s documentation

vmull_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed multiply long Arm’s documentation

vmull_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed multiply long Arm’s documentation

vmull_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned multiply long Arm’s documentation

vmull_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned multiply long Arm’s documentation

vmull_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned multiply long Arm’s documentation

vmulq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Multiply Arm’s documentation

vmulq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_f64neon

Multiply Arm’s documentation

vmulq_lane_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Multiply Arm’s documentation

vmulq_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point multiply Arm’s documentation

vmulq_lane_f64neon

Floating-point multiply Arm’s documentation

vmulq_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_laneq_f16neon and fp16

Floating-point multiply Arm’s documentation

vmulq_laneq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point multiply Arm’s documentation

vmulq_laneq_f64neon

Floating-point multiply Arm’s documentation

vmulq_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_laneq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_laneq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_n_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply by scalar Arm’s documentation

vmulq_n_f64neon

Vector multiply by scalar Arm’s documentation

vmulq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply by scalar Arm’s documentation

vmulq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply by scalar Arm’s documentation

vmulq_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply by scalar Arm’s documentation

vmulq_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector multiply by scalar Arm’s documentation

vmulq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Polynomial multiply Arm’s documentation

vmulq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmulq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Multiply Arm’s documentation

vmuls_lane_f32neon

Floating-point multiply Arm’s documentation

vmuls_laneq_f32neon

Floating-point multiply Arm’s documentation

vmulx_f16neon and fp16

Floating-point multiply extended Arm’s documentation

vmulx_f32neon

Floating-point multiply extended Arm’s documentation

vmulx_f64neon

Floating-point multiply extended Arm’s documentation

vmulx_lane_f16neon and fp16

Floating-point multiply extended Arm’s documentation

vmulx_lane_f32neon

Floating-point multiply extended Arm’s documentation

vmulx_lane_f64neon

Floating-point multiply extended Arm’s documentation

vmulx_laneq_f16neon and fp16

Floating-point multiply extended Arm’s documentation

vmulx_laneq_f32neon

Floating-point multiply extended Arm’s documentation

vmulx_laneq_f64neon

Floating-point multiply extended Arm’s documentation

vmulxd_f64neon

Floating-point multiply extended Arm’s documentation

vmulxd_lane_f64neon

Floating-point multiply extended Arm’s documentation

vmulxd_laneq_f64neon

Floating-point multiply extended Arm’s documentation

vmulxq_f16neon and fp16

Floating-point multiply extended Arm’s documentation

vmulxq_f32neon

Floating-point multiply extended Arm’s documentation

vmulxq_f64neon

Floating-point multiply extended Arm’s documentation

vmulxq_lane_f16neon and fp16

Floating-point multiply extended Arm’s documentation

vmulxq_lane_f32neon

Floating-point multiply extended Arm’s documentation

vmulxq_lane_f64neon

Floating-point multiply extended Arm’s documentation

vmulxq_laneq_f16neon and fp16

Floating-point multiply extended Arm’s documentation

vmulxq_laneq_f32neon

Floating-point multiply extended Arm’s documentation

vmulxq_laneq_f64neon

Floating-point multiply extended Arm’s documentation

vmulxs_f32neon

Floating-point multiply extended Arm’s documentation

vmulxs_lane_f32neon

Floating-point multiply extended Arm’s documentation

vmulxs_laneq_f32neon

Floating-point multiply extended Arm’s documentation

vmvn_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvn_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvn_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvn_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvn_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvn_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvn_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvnq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvnq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvnq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvnq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvnq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvnq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vmvnq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise not. Arm’s documentation

vneg_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Negate Arm’s documentation

vneg_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Negate Arm’s documentation

vneg_f64neon

Negate Arm’s documentation

vneg_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Negate Arm’s documentation

vneg_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Negate Arm’s documentation

vneg_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Negate Arm’s documentation

vneg_s64neon

Negate Arm’s documentation

vnegd_s64neon

Negate Arm’s documentation

vnegq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Negate Arm’s documentation

vnegq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Negate Arm’s documentation

vnegq_f64neon

Negate Arm’s documentation

vnegq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Negate Arm’s documentation

vnegq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Negate Arm’s documentation

vnegq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Negate Arm’s documentation

vnegq_s64neon

Negate Arm’s documentation

vorn_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vorn_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vorn_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vorn_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vorn_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vorn_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vorn_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vorn_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vornq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vornq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vornq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vornq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vornq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vornq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vornq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vornq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise inclusive OR NOT Arm’s documentation

vorr_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorr_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorr_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorr_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorr_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorr_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorr_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorr_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorrq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorrq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorrq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorrq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorrq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorrq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorrq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vorrq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector bitwise or (immediate, inclusive) Arm’s documentation

vpadal_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpadal_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpadal_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpadal_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpadal_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpadal_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpadalq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpadalq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpadalq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpadalq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpadalq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpadalq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpadd_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point add pairwise Arm’s documentation

vpadd_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point add pairwise Arm’s documentation

vpadd_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add pairwise. Arm’s documentation

vpadd_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add pairwise. Arm’s documentation

vpadd_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Add pairwise. Arm’s documentation

vpadd_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Add pairwise. Arm’s documentation

vpadd_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Add pairwise. Arm’s documentation

vpadd_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Add pairwise. Arm’s documentation

vpaddd_f64neon

Floating-point add pairwise Arm’s documentation

vpaddd_s64neon

Add pairwise Arm’s documentation

vpaddd_u64neon

Add pairwise Arm’s documentation

vpaddl_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpaddl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpaddl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpaddl_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpaddl_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpaddl_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpaddlq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpaddlq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpaddlq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Add and Accumulate Long Pairwise. Arm’s documentation

vpaddlq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpaddlq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpaddlq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Add and Accumulate Long Pairwise. Arm’s documentation

vpaddq_f16neon and fp16

Floating-point add pairwise Arm’s documentation

vpaddq_f32neon

Floating-point add pairwise Arm’s documentation

vpaddq_f64neon

Floating-point add pairwise Arm’s documentation

vpaddq_s8neon

Add Pairwise Arm’s documentation

vpaddq_s16neon

Add Pairwise Arm’s documentation

vpaddq_s32neon

Add Pairwise Arm’s documentation

vpaddq_s64neon

Add Pairwise Arm’s documentation

vpaddq_u8neon

Add Pairwise Arm’s documentation

vpaddq_u16neon

Add Pairwise Arm’s documentation

vpaddq_u32neon

Add Pairwise Arm’s documentation

vpaddq_u64neon

Add Pairwise Arm’s documentation

vpadds_f32neon

Floating-point add pairwise Arm’s documentation

vpmax_f16neon and fp16

Floating-point add pairwise Arm’s documentation

vpmax_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding maximum of adjacent pairs Arm’s documentation

vpmax_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding maximum of adjacent pairs Arm’s documentation

vpmax_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding maximum of adjacent pairs Arm’s documentation

vpmax_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding maximum of adjacent pairs Arm’s documentation

vpmax_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding maximum of adjacent pairs Arm’s documentation

vpmax_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding maximum of adjacent pairs Arm’s documentation

vpmax_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding maximum of adjacent pairs Arm’s documentation

vpmaxnm_f16neon and fp16

Floating-point add pairwise Arm’s documentation

vpmaxnm_f32neon

Floating-point Maximum Number Pairwise (vector). Arm’s documentation

vpmaxnmq_f16neon and fp16

Floating-point add pairwise Arm’s documentation

vpmaxnmq_f32neon

Floating-point Maximum Number Pairwise (vector). Arm’s documentation

vpmaxnmq_f64neon

Floating-point Maximum Number Pairwise (vector). Arm’s documentation

vpmaxnmqd_f64neon

Floating-point maximum number pairwise Arm’s documentation

vpmaxnms_f32neon

Floating-point maximum number pairwise Arm’s documentation

vpmaxq_f16neon and fp16

Floating-point add pairwise Arm’s documentation

vpmaxq_f32neon

Folding maximum of adjacent pairs Arm’s documentation

vpmaxq_f64neon

Folding maximum of adjacent pairs Arm’s documentation

vpmaxq_s8neon

Folding maximum of adjacent pairs Arm’s documentation

vpmaxq_s16neon

Folding maximum of adjacent pairs Arm’s documentation

vpmaxq_s32neon

Folding maximum of adjacent pairs Arm’s documentation

vpmaxq_u8neon

Folding maximum of adjacent pairs Arm’s documentation

vpmaxq_u16neon

Folding maximum of adjacent pairs Arm’s documentation

vpmaxq_u32neon

Folding maximum of adjacent pairs Arm’s documentation

vpmaxqd_f64neon

Floating-point maximum pairwise Arm’s documentation

vpmaxs_f32neon

Floating-point maximum pairwise Arm’s documentation

vpmin_f16neon and fp16

Floating-point add pairwise Arm’s documentation

vpmin_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding minimum of adjacent pairs Arm’s documentation

vpmin_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding minimum of adjacent pairs Arm’s documentation

vpmin_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding minimum of adjacent pairs Arm’s documentation

vpmin_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding minimum of adjacent pairs Arm’s documentation

vpmin_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding minimum of adjacent pairs Arm’s documentation

vpmin_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding minimum of adjacent pairs Arm’s documentation

vpmin_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Folding minimum of adjacent pairs Arm’s documentation

vpminnm_f16neon and fp16

Floating-point add pairwise Arm’s documentation

vpminnm_f32neon

Floating-point Minimum Number Pairwise (vector). Arm’s documentation

vpminnmq_f16neon and fp16

Floating-point add pairwise Arm’s documentation

vpminnmq_f32neon

Floating-point Minimum Number Pairwise (vector). Arm’s documentation

vpminnmq_f64neon

Floating-point Minimum Number Pairwise (vector). Arm’s documentation

vpminnmqd_f64neon

Floating-point minimum number pairwise Arm’s documentation

vpminnms_f32neon

Floating-point minimum number pairwise Arm’s documentation

vpminq_f16neon and fp16

Floating-point add pairwise Arm’s documentation

vpminq_f32neon

Folding minimum of adjacent pairs Arm’s documentation

vpminq_f64neon

Folding minimum of adjacent pairs Arm’s documentation

vpminq_s8neon

Folding minimum of adjacent pairs Arm’s documentation

vpminq_s16neon

Folding minimum of adjacent pairs Arm’s documentation

vpminq_s32neon

Folding minimum of adjacent pairs Arm’s documentation

vpminq_u8neon

Folding minimum of adjacent pairs Arm’s documentation

vpminq_u16neon

Folding minimum of adjacent pairs Arm’s documentation

vpminq_u32neon

Folding minimum of adjacent pairs Arm’s documentation

vpminqd_f64neon

Floating-point minimum pairwise Arm’s documentation

vpmins_f32neon

Floating-point minimum pairwise Arm’s documentation

vqabs_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating Absolute value Arm’s documentation

vqabs_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating Absolute value Arm’s documentation

vqabs_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating Absolute value Arm’s documentation

vqabs_s64neon

Signed saturating Absolute value Arm’s documentation

vqabsb_s8neon

Signed saturating absolute value Arm’s documentation

vqabsd_s64neon

Signed saturating absolute value Arm’s documentation

vqabsh_s16neon

Signed saturating absolute value Arm’s documentation

vqabsq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating Absolute value Arm’s documentation

vqabsq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating Absolute value Arm’s documentation

vqabsq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating Absolute value Arm’s documentation

vqabsq_s64neon

Signed saturating Absolute value Arm’s documentation

vqabss_s32neon

Signed saturating absolute value Arm’s documentation

vqadd_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqadd_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqadd_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqadd_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqadd_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqadd_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqadd_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqadd_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqaddb_s8neon

Saturating add Arm’s documentation

vqaddb_u8neon

Saturating add Arm’s documentation

vqaddd_s64neon

Saturating add Arm’s documentation

vqaddd_u64neon

Saturating add Arm’s documentation

vqaddh_s16neon

Saturating add Arm’s documentation

vqaddh_u16neon

Saturating add Arm’s documentation

vqaddq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqaddq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqaddq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqaddq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqaddq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqaddq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqaddq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqaddq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating add Arm’s documentation

vqadds_s32neon

Saturating add Arm’s documentation

vqadds_u32neon

Saturating add Arm’s documentation

vqdmlal_high_lane_s16neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlal_high_lane_s32neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlal_high_laneq_s16neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlal_high_laneq_s32neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlal_high_n_s16neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlal_high_n_s32neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlal_high_s16neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlal_high_s32neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlal_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation

vqdmlal_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation

vqdmlal_laneq_s16neon

Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation

vqdmlal_laneq_s32neon

Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation

vqdmlal_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation

vqdmlal_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation

vqdmlal_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlal_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlalh_lane_s16neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlalh_laneq_s16neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlalh_s16neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlals_lane_s32neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlals_laneq_s32neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlals_s32neon

Signed saturating doubling multiply-add long Arm’s documentation

vqdmlsl_high_lane_s16neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsl_high_lane_s32neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsl_high_laneq_s16neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsl_high_laneq_s32neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsl_high_n_s16neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsl_high_n_s32neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsl_high_s16neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsl_high_s32neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsl_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening saturating doubling multiply subtract with scalar Arm’s documentation

vqdmlsl_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening saturating doubling multiply subtract with scalar Arm’s documentation

vqdmlsl_laneq_s16neon

Vector widening saturating doubling multiply subtract with scalar Arm’s documentation

vqdmlsl_laneq_s32neon

Vector widening saturating doubling multiply subtract with scalar Arm’s documentation

vqdmlsl_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening saturating doubling multiply subtract with scalar Arm’s documentation

vqdmlsl_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector widening saturating doubling multiply subtract with scalar Arm’s documentation

vqdmlsl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlslh_lane_s16neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlslh_laneq_s16neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlslh_s16neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsls_lane_s32neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsls_laneq_s32neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmlsls_s32neon

Signed saturating doubling multiply-subtract long Arm’s documentation

vqdmulh_lane_s16neon

Vector saturating doubling multiply high by scalar Arm’s documentation

vqdmulh_lane_s32neon

Vector saturating doubling multiply high by scalar Arm’s documentation

vqdmulh_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling multiply high by scalar Arm’s documentation

vqdmulh_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling multiply high by scalar Arm’s documentation

vqdmulh_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling multiply high with scalar Arm’s documentation

vqdmulh_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling multiply high with scalar Arm’s documentation

vqdmulh_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating doubling multiply returning high half Arm’s documentation

vqdmulh_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating doubling multiply returning high half Arm’s documentation

vqdmulhh_lane_s16neon

Signed saturating doubling multiply returning high half Arm’s documentation

vqdmulhh_laneq_s16neon

Signed saturating doubling multiply returning high half Arm’s documentation

vqdmulhh_s16neon

Signed saturating doubling multiply returning high half Arm’s documentation

vqdmulhq_lane_s16neon

Vector saturating doubling multiply high by scalar Arm’s documentation

vqdmulhq_lane_s32neon

Vector saturating doubling multiply high by scalar Arm’s documentation

vqdmulhq_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling multiply high by scalar Arm’s documentation

vqdmulhq_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling multiply high by scalar Arm’s documentation

vqdmulhq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling multiply high with scalar Arm’s documentation

vqdmulhq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling multiply high with scalar Arm’s documentation

vqdmulhq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating doubling multiply returning high half Arm’s documentation

vqdmulhq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating doubling multiply returning high half Arm’s documentation

vqdmulhs_lane_s32neon

Signed saturating doubling multiply returning high half Arm’s documentation

vqdmulhs_laneq_s32neon

Signed saturating doubling multiply returning high half Arm’s documentation

vqdmulhs_s32neon

Signed saturating doubling multiply returning high half Arm’s documentation

vqdmull_high_lane_s16neon

Signed saturating doubling multiply long Arm’s documentation

vqdmull_high_lane_s32neon

Signed saturating doubling multiply long Arm’s documentation

vqdmull_high_laneq_s16neon

Signed saturating doubling multiply long Arm’s documentation

vqdmull_high_laneq_s32neon

Signed saturating doubling multiply long Arm’s documentation

vqdmull_high_n_s16neon

Signed saturating doubling multiply long Arm’s documentation

vqdmull_high_n_s32neon

Signed saturating doubling multiply long Arm’s documentation

vqdmull_high_s16neon

Signed saturating doubling multiply long Arm’s documentation

vqdmull_high_s32neon

Signed saturating doubling multiply long Arm’s documentation

vqdmull_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling long multiply by scalar Arm’s documentation

vqdmull_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling long multiply by scalar Arm’s documentation

vqdmull_laneq_s16neon

Vector saturating doubling long multiply by scalar Arm’s documentation

vqdmull_laneq_s32neon

Vector saturating doubling long multiply by scalar Arm’s documentation

vqdmull_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling long multiply with scalar Arm’s documentation

vqdmull_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating doubling long multiply with scalar Arm’s documentation

vqdmull_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating doubling multiply long Arm’s documentation

vqdmull_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating doubling multiply long Arm’s documentation

vqdmullh_lane_s16neon

Signed saturating doubling multiply long Arm’s documentation

vqdmullh_laneq_s16neon

Signed saturating doubling multiply long Arm’s documentation

vqdmullh_s16neon

Signed saturating doubling multiply long Arm’s documentation

vqdmulls_lane_s32neon

Signed saturating doubling multiply long Arm’s documentation

vqdmulls_laneq_s32neon

Signed saturating doubling multiply long Arm’s documentation

vqdmulls_s32neon

Signed saturating doubling multiply long Arm’s documentation

vqmovn_high_s16neon

Signed saturating extract narrow Arm’s documentation

vqmovn_high_s32neon

Signed saturating extract narrow Arm’s documentation

vqmovn_high_s64neon

Signed saturating extract narrow Arm’s documentation

vqmovn_high_u16neon

Signed saturating extract narrow Arm’s documentation

vqmovn_high_u32neon

Signed saturating extract narrow Arm’s documentation

vqmovn_high_u64neon

Signed saturating extract narrow Arm’s documentation

vqmovn_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating extract narrow Arm’s documentation

vqmovn_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating extract narrow Arm’s documentation

vqmovn_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating extract narrow Arm’s documentation

vqmovn_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating extract narrow Arm’s documentation

vqmovn_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating extract narrow Arm’s documentation

vqmovn_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating extract narrow Arm’s documentation

vqmovnd_s64neon

Saturating extract narrow Arm’s documentation

vqmovnd_u64neon

Saturating extract narrow Arm’s documentation

vqmovnh_s16neon

Saturating extract narrow Arm’s documentation

vqmovnh_u16neon

Saturating extract narrow Arm’s documentation

vqmovns_s32neon

Saturating extract narrow Arm’s documentation

vqmovns_u32neon

Saturating extract narrow Arm’s documentation

vqmovun_high_s16neon

Signed saturating extract unsigned narrow Arm’s documentation

vqmovun_high_s32neon

Signed saturating extract unsigned narrow Arm’s documentation

vqmovun_high_s64neon

Signed saturating extract unsigned narrow Arm’s documentation

vqmovun_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating extract unsigned narrow Arm’s documentation

vqmovun_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating extract unsigned narrow Arm’s documentation

vqmovun_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating extract unsigned narrow Arm’s documentation

vqmovund_s64neon

Signed saturating extract unsigned narrow Arm’s documentation

vqmovunh_s16neon

Signed saturating extract unsigned narrow Arm’s documentation

vqmovuns_s32neon

Signed saturating extract unsigned narrow Arm’s documentation

vqneg_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating negate Arm’s documentation

vqneg_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating negate Arm’s documentation

vqneg_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating negate Arm’s documentation

vqneg_s64neon

Signed saturating negate Arm’s documentation

vqnegb_s8neon

Signed saturating negate Arm’s documentation

vqnegd_s64neon

Signed saturating negate Arm’s documentation

vqnegh_s16neon

Signed saturating negate Arm’s documentation

vqnegq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating negate Arm’s documentation

vqnegq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating negate Arm’s documentation

vqnegq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating negate Arm’s documentation

vqnegq_s64neon

Signed saturating negate Arm’s documentation

vqnegs_s32neon

Signed saturating negate Arm’s documentation

vqrdmlah_lane_s16rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlah_lane_s32rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlah_laneq_s16rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlah_laneq_s32rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlah_s16rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlah_s32rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahh_lane_s16rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahh_laneq_s16rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahh_s16rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahq_lane_s16rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahq_lane_s32rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahq_laneq_s16rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahq_laneq_s32rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahq_s16rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahq_s32rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahs_lane_s32rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahs_laneq_s32rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlahs_s32rdm

Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation

vqrdmlsh_lane_s16rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlsh_lane_s32rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlsh_laneq_s16rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlsh_laneq_s32rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlsh_s16rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlsh_s32rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshh_lane_s16rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshh_laneq_s16rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshh_s16rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshq_lane_s16rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshq_lane_s32rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshq_laneq_s16rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshq_laneq_s32rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshq_s16rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshq_s32rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshs_lane_s32rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshs_laneq_s32rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmlshs_s32rdm

Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation

vqrdmulh_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector rounding saturating doubling multiply high by scalar Arm’s documentation

vqrdmulh_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector rounding saturating doubling multiply high by scalar Arm’s documentation

vqrdmulh_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector rounding saturating doubling multiply high by scalar Arm’s documentation

vqrdmulh_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector rounding saturating doubling multiply high by scalar Arm’s documentation

vqrdmulh_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating rounding doubling multiply high with scalar Arm’s documentation

vqrdmulh_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating rounding doubling multiply high with scalar Arm’s documentation

vqrdmulh_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding doubling multiply returning high half Arm’s documentation

vqrdmulh_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding doubling multiply returning high half Arm’s documentation

vqrdmulhh_lane_s16neon

Signed saturating rounding doubling multiply returning high half Arm’s documentation

vqrdmulhh_laneq_s16neon

Signed saturating rounding doubling multiply returning high half Arm’s documentation

vqrdmulhh_s16neon

Signed saturating rounding doubling multiply returning high half Arm’s documentation

vqrdmulhq_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector rounding saturating doubling multiply high by scalar Arm’s documentation

vqrdmulhq_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector rounding saturating doubling multiply high by scalar Arm’s documentation

vqrdmulhq_laneq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector rounding saturating doubling multiply high by scalar Arm’s documentation

vqrdmulhq_laneq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector rounding saturating doubling multiply high by scalar Arm’s documentation

vqrdmulhq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating rounding doubling multiply high with scalar Arm’s documentation

vqrdmulhq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector saturating rounding doubling multiply high with scalar Arm’s documentation

vqrdmulhq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding doubling multiply returning high half Arm’s documentation

vqrdmulhq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding doubling multiply returning high half Arm’s documentation

vqrdmulhs_lane_s32neon

Signed saturating rounding doubling multiply returning high half Arm’s documentation

vqrdmulhs_laneq_s32neon

Signed saturating rounding doubling multiply returning high half Arm’s documentation

vqrdmulhs_s32neon

Signed saturating rounding doubling multiply returning high half Arm’s documentation

vqrshl_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding shift left Arm’s documentation

vqrshl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding shift left Arm’s documentation

vqrshl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding shift left Arm’s documentation

vqrshl_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding shift left Arm’s documentation

vqrshl_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshl_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshl_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshl_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshlb_s8neon

Signed saturating rounding shift left Arm’s documentation

vqrshlb_u8neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshld_s64neon

Signed saturating rounding shift left Arm’s documentation

vqrshld_u64neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshlh_s16neon

Signed saturating rounding shift left Arm’s documentation

vqrshlh_u16neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshlq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding shift left Arm’s documentation

vqrshlq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding shift left Arm’s documentation

vqrshlq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding shift left Arm’s documentation

vqrshlq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating rounding shift left Arm’s documentation

vqrshlq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshlq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshlq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshlq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshls_s32neon

Signed saturating rounding shift left Arm’s documentation

vqrshls_u32neon

Unsigned signed saturating rounding shift left Arm’s documentation

vqrshrn_high_n_s16neon

Signed saturating rounded shift right narrow Arm’s documentation

vqrshrn_high_n_s32neon

Signed saturating rounded shift right narrow Arm’s documentation

vqrshrn_high_n_s64neon

Signed saturating rounded shift right narrow Arm’s documentation

vqrshrn_high_n_u16neon

Unsigned saturating rounded shift right narrow Arm’s documentation

vqrshrn_high_n_u32neon

Unsigned saturating rounded shift right narrow Arm’s documentation

vqrshrn_high_n_u64neon

Unsigned saturating rounded shift right narrow Arm’s documentation

vqrshrn_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating rounded shift right narrow Arm’s documentation

vqrshrn_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating rounded shift right narrow Arm’s documentation

vqrshrn_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating rounded shift right narrow Arm’s documentation

vqrshrn_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Unsigned signed saturating rounded shift right narrow Arm’s documentation

vqrshrn_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Unsigned signed saturating rounded shift right narrow Arm’s documentation

vqrshrn_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Unsigned signed saturating rounded shift right narrow Arm’s documentation

vqrshrnd_n_s64neon

Signed saturating rounded shift right narrow Arm’s documentation

vqrshrnd_n_u64neon

Unsigned saturating rounded shift right narrow Arm’s documentation

vqrshrnh_n_s16neon

Signed saturating rounded shift right narrow Arm’s documentation

vqrshrnh_n_u16neon

Unsigned saturating rounded shift right narrow Arm’s documentation

vqrshrns_n_s32neon

Signed saturating rounded shift right narrow Arm’s documentation

vqrshrns_n_u32neon

Unsigned saturating rounded shift right narrow Arm’s documentation

vqrshrun_high_n_s16neon

Signed saturating rounded shift right unsigned narrow Arm’s documentation

vqrshrun_high_n_s32neon

Signed saturating rounded shift right unsigned narrow Arm’s documentation

vqrshrun_high_n_s64neon

Signed saturating rounded shift right unsigned narrow Arm’s documentation

vqrshrun_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating rounded shift right unsigned narrow Arm’s documentation

vqrshrun_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating rounded shift right unsigned narrow Arm’s documentation

vqrshrun_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating rounded shift right unsigned narrow Arm’s documentation

vqrshrund_n_s64neon

Signed saturating rounded shift right unsigned narrow Arm’s documentation

vqrshrunh_n_s16neon

Signed saturating rounded shift right unsigned narrow Arm’s documentation

vqrshruns_n_s32neon

Signed saturating rounded shift right unsigned narrow Arm’s documentation

vqshl_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshl_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshl_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshl_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshl_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshl_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshl_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshl_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshl_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshl_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshl_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshl_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshl_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshl_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshlb_n_s8neon

Signed saturating shift left Arm’s documentation

vqshlb_n_u8neon

Unsigned saturating shift left Arm’s documentation

vqshlb_s8neon

Signed saturating shift left Arm’s documentation

vqshlb_u8neon

Unsigned saturating shift left Arm’s documentation

vqshld_n_s64neon

Signed saturating shift left Arm’s documentation

vqshld_n_u64neon

Unsigned saturating shift left Arm’s documentation

vqshld_s64neon

Signed saturating shift left Arm’s documentation

vqshld_u64neon

Unsigned saturating shift left Arm’s documentation

vqshlh_n_s16neon

Signed saturating shift left Arm’s documentation

vqshlh_n_u16neon

Unsigned saturating shift left Arm’s documentation

vqshlh_s16neon

Signed saturating shift left Arm’s documentation

vqshlh_u16neon

Unsigned saturating shift left Arm’s documentation

vqshlq_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshlq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshlq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshlq_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshlq_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshlq_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshlq_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshlq_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshlq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshlq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshlq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshlq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed saturating shift left Arm’s documentation

vqshlq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshlq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshlq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshlq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned saturating shift left Arm’s documentation

vqshls_n_s32neon

Signed saturating shift left Arm’s documentation

vqshls_n_u32neon

Unsigned saturating shift left Arm’s documentation

vqshls_s32neon

Signed saturating shift left Arm’s documentation

vqshls_u32neon

Unsigned saturating shift left Arm’s documentation

vqshlu_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift left unsigned Arm’s documentation

vqshlu_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift left unsigned Arm’s documentation

vqshlu_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift left unsigned Arm’s documentation

vqshlu_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift left unsigned Arm’s documentation

vqshlub_n_s8neon

Signed saturating shift left unsigned Arm’s documentation

vqshlud_n_s64neon

Signed saturating shift left unsigned Arm’s documentation

vqshluh_n_s16neon

Signed saturating shift left unsigned Arm’s documentation

vqshluq_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift left unsigned Arm’s documentation

vqshluq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift left unsigned Arm’s documentation

vqshluq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift left unsigned Arm’s documentation

vqshluq_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift left unsigned Arm’s documentation

vqshlus_n_s32neon

Signed saturating shift left unsigned Arm’s documentation

vqshrn_high_n_s16neon

Signed saturating shift right narrow Arm’s documentation

vqshrn_high_n_s32neon

Signed saturating shift right narrow Arm’s documentation

vqshrn_high_n_s64neon

Signed saturating shift right narrow Arm’s documentation

vqshrn_high_n_u16neon

Unsigned saturating shift right narrow Arm’s documentation

vqshrn_high_n_u32neon

Unsigned saturating shift right narrow Arm’s documentation

vqshrn_high_n_u64neon

Unsigned saturating shift right narrow Arm’s documentation

vqshrn_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift right narrow Arm’s documentation

vqshrn_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift right narrow Arm’s documentation

vqshrn_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift right narrow Arm’s documentation

vqshrn_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Unsigned saturating shift right narrow Arm’s documentation

vqshrn_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Unsigned saturating shift right narrow Arm’s documentation

vqshrn_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Unsigned saturating shift right narrow Arm’s documentation

vqshrnd_n_s64neon

Signed saturating shift right narrow Arm’s documentation

vqshrnd_n_u64neon

Unsigned saturating shift right narrow Arm’s documentation

vqshrnh_n_s16neon

Signed saturating shift right narrow Arm’s documentation

vqshrnh_n_u16neon

Unsigned saturating shift right narrow Arm’s documentation

vqshrns_n_s32neon

Signed saturating shift right narrow Arm’s documentation

vqshrns_n_u32neon

Unsigned saturating shift right narrow Arm’s documentation

vqshrun_high_n_s16neon

Signed saturating shift right unsigned narrow Arm’s documentation

vqshrun_high_n_s32neon

Signed saturating shift right unsigned narrow Arm’s documentation

vqshrun_high_n_s64neon

Signed saturating shift right unsigned narrow Arm’s documentation

vqshrun_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift right unsigned narrow Arm’s documentation

vqshrun_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift right unsigned narrow Arm’s documentation

vqshrun_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Signed saturating shift right unsigned narrow Arm’s documentation

vqshrund_n_s64neon

Signed saturating shift right unsigned narrow Arm’s documentation

vqshrunh_n_s16neon

Signed saturating shift right unsigned narrow Arm’s documentation

vqshruns_n_s32neon

Signed saturating shift right unsigned narrow Arm’s documentation

vqsub_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsub_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsub_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsub_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsub_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsub_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsub_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsub_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsubb_s8neon

Saturating subtract Arm’s documentation

vqsubb_u8neon

Saturating subtract Arm’s documentation

vqsubd_s64neon

Saturating subtract Arm’s documentation

vqsubd_u64neon

Saturating subtract Arm’s documentation

vqsubh_s16neon

Saturating subtract Arm’s documentation

vqsubh_u16neon

Saturating subtract Arm’s documentation

vqsubq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsubq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsubq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsubq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsubq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsubq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsubq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsubq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Saturating subtract Arm’s documentation

vqsubs_s32neon

Saturating subtract Arm’s documentation

vqsubs_u32neon

Saturating subtract Arm’s documentation

vqtbl1_p8neon

Table look-up Arm’s documentation

vqtbl1_s8neon

Table look-up Arm’s documentation

vqtbl1_u8neon

Table look-up Arm’s documentation

vqtbl1q_p8neon

Table look-up Arm’s documentation

vqtbl1q_s8neon

Table look-up Arm’s documentation

vqtbl1q_u8neon

Table look-up Arm’s documentation

vqtbl2_p8neon

Table look-up Arm’s documentation

vqtbl2_s8neon

Table look-up Arm’s documentation

vqtbl2_u8neon

Table look-up Arm’s documentation

vqtbl2q_p8neon

Table look-up Arm’s documentation

vqtbl2q_s8neon

Table look-up Arm’s documentation

vqtbl2q_u8neon

Table look-up Arm’s documentation

vqtbl3_p8neon

Table look-up Arm’s documentation

vqtbl3_s8neon

Table look-up Arm’s documentation

vqtbl3_u8neon

Table look-up Arm’s documentation

vqtbl3q_p8neon

Table look-up Arm’s documentation

vqtbl3q_s8neon

Table look-up Arm’s documentation

vqtbl3q_u8neon

Table look-up Arm’s documentation

vqtbl4_p8neon

Table look-up Arm’s documentation

vqtbl4_s8neon

Table look-up Arm’s documentation

vqtbl4_u8neon

Table look-up Arm’s documentation

vqtbl4q_p8neon

Table look-up Arm’s documentation

vqtbl4q_s8neon

Table look-up Arm’s documentation

vqtbl4q_u8neon

Table look-up Arm’s documentation

vqtbx1_p8neon

Extended table look-up Arm’s documentation

vqtbx1_s8neon

Extended table look-up Arm’s documentation

vqtbx1_u8neon

Extended table look-up Arm’s documentation

vqtbx1q_p8neon

Extended table look-up Arm’s documentation

vqtbx1q_s8neon

Extended table look-up Arm’s documentation

vqtbx1q_u8neon

Extended table look-up Arm’s documentation

vqtbx2_p8neon

Extended table look-up Arm’s documentation

vqtbx2_s8neon

Extended table look-up Arm’s documentation

vqtbx2_u8neon

Extended table look-up Arm’s documentation

vqtbx2q_p8neon

Extended table look-up Arm’s documentation

vqtbx2q_s8neon

Extended table look-up Arm’s documentation

vqtbx2q_u8neon

Extended table look-up Arm’s documentation

vqtbx3_p8neon

Extended table look-up Arm’s documentation

vqtbx3_s8neon

Extended table look-up Arm’s documentation

vqtbx3_u8neon

Extended table look-up Arm’s documentation

vqtbx3q_p8neon

Extended table look-up Arm’s documentation

vqtbx3q_s8neon

Extended table look-up Arm’s documentation

vqtbx3q_u8neon

Extended table look-up Arm’s documentation

vqtbx4_p8neon

Extended table look-up Arm’s documentation

vqtbx4_s8neon

Extended table look-up Arm’s documentation

vqtbx4_u8neon

Extended table look-up Arm’s documentation

vqtbx4q_p8neon

Extended table look-up Arm’s documentation

vqtbx4q_s8neon

Extended table look-up Arm’s documentation

vqtbx4q_u8neon

Extended table look-up Arm’s documentation

vraddhn_high_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding Add returning High Narrow (high half). Arm’s documentation

vraddhn_high_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding Add returning High Narrow (high half). Arm’s documentation

vraddhn_high_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding Add returning High Narrow (high half). Arm’s documentation

vraddhn_high_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding Add returning High Narrow (high half). Arm’s documentation

vraddhn_high_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding Add returning High Narrow (high half). Arm’s documentation

vraddhn_high_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding Add returning High Narrow (high half). Arm’s documentation

vraddhn_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding Add returning High Narrow. Arm’s documentation

vraddhn_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding Add returning High Narrow. Arm’s documentation

vraddhn_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding Add returning High Narrow. Arm’s documentation

vraddhn_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Rounding Add returning High Narrow. Arm’s documentation

vraddhn_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Rounding Add returning High Narrow. Arm’s documentation

vraddhn_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Rounding Add returning High Narrow. Arm’s documentation

vrax1q_u64neon and sha3

Rotate and exclusive OR Arm’s documentation

vrbit_p8neon

Reverse bit order Arm’s documentation

vrbit_s8neon

Reverse bit order Arm’s documentation

vrbit_u8neon

Reverse bit order Arm’s documentation

vrbitq_p8neon

Reverse bit order Arm’s documentation

vrbitq_s8neon

Reverse bit order Arm’s documentation

vrbitq_u8neon

Reverse bit order Arm’s documentation

vrecpe_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Reciprocal estimate. Arm’s documentation

vrecpe_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reciprocal estimate. Arm’s documentation

vrecpe_f64neon

Reciprocal estimate. Arm’s documentation

vrecpe_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned reciprocal estimate Arm’s documentation

vrecped_f64neon

Reciprocal estimate. Arm’s documentation

vrecpeq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Reciprocal estimate. Arm’s documentation

vrecpeq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reciprocal estimate. Arm’s documentation

vrecpeq_f64neon

Reciprocal estimate. Arm’s documentation

vrecpeq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned reciprocal estimate Arm’s documentation

vrecpes_f32neon

Reciprocal estimate. Arm’s documentation

vrecps_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point reciprocal step Arm’s documentation

vrecps_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point reciprocal step Arm’s documentation

vrecps_f64neon

Floating-point reciprocal step Arm’s documentation

vrecpsd_f64neon

Floating-point reciprocal step Arm’s documentation

vrecpsq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point reciprocal step Arm’s documentation

vrecpsq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point reciprocal step Arm’s documentation

vrecpsq_f64neon

Floating-point reciprocal step Arm’s documentation

vrecpss_f32neon

Floating-point reciprocal step Arm’s documentation

vrecpxd_f64neon

Floating-point reciprocal exponent Arm’s documentation

vrecpxs_f32neon

Floating-point reciprocal exponent Arm’s documentation

vreinterpret_f16_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f16_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_p64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f32_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_f16neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_f32neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_p8neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_p16neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_p64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_s8neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_s16neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_s32neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_s64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_u8neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_u16neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_u32neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_f64_u64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p8_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p16_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_f32neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_s64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_p64_u64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s8_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s16_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s32_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_p64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_s64_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u8_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u16_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u32_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_p64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpret_u64_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f16_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_p64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f32_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_f16neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_f32neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_p8neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_p16neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_p64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_p128neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_s8neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_s16neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_s32neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_s64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_u8neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_u16neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_u32neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_f64_u64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p8_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p16_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_f32neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_s64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p64_u64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_p128_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s8_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s16_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s32_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_p64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_s64_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u8_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u16_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u32_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and non-ARM64EC and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_f64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_p64neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_p128(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and aes

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vreinterpretq_u64_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Vector reinterpret cast operation Arm’s documentation

vrev16_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev16_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev16_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev16q_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev16q_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev16q_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32q_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32q_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32q_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32q_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32q_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev32q_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Reverse elements in 64-bit doublewords Arm’s documentation

vrev64_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64q_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Reverse elements in 64-bit doublewords Arm’s documentation

vrev64q_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64q_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64q_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64q_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64q_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64q_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64q_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64q_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrev64q_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reversing vector elements (swap endianness) Arm’s documentation

vrhadd_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrhadd_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrhadd_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrhadd_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrhadd_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrhadd_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrhaddq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrhaddq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrhaddq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrhaddq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrhaddq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrhaddq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding halving add Arm’s documentation

vrnd_f16neon and fp16

Floating-point round to integral, toward zero Arm’s documentation

vrnd_f32neon

Floating-point round to integral, toward zero Arm’s documentation

vrnd_f64neon

Floating-point round to integral, toward zero Arm’s documentation

vrnda_f16neon and fp16

Floating-point round to integral, to nearest with ties to away Arm’s documentation

vrnda_f32neon

Floating-point round to integral, to nearest with ties to away Arm’s documentation

vrnda_f64neon

Floating-point round to integral, to nearest with ties to away Arm’s documentation

vrndaq_f16neon and fp16

Floating-point round to integral, to nearest with ties to away Arm’s documentation

vrndaq_f32neon

Floating-point round to integral, to nearest with ties to away Arm’s documentation

vrndaq_f64neon

Floating-point round to integral, to nearest with ties to away Arm’s documentation

vrndi_f16neon and fp16

Floating-point round to integral, using current rounding mode Arm’s documentation

vrndi_f32neon

Floating-point round to integral, using current rounding mode Arm’s documentation

vrndi_f64neon

Floating-point round to integral, using current rounding mode Arm’s documentation

vrndiq_f16neon and fp16

Floating-point round to integral, using current rounding mode Arm’s documentation

vrndiq_f32neon

Floating-point round to integral, using current rounding mode Arm’s documentation

vrndiq_f64neon

Floating-point round to integral, using current rounding mode Arm’s documentation

vrndm_f16neon and fp16

Floating-point round to integral, toward minus infinity Arm’s documentation

vrndm_f32neon

Floating-point round to integral, toward minus infinity Arm’s documentation

vrndm_f64neon

Floating-point round to integral, toward minus infinity Arm’s documentation

vrndmq_f16neon and fp16

Floating-point round to integral, toward minus infinity Arm’s documentation

vrndmq_f32neon

Floating-point round to integral, toward minus infinity Arm’s documentation

vrndmq_f64neon

Floating-point round to integral, toward minus infinity Arm’s documentation

vrndn_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point round to integral, to nearest with ties to even Arm’s documentation

vrndn_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point round to integral, to nearest with ties to even Arm’s documentation

vrndn_f64neon

Floating-point round to integral, to nearest with ties to even Arm’s documentation

vrndnq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point round to integral, to nearest with ties to even Arm’s documentation

vrndnq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point round to integral, to nearest with ties to even Arm’s documentation

vrndnq_f64neon

Floating-point round to integral, to nearest with ties to even Arm’s documentation

vrndns_f32neon

Floating-point round to integral, to nearest with ties to even Arm’s documentation

vrndp_f16neon and fp16

Floating-point round to integral, toward plus infinity Arm’s documentation

vrndp_f32neon

Floating-point round to integral, toward plus infinity Arm’s documentation

vrndp_f64neon

Floating-point round to integral, toward plus infinity Arm’s documentation

vrndpq_f16neon and fp16

Floating-point round to integral, toward plus infinity Arm’s documentation

vrndpq_f32neon

Floating-point round to integral, toward plus infinity Arm’s documentation

vrndpq_f64neon

Floating-point round to integral, toward plus infinity Arm’s documentation

vrndq_f16neon and fp16

Floating-point round to integral, toward zero Arm’s documentation

vrndq_f32neon

Floating-point round to integral, toward zero Arm’s documentation

vrndq_f64neon

Floating-point round to integral, toward zero Arm’s documentation

vrndx_f16neon and fp16

Floating-point round to integral exact, using current rounding mode Arm’s documentation

vrndx_f32neon

Floating-point round to integral exact, using current rounding mode Arm’s documentation

vrndx_f64neon

Floating-point round to integral exact, using current rounding mode Arm’s documentation

vrndxq_f16neon and fp16

Floating-point round to integral exact, using current rounding mode Arm’s documentation

vrndxq_f32neon

Floating-point round to integral exact, using current rounding mode Arm’s documentation

vrndxq_f64neon

Floating-point round to integral exact, using current rounding mode Arm’s documentation

vrshl_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift left Arm’s documentation

vrshl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift left Arm’s documentation

vrshl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift left Arm’s documentation

vrshl_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift left Arm’s documentation

vrshl_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift left Arm’s documentation

vrshl_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift left Arm’s documentation

vrshl_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift left Arm’s documentation

vrshl_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift left Arm’s documentation

vrshld_s64neon

Signed rounding shift left Arm’s documentation

vrshld_u64neon

Unsigned rounding shift left Arm’s documentation

vrshlq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift left Arm’s documentation

vrshlq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift left Arm’s documentation

vrshlq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift left Arm’s documentation

vrshlq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift left Arm’s documentation

vrshlq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift left Arm’s documentation

vrshlq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift left Arm’s documentation

vrshlq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift left Arm’s documentation

vrshlq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift left Arm’s documentation

vrshr_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right Arm’s documentation

vrshr_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right Arm’s documentation

vrshr_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right Arm’s documentation

vrshr_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right Arm’s documentation

vrshr_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right Arm’s documentation

vrshr_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right Arm’s documentation

vrshr_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right Arm’s documentation

vrshr_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right Arm’s documentation

vrshrd_n_s64neon

Signed rounding shift right Arm’s documentation

vrshrd_n_u64neon

Unsigned rounding shift right Arm’s documentation

vrshrn_high_n_s16neon

Rounding shift right narrow Arm’s documentation

vrshrn_high_n_s32neon

Rounding shift right narrow Arm’s documentation

vrshrn_high_n_s64neon

Rounding shift right narrow Arm’s documentation

vrshrn_high_n_u16neon

Rounding shift right narrow Arm’s documentation

vrshrn_high_n_u32neon

Rounding shift right narrow Arm’s documentation

vrshrn_high_n_u64neon

Rounding shift right narrow Arm’s documentation

vrshrn_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Rounding shift right narrow Arm’s documentation

vrshrn_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Rounding shift right narrow Arm’s documentation

vrshrn_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Rounding shift right narrow Arm’s documentation

vrshrn_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding shift right narrow Arm’s documentation

vrshrn_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding shift right narrow Arm’s documentation

vrshrn_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding shift right narrow Arm’s documentation

vrshrq_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right Arm’s documentation

vrshrq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right Arm’s documentation

vrshrq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right Arm’s documentation

vrshrq_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right Arm’s documentation

vrshrq_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right Arm’s documentation

vrshrq_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right Arm’s documentation

vrshrq_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right Arm’s documentation

vrshrq_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right Arm’s documentation

vrsqrte_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Reciprocal square-root estimate. Arm’s documentation

vrsqrte_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reciprocal square-root estimate. Arm’s documentation

vrsqrte_f64neon

Reciprocal square-root estimate. Arm’s documentation

vrsqrte_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned reciprocal square root estimate Arm’s documentation

vrsqrted_f64neon

Reciprocal square-root estimate. Arm’s documentation

vrsqrteq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Reciprocal square-root estimate. Arm’s documentation

vrsqrteq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Reciprocal square-root estimate. Arm’s documentation

vrsqrteq_f64neon

Reciprocal square-root estimate. Arm’s documentation

vrsqrteq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned reciprocal square root estimate Arm’s documentation

vrsqrtes_f32neon

Reciprocal square-root estimate. Arm’s documentation

vrsqrts_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point reciprocal square root step Arm’s documentation

vrsqrts_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point reciprocal square root step Arm’s documentation

vrsqrts_f64neon

Floating-point reciprocal square root step Arm’s documentation

vrsqrtsd_f64neon

Floating-point reciprocal square root step Arm’s documentation

vrsqrtsq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point reciprocal square root step Arm’s documentation

vrsqrtsq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Floating-point reciprocal square root step Arm’s documentation

vrsqrtsq_f64neon

Floating-point reciprocal square root step Arm’s documentation

vrsqrtss_f32neon

Floating-point reciprocal square root step Arm’s documentation

vrsra_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right and accumulate Arm’s documentation

vrsra_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right and accumulate Arm’s documentation

vrsra_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right and accumulate Arm’s documentation

vrsra_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right and accumulate Arm’s documentation

vrsra_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right and accumulate Arm’s documentation

vrsra_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right and accumulate Arm’s documentation

vrsra_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right and accumulate Arm’s documentation

vrsra_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right and accumulate Arm’s documentation

vrsrad_n_s64neon

Signed rounding shift right and accumulate. Arm’s documentation

vrsrad_n_u64neon

Unsigned rounding shift right and accumulate. Arm’s documentation

vrsraq_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right and accumulate Arm’s documentation

vrsraq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right and accumulate Arm’s documentation

vrsraq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right and accumulate Arm’s documentation

vrsraq_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed rounding shift right and accumulate Arm’s documentation

vrsraq_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right and accumulate Arm’s documentation

vrsraq_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right and accumulate Arm’s documentation

vrsraq_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right and accumulate Arm’s documentation

vrsraq_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned rounding shift right and accumulate Arm’s documentation

vrsubhn_high_s16neon

Rounding subtract returning high narrow Arm’s documentation

vrsubhn_high_s32neon

Rounding subtract returning high narrow Arm’s documentation

vrsubhn_high_s64neon

Rounding subtract returning high narrow Arm’s documentation

vrsubhn_high_u16neon

Rounding subtract returning high narrow Arm’s documentation

vrsubhn_high_u32neon

Rounding subtract returning high narrow Arm’s documentation

vrsubhn_high_u64neon

Rounding subtract returning high narrow Arm’s documentation

vrsubhn_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding subtract returning high narrow Arm’s documentation

vrsubhn_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding subtract returning high narrow Arm’s documentation

vrsubhn_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Rounding subtract returning high narrow Arm’s documentation

vrsubhn_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Rounding subtract returning high narrow Arm’s documentation

vrsubhn_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Rounding subtract returning high narrow Arm’s documentation

vrsubhn_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon

Rounding subtract returning high narrow Arm’s documentation

vset_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vset_lane_f64neon

Insert vector element from another vector element Arm’s documentation

vset_lane_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vset_lane_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vset_lane_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Insert vector element from another vector element Arm’s documentation

vset_lane_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vset_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vset_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vset_lane_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vset_lane_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vset_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vset_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vset_lane_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_f64neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_p64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Insert vector element from another vector element Arm’s documentation

vsetq_lane_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsetq_lane_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Insert vector element from another vector element Arm’s documentation

vsha1cq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and sha2

SHA1 hash update accelerator, choose. Arm’s documentation

vsha1h_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and sha2

SHA1 fixed rotate. Arm’s documentation

vsha1mq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and sha2

SHA1 hash update accelerator, majority Arm’s documentation

vsha1pq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and sha2

SHA1 hash update accelerator, parity Arm’s documentation

vsha1su0q_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and sha2

SHA1 schedule update accelerator, first part. Arm’s documentation

vsha1su1q_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and sha2

SHA1 schedule update accelerator, second part. Arm’s documentation

vsha256h2q_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and sha2

SHA1 schedule update accelerator, upper part. Arm’s documentation

vsha256hq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and sha2

SHA1 schedule update accelerator, first part. Arm’s documentation

vsha256su0q_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and sha2

SHA256 schedule update accelerator, first part. Arm’s documentation

vsha256su1q_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and sha2

SHA256 schedule update accelerator, second part. Arm’s documentation

vsha512h2q_u64neon and sha3

SHA512 hash update part 2 Arm’s documentation

vsha512hq_u64neon and sha3

SHA512 hash update part 1 Arm’s documentation

vsha512su0q_u64neon and sha3

SHA512 schedule update 0 Arm’s documentation

vsha512su1q_u64neon and sha3

SHA512 schedule update 1 Arm’s documentation

vshl_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshl_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshl_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshl_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshl_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshl_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshl_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshl_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshl_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Shift left Arm’s documentation

vshl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Shift left Arm’s documentation

vshl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Shift left Arm’s documentation

vshl_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Shift left Arm’s documentation

vshl_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Shift left Arm’s documentation

vshl_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Shift left Arm’s documentation

vshl_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Shift left Arm’s documentation

vshl_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Shift left Arm’s documentation

vshld_n_s64neon

Shift left

vshld_n_u64neon

Shift left

vshld_s64neon

Signed Shift left Arm’s documentation

vshld_u64neon

Unsigned Shift left Arm’s documentation

vshll_high_n_s8neon

Signed shift left long Arm’s documentation

vshll_high_n_s16neon

Signed shift left long Arm’s documentation

vshll_high_n_s32neon

Signed shift left long Arm’s documentation

vshll_high_n_u8neon

Signed shift left long Arm’s documentation

vshll_high_n_u16neon

Signed shift left long Arm’s documentation

vshll_high_n_u32neon

Signed shift left long Arm’s documentation

vshll_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift left long Arm’s documentation

vshll_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift left long Arm’s documentation

vshll_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift left long Arm’s documentation

vshll_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift left long Arm’s documentation

vshll_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift left long Arm’s documentation

vshll_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift left long Arm’s documentation

vshlq_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshlq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshlq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshlq_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshlq_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshlq_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshlq_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshlq_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift left Arm’s documentation

vshlq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Shift left Arm’s documentation

vshlq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Shift left Arm’s documentation

vshlq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Shift left Arm’s documentation

vshlq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Shift left Arm’s documentation

vshlq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Shift left Arm’s documentation

vshlq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Shift left Arm’s documentation

vshlq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Shift left Arm’s documentation

vshlq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Shift left Arm’s documentation

vshr_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshr_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshr_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshr_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshr_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshr_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshr_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshr_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshrd_n_s64neon

Signed shift right

vshrd_n_u64neon

Unsigned shift right

vshrn_high_n_s16neon

Shift right narrow Arm’s documentation

vshrn_high_n_s32neon

Shift right narrow Arm’s documentation

vshrn_high_n_s64neon

Shift right narrow Arm’s documentation

vshrn_high_n_u16neon

Shift right narrow Arm’s documentation

vshrn_high_n_u32neon

Shift right narrow Arm’s documentation

vshrn_high_n_u64neon

Shift right narrow Arm’s documentation

vshrn_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right narrow Arm’s documentation

vshrn_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right narrow Arm’s documentation

vshrn_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right narrow Arm’s documentation

vshrn_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right narrow Arm’s documentation

vshrn_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right narrow Arm’s documentation

vshrn_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right narrow Arm’s documentation

vshrq_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshrq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshrq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshrq_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshrq_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshrq_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshrq_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vshrq_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Shift right Arm’s documentation

vsli_n_p8neon

Shift Left and Insert (immediate) Arm’s documentation

vsli_n_p16neon

Shift Left and Insert (immediate) Arm’s documentation

vsli_n_p64neon and aes

Shift Left and Insert (immediate) Arm’s documentation

vsli_n_s8neon

Shift Left and Insert (immediate) Arm’s documentation

vsli_n_s16neon

Shift Left and Insert (immediate) Arm’s documentation

vsli_n_s32neon

Shift Left and Insert (immediate) Arm’s documentation

vsli_n_s64neon

Shift Left and Insert (immediate) Arm’s documentation

vsli_n_u8neon

Shift Left and Insert (immediate) Arm’s documentation

vsli_n_u16neon

Shift Left and Insert (immediate) Arm’s documentation

vsli_n_u32neon

Shift Left and Insert (immediate) Arm’s documentation

vsli_n_u64neon

Shift Left and Insert (immediate) Arm’s documentation

vslid_n_s64neon

Shift left and insert Arm’s documentation

vslid_n_u64neon

Shift left and insert Arm’s documentation

vsliq_n_p8neon

Shift Left and Insert (immediate) Arm’s documentation

vsliq_n_p16neon

Shift Left and Insert (immediate) Arm’s documentation

vsliq_n_p64neon and aes

Shift Left and Insert (immediate) Arm’s documentation

vsliq_n_s8neon

Shift Left and Insert (immediate) Arm’s documentation

vsliq_n_s16neon

Shift Left and Insert (immediate) Arm’s documentation

vsliq_n_s32neon

Shift Left and Insert (immediate) Arm’s documentation

vsliq_n_s64neon

Shift Left and Insert (immediate) Arm’s documentation

vsliq_n_u8neon

Shift Left and Insert (immediate) Arm’s documentation

vsliq_n_u16neon

Shift Left and Insert (immediate) Arm’s documentation

vsliq_n_u32neon

Shift Left and Insert (immediate) Arm’s documentation

vsliq_n_u64neon

Shift Left and Insert (immediate) Arm’s documentation

vsqadd_u8neon

Unsigned saturating Accumulate of Signed value. Arm’s documentation

vsqadd_u16neon

Unsigned saturating Accumulate of Signed value. Arm’s documentation

vsqadd_u32neon

Unsigned saturating Accumulate of Signed value. Arm’s documentation

vsqadd_u64neon

Unsigned saturating Accumulate of Signed value. Arm’s documentation

vsqaddb_u8neon

Unsigned saturating accumulate of signed value Arm’s documentation

vsqaddd_u64neon

Unsigned saturating accumulate of signed value Arm’s documentation

vsqaddh_u16neon

Unsigned saturating accumulate of signed value Arm’s documentation

vsqaddq_u8neon

Unsigned saturating Accumulate of Signed value. Arm’s documentation

vsqaddq_u16neon

Unsigned saturating Accumulate of Signed value. Arm’s documentation

vsqaddq_u32neon

Unsigned saturating Accumulate of Signed value. Arm’s documentation

vsqaddq_u64neon

Unsigned saturating Accumulate of Signed value. Arm’s documentation

vsqadds_u32neon

Unsigned saturating accumulate of signed value Arm’s documentation

vsqrt_f16neon and fp16

Calculates the square root of each lane. Arm’s documentation

vsqrt_f32neon

Calculates the square root of each lane. Arm’s documentation

vsqrt_f64neon

Calculates the square root of each lane. Arm’s documentation

vsqrtq_f16neon and fp16

Calculates the square root of each lane. Arm’s documentation

vsqrtq_f32neon

Calculates the square root of each lane. Arm’s documentation

vsqrtq_f64neon

Calculates the square root of each lane. Arm’s documentation

vsra_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift right and accumulate Arm’s documentation

vsra_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift right and accumulate Arm’s documentation

vsra_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift right and accumulate Arm’s documentation

vsra_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift right and accumulate Arm’s documentation

vsra_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned shift right and accumulate Arm’s documentation

vsra_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned shift right and accumulate Arm’s documentation

vsra_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned shift right and accumulate Arm’s documentation

vsra_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned shift right and accumulate Arm’s documentation

vsrad_n_s64neon

Signed shift right and accumulate

vsrad_n_u64neon

Unsigned shift right and accumulate

vsraq_n_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift right and accumulate Arm’s documentation

vsraq_n_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift right and accumulate Arm’s documentation

vsraq_n_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift right and accumulate Arm’s documentation

vsraq_n_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed shift right and accumulate Arm’s documentation

vsraq_n_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned shift right and accumulate Arm’s documentation

vsraq_n_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned shift right and accumulate Arm’s documentation

vsraq_n_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned shift right and accumulate Arm’s documentation

vsraq_n_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned shift right and accumulate Arm’s documentation

vsri_n_p8neon

Shift Right and Insert (immediate) Arm’s documentation

vsri_n_p16neon

Shift Right and Insert (immediate) Arm’s documentation

vsri_n_p64neon and aes

Shift Right and Insert (immediate) Arm’s documentation

vsri_n_s8neon

Shift Right and Insert (immediate) Arm’s documentation

vsri_n_s16neon

Shift Right and Insert (immediate) Arm’s documentation

vsri_n_s32neon

Shift Right and Insert (immediate) Arm’s documentation

vsri_n_s64neon

Shift Right and Insert (immediate) Arm’s documentation

vsri_n_u8neon

Shift Right and Insert (immediate) Arm’s documentation

vsri_n_u16neon

Shift Right and Insert (immediate) Arm’s documentation

vsri_n_u32neon

Shift Right and Insert (immediate) Arm’s documentation

vsri_n_u64neon

Shift Right and Insert (immediate) Arm’s documentation

vsrid_n_s64neon

Shift right and insert Arm’s documentation

vsrid_n_u64neon

Shift right and insert Arm’s documentation

vsriq_n_p8neon

Shift Right and Insert (immediate) Arm’s documentation

vsriq_n_p16neon

Shift Right and Insert (immediate) Arm’s documentation

vsriq_n_p64neon and aes

Shift Right and Insert (immediate) Arm’s documentation

vsriq_n_s8neon

Shift Right and Insert (immediate) Arm’s documentation

vsriq_n_s16neon

Shift Right and Insert (immediate) Arm’s documentation

vsriq_n_s32neon

Shift Right and Insert (immediate) Arm’s documentation

vsriq_n_s64neon

Shift Right and Insert (immediate) Arm’s documentation

vsriq_n_u8neon

Shift Right and Insert (immediate) Arm’s documentation

vsriq_n_u16neon

Shift Right and Insert (immediate) Arm’s documentation

vsriq_n_u32neon

Shift Right and Insert (immediate) Arm’s documentation

vsriq_n_u64neon

Shift Right and Insert (immediate) Arm’s documentation

vst1_f32^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_f64^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_f32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_f32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_f32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_f64_x2^⚠neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_f64_x3^⚠neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_f64_x4^⚠neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_f64^⚠neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_lane_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_p8^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_p8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_p8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_p8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_p16^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_p64^⚠neon and aes

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_p16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_p16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_p16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_p64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_p64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_p64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_s8^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_s8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_s8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_s8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_s16^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_s32^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_s64^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_s16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_s16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_s16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_s32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_s32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_s32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_s64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_s64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_s64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1_u8^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_u8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_u8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_u8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_u16^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_u32^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_u64^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_u16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_u16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_u16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_u32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_u32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_u32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_u64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_u64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_u64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_f32^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_f64^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_f32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_f32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_f32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_f64_x2^⚠neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_f64_x3^⚠neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_f64_x4^⚠neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_f64^⚠neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_lane_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_p8^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_p8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_p8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_p8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_p16^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_p64^⚠neon and aes

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_p16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_p16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_p16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_p64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_p64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_p64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_s8^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_s8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_s8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_s8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_s16^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_s32^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_s64^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_s16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_s16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_s16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_s32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_s32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_s32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_s64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_s64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_s64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_u8^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_u8_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_u8_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_u8_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_u16^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_u32^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_u64^⚠neon

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_u16_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_u16_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_u16_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_u32_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_u32_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_u32_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_u64_x2^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_u64_x3^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_u64_x4^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst2_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_f64^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_f64^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_p64^⚠neon and aes

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_s64^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_u64^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Store multiple 2-element structures from two registers Arm’s documentation

vst2_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_f64^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_f64^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_p8^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_p64^⚠neon and aes

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_s8^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_s64^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_u8^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_u64^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_p64^⚠neon and aes

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_s64^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_u64^⚠neon

Store multiple 2-element structures from two registers Arm’s documentation

vst3_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_f64^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_f64^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_p64^⚠neon and aes

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_s64^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_u64^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Store multiple 3-element structures from three registers Arm’s documentation

vst3_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_f64^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_f64^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_p8^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_p64^⚠neon and aes

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_s8^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_s64^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_u8^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_u64^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_p64^⚠neon and aes

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_s64^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_u64^⚠neon

Store multiple 3-element structures from three registers Arm’s documentation

vst4_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_f64^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_f64^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_p64^⚠neon and aes

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_s64^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_u64^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_p64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and aes

Store multiple 4-element structures from four registers Arm’s documentation

vst4_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_s64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_u64^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_f64^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_f32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_f64^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_p8^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_p64^⚠neon and aes

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_s8^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_s64^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_u8^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_u64^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_p8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_p16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_p64^⚠neon and aes

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_s8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_s16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_s32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_s64^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_u8^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_u16^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_u32^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_u64^⚠neon

Store multiple 4-element structures from four registers Arm’s documentation

vstrq_p128^⚠(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Store SIMD&FP register (immediate offset) Arm’s documentation

vsub_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Subtract Arm’s documentation

vsub_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsub_f64neon

Subtract Arm’s documentation

vsub_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsub_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsub_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsub_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsub_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsub_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsub_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsub_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsubd_s64neon

Subtract Arm’s documentation

vsubd_u64neon

Subtract Arm’s documentation

vsubhn_high_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubhn_high_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubhn_high_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubhn_high_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubhn_high_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubhn_high_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubhn_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubhn_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubhn_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubhn_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubhn_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubhn_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract returning high narrow Arm’s documentation

vsubl_high_s8neon

Signed Subtract Long Arm’s documentation

vsubl_high_s16neon

Signed Subtract Long Arm’s documentation

vsubl_high_s32neon

Signed Subtract Long Arm’s documentation

vsubl_high_u8neon

Unsigned Subtract Long Arm’s documentation

vsubl_high_u16neon

Unsigned Subtract Long Arm’s documentation

vsubl_high_u32neon

Unsigned Subtract Long Arm’s documentation

vsubl_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Subtract Long Arm’s documentation

vsubl_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Subtract Long Arm’s documentation

vsubl_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Subtract Long Arm’s documentation

vsubl_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Subtract Long Arm’s documentation

vsubl_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Subtract Long Arm’s documentation

vsubl_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Subtract Long Arm’s documentation

vsubq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Subtract Arm’s documentation

vsubq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsubq_f64neon

Subtract Arm’s documentation

vsubq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsubq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsubq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsubq_s64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsubq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsubq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsubq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsubq_u64(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Subtract Arm’s documentation

vsubw_high_s8neon

Signed Subtract Wide Arm’s documentation

vsubw_high_s16neon

Signed Subtract Wide Arm’s documentation

vsubw_high_s32neon

Signed Subtract Wide Arm’s documentation

vsubw_high_u8neon

Unsigned Subtract Wide Arm’s documentation

vsubw_high_u16neon

Unsigned Subtract Wide Arm’s documentation

vsubw_high_u32neon

Unsigned Subtract Wide Arm’s documentation

vsubw_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Subtract Wide Arm’s documentation

vsubw_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Subtract Wide Arm’s documentation

vsubw_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed Subtract Wide Arm’s documentation

vsubw_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Subtract Wide Arm’s documentation

vsubw_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Subtract Wide Arm’s documentation

vsubw_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned Subtract Wide Arm’s documentation

vtbl1_p8neon

Table look-up Arm’s documentation

vtbl1_s8neon

Table look-up Arm’s documentation

vtbl1_u8neon

Table look-up Arm’s documentation

vtbl2_p8neon

Table look-up Arm’s documentation

vtbl2_s8neon

Table look-up Arm’s documentation

vtbl2_u8neon

Table look-up Arm’s documentation

vtbl3_p8neon

Table look-up Arm’s documentation

vtbl3_s8neon

Table look-up Arm’s documentation

vtbl3_u8neon

Table look-up Arm’s documentation

vtbl4_p8neon

Table look-up Arm’s documentation

vtbl4_s8neon

Table look-up Arm’s documentation

vtbl4_u8neon

Table look-up Arm’s documentation

vtbx1_p8neon

Extended table look-up Arm’s documentation

vtbx1_s8neon

Extended table look-up Arm’s documentation

vtbx1_u8neon

Extended table look-up Arm’s documentation

vtbx2_p8neon

Extended table look-up Arm’s documentation

vtbx2_s8neon

Extended table look-up Arm’s documentation

vtbx2_u8neon

Extended table look-up Arm’s documentation

vtbx3_p8neon

Extended table look-up Arm’s documentation

vtbx3_s8neon

Extended table look-up Arm’s documentation

vtbx3_u8neon

Extended table look-up Arm’s documentation

vtbx4_p8neon

Extended table look-up Arm’s documentation

vtbx4_s8neon

Extended table look-up Arm’s documentation

vtbx4_u8neon

Extended table look-up Arm’s documentation

vtrn1_f16neon and fp16

Transpose vectors Arm’s documentation

vtrn1_f32neon

Transpose vectors Arm’s documentation

vtrn1_p8neon

Transpose vectors Arm’s documentation

vtrn1_p16neon

Transpose vectors Arm’s documentation

vtrn1_s8neon

Transpose vectors Arm’s documentation

vtrn1_s16neon

Transpose vectors Arm’s documentation

vtrn1_s32neon

Transpose vectors Arm’s documentation

vtrn1_u8neon

Transpose vectors Arm’s documentation

vtrn1_u16neon

Transpose vectors Arm’s documentation

vtrn1_u32neon

Transpose vectors Arm’s documentation

vtrn1q_f16neon and fp16

Transpose vectors Arm’s documentation

vtrn1q_f32neon

Transpose vectors Arm’s documentation

vtrn1q_f64neon

Transpose vectors Arm’s documentation

vtrn1q_p8neon

Transpose vectors Arm’s documentation

vtrn1q_p16neon

Transpose vectors Arm’s documentation

vtrn1q_p64neon

Transpose vectors Arm’s documentation

vtrn1q_s8neon

Transpose vectors Arm’s documentation

vtrn1q_s16neon

Transpose vectors Arm’s documentation

vtrn1q_s32neon

Transpose vectors Arm’s documentation

vtrn1q_s64neon

Transpose vectors Arm’s documentation

vtrn1q_u8neon

Transpose vectors Arm’s documentation

vtrn1q_u16neon

Transpose vectors Arm’s documentation

vtrn1q_u32neon

Transpose vectors Arm’s documentation

vtrn1q_u64neon

Transpose vectors Arm’s documentation

vtrn2_f16neon and fp16

Transpose vectors Arm’s documentation

vtrn2_f32neon

Transpose vectors Arm’s documentation

vtrn2_p8neon

Transpose vectors Arm’s documentation

vtrn2_p16neon

Transpose vectors Arm’s documentation

vtrn2_s8neon

Transpose vectors Arm’s documentation

vtrn2_s16neon

Transpose vectors Arm’s documentation

vtrn2_s32neon

Transpose vectors Arm’s documentation

vtrn2_u8neon

Transpose vectors Arm’s documentation

vtrn2_u16neon

Transpose vectors Arm’s documentation

vtrn2_u32neon

Transpose vectors Arm’s documentation

vtrn2q_f16neon and fp16

Transpose vectors Arm’s documentation

vtrn2q_f32neon

Transpose vectors Arm’s documentation

vtrn2q_f64neon

Transpose vectors Arm’s documentation

vtrn2q_p8neon

Transpose vectors Arm’s documentation

vtrn2q_p16neon

Transpose vectors Arm’s documentation

vtrn2q_p64neon

Transpose vectors Arm’s documentation

vtrn2q_s8neon

Transpose vectors Arm’s documentation

vtrn2q_s16neon

Transpose vectors Arm’s documentation

vtrn2q_s32neon

Transpose vectors Arm’s documentation

vtrn2q_s64neon

Transpose vectors Arm’s documentation

vtrn2q_u8neon

Transpose vectors Arm’s documentation

vtrn2q_u16neon

Transpose vectors Arm’s documentation

vtrn2q_u32neon

Transpose vectors Arm’s documentation

vtrn2q_u64neon

Transpose vectors Arm’s documentation

vtrn_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Transpose elements Arm’s documentation

vtrn_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrn_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrn_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrn_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrn_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrn_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrn_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrn_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrn_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrnq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Transpose elements Arm’s documentation

vtrnq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrnq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrnq_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrnq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrnq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrnq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrnq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrnq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtrnq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Transpose elements Arm’s documentation

vtst_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtst_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtst_p64neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtst_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtst_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtst_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtst_s64neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtst_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned compare bitwise Test bits nonzero Arm’s documentation

vtst_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned compare bitwise Test bits nonzero Arm’s documentation

vtst_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned compare bitwise Test bits nonzero Arm’s documentation

vtst_u64neon

Unsigned compare bitwise Test bits nonzero Arm’s documentation

vtstd_s64neon

Compare bitwise test bits nonzero Arm’s documentation

vtstd_u64neon

Compare bitwise test bits nonzero Arm’s documentation

vtstq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtstq_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtstq_p64neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtstq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtstq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtstq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtstq_s64neon

Signed compare bitwise Test bits nonzero Arm’s documentation

vtstq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned compare bitwise Test bits nonzero Arm’s documentation

vtstq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned compare bitwise Test bits nonzero Arm’s documentation

vtstq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unsigned compare bitwise Test bits nonzero Arm’s documentation

vtstq_u64neon

Unsigned compare bitwise Test bits nonzero Arm’s documentation

vuqadd_s8neon

Signed saturating Accumulate of Unsigned value. Arm’s documentation

vuqadd_s16neon

Signed saturating Accumulate of Unsigned value. Arm’s documentation

vuqadd_s32neon

Signed saturating Accumulate of Unsigned value. Arm’s documentation

vuqadd_s64neon

Signed saturating Accumulate of Unsigned value. Arm’s documentation

vuqaddb_s8neon

Signed saturating accumulate of unsigned value Arm’s documentation

vuqaddd_s64neon

Signed saturating accumulate of unsigned value Arm’s documentation

vuqaddh_s16neon

Signed saturating accumulate of unsigned value Arm’s documentation

vuqaddq_s8neon

Signed saturating Accumulate of Unsigned value. Arm’s documentation

vuqaddq_s16neon

Signed saturating Accumulate of Unsigned value. Arm’s documentation

vuqaddq_s32neon

Signed saturating Accumulate of Unsigned value. Arm’s documentation

vuqaddq_s64neon

Signed saturating Accumulate of Unsigned value. Arm’s documentation

vuqadds_s32neon

Signed saturating accumulate of unsigned value Arm’s documentation

vuzp1_f16neon and fp16

Unzip vectors Arm’s documentation

vuzp1_f32neon

Unzip vectors Arm’s documentation

vuzp1_p8neon

Unzip vectors Arm’s documentation

vuzp1_p16neon

Unzip vectors Arm’s documentation

vuzp1_s8neon

Unzip vectors Arm’s documentation

vuzp1_s16neon

Unzip vectors Arm’s documentation

vuzp1_s32neon

Unzip vectors Arm’s documentation

vuzp1_u8neon

Unzip vectors Arm’s documentation

vuzp1_u16neon

Unzip vectors Arm’s documentation

vuzp1_u32neon

Unzip vectors Arm’s documentation

vuzp1q_f16neon and fp16

Unzip vectors Arm’s documentation

vuzp1q_f32neon

Unzip vectors Arm’s documentation

vuzp1q_f64neon

Unzip vectors Arm’s documentation

vuzp1q_p8neon

Unzip vectors Arm’s documentation

vuzp1q_p16neon

Unzip vectors Arm’s documentation

vuzp1q_p64neon

Unzip vectors Arm’s documentation

vuzp1q_s8neon

Unzip vectors Arm’s documentation

vuzp1q_s16neon

Unzip vectors Arm’s documentation

vuzp1q_s32neon

Unzip vectors Arm’s documentation

vuzp1q_s64neon

Unzip vectors Arm’s documentation

vuzp1q_u8neon

Unzip vectors Arm’s documentation

vuzp1q_u16neon

Unzip vectors Arm’s documentation

vuzp1q_u32neon

Unzip vectors Arm’s documentation

vuzp1q_u64neon

Unzip vectors Arm’s documentation

vuzp2_f16neon and fp16

Unzip vectors Arm’s documentation

vuzp2_f32neon

Unzip vectors Arm’s documentation

vuzp2_p8neon

Unzip vectors Arm’s documentation

vuzp2_p16neon

Unzip vectors Arm’s documentation

vuzp2_s8neon

Unzip vectors Arm’s documentation

vuzp2_s16neon

Unzip vectors Arm’s documentation

vuzp2_s32neon

Unzip vectors Arm’s documentation

vuzp2_u8neon

Unzip vectors Arm’s documentation

vuzp2_u16neon

Unzip vectors Arm’s documentation

vuzp2_u32neon

Unzip vectors Arm’s documentation

vuzp2q_f16neon and fp16

Unzip vectors Arm’s documentation

vuzp2q_f32neon

Unzip vectors Arm’s documentation

vuzp2q_f64neon

Unzip vectors Arm’s documentation

vuzp2q_p8neon

Unzip vectors Arm’s documentation

vuzp2q_p16neon

Unzip vectors Arm’s documentation

vuzp2q_p64neon

Unzip vectors Arm’s documentation

vuzp2q_s8neon

Unzip vectors Arm’s documentation

vuzp2q_s16neon

Unzip vectors Arm’s documentation

vuzp2q_s32neon

Unzip vectors Arm’s documentation

vuzp2q_s64neon

Unzip vectors Arm’s documentation

vuzp2q_u8neon

Unzip vectors Arm’s documentation

vuzp2q_u16neon

Unzip vectors Arm’s documentation

vuzp2q_u32neon

Unzip vectors Arm’s documentation

vuzp2q_u64neon

Unzip vectors Arm’s documentation

vuzp_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Unzip vectors Arm’s documentation

vuzp_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzp_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzp_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzp_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzp_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzp_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzp_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzp_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzp_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzpq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Unzip vectors Arm’s documentation

vuzpq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzpq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzpq_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzpq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzpq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzpq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzpq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzpq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vuzpq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Unzip vectors Arm’s documentation

vxarq_u64neon and sha3

Exclusive OR and rotate Arm’s documentation

vzip1_f16neon and fp16

Zip vectors Arm’s documentation

vzip1_f32neon

Zip vectors Arm’s documentation

vzip1_p8neon

Zip vectors Arm’s documentation

vzip1_p16neon

Zip vectors Arm’s documentation

vzip1_s8neon

Zip vectors Arm’s documentation

vzip1_s16neon

Zip vectors Arm’s documentation

vzip1_s32neon

Zip vectors Arm’s documentation

vzip1_u8neon

Zip vectors Arm’s documentation

vzip1_u16neon

Zip vectors Arm’s documentation

vzip1_u32neon

Zip vectors Arm’s documentation

vzip1q_f16neon and fp16

Zip vectors Arm’s documentation

vzip1q_f32neon

Zip vectors Arm’s documentation

vzip1q_f64neon

Zip vectors Arm’s documentation

vzip1q_p8neon

Zip vectors Arm’s documentation

vzip1q_p16neon

Zip vectors Arm’s documentation

vzip1q_p64neon

Zip vectors Arm’s documentation

vzip1q_s8neon

Zip vectors Arm’s documentation

vzip1q_s16neon

Zip vectors Arm’s documentation

vzip1q_s32neon

Zip vectors Arm’s documentation

vzip1q_s64neon

Zip vectors Arm’s documentation

vzip1q_u8neon

Zip vectors Arm’s documentation

vzip1q_u16neon

Zip vectors Arm’s documentation

vzip1q_u32neon

Zip vectors Arm’s documentation

vzip1q_u64neon

Zip vectors Arm’s documentation

vzip2_f16neon and fp16

Zip vectors Arm’s documentation

vzip2_f32neon

Zip vectors Arm’s documentation

vzip2_p8neon

Zip vectors Arm’s documentation

vzip2_p16neon

Zip vectors Arm’s documentation

vzip2_s8neon

Zip vectors Arm’s documentation

vzip2_s16neon

Zip vectors Arm’s documentation

vzip2_s32neon

Zip vectors Arm’s documentation

vzip2_u8neon

Zip vectors Arm’s documentation

vzip2_u16neon

Zip vectors Arm’s documentation

vzip2_u32neon

Zip vectors Arm’s documentation

vzip2q_f16neon and fp16

Zip vectors Arm’s documentation

vzip2q_f32neon

Zip vectors Arm’s documentation

vzip2q_f64neon

Zip vectors Arm’s documentation

vzip2q_p8neon

Zip vectors Arm’s documentation

vzip2q_p16neon

Zip vectors Arm’s documentation

vzip2q_p64neon

Zip vectors Arm’s documentation

vzip2q_s8neon

Zip vectors Arm’s documentation

vzip2q_s16neon

Zip vectors Arm’s documentation

vzip2q_s32neon

Zip vectors Arm’s documentation

vzip2q_s64neon

Zip vectors Arm’s documentation

vzip2q_u8neon

Zip vectors Arm’s documentation

vzip2q_u16neon

Zip vectors Arm’s documentation

vzip2q_u32neon

Zip vectors Arm’s documentation

vzip2q_u64neon

Zip vectors Arm’s documentation

vzip_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Zip vectors Arm’s documentation

vzip_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzip_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzip_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzip_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzip_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzip_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzip_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzip_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzip_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzipq_f16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Zip vectors Arm’s documentation

vzipq_f32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzipq_p8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzipq_p16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzipq_s8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzipq_s16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzipq_s32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzipq_u8(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzipq_u16(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

vzipq_u32(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon

Zip vectors Arm’s documentation

__arm_mte_create_random_tag^⚠Experimentalmte

Return a pointer containing a randomly generated logical address tag.

__arm_mte_exclude_tag^⚠Experimentalmte

Add a logical tag to the set of excluded logical tags.

__arm_mte_get_tag^⚠Experimentalmte

Load an allocation tag from memory, returning a new pointer with the corresponding logical tag.

__arm_mte_increment_tag^⚠Experimentalmte

Return a pointer with the logical address tag offset by a value.

__arm_mte_ptrdiff^⚠Experimentalmte

Calculate the difference between the address parts of two pointers, ignoring the tags, and sign-extending the result.

__arm_mte_set_tag^⚠Experimentalmte

Store an allocation tag for the 16-byte granule of memory.

__dmb^⚠ExperimentalARM or AArch64 or ARM64EC

Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.

__dsb^⚠ExperimentalARM or AArch64 or ARM64EC

Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.

__isb^⚠ExperimentalARM or AArch64 or ARM64EC

Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.

__nop^⚠ExperimentalARM or AArch64 or ARM64EC

Generates an unspecified no-op instruction.

__rndr^⚠Experimentalrand

Stores a 64-bit random number into the object pointed to by the argument and returns zero. If the implementation could not generate a random number within a reasonable period of time the object pointed to by the input is set to zero and a non-zero value is returned.

__rndrrs^⚠Experimentalrand

Reseeds the random number generator. After that stores a 64-bit random number into the object pointed to by the argument and returns zero. If the implementation could not generate a random number within a reasonable period of time the object pointed to by the input is set to zero and a non-zero value is returned.

__sev^⚠Experimental(ARM or AArch64 or ARM64EC) and (v6 or AArch64 or ARM64EC)

Generates a SEV (send a global event) hint instruction.

__sevl^⚠Experimental(ARM or AArch64 or ARM64EC) and (v8 or AArch64 or ARM64EC)

Generates a send a local event hint instruction.

__wfe^⚠Experimental(ARM or AArch64 or ARM64EC) and (v6 or AArch64 or ARM64EC)

Generates a WFE (wait for event) hint instruction, or nothing.

__wfi^⚠Experimental(ARM or AArch64 or ARM64EC) and (v6 or AArch64 or ARM64EC)

Generates a WFI (wait for interrupt) hint instruction, or nothing.

__yield^⚠Experimental(ARM or AArch64 or ARM64EC) and (v6k and non-thumb-mode, or v6t2, or v6 and mclass, or AArch64, or ARM64EC)

Generates a YIELD hint instruction.

_prefetch^⚠Experimental

Fetch the cache line that contains address p using the given RW and LOCALITY.

svaba_n_s8Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_n_s16Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_n_s32Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_n_s64Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_n_u8Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_n_u16Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_n_u32Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_n_u64Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_s8Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_s16Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_s32Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_s64Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_u8Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_u16Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_u32Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svaba_u64Experimentalsve and sve2

Absolute difference and accumulate Arm’s documentation

svabalb_n_s16Experimentalsve and sve2

Absolute difference long (bottom) Arm’s documentation

svabalb_n_s32Experimentalsve and sve2

Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (top) Arm’s documentation

svabalt_n_s32Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

svabalt_n_s64Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

svabalt_n_u16Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

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Absolute difference long (top) Arm’s documentation

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Absolute difference long (top) Arm’s documentation

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Absolute difference long (top) Arm’s documentation

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Absolute difference long (top) Arm’s documentation

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Absolute difference long (top) Arm’s documentation

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Absolute difference long (top) Arm’s documentation

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Absolute difference long (top) Arm’s documentation

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Absolute difference long (top) Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

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Absolute difference long (bottom) Arm’s documentation

svabdlb_s64Experimentalsve and sve2

Absolute difference long (bottom) Arm’s documentation

svabdlb_u16Experimentalsve and sve2

Absolute difference long (bottom) Arm’s documentation

svabdlb_u32Experimentalsve and sve2

Absolute difference long (bottom) Arm’s documentation

svabdlb_u64Experimentalsve and sve2

Absolute difference long (bottom) Arm’s documentation

svabdlt_n_s16Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

svabdlt_n_s32Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

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Absolute difference long (top) Arm’s documentation

svabdlt_n_u16Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

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Absolute difference long (top) Arm’s documentation

svabdlt_n_u64Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

svabdlt_s16Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

svabdlt_s32Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

svabdlt_s64Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

svabdlt_u16Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

svabdlt_u32Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

svabdlt_u64Experimentalsve and sve2

Absolute difference long (top) Arm’s documentation

svabs_f32_mExperimentalsve

Absolute value Arm’s documentation

svabs_f32_xExperimentalsve

Absolute value Arm’s documentation

svabs_f32_zExperimentalsve

Absolute value Arm’s documentation

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Absolute value Arm’s documentation

svabs_f64_xExperimentalsve

Absolute value Arm’s documentation

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Absolute value Arm’s documentation

svabs_s8_mExperimentalsve

Absolute value Arm’s documentation

svabs_s8_xExperimentalsve

Absolute value Arm’s documentation

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Absolute value Arm’s documentation

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Absolute value Arm’s documentation

svabs_s16_xExperimentalsve

Absolute value Arm’s documentation

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Absolute value Arm’s documentation

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Absolute value Arm’s documentation

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Absolute value Arm’s documentation

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Absolute value Arm’s documentation

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Absolute value Arm’s documentation

svabs_s64_xExperimentalsve

Absolute value Arm’s documentation

svabs_s64_zExperimentalsve

Absolute value Arm’s documentation

svacge_f32Experimentalsve

Absolute compare greater than or equal to Arm’s documentation

svacge_f64Experimentalsve

Absolute compare greater than or equal to Arm’s documentation

svacge_n_f32Experimentalsve

Absolute compare greater than or equal to Arm’s documentation

svacge_n_f64Experimentalsve

Absolute compare greater than or equal to Arm’s documentation

svacgt_f32Experimentalsve

Absolute compare greater than Arm’s documentation

svacgt_f64Experimentalsve

Absolute compare greater than Arm’s documentation

svacgt_n_f32Experimentalsve

Absolute compare greater than Arm’s documentation

svacgt_n_f64Experimentalsve

Absolute compare greater than Arm’s documentation

svacle_f32Experimentalsve

Absolute compare less than or equal to Arm’s documentation

svacle_f64Experimentalsve

Absolute compare less than or equal to Arm’s documentation

svacle_n_f32Experimentalsve

Absolute compare less than or equal to Arm’s documentation

svacle_n_f64Experimentalsve

Absolute compare less than or equal to Arm’s documentation

svaclt_f32Experimentalsve

Absolute compare less than Arm’s documentation

svaclt_f64Experimentalsve

Absolute compare less than Arm’s documentation

svaclt_n_f32Experimentalsve

Absolute compare less than Arm’s documentation

svaclt_n_f64Experimentalsve

Absolute compare less than Arm’s documentation

svadalp_s16_mExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_s16_xExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_s16_zExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_s32_mExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_s32_xExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_s32_zExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_s64_mExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_s64_xExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_s64_zExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_u16_mExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_u16_xExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_u16_zExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_u32_mExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_u32_xExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_u32_zExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_u64_mExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_u64_xExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadalp_u64_zExperimentalsve and sve2

Add and accumulate long pairwise Arm’s documentation

svadclb_n_u32Experimentalsve and sve2

Add with carry long (bottom) Arm’s documentation

svadclb_n_u64Experimentalsve and sve2

Add with carry long (bottom) Arm’s documentation

svadclb_u32Experimentalsve and sve2

Add with carry long (bottom) Arm’s documentation

svadclb_u64Experimentalsve and sve2

Add with carry long (bottom) Arm’s documentation

svadclt_n_u32Experimentalsve and sve2

Add with carry long (top) Arm’s documentation

svadclt_n_u64Experimentalsve and sve2

Add with carry long (top) Arm’s documentation

svadclt_u32Experimentalsve and sve2

Add with carry long (top) Arm’s documentation

svadclt_u64Experimentalsve and sve2

Add with carry long (top) Arm’s documentation

svadd_f32_mExperimentalsve

Add Arm’s documentation

svadd_f32_xExperimentalsve

Add Arm’s documentation

svadd_f32_zExperimentalsve

Add Arm’s documentation

svadd_f64_mExperimentalsve

Add Arm’s documentation

svadd_f64_xExperimentalsve

Add Arm’s documentation

svadd_f64_zExperimentalsve

Add Arm’s documentation

svadd_n_f32_mExperimentalsve

Add Arm’s documentation

svadd_n_f32_xExperimentalsve

Add Arm’s documentation

svadd_n_f32_zExperimentalsve

Add Arm’s documentation

svadd_n_f64_mExperimentalsve

Add Arm’s documentation

svadd_n_f64_xExperimentalsve

Add Arm’s documentation

svadd_n_f64_zExperimentalsve

Add Arm’s documentation

svadd_n_s8_mExperimentalsve

Add Arm’s documentation

svadd_n_s8_xExperimentalsve

Add Arm’s documentation

svadd_n_s8_zExperimentalsve

Add Arm’s documentation

svadd_n_s16_mExperimentalsve

Add Arm’s documentation

svadd_n_s16_xExperimentalsve

Add Arm’s documentation

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Add Arm’s documentation

svadd_n_s32_mExperimentalsve

Add Arm’s documentation

svadd_n_s32_xExperimentalsve

Add Arm’s documentation

svadd_n_s32_zExperimentalsve

Add Arm’s documentation

svadd_n_s64_mExperimentalsve

Add Arm’s documentation

svadd_n_s64_xExperimentalsve

Add Arm’s documentation

svadd_n_s64_zExperimentalsve

Add Arm’s documentation

svadd_n_u8_mExperimentalsve

Add Arm’s documentation

svadd_n_u8_xExperimentalsve

Add Arm’s documentation

svadd_n_u8_zExperimentalsve

Add Arm’s documentation

svadd_n_u16_mExperimentalsve

Add Arm’s documentation

svadd_n_u16_xExperimentalsve

Add Arm’s documentation

svadd_n_u16_zExperimentalsve

Add Arm’s documentation

svadd_n_u32_mExperimentalsve

Add Arm’s documentation

svadd_n_u32_xExperimentalsve

Add Arm’s documentation

svadd_n_u32_zExperimentalsve

Add Arm’s documentation

svadd_n_u64_mExperimentalsve

Add Arm’s documentation

svadd_n_u64_xExperimentalsve

Add Arm’s documentation

svadd_n_u64_zExperimentalsve

Add Arm’s documentation

svadd_s8_mExperimentalsve

Add Arm’s documentation

svadd_s8_xExperimentalsve

Add Arm’s documentation

svadd_s8_zExperimentalsve

Add Arm’s documentation

svadd_s16_mExperimentalsve

Add Arm’s documentation

svadd_s16_xExperimentalsve

Add Arm’s documentation

svadd_s16_zExperimentalsve

Add Arm’s documentation

svadd_s32_mExperimentalsve

Add Arm’s documentation

svadd_s32_xExperimentalsve

Add Arm’s documentation

svadd_s32_zExperimentalsve

Add Arm’s documentation

svadd_s64_mExperimentalsve

Add Arm’s documentation

svadd_s64_xExperimentalsve

Add Arm’s documentation

svadd_s64_zExperimentalsve

Add Arm’s documentation

svadd_u8_mExperimentalsve

Add Arm’s documentation

svadd_u8_xExperimentalsve

Add Arm’s documentation

svadd_u8_zExperimentalsve

Add Arm’s documentation

svadd_u16_mExperimentalsve

Add Arm’s documentation

svadd_u16_xExperimentalsve

Add Arm’s documentation

svadd_u16_zExperimentalsve

Add Arm’s documentation

svadd_u32_mExperimentalsve

Add Arm’s documentation

svadd_u32_xExperimentalsve

Add Arm’s documentation

svadd_u32_zExperimentalsve

Add Arm’s documentation

svadd_u64_mExperimentalsve

Add Arm’s documentation

svadd_u64_xExperimentalsve

Add Arm’s documentation

svadd_u64_zExperimentalsve

Add Arm’s documentation

svadda_f32Experimentalsve

Add reduction (strictly-ordered) Arm’s documentation

svadda_f64Experimentalsve

Add reduction (strictly-ordered) Arm’s documentation

svaddhnb_n_s16Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnb_n_s32Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnb_n_s64Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnb_n_u16Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnb_n_u32Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnb_n_u64Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnb_s16Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnb_s32Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnb_s64Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnb_u16Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnb_u32Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnb_u64Experimentalsve and sve2

Add narrow high part (bottom) Arm’s documentation

svaddhnt_n_s16Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddhnt_n_s32Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddhnt_n_s64Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddhnt_n_u16Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddhnt_n_u32Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddhnt_n_u64Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddhnt_s16Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddhnt_s32Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddhnt_s64Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddhnt_u16Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddhnt_u32Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddhnt_u64Experimentalsve and sve2

Add narrow high part (top) Arm’s documentation

svaddlb_n_s16Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlb_n_s32Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlb_n_s64Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlb_n_u16Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlb_n_u32Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlb_n_u64Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlb_s16Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlb_s32Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlb_s64Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlb_u16Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlb_u32Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlb_u64Experimentalsve and sve2

Add long (bottom) Arm’s documentation

svaddlbt_n_s16Experimentalsve and sve2

Add long (bottom + top) Arm’s documentation

svaddlbt_n_s32Experimentalsve and sve2

Add long (bottom + top) Arm’s documentation

svaddlbt_n_s64Experimentalsve and sve2

Add long (bottom + top) Arm’s documentation

svaddlbt_s16Experimentalsve and sve2

Add long (bottom + top) Arm’s documentation

svaddlbt_s32Experimentalsve and sve2

Add long (bottom + top) Arm’s documentation

svaddlbt_s64Experimentalsve and sve2

Add long (bottom + top) Arm’s documentation

svaddlt_n_s16Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddlt_n_s32Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddlt_n_s64Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddlt_n_u16Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddlt_n_u32Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddlt_n_u64Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddlt_s16Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddlt_s32Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddlt_s64Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddlt_u16Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddlt_u32Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddlt_u64Experimentalsve and sve2

Add long (top) Arm’s documentation

svaddp_f32_mExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_f32_xExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_f64_mExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_f64_xExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_s8_mExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_s8_xExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_s16_mExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_s16_xExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_s32_mExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_s32_xExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_s64_mExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_s64_xExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_u8_mExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_u8_xExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_u16_mExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_u16_xExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_u32_mExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_u32_xExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_u64_mExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddp_u64_xExperimentalsve and sve2

Add pairwise Arm’s documentation

svaddv_f32Experimentalsve

Add reduction Arm’s documentation

svaddv_f64Experimentalsve

Add reduction Arm’s documentation

svaddv_s8Experimentalsve

Add reduction Arm’s documentation

svaddv_s16Experimentalsve

Add reduction Arm’s documentation

svaddv_s32Experimentalsve

Add reduction Arm’s documentation

svaddv_s64Experimentalsve

Add reduction Arm’s documentation

svaddv_u8Experimentalsve

Add reduction Arm’s documentation

svaddv_u16Experimentalsve

Add reduction Arm’s documentation

svaddv_u32Experimentalsve

Add reduction Arm’s documentation

svaddv_u64Experimentalsve

Add reduction Arm’s documentation

svaddwb_n_s16Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwb_n_s32Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwb_n_s64Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwb_n_u16Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwb_n_u32Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwb_n_u64Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwb_s16Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwb_s32Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwb_s64Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwb_u16Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwb_u32Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwb_u64Experimentalsve and sve2

Add wide (bottom) Arm’s documentation

svaddwt_n_s16Experimentalsve and sve2

Add wide (top) Arm’s documentation

svaddwt_n_s32Experimentalsve and sve2

Add wide (top) Arm’s documentation

svaddwt_n_s64Experimentalsve and sve2

Add wide (top) Arm’s documentation

svaddwt_n_u16Experimentalsve and sve2

Add wide (top) Arm’s documentation

svaddwt_n_u32Experimentalsve and sve2

Add wide (top) Arm’s documentation

svaddwt_n_u64Experimentalsve and sve2

Add wide (top) Arm’s documentation

svaddwt_s16Experimentalsve and sve2

Add wide (top) Arm’s documentation

svaddwt_s32Experimentalsve and sve2

Add wide (top) Arm’s documentation

svaddwt_s64Experimentalsve and sve2

Add wide (top) Arm’s documentation

svaddwt_u16Experimentalsve and sve2

Add wide (top) Arm’s documentation

svaddwt_u32Experimentalsve and sve2

Add wide (top) Arm’s documentation

svaddwt_u64Experimentalsve and sve2

Add wide (top) Arm’s documentation

svadrb_u32base_s32offsetExperimentalsve

Compute vector addresses for 8-bit data Arm’s documentation

svadrb_u32base_u32offsetExperimentalsve

Compute vector addresses for 8-bit data Arm’s documentation

svadrb_u64base_s64offsetExperimentalsve

Compute vector addresses for 8-bit data Arm’s documentation

svadrb_u64base_u64offsetExperimentalsve

Compute vector addresses for 8-bit data Arm’s documentation

svadrd_u32base_s32indexExperimentalsve

Compute vector addresses for 64-bit data Arm’s documentation

svadrd_u32base_u32indexExperimentalsve

Compute vector addresses for 64-bit data Arm’s documentation

svadrd_u64base_s64indexExperimentalsve

Compute vector addresses for 64-bit data Arm’s documentation

svadrd_u64base_u64indexExperimentalsve

Compute vector addresses for 64-bit data Arm’s documentation

svadrh_u32base_s32indexExperimentalsve

Compute vector addresses for 16-bit data Arm’s documentation

svadrh_u32base_u32indexExperimentalsve

Compute vector addresses for 16-bit data Arm’s documentation

svadrh_u64base_s64indexExperimentalsve

Compute vector addresses for 16-bit data Arm’s documentation

svadrh_u64base_u64indexExperimentalsve

Compute vector addresses for 16-bit data Arm’s documentation

svadrw_u32base_s32indexExperimentalsve

Compute vector addresses for 32-bit data Arm’s documentation

svadrw_u32base_u32indexExperimentalsve

Compute vector addresses for 32-bit data Arm’s documentation

svadrw_u64base_s64indexExperimentalsve

Compute vector addresses for 32-bit data Arm’s documentation

svadrw_u64base_u64indexExperimentalsve

Compute vector addresses for 32-bit data Arm’s documentation

svaesd_u8Experimentalsve and sve2 and sve2-aes

AES single round decryption Arm’s documentation

svaese_u8Experimentalsve and sve2 and sve2-aes

AES single round encryption Arm’s documentation

svaesimc_u8Experimentalsve and sve2 and sve2-aes

AES inverse mix columns Arm’s documentation

svaesmc_u8Experimentalsve and sve2 and sve2-aes

AES mix columns Arm’s documentation

svand_b_zExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s8_mExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s8_xExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s8_zExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s16_mExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s16_xExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s16_zExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s32_mExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s32_xExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s32_zExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s64_mExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s64_xExperimentalsve

Bitwise AND Arm’s documentation

svand_n_s64_zExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u8_mExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u8_xExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u8_zExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u16_mExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u16_xExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u16_zExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u32_mExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u32_xExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u32_zExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u64_mExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u64_xExperimentalsve

Bitwise AND Arm’s documentation

svand_n_u64_zExperimentalsve

Bitwise AND Arm’s documentation

svand_s8_mExperimentalsve

Bitwise AND Arm’s documentation

svand_s8_xExperimentalsve

Bitwise AND Arm’s documentation

svand_s8_zExperimentalsve

Bitwise AND Arm’s documentation

svand_s16_mExperimentalsve

Bitwise AND Arm’s documentation

svand_s16_xExperimentalsve

Bitwise AND Arm’s documentation

svand_s16_zExperimentalsve

Bitwise AND Arm’s documentation

svand_s32_mExperimentalsve

Bitwise AND Arm’s documentation

svand_s32_xExperimentalsve

Bitwise AND Arm’s documentation

svand_s32_zExperimentalsve

Bitwise AND Arm’s documentation

svand_s64_mExperimentalsve

Bitwise AND Arm’s documentation

svand_s64_xExperimentalsve

Bitwise AND Arm’s documentation

svand_s64_zExperimentalsve

Bitwise AND Arm’s documentation

svand_u8_mExperimentalsve

Bitwise AND Arm’s documentation

svand_u8_xExperimentalsve

Bitwise AND Arm’s documentation

svand_u8_zExperimentalsve

Bitwise AND Arm’s documentation

svand_u16_mExperimentalsve

Bitwise AND Arm’s documentation

svand_u16_xExperimentalsve

Bitwise AND Arm’s documentation

svand_u16_zExperimentalsve

Bitwise AND Arm’s documentation

svand_u32_mExperimentalsve

Bitwise AND Arm’s documentation

svand_u32_xExperimentalsve

Bitwise AND Arm’s documentation

svand_u32_zExperimentalsve

Bitwise AND Arm’s documentation

svand_u64_mExperimentalsve

Bitwise AND Arm’s documentation

svand_u64_xExperimentalsve

Bitwise AND Arm’s documentation

svand_u64_zExperimentalsve

Bitwise AND Arm’s documentation

svandv_s8Experimentalsve

Bitwise AND reduction to scalar Arm’s documentation

svandv_s16Experimentalsve

Bitwise AND reduction to scalar Arm’s documentation

svandv_s32Experimentalsve

Bitwise AND reduction to scalar Arm’s documentation

svandv_s64Experimentalsve

Bitwise AND reduction to scalar Arm’s documentation

svandv_u8Experimentalsve

Bitwise AND reduction to scalar Arm’s documentation

svandv_u16Experimentalsve

Bitwise AND reduction to scalar Arm’s documentation

svandv_u32Experimentalsve

Bitwise AND reduction to scalar Arm’s documentation

svandv_u64Experimentalsve

Bitwise AND reduction to scalar Arm’s documentation

svasr_n_s8_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_n_s8_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_n_s8_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_n_s16_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_n_s16_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_n_s16_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_n_s32_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_n_s32_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_n_s32_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_n_s64_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_n_s64_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_n_s64_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s8_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s8_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s8_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s16_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s16_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s16_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s32_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s32_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s32_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s64_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s64_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_s64_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_n_s8_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_n_s8_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_n_s8_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_n_s16_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_n_s16_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_n_s16_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_n_s32_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_n_s32_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_n_s32_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_s8_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_s8_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_s8_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_s16_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_s16_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_s16_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_s32_mExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_s32_xExperimentalsve

Arithmetic shift right Arm’s documentation

svasr_wide_s32_zExperimentalsve

Arithmetic shift right Arm’s documentation

svasrd_n_s8_mExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svasrd_n_s8_xExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svasrd_n_s8_zExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svasrd_n_s16_mExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svasrd_n_s16_xExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svasrd_n_s16_zExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svasrd_n_s32_mExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svasrd_n_s32_xExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svasrd_n_s32_zExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svasrd_n_s64_mExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svasrd_n_s64_xExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svasrd_n_s64_zExperimentalsve

Arithmetic shift right for divide by immediate Arm’s documentation

svbcax_n_s8Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_n_s16Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_n_s32Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_n_s64Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_n_u8Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_n_u16Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_n_u32Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_n_u64Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_s8Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_s16Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_s32Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_s64Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_u8Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_u16Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_u32Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbcax_u64Experimentalsve and sve2

Bitwise clear and exclusive OR Arm’s documentation

svbdep_n_u8Experimentalsve and sve2 and sve2-bitperm

Scatter lower bits into positions selected by bitmask Arm’s documentation

svbdep_n_u16Experimentalsve and sve2 and sve2-bitperm

Scatter lower bits into positions selected by bitmask Arm’s documentation

svbdep_n_u32Experimentalsve and sve2 and sve2-bitperm

Scatter lower bits into positions selected by bitmask Arm’s documentation

svbdep_n_u64Experimentalsve and sve2 and sve2-bitperm

Scatter lower bits into positions selected by bitmask Arm’s documentation

svbdep_u8Experimentalsve and sve2 and sve2-bitperm

Scatter lower bits into positions selected by bitmask Arm’s documentation

svbdep_u16Experimentalsve and sve2 and sve2-bitperm

Scatter lower bits into positions selected by bitmask Arm’s documentation

svbdep_u32Experimentalsve and sve2 and sve2-bitperm

Scatter lower bits into positions selected by bitmask Arm’s documentation

svbdep_u64Experimentalsve and sve2 and sve2-bitperm

Scatter lower bits into positions selected by bitmask Arm’s documentation

svbext_n_u8Experimentalsve and sve2 and sve2-bitperm

Gather lower bits from positions selected by bitmask Arm’s documentation

svbext_n_u16Experimentalsve and sve2 and sve2-bitperm

Gather lower bits from positions selected by bitmask Arm’s documentation

svbext_n_u32Experimentalsve and sve2 and sve2-bitperm

Gather lower bits from positions selected by bitmask Arm’s documentation

svbext_n_u64Experimentalsve and sve2 and sve2-bitperm

Gather lower bits from positions selected by bitmask Arm’s documentation

svbext_u8Experimentalsve and sve2 and sve2-bitperm

Gather lower bits from positions selected by bitmask Arm’s documentation

svbext_u16Experimentalsve and sve2 and sve2-bitperm

Gather lower bits from positions selected by bitmask Arm’s documentation

svbext_u32Experimentalsve and sve2 and sve2-bitperm

Gather lower bits from positions selected by bitmask Arm’s documentation

svbext_u64Experimentalsve and sve2 and sve2-bitperm

Gather lower bits from positions selected by bitmask Arm’s documentation

svbgrp_n_u8Experimentalsve and sve2 and sve2-bitperm

Group bits to right or left as selected by bitmask Arm’s documentation

svbgrp_n_u16Experimentalsve and sve2 and sve2-bitperm

Group bits to right or left as selected by bitmask Arm’s documentation

svbgrp_n_u32Experimentalsve and sve2 and sve2-bitperm

Group bits to right or left as selected by bitmask Arm’s documentation

svbgrp_n_u64Experimentalsve and sve2 and sve2-bitperm

Group bits to right or left as selected by bitmask Arm’s documentation

svbgrp_u8Experimentalsve and sve2 and sve2-bitperm

Group bits to right or left as selected by bitmask Arm’s documentation

svbgrp_u16Experimentalsve and sve2 and sve2-bitperm

Group bits to right or left as selected by bitmask Arm’s documentation

svbgrp_u32Experimentalsve and sve2 and sve2-bitperm

Group bits to right or left as selected by bitmask Arm’s documentation

svbgrp_u64Experimentalsve and sve2 and sve2-bitperm

Group bits to right or left as selected by bitmask Arm’s documentation

svbic_b_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s8_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s8_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s8_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s16_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s16_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s16_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s32_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s32_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s32_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s64_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s64_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_s64_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u8_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u8_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u8_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u16_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u16_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u16_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u32_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u32_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u32_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u64_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u64_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_n_u64_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_s8_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_s8_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_s8_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_s16_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_s16_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_s16_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_s32_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_s32_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_s32_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_s64_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_s64_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_s64_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_u8_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_u8_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_u8_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_u16_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_u16_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_u16_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_u32_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_u32_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_u32_zExperimentalsve

Bitwise clear Arm’s documentation

svbic_u64_mExperimentalsve

Bitwise clear Arm’s documentation

svbic_u64_xExperimentalsve

Bitwise clear Arm’s documentation

svbic_u64_zExperimentalsve

Bitwise clear Arm’s documentation

svbrka_b_mExperimentalsve

Break after first true condition Arm’s documentation

svbrka_b_zExperimentalsve

Break after first true condition Arm’s documentation

svbrkb_b_mExperimentalsve

Break before first true condition Arm’s documentation

svbrkb_b_zExperimentalsve

Break before first true condition Arm’s documentation

svbrkn_b_zExperimentalsve

Propagate break to next partition Arm’s documentation

svbrkpa_b_zExperimentalsve

Break after first true condition, propagating from previous partition Arm’s documentation

svbrkpb_b_zExperimentalsve

Break before first true condition, propagating from previous partition Arm’s documentation

svbsl1n_n_s8Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_n_s16Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_n_s32Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_n_s64Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_n_u8Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_n_u16Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_n_u32Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_n_u64Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_s8Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_s16Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_s32Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_s64Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_u8Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_u16Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_u32Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl1n_u64Experimentalsve and sve2

Bitwise select with first input inverted Arm’s documentation

svbsl2n_n_s8Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_n_s16Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_n_s32Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_n_s64Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_n_u8Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_n_u16Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_n_u32Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_n_u64Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_s8Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_s16Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_s32Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_s64Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_u8Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_u16Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_u32Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl2n_u64Experimentalsve and sve2

Bitwise select with second input inverted Arm’s documentation

svbsl_n_s8Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_n_s16Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_n_s32Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_n_s64Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_n_u8Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_n_u16Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_n_u32Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_n_u64Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_s8Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_s16Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_s32Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_s64Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_u8Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_u16Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_u32Experimentalsve and sve2

Bitwise select Arm’s documentation

svbsl_u64Experimentalsve and sve2

Bitwise select Arm’s documentation

svcadd_f32_mExperimentalsve

Complex add with rotate Arm’s documentation

svcadd_f32_xExperimentalsve

Complex add with rotate Arm’s documentation

svcadd_f32_zExperimentalsve

Complex add with rotate Arm’s documentation

svcadd_f64_mExperimentalsve

Complex add with rotate Arm’s documentation

svcadd_f64_xExperimentalsve

Complex add with rotate Arm’s documentation

svcadd_f64_zExperimentalsve

Complex add with rotate Arm’s documentation

svcadd_s8Experimentalsve and sve2

Complex add with rotate Arm’s documentation

svcadd_s16Experimentalsve and sve2

Complex add with rotate Arm’s documentation

svcadd_s32Experimentalsve and sve2

Complex add with rotate Arm’s documentation

svcadd_s64Experimentalsve and sve2

Complex add with rotate Arm’s documentation

svcadd_u8Experimentalsve and sve2

Complex add with rotate Arm’s documentation

svcadd_u16Experimentalsve and sve2

Complex add with rotate Arm’s documentation

svcadd_u32Experimentalsve and sve2

Complex add with rotate Arm’s documentation

svcadd_u64Experimentalsve and sve2

Complex add with rotate Arm’s documentation

svcdot_lane_s32Experimentalsve and sve2

Complex dot product Arm’s documentation

svcdot_lane_s64Experimentalsve and sve2

Complex dot product Arm’s documentation

svcdot_s32Experimentalsve and sve2

Complex dot product Arm’s documentation

svcdot_s64Experimentalsve and sve2

Complex dot product Arm’s documentation

svclasta_f32Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_f64Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_n_f32Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_n_f64Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_n_s8Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_n_s16Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_n_s32Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_n_s64Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_n_u8Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_n_u16Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_n_u32Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_n_u64Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_s8Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_s16Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_s32Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_s64Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_u8Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_u16Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_u32Experimentalsve

Conditionally extract element after last Arm’s documentation

svclasta_u64Experimentalsve

Conditionally extract element after last Arm’s documentation

svclastb_f32Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_f64Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_n_f32Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_n_f64Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_n_s8Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_n_s16Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_n_s32Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_n_s64Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_n_u8Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_n_u16Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_n_u32Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_n_u64Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_s8Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_s16Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_s32Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_s64Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_u8Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_u16Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_u32Experimentalsve

Conditionally extract last element Arm’s documentation

svclastb_u64Experimentalsve

Conditionally extract last element Arm’s documentation

svcls_s8_mExperimentalsve

Count leading sign bits Arm’s documentation

svcls_s8_xExperimentalsve

Count leading sign bits Arm’s documentation

svcls_s8_zExperimentalsve

Count leading sign bits Arm’s documentation

svcls_s16_mExperimentalsve

Count leading sign bits Arm’s documentation

svcls_s16_xExperimentalsve

Count leading sign bits Arm’s documentation

svcls_s16_zExperimentalsve

Count leading sign bits Arm’s documentation

svcls_s32_mExperimentalsve

Count leading sign bits Arm’s documentation

svcls_s32_xExperimentalsve

Count leading sign bits Arm’s documentation

svcls_s32_zExperimentalsve

Count leading sign bits Arm’s documentation

svcls_s64_mExperimentalsve

Count leading sign bits Arm’s documentation

svcls_s64_xExperimentalsve

Count leading sign bits Arm’s documentation

svcls_s64_zExperimentalsve

Count leading sign bits Arm’s documentation

svclz_s8_mExperimentalsve

Count leading zero bits Arm’s documentation

svclz_s8_xExperimentalsve

Count leading zero bits Arm’s documentation

svclz_s8_zExperimentalsve

Count leading zero bits Arm’s documentation

svclz_s16_mExperimentalsve

Count leading zero bits Arm’s documentation

svclz_s16_xExperimentalsve

Count leading zero bits Arm’s documentation

svclz_s16_zExperimentalsve

Count leading zero bits Arm’s documentation

svclz_s32_mExperimentalsve

Count leading zero bits Arm’s documentation

svclz_s32_xExperimentalsve

Count leading zero bits Arm’s documentation

svclz_s32_zExperimentalsve

Count leading zero bits Arm’s documentation

svclz_s64_mExperimentalsve

Count leading zero bits Arm’s documentation

svclz_s64_xExperimentalsve

Count leading zero bits Arm’s documentation

svclz_s64_zExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u8_mExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u8_xExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u8_zExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u16_mExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u16_xExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u16_zExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u32_mExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u32_xExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u32_zExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u64_mExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u64_xExperimentalsve

Count leading zero bits Arm’s documentation

svclz_u64_zExperimentalsve

Count leading zero bits Arm’s documentation

svcmla_f32_mExperimentalsve

Complex multiply-add with rotate Arm’s documentation

svcmla_f32_xExperimentalsve

Complex multiply-add with rotate Arm’s documentation

svcmla_f32_zExperimentalsve

Complex multiply-add with rotate Arm’s documentation

svcmla_f64_mExperimentalsve

Complex multiply-add with rotate Arm’s documentation

svcmla_f64_xExperimentalsve

Complex multiply-add with rotate Arm’s documentation

svcmla_f64_zExperimentalsve

Complex multiply-add with rotate Arm’s documentation

svcmla_lane_f32Experimentalsve

Complex multiply-add with rotate Arm’s documentation

svcmla_lane_s16Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmla_lane_s32Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmla_lane_u16Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmla_lane_u32Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmla_s8Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmla_s16Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmla_s32Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmla_s64Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmla_u8Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmla_u16Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmla_u32Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmla_u64Experimentalsve and sve2

Complex multiply-add with rotate Arm’s documentation

svcmpeq_f32Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_f64Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_n_f32Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_n_f64Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_n_s8Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_n_s16Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_n_s32Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_n_s64Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_n_u8Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_n_u16Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_n_u32Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_n_u64Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_s8Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_s16Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_s32Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_s64Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_u8Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_u16Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_u32Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_u64Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_wide_n_s8Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_wide_n_s16Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_wide_n_s32Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_wide_s8Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_wide_s16Experimentalsve

Compare equal to Arm’s documentation

svcmpeq_wide_s32Experimentalsve

Compare equal to Arm’s documentation

svcmpge_f32Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_f64Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_n_f32Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_n_f64Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_n_s8Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_n_s16Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_n_s32Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_n_s64Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_n_u8Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_n_u16Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_n_u32Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_n_u64Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_s8Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_s16Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_s32Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_s64Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_u8Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_u16Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_u32Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_u64Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_n_s8Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_n_s16Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_n_s32Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_n_u8Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_n_u16Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_n_u32Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_s8Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_s16Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_s32Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_u8Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_u16Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpge_wide_u32Experimentalsve

Compare greater than or equal to Arm’s documentation

svcmpgt_f32Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_f64Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_n_f32Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_n_f64Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_n_s8Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_n_s16Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_n_s32Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_n_s64Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_n_u8Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_n_u16Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_n_u32Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_n_u64Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_s8Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_s16Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_s32Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_s64Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_u8Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_u16Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_u32Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_u64Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_n_s8Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_n_s16Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_n_s32Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_n_u8Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_n_u16Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_n_u32Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_s8Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_s16Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_s32Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_u8Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_u16Experimentalsve

Compare greater than Arm’s documentation

svcmpgt_wide_u32Experimentalsve

Compare greater than Arm’s documentation

svcmple_f32Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_f64Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_n_f32Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_n_f64Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_n_s8Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_n_s16Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_n_s32Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_n_s64Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_n_u8Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_n_u16Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_n_u32Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_n_u64Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_s8Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_s16Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_s32Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_s64Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_u8Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_u16Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_u32Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_u64Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_n_s8Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_n_s16Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_n_s32Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_n_u8Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_n_u16Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_n_u32Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_s8Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_s16Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_s32Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_u8Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_u16Experimentalsve

Compare less than or equal to Arm’s documentation

svcmple_wide_u32Experimentalsve

Compare less than or equal to Arm’s documentation

svcmplt_f32Experimentalsve

Compare less than Arm’s documentation

svcmplt_f64Experimentalsve

Compare less than Arm’s documentation

svcmplt_n_f32Experimentalsve

Compare less than Arm’s documentation

svcmplt_n_f64Experimentalsve

Compare less than Arm’s documentation

svcmplt_n_s8Experimentalsve

Compare less than Arm’s documentation

svcmplt_n_s16Experimentalsve

Compare less than Arm’s documentation

svcmplt_n_s32Experimentalsve

Compare less than Arm’s documentation

svcmplt_n_s64Experimentalsve

Compare less than Arm’s documentation

svcmplt_n_u8Experimentalsve

Compare less than Arm’s documentation

svcmplt_n_u16Experimentalsve

Compare less than Arm’s documentation

svcmplt_n_u32Experimentalsve

Compare less than Arm’s documentation

svcmplt_n_u64Experimentalsve

Compare less than Arm’s documentation

svcmplt_s8Experimentalsve

Compare less than Arm’s documentation

svcmplt_s16Experimentalsve

Compare less than Arm’s documentation

svcmplt_s32Experimentalsve

Compare less than Arm’s documentation

svcmplt_s64Experimentalsve

Compare less than Arm’s documentation

svcmplt_u8Experimentalsve

Compare less than Arm’s documentation

svcmplt_u16Experimentalsve

Compare less than Arm’s documentation

svcmplt_u32Experimentalsve

Compare less than Arm’s documentation

svcmplt_u64Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_n_s8Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_n_s16Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_n_s32Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_n_u8Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_n_u16Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_n_u32Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_s8Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_s16Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_s32Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_u8Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_u16Experimentalsve

Compare less than Arm’s documentation

svcmplt_wide_u32Experimentalsve

Compare less than Arm’s documentation

svcmpne_f32Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_f64Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_n_f32Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_n_f64Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_n_s8Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_n_s16Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_n_s32Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_n_s64Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_n_u8Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_n_u16Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_n_u32Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_n_u64Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_s8Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_s16Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_s32Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_s64Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_u8Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_u16Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_u32Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_u64Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_wide_n_s8Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_wide_n_s16Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_wide_n_s32Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_wide_s8Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_wide_s16Experimentalsve

Compare not equal to Arm’s documentation

svcmpne_wide_s32Experimentalsve

Compare not equal to Arm’s documentation

svcmpuo_f32Experimentalsve

Compare unordered with Arm’s documentation

svcmpuo_f64Experimentalsve

Compare unordered with Arm’s documentation

svcmpuo_n_f32Experimentalsve

Compare unordered with Arm’s documentation

svcmpuo_n_f64Experimentalsve

Compare unordered with Arm’s documentation

svcnot_s8_mExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_s8_xExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_s8_zExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_s16_mExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_s16_xExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_s16_zExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_s32_mExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_s32_xExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_s32_zExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_s64_mExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_s64_xExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_s64_zExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u8_mExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u8_xExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u8_zExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u16_mExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u16_xExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u16_zExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u32_mExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u32_xExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u32_zExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u64_mExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u64_xExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnot_u64_zExperimentalsve

Logically invert boolean condition Arm’s documentation

svcnt_f32_mExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_f32_xExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_f32_zExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_f64_mExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_f64_xExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_f64_zExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s8_mExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s8_xExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s8_zExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s16_mExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s16_xExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s16_zExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s32_mExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s32_xExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s32_zExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s64_mExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s64_xExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_s64_zExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u8_mExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u8_xExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u8_zExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u16_mExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u16_xExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u16_zExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u32_mExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u32_xExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u32_zExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u64_mExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u64_xExperimentalsve

Count nonzero bits Arm’s documentation

svcnt_u64_zExperimentalsve

Count nonzero bits Arm’s documentation

svcntbExperimentalsve

Count the number of 8-bit elements in a vector Arm’s documentation

svcntb_patExperimentalsve

Count the number of 8-bit elements in a vector Arm’s documentation

svcntdExperimentalsve

Count the number of 64-bit elements in a vector Arm’s documentation

svcntd_patExperimentalsve

Count the number of 64-bit elements in a vector Arm’s documentation

svcnthExperimentalsve

Count the number of 16-bit elements in a vector Arm’s documentation

svcnth_patExperimentalsve

Count the number of 16-bit elements in a vector Arm’s documentation

svcntp_b8Experimentalsve

Count set predicate bits Arm’s documentation

svcntp_b16Experimentalsve

Count set predicate bits Arm’s documentation

svcntp_b32Experimentalsve

Count set predicate bits Arm’s documentation

svcntp_b64Experimentalsve

Count set predicate bits Arm’s documentation

svcntwExperimentalsve

Count the number of 32-bit elements in a vector Arm’s documentation

svcntw_patExperimentalsve

Count the number of 32-bit elements in a vector Arm’s documentation

svcompact_f32Experimentalsve

Shuffle active elements of vector to the right and fill with zero Arm’s documentation

svcompact_f64Experimentalsve

Shuffle active elements of vector to the right and fill with zero Arm’s documentation

svcompact_s32Experimentalsve

Shuffle active elements of vector to the right and fill with zero Arm’s documentation

svcompact_s64Experimentalsve

Shuffle active elements of vector to the right and fill with zero Arm’s documentation

svcompact_u32Experimentalsve

Shuffle active elements of vector to the right and fill with zero Arm’s documentation

svcompact_u64Experimentalsve

Shuffle active elements of vector to the right and fill with zero Arm’s documentation

svcreate2_f32Experimentalsve

Create a tuple of two vectors Arm’s documentation

svcreate2_f64Experimentalsve

Create a tuple of two vectors Arm’s documentation

svcreate2_s8Experimentalsve

Create a tuple of two vectors Arm’s documentation

svcreate2_s16Experimentalsve

Create a tuple of two vectors Arm’s documentation

svcreate2_s32Experimentalsve

Create a tuple of two vectors Arm’s documentation

svcreate2_s64Experimentalsve

Create a tuple of two vectors Arm’s documentation

svcreate2_u8Experimentalsve

Create a tuple of two vectors Arm’s documentation

svcreate2_u16Experimentalsve

Create a tuple of two vectors Arm’s documentation

svcreate2_u32Experimentalsve

Create a tuple of two vectors Arm’s documentation

svcreate2_u64Experimentalsve

Create a tuple of two vectors Arm’s documentation

svcreate3_f32Experimentalsve

Create a tuple of three vectors Arm’s documentation

svcreate3_f64Experimentalsve

Create a tuple of three vectors Arm’s documentation

svcreate3_s8Experimentalsve

Create a tuple of three vectors Arm’s documentation

svcreate3_s16Experimentalsve

Create a tuple of three vectors Arm’s documentation

svcreate3_s32Experimentalsve

Create a tuple of three vectors Arm’s documentation

svcreate3_s64Experimentalsve

Create a tuple of three vectors Arm’s documentation

svcreate3_u8Experimentalsve

Create a tuple of three vectors Arm’s documentation

svcreate3_u16Experimentalsve

Create a tuple of three vectors Arm’s documentation

svcreate3_u32Experimentalsve

Create a tuple of three vectors Arm’s documentation

svcreate3_u64Experimentalsve

Create a tuple of three vectors Arm’s documentation

svcreate4_f32Experimentalsve

Create a tuple of four vectors Arm’s documentation

svcreate4_f64Experimentalsve

Create a tuple of four vectors Arm’s documentation

svcreate4_s8Experimentalsve

Create a tuple of four vectors Arm’s documentation

svcreate4_s16Experimentalsve

Create a tuple of four vectors Arm’s documentation

svcreate4_s32Experimentalsve

Create a tuple of four vectors Arm’s documentation

svcreate4_s64Experimentalsve

Create a tuple of four vectors Arm’s documentation

svcreate4_u8Experimentalsve

Create a tuple of four vectors Arm’s documentation

svcreate4_u16Experimentalsve

Create a tuple of four vectors Arm’s documentation

svcreate4_u32Experimentalsve

Create a tuple of four vectors Arm’s documentation

svcreate4_u64Experimentalsve

Create a tuple of four vectors Arm’s documentation

svcvt_f32_f64_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_f64_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_f64_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_s32_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_s32_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_s32_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_s64_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_s64_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_s64_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_u32_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_u32_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_u32_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_u64_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_u64_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f32_u64_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_f32_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_f32_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_f32_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_s32_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_s32_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_s32_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_s64_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_s64_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_s64_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_u32_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_u32_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_u32_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_u64_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_u64_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_f64_u64_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s32_f32_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s32_f32_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s32_f32_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s32_f64_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s32_f64_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s32_f64_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s64_f32_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s64_f32_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s64_f32_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s64_f64_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s64_f64_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_s64_f64_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u32_f32_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u32_f32_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u32_f32_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u32_f64_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u32_f64_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u32_f64_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u64_f32_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u64_f32_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u64_f32_zExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u64_f64_mExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u64_f64_xExperimentalsve

Floating-point convert Arm’s documentation

svcvt_u64_f64_zExperimentalsve

Floating-point convert Arm’s documentation

svcvtlt_f64_f32_mExperimentalsve and sve2

Up convert long (top) Arm’s documentation

svcvtlt_f64_f32_xExperimentalsve and sve2

Up convert long (top) Arm’s documentation

svcvtnt_f32_f64_mExperimentalsve and sve2

Down convert and narrow (top) Arm’s documentation

svcvtnt_f32_f64_xExperimentalsve and sve2

Down convert and narrow (top) Arm’s documentation

svcvtx_f32_f64_mExperimentalsve and sve2

Down convert, rounding to odd Arm’s documentation

svcvtx_f32_f64_xExperimentalsve and sve2

Down convert, rounding to odd Arm’s documentation

svcvtx_f32_f64_zExperimentalsve and sve2

Down convert, rounding to odd Arm’s documentation

svcvtxnt_f32_f64_mExperimentalsve and sve2

Down convert, rounding to odd (top) Arm’s documentation

svcvtxnt_f32_f64_xExperimentalsve and sve2

Down convert, rounding to odd (top) Arm’s documentation

svdiv_f32_mExperimentalsve

Divide Arm’s documentation

svdiv_f32_xExperimentalsve

Divide Arm’s documentation

svdiv_f32_zExperimentalsve

Divide Arm’s documentation

svdiv_f64_mExperimentalsve

Divide Arm’s documentation

svdiv_f64_xExperimentalsve

Divide Arm’s documentation

svdiv_f64_zExperimentalsve

Divide Arm’s documentation

svdiv_n_f32_mExperimentalsve

Divide Arm’s documentation

svdiv_n_f32_xExperimentalsve

Divide Arm’s documentation

svdiv_n_f32_zExperimentalsve

Divide Arm’s documentation

svdiv_n_f64_mExperimentalsve

Divide Arm’s documentation

svdiv_n_f64_xExperimentalsve

Divide Arm’s documentation

svdiv_n_f64_zExperimentalsve

Divide Arm’s documentation

svdiv_n_s32_mExperimentalsve

Divide Arm’s documentation

svdiv_n_s32_xExperimentalsve

Divide Arm’s documentation

svdiv_n_s32_zExperimentalsve

Divide Arm’s documentation

svdiv_n_s64_mExperimentalsve

Divide Arm’s documentation

svdiv_n_s64_xExperimentalsve

Divide Arm’s documentation

svdiv_n_s64_zExperimentalsve

Divide Arm’s documentation

svdiv_n_u32_mExperimentalsve

Divide Arm’s documentation

svdiv_n_u32_xExperimentalsve

Divide Arm’s documentation

svdiv_n_u32_zExperimentalsve

Divide Arm’s documentation

svdiv_n_u64_mExperimentalsve

Divide Arm’s documentation

svdiv_n_u64_xExperimentalsve

Divide Arm’s documentation

svdiv_n_u64_zExperimentalsve

Divide Arm’s documentation

svdiv_s32_mExperimentalsve

Divide Arm’s documentation

svdiv_s32_xExperimentalsve

Divide Arm’s documentation

svdiv_s32_zExperimentalsve

Divide Arm’s documentation

svdiv_s64_mExperimentalsve

Divide Arm’s documentation

svdiv_s64_xExperimentalsve

Divide Arm’s documentation

svdiv_s64_zExperimentalsve

Divide Arm’s documentation

svdiv_u32_mExperimentalsve

Divide Arm’s documentation

svdiv_u32_xExperimentalsve

Divide Arm’s documentation

svdiv_u32_zExperimentalsve

Divide Arm’s documentation

svdiv_u64_mExperimentalsve

Divide Arm’s documentation

svdiv_u64_xExperimentalsve

Divide Arm’s documentation

svdiv_u64_zExperimentalsve

Divide Arm’s documentation

svdivr_f32_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_f32_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_f32_zExperimentalsve

Divide reversed Arm’s documentation

svdivr_f64_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_f64_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_f64_zExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_f32_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_f32_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_f32_zExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_f64_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_f64_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_f64_zExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_s32_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_s32_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_s32_zExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_s64_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_s64_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_s64_zExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_u32_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_u32_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_u32_zExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_u64_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_u64_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_n_u64_zExperimentalsve

Divide reversed Arm’s documentation

svdivr_s32_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_s32_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_s32_zExperimentalsve

Divide reversed Arm’s documentation

svdivr_s64_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_s64_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_s64_zExperimentalsve

Divide reversed Arm’s documentation

svdivr_u32_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_u32_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_u32_zExperimentalsve

Divide reversed Arm’s documentation

svdivr_u64_mExperimentalsve

Divide reversed Arm’s documentation

svdivr_u64_xExperimentalsve

Divide reversed Arm’s documentation

svdivr_u64_zExperimentalsve

Divide reversed Arm’s documentation

svdot_lane_s32Experimentalsve

Dot product Arm’s documentation

svdot_lane_s64Experimentalsve

Dot product Arm’s documentation

svdot_lane_u32Experimentalsve

Dot product Arm’s documentation

svdot_lane_u64Experimentalsve

Dot product Arm’s documentation

svdot_n_s32Experimentalsve

Dot product Arm’s documentation

svdot_n_s64Experimentalsve

Dot product Arm’s documentation

svdot_n_u32Experimentalsve

Dot product Arm’s documentation

svdot_n_u64Experimentalsve

Dot product Arm’s documentation

svdot_s32Experimentalsve

Dot product Arm’s documentation

svdot_s64Experimentalsve

Dot product Arm’s documentation

svdot_u32Experimentalsve

Dot product Arm’s documentation

svdot_u64Experimentalsve

Dot product Arm’s documentation

svdup_lane_f32Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_lane_f64Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_lane_s8Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_lane_s16Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_lane_s32Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_lane_s64Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_lane_u8Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_lane_u16Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_lane_u32Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_lane_u64Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_b8Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_b16Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_b32Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_b64Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_f32Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_f64Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_f32_mExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_f32_xExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_f32_zExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_f64_mExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_f64_xExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_f64_zExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s8Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s8_mExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s8_xExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s8_zExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s16Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s32Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s64Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s16_mExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s16_xExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s16_zExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s32_mExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s32_xExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s32_zExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s64_mExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s64_xExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_s64_zExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u8Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u8_mExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u8_xExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u8_zExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u16Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u32Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u64Experimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u16_mExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u16_xExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u16_zExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u32_mExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u32_xExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u32_zExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u64_mExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u64_xExperimentalsve

Broadcast a scalar value Arm’s documentation

svdup_n_u64_zExperimentalsve

Broadcast a scalar value Arm’s documentation

svdupq_lane_f32Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_lane_f64Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_lane_s8Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_lane_s16Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_lane_s32Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_lane_s64Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_lane_u8Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_lane_u16Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_lane_u32Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_lane_u64Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_b8Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_b16Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_b32Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_b64Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_f32Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_f64Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_s8Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_s16Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_s32Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_s64Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_u8Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_u16Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_u32Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

svdupq_n_u64Experimentalsve

Broadcast a quadword of scalars Arm’s documentation

sveor3_n_s8Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_n_s16Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_n_s32Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_n_s64Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_n_u8Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_n_u16Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_n_u32Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_n_u64Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_s8Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_s16Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_s32Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_s64Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_u8Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_u16Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_u32Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor3_u64Experimentalsve and sve2

Bitwise exclusive OR of three vectors Arm’s documentation

sveor_b_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s8_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s8_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s8_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s16_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s16_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s16_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s32_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s32_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s32_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s64_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s64_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_s64_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u8_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u8_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u8_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u16_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u16_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u16_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u32_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u32_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u32_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u64_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u64_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_n_u64_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s8_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s8_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s8_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s16_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s16_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s16_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s32_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s32_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s32_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s64_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s64_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_s64_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u8_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u8_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u8_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u16_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u16_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u16_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u32_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u32_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u32_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u64_mExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u64_xExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveor_u64_zExperimentalsve

Bitwise exclusive OR Arm’s documentation

sveorbt_n_s8Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_n_s16Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_n_s32Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_n_s64Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_n_u8Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_n_u16Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_n_u32Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_n_u64Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_s8Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_s16Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_s32Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_s64Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_u8Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_u16Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_u32Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveorbt_u64Experimentalsve and sve2

Interleaving exclusive OR (bottom, top) Arm’s documentation

sveortb_n_s8Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_n_s16Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_n_s32Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_n_s64Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_n_u8Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_n_u16Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_n_u32Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_n_u64Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_s8Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_s16Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_s32Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_s64Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_u8Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_u16Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_u32Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveortb_u64Experimentalsve and sve2

Interleaving exclusive OR (top, bottom) Arm’s documentation

sveorv_s8Experimentalsve

Bitwise exclusive OR reduction to scalar Arm’s documentation

sveorv_s16Experimentalsve

Bitwise exclusive OR reduction to scalar Arm’s documentation

sveorv_s32Experimentalsve

Bitwise exclusive OR reduction to scalar Arm’s documentation

sveorv_s64Experimentalsve

Bitwise exclusive OR reduction to scalar Arm’s documentation

sveorv_u8Experimentalsve

Bitwise exclusive OR reduction to scalar Arm’s documentation

sveorv_u16Experimentalsve

Bitwise exclusive OR reduction to scalar Arm’s documentation

sveorv_u32Experimentalsve

Bitwise exclusive OR reduction to scalar Arm’s documentation

sveorv_u64Experimentalsve

Bitwise exclusive OR reduction to scalar Arm’s documentation

svexpa_f32Experimentalsve

Floating-point exponential accelerator Arm’s documentation

svexpa_f64Experimentalsve

Floating-point exponential accelerator Arm’s documentation

svext_f32Experimentalsve

Extract vector from pair of vectors Arm’s documentation

svext_f64Experimentalsve

Extract vector from pair of vectors Arm’s documentation

svext_s8Experimentalsve

Extract vector from pair of vectors Arm’s documentation

svext_s16Experimentalsve

Extract vector from pair of vectors Arm’s documentation

svext_s32Experimentalsve

Extract vector from pair of vectors Arm’s documentation

svext_s64Experimentalsve

Extract vector from pair of vectors Arm’s documentation

svext_u8Experimentalsve

Extract vector from pair of vectors Arm’s documentation

svext_u16Experimentalsve

Extract vector from pair of vectors Arm’s documentation

svext_u32Experimentalsve

Extract vector from pair of vectors Arm’s documentation

svext_u64Experimentalsve

Extract vector from pair of vectors Arm’s documentation

svextb_s16_mExperimentalsve

Sign-extend the low 8 bits Arm’s documentation

svextb_s16_xExperimentalsve

Sign-extend the low 8 bits Arm’s documentation

svextb_s16_zExperimentalsve

Sign-extend the low 8 bits Arm’s documentation

svextb_s32_mExperimentalsve

Sign-extend the low 8 bits Arm’s documentation

svextb_s32_xExperimentalsve

Sign-extend the low 8 bits Arm’s documentation

svextb_s32_zExperimentalsve

Sign-extend the low 8 bits Arm’s documentation

svextb_s64_mExperimentalsve

Sign-extend the low 8 bits Arm’s documentation

svextb_s64_xExperimentalsve

Sign-extend the low 8 bits Arm’s documentation

svextb_s64_zExperimentalsve

Sign-extend the low 8 bits Arm’s documentation

svextb_u16_mExperimentalsve

Zero-extend the low 8 bits Arm’s documentation

svextb_u16_xExperimentalsve

Zero-extend the low 8 bits Arm’s documentation

svextb_u16_zExperimentalsve

Zero-extend the low 8 bits Arm’s documentation

svextb_u32_mExperimentalsve

Zero-extend the low 8 bits Arm’s documentation

svextb_u32_xExperimentalsve

Zero-extend the low 8 bits Arm’s documentation

svextb_u32_zExperimentalsve

Zero-extend the low 8 bits Arm’s documentation

svextb_u64_mExperimentalsve

Zero-extend the low 8 bits Arm’s documentation

svextb_u64_xExperimentalsve

Zero-extend the low 8 bits Arm’s documentation

svextb_u64_zExperimentalsve

Zero-extend the low 8 bits Arm’s documentation

svexth_s32_mExperimentalsve

Sign-extend the low 16 bits Arm’s documentation

svexth_s32_xExperimentalsve

Sign-extend the low 16 bits Arm’s documentation

svexth_s32_zExperimentalsve

Sign-extend the low 16 bits Arm’s documentation

svexth_s64_mExperimentalsve

Sign-extend the low 16 bits Arm’s documentation

svexth_s64_xExperimentalsve

Sign-extend the low 16 bits Arm’s documentation

svexth_s64_zExperimentalsve

Sign-extend the low 16 bits Arm’s documentation

svexth_u32_mExperimentalsve

Zero-extend the low 16 bits Arm’s documentation

svexth_u32_xExperimentalsve

Zero-extend the low 16 bits Arm’s documentation

svexth_u32_zExperimentalsve

Zero-extend the low 16 bits Arm’s documentation

svexth_u64_mExperimentalsve

Zero-extend the low 16 bits Arm’s documentation

svexth_u64_xExperimentalsve

Zero-extend the low 16 bits Arm’s documentation

svexth_u64_zExperimentalsve

Zero-extend the low 16 bits Arm’s documentation

svextw_s64_mExperimentalsve

Sign-extend the low 32 bits Arm’s documentation

svextw_s64_xExperimentalsve

Sign-extend the low 32 bits Arm’s documentation

svextw_s64_zExperimentalsve

Sign-extend the low 32 bits Arm’s documentation

svextw_u64_mExperimentalsve

Zero-extend the low 32 bits Arm’s documentation

svextw_u64_xExperimentalsve

Zero-extend the low 32 bits Arm’s documentation

svextw_u64_zExperimentalsve

Zero-extend the low 32 bits Arm’s documentation

svget2_f32Experimentalsve

Extract one vector from a tuple of two vectors Arm’s documentation

svget2_f64Experimentalsve

Extract one vector from a tuple of two vectors Arm’s documentation

svget2_s8Experimentalsve

Extract one vector from a tuple of two vectors Arm’s documentation

svget2_s16Experimentalsve

Extract one vector from a tuple of two vectors Arm’s documentation

svget2_s32Experimentalsve

Extract one vector from a tuple of two vectors Arm’s documentation

svget2_s64Experimentalsve

Extract one vector from a tuple of two vectors Arm’s documentation

svget2_u8Experimentalsve

Extract one vector from a tuple of two vectors Arm’s documentation

svget2_u16Experimentalsve

Extract one vector from a tuple of two vectors Arm’s documentation

svget2_u32Experimentalsve

Extract one vector from a tuple of two vectors Arm’s documentation

svget2_u64Experimentalsve

Extract one vector from a tuple of two vectors Arm’s documentation

svget3_f32Experimentalsve

Extract one vector from a tuple of three vectors Arm’s documentation

svget3_f64Experimentalsve

Extract one vector from a tuple of three vectors Arm’s documentation

svget3_s8Experimentalsve

Extract one vector from a tuple of three vectors Arm’s documentation

svget3_s16Experimentalsve

Extract one vector from a tuple of three vectors Arm’s documentation

svget3_s32Experimentalsve

Extract one vector from a tuple of three vectors Arm’s documentation

svget3_s64Experimentalsve

Extract one vector from a tuple of three vectors Arm’s documentation

svget3_u8Experimentalsve

Extract one vector from a tuple of three vectors Arm’s documentation

svget3_u16Experimentalsve

Extract one vector from a tuple of three vectors Arm’s documentation

svget3_u32Experimentalsve

Extract one vector from a tuple of three vectors Arm’s documentation

svget3_u64Experimentalsve

Extract one vector from a tuple of three vectors Arm’s documentation

svget4_f32Experimentalsve

Extract one vector from a tuple of four vectors Arm’s documentation

svget4_f64Experimentalsve

Extract one vector from a tuple of four vectors Arm’s documentation

svget4_s8Experimentalsve

Extract one vector from a tuple of four vectors Arm’s documentation

svget4_s16Experimentalsve

Extract one vector from a tuple of four vectors Arm’s documentation

svget4_s32Experimentalsve

Extract one vector from a tuple of four vectors Arm’s documentation

svget4_s64Experimentalsve

Extract one vector from a tuple of four vectors Arm’s documentation

svget4_u8Experimentalsve

Extract one vector from a tuple of four vectors Arm’s documentation

svget4_u16Experimentalsve

Extract one vector from a tuple of four vectors Arm’s documentation

svget4_u32Experimentalsve

Extract one vector from a tuple of four vectors Arm’s documentation

svget4_u64Experimentalsve

Extract one vector from a tuple of four vectors Arm’s documentation

svhadd_n_s8_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_s8_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_s8_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_s16_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_s16_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_s16_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_s32_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_s32_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_s32_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_s64_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_s64_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_s64_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u8_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u8_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u8_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u16_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u16_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u16_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u32_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u32_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u32_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u64_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u64_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_n_u64_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s8_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s8_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s8_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s16_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s16_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s16_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s32_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s32_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s32_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s64_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s64_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_s64_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u8_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u8_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u8_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u16_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u16_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u16_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u32_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u32_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u32_zExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u64_mExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u64_xExperimentalsve and sve2

Halving add Arm’s documentation

svhadd_u64_zExperimentalsve and sve2

Halving add Arm’s documentation

svhistcnt_s32_zExperimentalsve and sve2

Count matching elements Arm’s documentation

svhistcnt_s64_zExperimentalsve and sve2

Count matching elements Arm’s documentation

svhistcnt_u32_zExperimentalsve and sve2

Count matching elements Arm’s documentation

svhistcnt_u64_zExperimentalsve and sve2

Count matching elements Arm’s documentation

svhistseg_s8Experimentalsve and sve2

Count matching elements in 128-bit segments Arm’s documentation

svhistseg_u8Experimentalsve and sve2

Count matching elements in 128-bit segments Arm’s documentation

svhsub_n_s8_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_s8_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_s8_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_s16_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_s16_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_s16_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_s32_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_s32_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_s32_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_s64_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_s64_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_s64_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u8_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u8_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u8_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u16_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u16_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u16_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u32_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u32_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u32_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u64_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u64_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_n_u64_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s8_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s8_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s8_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s16_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s16_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s16_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s32_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s32_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s32_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s64_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s64_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_s64_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u8_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u8_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u8_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u16_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u16_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u16_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u32_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u32_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u32_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u64_mExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u64_xExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsub_u64_zExperimentalsve and sve2

Halving subtract Arm’s documentation

svhsubr_n_s8_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_s8_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_s8_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_s16_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_s16_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_s16_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_s32_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_s32_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_s32_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_s64_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_s64_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_s64_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u8_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u8_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u8_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u16_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u16_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u16_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u32_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u32_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u32_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u64_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u64_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_n_u64_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s8_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s8_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s8_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s16_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s16_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s16_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s32_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s32_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s32_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s64_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s64_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_s64_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u8_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u8_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u8_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u16_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u16_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u16_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u32_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u32_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u32_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u64_mExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u64_xExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svhsubr_u64_zExperimentalsve and sve2

Halving subtract reversed Arm’s documentation

svindex_s8Experimentalsve

Create linear series Arm’s documentation

svindex_s16Experimentalsve

Create linear series Arm’s documentation

svindex_s32Experimentalsve

Create linear series Arm’s documentation

svindex_s64Experimentalsve

Create linear series Arm’s documentation

svindex_u8Experimentalsve

Create linear series Arm’s documentation

svindex_u16Experimentalsve

Create linear series Arm’s documentation

svindex_u32Experimentalsve

Create linear series Arm’s documentation

svindex_u64Experimentalsve

Create linear series Arm’s documentation

svinsr_n_f32Experimentalsve

Insert scalar in shifted vector Arm’s documentation

svinsr_n_f64Experimentalsve

Insert scalar in shifted vector Arm’s documentation

svinsr_n_s8Experimentalsve

Insert scalar in shifted vector Arm’s documentation

svinsr_n_s16Experimentalsve

Insert scalar in shifted vector Arm’s documentation

svinsr_n_s32Experimentalsve

Insert scalar in shifted vector Arm’s documentation

svinsr_n_s64Experimentalsve

Insert scalar in shifted vector Arm’s documentation

svinsr_n_u8Experimentalsve

Insert scalar in shifted vector Arm’s documentation

svinsr_n_u16Experimentalsve

Insert scalar in shifted vector Arm’s documentation

svinsr_n_u32Experimentalsve

Insert scalar in shifted vector Arm’s documentation

svinsr_n_u64Experimentalsve

Insert scalar in shifted vector Arm’s documentation

svlasta_f32Experimentalsve

Extract element after last Arm’s documentation

svlasta_f64Experimentalsve

Extract element after last Arm’s documentation

svlasta_s8Experimentalsve

Extract element after last Arm’s documentation

svlasta_s16Experimentalsve

Extract element after last Arm’s documentation

svlasta_s32Experimentalsve

Extract element after last Arm’s documentation

svlasta_s64Experimentalsve

Extract element after last Arm’s documentation

svlasta_u8Experimentalsve

Extract element after last Arm’s documentation

svlasta_u16Experimentalsve

Extract element after last Arm’s documentation

svlasta_u32Experimentalsve

Extract element after last Arm’s documentation

svlasta_u64Experimentalsve

Extract element after last Arm’s documentation

svlastb_f32Experimentalsve

Extract last element Arm’s documentation

svlastb_f64Experimentalsve

Extract last element Arm’s documentation

svlastb_s8Experimentalsve

Extract last element Arm’s documentation

svlastb_s16Experimentalsve

Extract last element Arm’s documentation

svlastb_s32Experimentalsve

Extract last element Arm’s documentation

svlastb_s64Experimentalsve

Extract last element Arm’s documentation

svlastb_u8Experimentalsve

Extract last element Arm’s documentation

svlastb_u16Experimentalsve

Extract last element Arm’s documentation

svlastb_u32Experimentalsve

Extract last element Arm’s documentation

svlastb_u64Experimentalsve

Extract last element Arm’s documentation

svld1_f32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_f64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s32index_f32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s32index_s32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s32index_u32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s32offset_f32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s32offset_s32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s32offset_u32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s64index_f64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s64index_s64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s64index_u64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s64offset_f64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s64offset_s64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_s64offset_u64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32base_f32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32base_index_f32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32base_index_s32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32base_index_u32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32base_offset_f32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32base_offset_s32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32base_offset_u32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32base_s32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32base_u32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32index_f32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32index_s32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32index_u32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32offset_f32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32offset_s32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u32offset_u32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64base_f64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64base_index_f64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64base_index_s64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64base_index_u64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64base_offset_f64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64base_offset_s64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64base_offset_u64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64base_s64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64base_u64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64index_f64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64index_s64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64index_u64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64offset_f64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64offset_s64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_gather_u64offset_u64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_s8^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_s16^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_s32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_s64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_u8^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_u16^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_u32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_u64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_vnum_f32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_vnum_f64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_vnum_s8^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_vnum_s16^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_vnum_s32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_vnum_s64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_vnum_u8^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_vnum_u16^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_vnum_u32^⚠Experimentalsve

Unextended load Arm’s documentation

svld1_vnum_u64^⚠Experimentalsve

Unextended load Arm’s documentation

svld1ro_f32^⚠Experimentalsve and f64mm

Load and replicate 256 bits of data Arm’s documentation

svld1ro_f64^⚠Experimentalsve and f64mm

Load and replicate 256 bits of data Arm’s documentation

svld1ro_s8^⚠Experimentalsve and f64mm

Load and replicate 256 bits of data Arm’s documentation

svld1ro_s16^⚠Experimentalsve and f64mm

Load and replicate 256 bits of data Arm’s documentation

svld1ro_s32^⚠Experimentalsve and f64mm

Load and replicate 256 bits of data Arm’s documentation

svld1ro_s64^⚠Experimentalsve and f64mm

Load and replicate 256 bits of data Arm’s documentation

svld1ro_u8^⚠Experimentalsve and f64mm

Load and replicate 256 bits of data Arm’s documentation

svld1ro_u16^⚠Experimentalsve and f64mm

Load and replicate 256 bits of data Arm’s documentation

svld1ro_u32^⚠Experimentalsve and f64mm

Load and replicate 256 bits of data Arm’s documentation

svld1ro_u64^⚠Experimentalsve and f64mm

Load and replicate 256 bits of data Arm’s documentation

svld1rq_f32^⚠Experimentalsve

Load and replicate 128 bits of data Arm’s documentation

svld1rq_f64^⚠Experimentalsve

Load and replicate 128 bits of data Arm’s documentation

svld1rq_s8^⚠Experimentalsve

Load and replicate 128 bits of data Arm’s documentation

svld1rq_s16^⚠Experimentalsve

Load and replicate 128 bits of data Arm’s documentation

svld1rq_s32^⚠Experimentalsve

Load and replicate 128 bits of data Arm’s documentation

svld1rq_s64^⚠Experimentalsve

Load and replicate 128 bits of data Arm’s documentation

svld1rq_u8^⚠Experimentalsve

Load and replicate 128 bits of data Arm’s documentation

svld1rq_u16^⚠Experimentalsve

Load and replicate 128 bits of data Arm’s documentation

svld1rq_u32^⚠Experimentalsve

Load and replicate 128 bits of data Arm’s documentation

svld1rq_u64^⚠Experimentalsve

Load and replicate 128 bits of data Arm’s documentation

svld1sb_gather_s32offset_s32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_s32offset_u32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_s64offset_s64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_s64offset_u64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u32base_offset_s32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u32base_offset_u32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u32base_s32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u32base_u32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u32offset_s32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u32offset_u32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u64base_offset_s64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u64base_offset_u64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u64base_s64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u64base_u64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u64offset_s64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_gather_u64offset_u64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_s16^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_s32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_s64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_u16^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_u32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_u64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_vnum_s16^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_vnum_s32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_vnum_s64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_vnum_u16^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_vnum_u32^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sb_vnum_u64^⚠Experimentalsve

Load 8-bit data and sign-extend Arm’s documentation

svld1sh_gather_s32index_s32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_s32index_u32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_s32offset_s32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_s32offset_u32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_s64index_s64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_s64index_u64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_s64offset_s64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_s64offset_u64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u32base_index_s32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u32base_index_u32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u32base_offset_s32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u32base_offset_u32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u32base_s32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u32base_u32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u32index_s32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u32index_u32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u32offset_s32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u32offset_u32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u64base_index_s64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u64base_index_u64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u64base_offset_s64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u64base_offset_u64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u64base_s64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u64base_u64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u64index_s64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u64index_u64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u64offset_s64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_gather_u64offset_u64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_s32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_s64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_u32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_u64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_vnum_s32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_vnum_s64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_vnum_u32^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sh_vnum_u64^⚠Experimentalsve

Load 16-bit data and sign-extend Arm’s documentation

svld1sw_gather_s64index_s64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_s64index_u64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_s64offset_s64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_s64offset_u64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_u64base_index_s64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_u64base_index_u64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_u64base_offset_s64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_u64base_offset_u64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_u64base_s64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_u64base_u64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_u64index_s64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_u64index_u64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_u64offset_s64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_gather_u64offset_u64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_s64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_u64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_vnum_s64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1sw_vnum_u64^⚠Experimentalsve

Load 32-bit data and sign-extend Arm’s documentation

svld1ub_gather_s32offset_s32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_s32offset_u32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_s64offset_s64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_s64offset_u64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u32base_offset_s32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u32base_offset_u32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u32base_s32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u32base_u32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u32offset_s32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u32offset_u32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u64base_offset_s64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u64base_offset_u64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u64base_s64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u64base_u64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u64offset_s64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_gather_u64offset_u64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_s16^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_s32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_s64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_u16^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_u32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_u64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_vnum_s16^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_vnum_s32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_vnum_s64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_vnum_u16^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_vnum_u32^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1ub_vnum_u64^⚠Experimentalsve

Load 8-bit data and zero-extend Arm’s documentation

svld1uh_gather_s32index_s32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_s32index_u32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_s32offset_s32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_s32offset_u32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_s64index_s64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_s64index_u64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_s64offset_s64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_s64offset_u64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u32base_index_s32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u32base_index_u32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u32base_offset_s32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u32base_offset_u32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u32base_s32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u32base_u32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u32index_s32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u32index_u32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u32offset_s32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u32offset_u32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u64base_index_s64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u64base_index_u64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u64base_offset_s64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u64base_offset_u64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u64base_s64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u64base_u64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u64index_s64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u64index_u64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u64offset_s64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_gather_u64offset_u64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_s32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_s64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_u32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_u64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_vnum_s32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_vnum_s64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_vnum_u32^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uh_vnum_u64^⚠Experimentalsve

Load 16-bit data and zero-extend Arm’s documentation

svld1uw_gather_s64index_s64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_s64index_u64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_s64offset_s64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_s64offset_u64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_u64base_index_s64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_u64base_index_u64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_u64base_offset_s64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_u64base_offset_u64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_u64base_s64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_u64base_u64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_u64index_s64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_u64index_u64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_u64offset_s64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_gather_u64offset_u64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_s64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_u64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_vnum_s64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld1uw_vnum_u64^⚠Experimentalsve

Load 32-bit data and zero-extend Arm’s documentation

svld2_f32^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_f64^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_s8^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_s16^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_s32^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_s64^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_u8^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_u16^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_u32^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_u64^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_vnum_f32^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_vnum_f64^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_vnum_s8^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_vnum_s16^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_vnum_s32^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_vnum_s64^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_vnum_u8^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_vnum_u16^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_vnum_u32^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld2_vnum_u64^⚠Experimentalsve

Load two-element tuples into two vectors Arm’s documentation

svld3_f32^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_f64^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_s8^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_s16^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_s32^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_s64^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_u8^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_u16^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_u32^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_u64^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_vnum_f32^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_vnum_f64^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_vnum_s8^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_vnum_s16^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_vnum_s32^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_vnum_s64^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_vnum_u8^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_vnum_u16^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_vnum_u32^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld3_vnum_u64^⚠Experimentalsve

Load three-element tuples into three vectors Arm’s documentation

svld4_f32^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_f64^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_s8^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_s16^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_s32^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_s64^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_u8^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_u16^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_u32^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_u64^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_vnum_f32^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_vnum_f64^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_vnum_s8^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_vnum_s16^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_vnum_s32^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_vnum_s64^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_vnum_u8^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_vnum_u16^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_vnum_u32^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svld4_vnum_u64^⚠Experimentalsve

Load four-element tuples into four vectors Arm’s documentation

svldff1_f32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_f64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s32index_f32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s32index_s32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s32index_u32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s32offset_f32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s32offset_s32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s32offset_u32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s64index_f64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s64index_s64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s64index_u64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s64offset_f64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s64offset_s64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_s64offset_u64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32base_f32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32base_index_f32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32base_index_s32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32base_index_u32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32base_offset_f32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32base_offset_s32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32base_offset_u32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32base_s32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32base_u32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32index_f32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32index_s32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32index_u32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32offset_f32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32offset_s32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u32offset_u32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64base_f64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64base_index_f64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64base_index_s64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64base_index_u64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64base_offset_f64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64base_offset_s64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64base_offset_u64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64base_s64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64base_u64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64index_f64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64index_s64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64index_u64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64offset_f64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64offset_s64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_gather_u64offset_u64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_s8^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_s16^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_s32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_s64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_u8^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_u16^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_u32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_u64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_vnum_f32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_vnum_f64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_vnum_s8^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_vnum_s16^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_vnum_s32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_vnum_s64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_vnum_u8^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_vnum_u16^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_vnum_u32^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1_vnum_u64^⚠Experimentalsve

Unextended load, first-faulting Arm’s documentation

svldff1sb_gather_s32offset_s32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_s32offset_u32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_s64offset_s64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_s64offset_u64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u32base_offset_s32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u32base_offset_u32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u32base_s32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u32base_u32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u32offset_s32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u32offset_u32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u64base_offset_s64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u64base_offset_u64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u64base_s64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u64base_u64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u64offset_s64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_gather_u64offset_u64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_s16^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_s32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_s64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_u16^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_u32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_u64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_vnum_s16^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_vnum_s32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_vnum_s64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_vnum_u16^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_vnum_u32^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sb_vnum_u64^⚠Experimentalsve

Load 8-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_s32index_s32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_s32index_u32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_s32offset_s32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_s32offset_u32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_s64index_s64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_s64index_u64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_s64offset_s64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_s64offset_u64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u32base_index_s32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u32base_index_u32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u32base_offset_s32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u32base_offset_u32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u32base_s32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u32base_u32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u32index_s32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u32index_u32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u32offset_s32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u32offset_u32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u64base_index_s64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u64base_index_u64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u64base_offset_s64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u64base_offset_u64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u64base_s64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u64base_u64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u64index_s64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u64index_u64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u64offset_s64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_gather_u64offset_u64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_s32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_s64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_u32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_u64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_vnum_s32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_vnum_s64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_vnum_u32^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sh_vnum_u64^⚠Experimentalsve

Load 16-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_s64index_s64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_s64index_u64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_s64offset_s64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_s64offset_u64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_u64base_index_s64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_u64base_index_u64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_u64base_offset_s64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_u64base_offset_u64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_u64base_s64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_u64base_u64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_u64index_s64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_u64index_u64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_u64offset_s64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_gather_u64offset_u64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_s64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_u64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_vnum_s64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1sw_vnum_u64^⚠Experimentalsve

Load 32-bit data and sign-extend, first-faulting Arm’s documentation

svldff1ub_gather_s32offset_s32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_s32offset_u32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_s64offset_s64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_s64offset_u64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u32base_offset_s32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u32base_offset_u32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u32base_s32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u32base_u32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u32offset_s32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u32offset_u32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u64base_offset_s64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u64base_offset_u64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u64base_s64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u64base_u64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u64offset_s64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_gather_u64offset_u64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_s16^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_s32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_s64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_u16^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_u32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_u64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_vnum_s16^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_vnum_s32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_vnum_s64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_vnum_u16^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_vnum_u32^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1ub_vnum_u64^⚠Experimentalsve

Load 8-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_s32index_s32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_s32index_u32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_s32offset_s32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_s32offset_u32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_s64index_s64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_s64index_u64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_s64offset_s64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_s64offset_u64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u32base_index_s32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u32base_index_u32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u32base_offset_s32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u32base_offset_u32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u32base_s32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u32base_u32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u32index_s32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u32index_u32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u32offset_s32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u32offset_u32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u64base_index_s64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u64base_index_u64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u64base_offset_s64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u64base_offset_u64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u64base_s64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u64base_u64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u64index_s64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u64index_u64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u64offset_s64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_gather_u64offset_u64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_s32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_s64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_u32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_u64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_vnum_s32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_vnum_s64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_vnum_u32^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uh_vnum_u64^⚠Experimentalsve

Load 16-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_s64index_s64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_s64index_u64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_s64offset_s64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_s64offset_u64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_u64base_index_s64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_u64base_index_u64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_u64base_offset_s64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_u64base_offset_u64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_u64base_s64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_u64base_u64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_u64index_s64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_u64index_u64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_u64offset_s64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_gather_u64offset_u64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_s64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_u64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_vnum_s64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldff1uw_vnum_u64^⚠Experimentalsve

Load 32-bit data and zero-extend, first-faulting Arm’s documentation

svldnf1_f32^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_f64^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_s8^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_s16^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_s32^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_s64^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_u8^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_u16^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_u32^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_u64^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_vnum_f32^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_vnum_f64^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_vnum_s8^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_vnum_s16^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_vnum_s32^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_vnum_s64^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_vnum_u8^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_vnum_u16^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_vnum_u32^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1_vnum_u64^⚠Experimentalsve

Unextended load, non-faulting Arm’s documentation

svldnf1sb_s16^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sb_s32^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sb_s64^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sb_u16^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sb_u32^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sb_u64^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sb_vnum_s16^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sb_vnum_s32^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sb_vnum_s64^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sb_vnum_u16^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sb_vnum_u32^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sb_vnum_u64^⚠Experimentalsve

Load 8-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sh_s32^⚠Experimentalsve

Load 16-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sh_s64^⚠Experimentalsve

Load 16-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sh_u32^⚠Experimentalsve

Load 16-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sh_u64^⚠Experimentalsve

Load 16-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sh_vnum_s32^⚠Experimentalsve

Load 16-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sh_vnum_s64^⚠Experimentalsve

Load 16-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sh_vnum_u32^⚠Experimentalsve

Load 16-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sh_vnum_u64^⚠Experimentalsve

Load 16-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sw_s64^⚠Experimentalsve

Load 32-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sw_u64^⚠Experimentalsve

Load 32-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sw_vnum_s64^⚠Experimentalsve

Load 32-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1sw_vnum_u64^⚠Experimentalsve

Load 32-bit data and sign-extend, non-faulting Arm’s documentation

svldnf1ub_s16^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1ub_s32^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1ub_s64^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1ub_u16^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1ub_u32^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1ub_u64^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1ub_vnum_s16^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1ub_vnum_s32^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1ub_vnum_s64^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1ub_vnum_u16^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1ub_vnum_u32^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1ub_vnum_u64^⚠Experimentalsve

Load 8-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uh_s32^⚠Experimentalsve

Load 16-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uh_s64^⚠Experimentalsve

Load 16-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uh_u32^⚠Experimentalsve

Load 16-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uh_u64^⚠Experimentalsve

Load 16-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uh_vnum_s32^⚠Experimentalsve

Load 16-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uh_vnum_s64^⚠Experimentalsve

Load 16-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uh_vnum_u32^⚠Experimentalsve

Load 16-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uh_vnum_u64^⚠Experimentalsve

Load 16-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uw_s64^⚠Experimentalsve

Load 32-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uw_u64^⚠Experimentalsve

Load 32-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uw_vnum_s64^⚠Experimentalsve

Load 32-bit data and zero-extend, non-faulting Arm’s documentation

svldnf1uw_vnum_u64^⚠Experimentalsve

Load 32-bit data and zero-extend, non-faulting Arm’s documentation

svldnt1_f32^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_f64^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_s64index_f64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_s64index_s64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_s64index_u64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_s64offset_f64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_s64offset_s64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_s64offset_u64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32base_f32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32base_index_f32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32base_index_s32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32base_index_u32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32base_offset_f32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32base_offset_s32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32base_offset_u32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32base_s32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32base_u32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32offset_f32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32offset_s32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u32offset_u32^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64base_f64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64base_index_f64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64base_index_s64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64base_index_u64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64base_offset_f64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64base_offset_s64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64base_offset_u64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64base_s64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64base_u64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64index_f64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64index_s64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64index_u64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64offset_f64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64offset_s64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_gather_u64offset_u64^⚠Experimentalsve and sve2

Unextended load, non-temporal Arm’s documentation

svldnt1_s8^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_s16^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_s32^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_s64^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_u8^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_u16^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_u32^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_u64^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_vnum_f32^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_vnum_f64^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_vnum_s8^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_vnum_s16^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_vnum_s32^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_vnum_s64^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_vnum_u8^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_vnum_u16^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_vnum_u32^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1_vnum_u64^⚠Experimentalsve

Unextended load, non-temporal Arm’s documentation

svldnt1sb_gather_s64offset_s64^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_s64offset_u64^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u32base_offset_s32^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u32base_offset_u32^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u32base_s32^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u32base_u32^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u32offset_s32^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u32offset_u32^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u64base_offset_s64^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u64base_offset_u64^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u64base_s64^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u64base_u64^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u64offset_s64^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sb_gather_u64offset_u64^⚠Experimentalsve and sve2

Load 8-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_s64index_s64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_s64index_u64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_s64offset_s64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_s64offset_u64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u32base_index_s32^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u32base_index_u32^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u32base_offset_s32^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u32base_offset_u32^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u32base_s32^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u32base_u32^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u32offset_s32^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u32offset_u32^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u64base_index_s64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u64base_index_u64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u64base_offset_s64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u64base_offset_u64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u64base_s64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u64base_u64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u64index_s64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u64index_u64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u64offset_s64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sh_gather_u64offset_u64^⚠Experimentalsve and sve2

Load 16-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_s64index_s64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_s64index_u64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_s64offset_s64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_s64offset_u64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_u64base_index_s64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_u64base_index_u64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_u64base_offset_s64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_u64base_offset_u64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_u64base_s64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_u64base_u64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_u64index_s64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_u64index_u64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_u64offset_s64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1sw_gather_u64offset_u64^⚠Experimentalsve and sve2

Load 32-bit data and sign-extend, non-temporal Arm’s documentation

svldnt1ub_gather_s64offset_s64^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_s64offset_u64^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u32base_offset_s32^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u32base_offset_u32^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u32base_s32^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u32base_u32^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u32offset_s32^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u32offset_u32^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u64base_offset_s64^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u64base_offset_u64^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u64base_s64^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u64base_u64^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u64offset_s64^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1ub_gather_u64offset_u64^⚠Experimentalsve and sve2

Load 8-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_s64index_s64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_s64index_u64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_s64offset_s64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_s64offset_u64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u32base_index_s32^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u32base_index_u32^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u32base_offset_s32^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u32base_offset_u32^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u32base_s32^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u32base_u32^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u32offset_s32^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u32offset_u32^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u64base_index_s64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u64base_index_u64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u64base_offset_s64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u64base_offset_u64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u64base_s64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u64base_u64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u64index_s64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u64index_u64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u64offset_s64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uh_gather_u64offset_u64^⚠Experimentalsve and sve2

Load 16-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_s64index_s64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_s64index_u64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_s64offset_s64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_s64offset_u64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_u64base_index_s64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_u64base_index_u64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_u64base_offset_s64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_u64base_offset_u64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_u64base_s64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_u64base_u64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_u64index_s64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_u64index_u64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_u64offset_s64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svldnt1uw_gather_u64offset_u64^⚠Experimentalsve and sve2

Load 32-bit data and zero-extend, non-temporal Arm’s documentation

svlen_f32Experimentalsve

Count the number of elements in a full vector Arm’s documentation

svlen_f64Experimentalsve

Count the number of elements in a full vector Arm’s documentation

svlen_s8Experimentalsve

Count the number of elements in a full vector Arm’s documentation

svlen_s16Experimentalsve

Count the number of elements in a full vector Arm’s documentation

svlen_s32Experimentalsve

Count the number of elements in a full vector Arm’s documentation

svlen_s64Experimentalsve

Count the number of elements in a full vector Arm’s documentation

svlen_u8Experimentalsve

Count the number of elements in a full vector Arm’s documentation

svlen_u16Experimentalsve

Count the number of elements in a full vector Arm’s documentation

svlen_u32Experimentalsve

Count the number of elements in a full vector Arm’s documentation

svlen_u64Experimentalsve

Count the number of elements in a full vector Arm’s documentation

svlogb_f32_mExperimentalsve and sve2

Base 2 logarithm as integer Arm’s documentation

svlogb_f32_xExperimentalsve and sve2

Base 2 logarithm as integer Arm’s documentation

svlogb_f32_zExperimentalsve and sve2

Base 2 logarithm as integer Arm’s documentation

svlogb_f64_mExperimentalsve and sve2

Base 2 logarithm as integer Arm’s documentation

svlogb_f64_xExperimentalsve and sve2

Base 2 logarithm as integer Arm’s documentation

svlogb_f64_zExperimentalsve and sve2

Base 2 logarithm as integer Arm’s documentation

svlsl_n_s8_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_s8_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_s8_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_s16_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_s16_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_s16_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_s32_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_s32_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_s32_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_s64_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_s64_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_s64_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u8_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u8_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u8_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u16_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u16_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u16_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u32_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u32_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u32_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u64_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u64_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_n_u64_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_s8_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_s8_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_s8_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_s16_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_s16_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_s16_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_s32_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_s32_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_s32_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_s64_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_s64_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_s64_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_u8_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_u8_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_u8_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_u16_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_u16_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_u16_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_u32_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_u32_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_u32_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_u64_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_u64_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_u64_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_s8_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_s8_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_s8_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_s16_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_s16_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_s16_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_s32_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_s32_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_s32_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_u8_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_u8_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_u8_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_u16_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_u16_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_u16_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_u32_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_u32_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_n_u32_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_s8_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_s8_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_s8_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_s16_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_s16_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_s16_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_s32_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_s32_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_s32_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_u8_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_u8_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_u8_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_u16_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_u16_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_u16_zExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_u32_mExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_u32_xExperimentalsve

Logical shift left Arm’s documentation

svlsl_wide_u32_zExperimentalsve

Logical shift left Arm’s documentation

svlsr_n_u8_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_n_u8_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_n_u8_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_n_u16_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_n_u16_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_n_u16_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_n_u32_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_n_u32_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_n_u32_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_n_u64_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_n_u64_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_n_u64_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_u8_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_u8_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_u8_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_u16_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_u16_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_u16_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_u32_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_u32_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_u32_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_u64_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_u64_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_u64_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_n_u8_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_n_u8_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_n_u8_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_n_u16_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_n_u16_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_n_u16_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_n_u32_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_n_u32_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_n_u32_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_u8_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_u8_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_u8_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_u16_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_u16_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_u16_zExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_u32_mExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_u32_xExperimentalsve

Logical shift right Arm’s documentation

svlsr_wide_u32_zExperimentalsve

Logical shift right Arm’s documentation

svmad_f32_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_f32_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_f32_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_f64_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_f64_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_f64_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_f32_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_f32_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_f32_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_f64_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_f64_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_f64_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s8_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s8_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s8_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s16_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s16_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s16_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s32_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s32_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s32_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s64_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s64_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_s64_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u8_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u8_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u8_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u16_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u16_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u16_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u32_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u32_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u32_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u64_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u64_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_n_u64_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s8_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s8_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s8_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s16_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s16_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s16_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s32_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s32_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s32_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s64_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s64_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_s64_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u8_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u8_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u8_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u16_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u16_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u16_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u32_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u32_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u32_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u64_mExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u64_xExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmad_u64_zExperimentalsve

Multiply-add, multiplicand first Arm’s documentation

svmatch_s8Experimentalsve and sve2

Detect any matching elements Arm’s documentation

svmatch_s16Experimentalsve and sve2

Detect any matching elements Arm’s documentation

svmatch_u8Experimentalsve and sve2

Detect any matching elements Arm’s documentation

svmatch_u16Experimentalsve and sve2

Detect any matching elements Arm’s documentation

svmax_f32_mExperimentalsve

Maximum Arm’s documentation

svmax_f32_xExperimentalsve

Maximum Arm’s documentation

svmax_f32_zExperimentalsve

Maximum Arm’s documentation

svmax_f64_mExperimentalsve

Maximum Arm’s documentation

svmax_f64_xExperimentalsve

Maximum Arm’s documentation

svmax_f64_zExperimentalsve

Maximum Arm’s documentation

svmax_n_f32_mExperimentalsve

Maximum Arm’s documentation

svmax_n_f32_xExperimentalsve

Maximum Arm’s documentation

svmax_n_f32_zExperimentalsve

Maximum Arm’s documentation

svmax_n_f64_mExperimentalsve

Maximum Arm’s documentation

svmax_n_f64_xExperimentalsve

Maximum Arm’s documentation

svmax_n_f64_zExperimentalsve

Maximum Arm’s documentation

svmax_n_s8_mExperimentalsve

Maximum Arm’s documentation

svmax_n_s8_xExperimentalsve

Maximum Arm’s documentation

svmax_n_s8_zExperimentalsve

Maximum Arm’s documentation

svmax_n_s16_mExperimentalsve

Maximum Arm’s documentation

svmax_n_s16_xExperimentalsve

Maximum Arm’s documentation

svmax_n_s16_zExperimentalsve

Maximum Arm’s documentation

svmax_n_s32_mExperimentalsve

Maximum Arm’s documentation

svmax_n_s32_xExperimentalsve

Maximum Arm’s documentation

svmax_n_s32_zExperimentalsve

Maximum Arm’s documentation

svmax_n_s64_mExperimentalsve

Maximum Arm’s documentation

svmax_n_s64_xExperimentalsve

Maximum Arm’s documentation

svmax_n_s64_zExperimentalsve

Maximum Arm’s documentation

svmax_n_u8_mExperimentalsve

Maximum Arm’s documentation

svmax_n_u8_xExperimentalsve

Maximum Arm’s documentation

svmax_n_u8_zExperimentalsve

Maximum Arm’s documentation

svmax_n_u16_mExperimentalsve

Maximum Arm’s documentation

svmax_n_u16_xExperimentalsve

Maximum Arm’s documentation

svmax_n_u16_zExperimentalsve

Maximum Arm’s documentation

svmax_n_u32_mExperimentalsve

Maximum Arm’s documentation

svmax_n_u32_xExperimentalsve

Maximum Arm’s documentation

svmax_n_u32_zExperimentalsve

Maximum Arm’s documentation

svmax_n_u64_mExperimentalsve

Maximum Arm’s documentation

svmax_n_u64_xExperimentalsve

Maximum Arm’s documentation

svmax_n_u64_zExperimentalsve

Maximum Arm’s documentation

svmax_s8_mExperimentalsve

Maximum Arm’s documentation

svmax_s8_xExperimentalsve

Maximum Arm’s documentation

svmax_s8_zExperimentalsve

Maximum Arm’s documentation

svmax_s16_mExperimentalsve

Maximum Arm’s documentation

svmax_s16_xExperimentalsve

Maximum Arm’s documentation

svmax_s16_zExperimentalsve

Maximum Arm’s documentation

svmax_s32_mExperimentalsve

Maximum Arm’s documentation

svmax_s32_xExperimentalsve

Maximum Arm’s documentation

svmax_s32_zExperimentalsve

Maximum Arm’s documentation

svmax_s64_mExperimentalsve

Maximum Arm’s documentation

svmax_s64_xExperimentalsve

Maximum Arm’s documentation

svmax_s64_zExperimentalsve

Maximum Arm’s documentation

svmax_u8_mExperimentalsve

Maximum Arm’s documentation

svmax_u8_xExperimentalsve

Maximum Arm’s documentation

svmax_u8_zExperimentalsve

Maximum Arm’s documentation

svmax_u16_mExperimentalsve

Maximum Arm’s documentation

svmax_u16_xExperimentalsve

Maximum Arm’s documentation

svmax_u16_zExperimentalsve

Maximum Arm’s documentation

svmax_u32_mExperimentalsve

Maximum Arm’s documentation

svmax_u32_xExperimentalsve

Maximum Arm’s documentation

svmax_u32_zExperimentalsve

Maximum Arm’s documentation

svmax_u64_mExperimentalsve

Maximum Arm’s documentation

svmax_u64_xExperimentalsve

Maximum Arm’s documentation

svmax_u64_zExperimentalsve

Maximum Arm’s documentation

svmaxnm_f32_mExperimentalsve

Maximum number Arm’s documentation

svmaxnm_f32_xExperimentalsve

Maximum number Arm’s documentation

svmaxnm_f32_zExperimentalsve

Maximum number Arm’s documentation

svmaxnm_f64_mExperimentalsve

Maximum number Arm’s documentation

svmaxnm_f64_xExperimentalsve

Maximum number Arm’s documentation

svmaxnm_f64_zExperimentalsve

Maximum number Arm’s documentation

svmaxnm_n_f32_mExperimentalsve

Maximum number Arm’s documentation

svmaxnm_n_f32_xExperimentalsve

Maximum number Arm’s documentation

svmaxnm_n_f32_zExperimentalsve

Maximum number Arm’s documentation

svmaxnm_n_f64_mExperimentalsve

Maximum number Arm’s documentation

svmaxnm_n_f64_xExperimentalsve

Maximum number Arm’s documentation

svmaxnm_n_f64_zExperimentalsve

Maximum number Arm’s documentation

svmaxnmp_f32_mExperimentalsve and sve2

Maximum number pairwise Arm’s documentation

svmaxnmp_f32_xExperimentalsve and sve2

Maximum number pairwise Arm’s documentation

svmaxnmp_f64_mExperimentalsve and sve2

Maximum number pairwise Arm’s documentation

svmaxnmp_f64_xExperimentalsve and sve2

Maximum number pairwise Arm’s documentation

svmaxnmv_f32Experimentalsve

Maximum number reduction to scalar Arm’s documentation

svmaxnmv_f64Experimentalsve

Maximum number reduction to scalar Arm’s documentation

svmaxp_f32_mExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_f32_xExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_f64_mExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_f64_xExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_s8_mExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_s8_xExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_s16_mExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_s16_xExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_s32_mExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_s32_xExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_s64_mExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_s64_xExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_u8_mExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_u8_xExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_u16_mExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_u16_xExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_u32_mExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_u32_xExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_u64_mExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxp_u64_xExperimentalsve and sve2

Maximum pairwise Arm’s documentation

svmaxv_f32Experimentalsve

Maximum reduction to scalar Arm’s documentation

svmaxv_f64Experimentalsve

Maximum reduction to scalar Arm’s documentation

svmaxv_s8Experimentalsve

Maximum reduction to scalar Arm’s documentation

svmaxv_s16Experimentalsve

Maximum reduction to scalar Arm’s documentation

svmaxv_s32Experimentalsve

Maximum reduction to scalar Arm’s documentation

svmaxv_s64Experimentalsve

Maximum reduction to scalar Arm’s documentation

svmaxv_u8Experimentalsve

Maximum reduction to scalar Arm’s documentation

svmaxv_u16Experimentalsve

Maximum reduction to scalar Arm’s documentation

svmaxv_u32Experimentalsve

Maximum reduction to scalar Arm’s documentation

svmaxv_u64Experimentalsve

Maximum reduction to scalar Arm’s documentation

svmin_f32_mExperimentalsve

Minimum Arm’s documentation

svmin_f32_xExperimentalsve

Minimum Arm’s documentation

svmin_f32_zExperimentalsve

Minimum Arm’s documentation

svmin_f64_mExperimentalsve

Minimum Arm’s documentation

svmin_f64_xExperimentalsve

Minimum Arm’s documentation

svmin_f64_zExperimentalsve

Minimum Arm’s documentation

svmin_n_f32_mExperimentalsve

Minimum Arm’s documentation

svmin_n_f32_xExperimentalsve

Minimum Arm’s documentation

svmin_n_f32_zExperimentalsve

Minimum Arm’s documentation

svmin_n_f64_mExperimentalsve

Minimum Arm’s documentation

svmin_n_f64_xExperimentalsve

Minimum Arm’s documentation

svmin_n_f64_zExperimentalsve

Minimum Arm’s documentation

svmin_n_s8_mExperimentalsve

Minimum Arm’s documentation

svmin_n_s8_xExperimentalsve

Minimum Arm’s documentation

svmin_n_s8_zExperimentalsve

Minimum Arm’s documentation

svmin_n_s16_mExperimentalsve

Minimum Arm’s documentation

svmin_n_s16_xExperimentalsve

Minimum Arm’s documentation

svmin_n_s16_zExperimentalsve

Minimum Arm’s documentation

svmin_n_s32_mExperimentalsve

Minimum Arm’s documentation

svmin_n_s32_xExperimentalsve

Minimum Arm’s documentation

svmin_n_s32_zExperimentalsve

Minimum Arm’s documentation

svmin_n_s64_mExperimentalsve

Minimum Arm’s documentation

svmin_n_s64_xExperimentalsve

Minimum Arm’s documentation

svmin_n_s64_zExperimentalsve

Minimum Arm’s documentation

svmin_n_u8_mExperimentalsve

Minimum Arm’s documentation

svmin_n_u8_xExperimentalsve

Minimum Arm’s documentation

svmin_n_u8_zExperimentalsve

Minimum Arm’s documentation

svmin_n_u16_mExperimentalsve

Minimum Arm’s documentation

svmin_n_u16_xExperimentalsve

Minimum Arm’s documentation

svmin_n_u16_zExperimentalsve

Minimum Arm’s documentation

svmin_n_u32_mExperimentalsve

Minimum Arm’s documentation

svmin_n_u32_xExperimentalsve

Minimum Arm’s documentation

svmin_n_u32_zExperimentalsve

Minimum Arm’s documentation

svmin_n_u64_mExperimentalsve

Minimum Arm’s documentation

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Minimum Arm’s documentation

svmin_n_u64_zExperimentalsve

Minimum Arm’s documentation

svmin_s8_mExperimentalsve

Minimum Arm’s documentation

svmin_s8_xExperimentalsve

Minimum Arm’s documentation

svmin_s8_zExperimentalsve

Minimum Arm’s documentation

svmin_s16_mExperimentalsve

Minimum Arm’s documentation

svmin_s16_xExperimentalsve

Minimum Arm’s documentation

svmin_s16_zExperimentalsve

Minimum Arm’s documentation

svmin_s32_mExperimentalsve

Minimum Arm’s documentation

svmin_s32_xExperimentalsve

Minimum Arm’s documentation

svmin_s32_zExperimentalsve

Minimum Arm’s documentation

svmin_s64_mExperimentalsve

Minimum Arm’s documentation

svmin_s64_xExperimentalsve

Minimum Arm’s documentation

svmin_s64_zExperimentalsve

Minimum Arm’s documentation

svmin_u8_mExperimentalsve

Minimum Arm’s documentation

svmin_u8_xExperimentalsve

Minimum Arm’s documentation

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svmin_u16_mExperimentalsve

Minimum Arm’s documentation

svmin_u16_xExperimentalsve

Minimum Arm’s documentation

svmin_u16_zExperimentalsve

Minimum Arm’s documentation

svmin_u32_mExperimentalsve

Minimum Arm’s documentation

svmin_u32_xExperimentalsve

Minimum Arm’s documentation

svmin_u32_zExperimentalsve

Minimum Arm’s documentation

svmin_u64_mExperimentalsve

Minimum Arm’s documentation

svmin_u64_xExperimentalsve

Minimum Arm’s documentation

svmin_u64_zExperimentalsve

Minimum Arm’s documentation

svminnm_f32_mExperimentalsve

Minimum number Arm’s documentation

svminnm_f32_xExperimentalsve

Minimum number Arm’s documentation

svminnm_f32_zExperimentalsve

Minimum number Arm’s documentation

svminnm_f64_mExperimentalsve

Minimum number Arm’s documentation

svminnm_f64_xExperimentalsve

Minimum number Arm’s documentation

svminnm_f64_zExperimentalsve

Minimum number Arm’s documentation

svminnm_n_f32_mExperimentalsve

Minimum number Arm’s documentation

svminnm_n_f32_xExperimentalsve

Minimum number Arm’s documentation

svminnm_n_f32_zExperimentalsve

Minimum number Arm’s documentation

svminnm_n_f64_mExperimentalsve

Minimum number Arm’s documentation

svminnm_n_f64_xExperimentalsve

Minimum number Arm’s documentation

svminnm_n_f64_zExperimentalsve

Minimum number Arm’s documentation

svminnmp_f32_mExperimentalsve and sve2

Minimum number pairwise Arm’s documentation

svminnmp_f32_xExperimentalsve and sve2

Minimum number pairwise Arm’s documentation

svminnmp_f64_mExperimentalsve and sve2

Minimum number pairwise Arm’s documentation

svminnmp_f64_xExperimentalsve and sve2

Minimum number pairwise Arm’s documentation

svminnmv_f32Experimentalsve

Minimum number reduction to scalar Arm’s documentation

svminnmv_f64Experimentalsve

Minimum number reduction to scalar Arm’s documentation

svminp_f32_mExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_f32_xExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_f64_mExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_f64_xExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_s8_mExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_s8_xExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_s16_mExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_s16_xExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_s32_mExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_s32_xExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_s64_mExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_s64_xExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_u8_mExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_u8_xExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_u16_mExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_u16_xExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_u32_mExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_u32_xExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_u64_mExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminp_u64_xExperimentalsve and sve2

Minimum pairwise Arm’s documentation

svminv_f32Experimentalsve

Minimum reduction to scalar Arm’s documentation

svminv_f64Experimentalsve

Minimum reduction to scalar Arm’s documentation

svminv_s8Experimentalsve

Minimum reduction to scalar Arm’s documentation

svminv_s16Experimentalsve

Minimum reduction to scalar Arm’s documentation

svminv_s32Experimentalsve

Minimum reduction to scalar Arm’s documentation

svminv_s64Experimentalsve

Minimum reduction to scalar Arm’s documentation

svminv_u8Experimentalsve

Minimum reduction to scalar Arm’s documentation

svminv_u16Experimentalsve

Minimum reduction to scalar Arm’s documentation

svminv_u32Experimentalsve

Minimum reduction to scalar Arm’s documentation

svminv_u64Experimentalsve

Minimum reduction to scalar Arm’s documentation

svmla_f32_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_f32_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_f32_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_f64_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_f64_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_f64_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_lane_f32Experimentalsve

Multiply-add, addend first Arm’s documentation

svmla_lane_f64Experimentalsve

Multiply-add, addend first Arm’s documentation

svmla_lane_s16Experimentalsve and sve2

Multiply-add, addend first Arm’s documentation

svmla_lane_s32Experimentalsve and sve2

Multiply-add, addend first Arm’s documentation

svmla_lane_s64Experimentalsve and sve2

Multiply-add, addend first Arm’s documentation

svmla_lane_u16Experimentalsve and sve2

Multiply-add, addend first Arm’s documentation

svmla_lane_u32Experimentalsve and sve2

Multiply-add, addend first Arm’s documentation

svmla_lane_u64Experimentalsve and sve2

Multiply-add, addend first Arm’s documentation

svmla_n_f32_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_f32_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_f32_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_f64_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_f64_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_f64_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s8_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s8_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s8_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s16_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s16_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s16_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s32_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s32_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s32_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s64_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s64_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_s64_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u8_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u8_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u8_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u16_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u16_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u16_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u32_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u32_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u32_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u64_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u64_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_n_u64_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s8_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s8_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s8_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s16_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s16_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s16_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s32_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s32_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s32_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s64_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s64_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_s64_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u8_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u8_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u8_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u16_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u16_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u16_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u32_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u32_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u32_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u64_mExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u64_xExperimentalsve

Multiply-add, addend first Arm’s documentation

svmla_u64_zExperimentalsve

Multiply-add, addend first Arm’s documentation

svmlalb_lane_s32Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_lane_s64Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_lane_u32Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_lane_u64Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_n_s16Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_n_s32Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_n_s64Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_n_u16Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_n_u32Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_n_u64Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_s16Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_s32Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_s64Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_u16Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_u32Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalb_u64Experimentalsve and sve2

Multiply-add long (bottom) Arm’s documentation

svmlalt_lane_s32Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_lane_s64Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_lane_u32Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_lane_u64Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_n_s16Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_n_s32Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_n_s64Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_n_u16Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_n_u32Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_n_u64Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_s16Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_s32Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_s64Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_u16Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_u32Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmlalt_u64Experimentalsve and sve2

Multiply-add long (top) Arm’s documentation

svmls_f32_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_f32_xExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_f32_zExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_f64_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_f64_xExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_f64_zExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_lane_f32Experimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_lane_f64Experimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_lane_s16Experimentalsve and sve2

Multiply-subtract, minuend first Arm’s documentation

svmls_lane_s32Experimentalsve and sve2

Multiply-subtract, minuend first Arm’s documentation

svmls_lane_s64Experimentalsve and sve2

Multiply-subtract, minuend first Arm’s documentation

svmls_lane_u16Experimentalsve and sve2

Multiply-subtract, minuend first Arm’s documentation

svmls_lane_u32Experimentalsve and sve2

Multiply-subtract, minuend first Arm’s documentation

svmls_lane_u64Experimentalsve and sve2

Multiply-subtract, minuend first Arm’s documentation

svmls_n_f32_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_f32_xExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_f32_zExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_f64_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_f64_xExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_f64_zExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_s8_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_s8_xExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_s8_zExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_s16_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_s16_xExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_s16_zExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_s32_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_s32_xExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_s32_zExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_s64_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_s64_xExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

svmls_n_u8_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

svmls_n_u16_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

svmls_n_u16_zExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_u32_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_u32_xExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_u32_zExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_n_u64_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

svmls_s8_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

svmls_s16_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

svmls_s32_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

svmls_u16_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

svmls_u16_zExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

svmls_u32_mExperimentalsve

Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

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Multiply-subtract, minuend first Arm’s documentation

svmlslb_lane_s32Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_lane_s64Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_lane_u32Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_lane_u64Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_n_s16Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_n_s32Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_n_s64Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_n_u16Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_n_u32Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_n_u64Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_s16Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_s32Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_s64Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_u16Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_u32Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslb_u64Experimentalsve and sve2

Multiply-subtract long (bottom) Arm’s documentation

svmlslt_lane_s32Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_lane_s64Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_lane_u32Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_lane_u64Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_n_s16Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_n_s32Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_n_s64Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_n_u16Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_n_u32Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_n_u64Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_s16Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_s32Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_s64Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_u16Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_u32Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmlslt_u64Experimentalsve and sve2

Multiply-subtract long (top) Arm’s documentation

svmmla_f32Experimentalsve and f32mm

Matrix multiply-accumulate Arm’s documentation

svmmla_f64Experimentalsve and f64mm

Matrix multiply-accumulate Arm’s documentation

svmmla_s32Experimentalsve and i8mm

Matrix multiply-accumulate Arm’s documentation

svmmla_u32Experimentalsve and i8mm

Matrix multiply-accumulate Arm’s documentation

svmov_b_zExperimentalsve

Move Arm’s documentation

svmovlb_s16Experimentalsve and sve2

Move long (bottom) Arm’s documentation

svmovlb_s32Experimentalsve and sve2

Move long (bottom) Arm’s documentation

svmovlb_s64Experimentalsve and sve2

Move long (bottom) Arm’s documentation

svmovlb_u16Experimentalsve and sve2

Move long (bottom) Arm’s documentation

svmovlb_u32Experimentalsve and sve2

Move long (bottom) Arm’s documentation

svmovlb_u64Experimentalsve and sve2

Move long (bottom) Arm’s documentation

svmovlt_s16Experimentalsve and sve2

Move long (top) Arm’s documentation

svmovlt_s32Experimentalsve and sve2

Move long (top) Arm’s documentation

svmovlt_s64Experimentalsve and sve2

Move long (top) Arm’s documentation

svmovlt_u16Experimentalsve and sve2

Move long (top) Arm’s documentation

svmovlt_u32Experimentalsve and sve2

Move long (top) Arm’s documentation

svmovlt_u64Experimentalsve and sve2

Move long (top) Arm’s documentation

svmsb_f32_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_f32_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_f64_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_f64_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_s16_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

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Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_s32_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_s32_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_s32_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_s64_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_s64_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_s64_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u8_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u8_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u8_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u16_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u16_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u16_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u32_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u32_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u32_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u64_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u64_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_n_u64_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s8_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s8_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s8_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s16_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s16_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s16_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s32_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s32_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s32_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s64_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s64_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_s64_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u8_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u8_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u8_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u16_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u16_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u16_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u32_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u32_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u32_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u64_mExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u64_xExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmsb_u64_zExperimentalsve

Multiply-subtract, multiplicand first Arm’s documentation

svmul_f32_mExperimentalsve

Multiply Arm’s documentation

svmul_f32_xExperimentalsve

Multiply Arm’s documentation

svmul_f32_zExperimentalsve

Multiply Arm’s documentation

svmul_f64_mExperimentalsve

Multiply Arm’s documentation

svmul_f64_xExperimentalsve

Multiply Arm’s documentation

svmul_f64_zExperimentalsve

Multiply Arm’s documentation

svmul_lane_f32Experimentalsve and sve2

Multiply Arm’s documentation

svmul_lane_f64Experimentalsve and sve2

Multiply Arm’s documentation

svmul_lane_s16Experimentalsve and sve2

Multiply Arm’s documentation

svmul_lane_s32Experimentalsve and sve2

Multiply Arm’s documentation

svmul_lane_s64Experimentalsve and sve2

Multiply Arm’s documentation

svmul_lane_u16Experimentalsve and sve2

Multiply Arm’s documentation

svmul_lane_u32Experimentalsve and sve2

Multiply Arm’s documentation

svmul_lane_u64Experimentalsve and sve2

Multiply Arm’s documentation

svmul_n_f32_mExperimentalsve

Multiply Arm’s documentation

svmul_n_f32_xExperimentalsve

Multiply Arm’s documentation

svmul_n_f32_zExperimentalsve

Multiply Arm’s documentation

svmul_n_f64_mExperimentalsve

Multiply Arm’s documentation

svmul_n_f64_xExperimentalsve

Multiply Arm’s documentation

svmul_n_f64_zExperimentalsve

Multiply Arm’s documentation

svmul_n_s8_mExperimentalsve

Multiply Arm’s documentation

svmul_n_s8_xExperimentalsve

Multiply Arm’s documentation

svmul_n_s8_zExperimentalsve

Multiply Arm’s documentation

svmul_n_s16_mExperimentalsve

Multiply Arm’s documentation

svmul_n_s16_xExperimentalsve

Multiply Arm’s documentation

svmul_n_s16_zExperimentalsve

Multiply Arm’s documentation

svmul_n_s32_mExperimentalsve

Multiply Arm’s documentation

svmul_n_s32_xExperimentalsve

Multiply Arm’s documentation

svmul_n_s32_zExperimentalsve

Multiply Arm’s documentation

svmul_n_s64_mExperimentalsve

Multiply Arm’s documentation

svmul_n_s64_xExperimentalsve

Multiply Arm’s documentation

svmul_n_s64_zExperimentalsve

Multiply Arm’s documentation

svmul_n_u8_mExperimentalsve

Multiply Arm’s documentation

svmul_n_u8_xExperimentalsve

Multiply Arm’s documentation

svmul_n_u8_zExperimentalsve

Multiply Arm’s documentation

svmul_n_u16_mExperimentalsve

Multiply Arm’s documentation

svmul_n_u16_xExperimentalsve

Multiply Arm’s documentation

svmul_n_u16_zExperimentalsve

Multiply Arm’s documentation

svmul_n_u32_mExperimentalsve

Multiply Arm’s documentation

svmul_n_u32_xExperimentalsve

Multiply Arm’s documentation

svmul_n_u32_zExperimentalsve

Multiply Arm’s documentation

svmul_n_u64_mExperimentalsve

Multiply Arm’s documentation

svmul_n_u64_xExperimentalsve

Multiply Arm’s documentation

svmul_n_u64_zExperimentalsve

Multiply Arm’s documentation

svmul_s8_mExperimentalsve

Multiply Arm’s documentation

svmul_s8_xExperimentalsve

Multiply Arm’s documentation

svmul_s8_zExperimentalsve

Multiply Arm’s documentation

svmul_s16_mExperimentalsve

Multiply Arm’s documentation

svmul_s16_xExperimentalsve

Multiply Arm’s documentation

svmul_s16_zExperimentalsve

Multiply Arm’s documentation

svmul_s32_mExperimentalsve

Multiply Arm’s documentation

svmul_s32_xExperimentalsve

Multiply Arm’s documentation

svmul_s32_zExperimentalsve

Multiply Arm’s documentation

svmul_s64_mExperimentalsve

Multiply Arm’s documentation

svmul_s64_xExperimentalsve

Multiply Arm’s documentation

svmul_s64_zExperimentalsve

Multiply Arm’s documentation

svmul_u8_mExperimentalsve

Multiply Arm’s documentation

svmul_u8_xExperimentalsve

Multiply Arm’s documentation

svmul_u8_zExperimentalsve

Multiply Arm’s documentation

svmul_u16_mExperimentalsve

Multiply Arm’s documentation

svmul_u16_xExperimentalsve

Multiply Arm’s documentation

svmul_u16_zExperimentalsve

Multiply Arm’s documentation

svmul_u32_mExperimentalsve

Multiply Arm’s documentation

svmul_u32_xExperimentalsve

Multiply Arm’s documentation

svmul_u32_zExperimentalsve

Multiply Arm’s documentation

svmul_u64_mExperimentalsve

Multiply Arm’s documentation

svmul_u64_xExperimentalsve

Multiply Arm’s documentation

svmul_u64_zExperimentalsve

Multiply Arm’s documentation

svmulh_n_s8_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_s8_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_s8_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_s16_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_s16_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_s16_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_s32_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_s32_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_s32_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_s64_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_s64_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_s64_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u8_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u8_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u8_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u16_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u16_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u16_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u32_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u32_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u32_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u64_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u64_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_n_u64_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s8_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s8_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s8_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s16_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s16_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s16_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s32_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s32_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s32_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s64_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s64_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_s64_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u8_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u8_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u8_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u16_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u16_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u16_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u32_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u32_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u32_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u64_mExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u64_xExperimentalsve

Multiply, returning high-half Arm’s documentation

svmulh_u64_zExperimentalsve

Multiply, returning high-half Arm’s documentation

svmullb_lane_s32Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_lane_s64Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_lane_u32Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_lane_u64Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_n_s16Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_n_s32Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_n_s64Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_n_u16Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_n_u32Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_n_u64Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_s16Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_s32Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_s64Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_u16Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_u32Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullb_u64Experimentalsve and sve2

Multiply long (bottom) Arm’s documentation

svmullt_lane_s32Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_lane_s64Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_lane_u32Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_lane_u64Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_n_s16Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_n_s32Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_n_s64Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_n_u16Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_n_u32Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_n_u64Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_s16Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_s32Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_s64Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_u16Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_u32Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmullt_u64Experimentalsve and sve2

Multiply long (top) Arm’s documentation

svmulx_f32_mExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svmulx_f32_xExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svmulx_f32_zExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svmulx_f64_mExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svmulx_f64_xExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svmulx_f64_zExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svmulx_n_f32_mExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svmulx_n_f32_xExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svmulx_n_f32_zExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svmulx_n_f64_mExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svmulx_n_f64_xExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svmulx_n_f64_zExperimentalsve

Multiply extended (∞×0=2) Arm’s documentation

svnand_b_zExperimentalsve

Bitwise NAND Arm’s documentation

svnbsl_n_s8Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_n_s16Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_n_s32Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_n_s64Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_n_u8Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_n_u16Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_n_u32Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_n_u64Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_s8Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_s16Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_s32Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_s64Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_u8Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_u16Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_u32Experimentalsve and sve2

Bitwise select Arm’s documentation

svnbsl_u64Experimentalsve and sve2

Bitwise select Arm’s documentation

svneg_f32_mExperimentalsve

Negate Arm’s documentation

svneg_f32_xExperimentalsve

Negate Arm’s documentation

svneg_f32_zExperimentalsve

Negate Arm’s documentation

svneg_f64_mExperimentalsve

Negate Arm’s documentation

svneg_f64_xExperimentalsve

Negate Arm’s documentation

svneg_f64_zExperimentalsve

Negate Arm’s documentation

svneg_s8_mExperimentalsve

Negate Arm’s documentation

svneg_s8_xExperimentalsve

Negate Arm’s documentation

svneg_s8_zExperimentalsve

Negate Arm’s documentation

svneg_s16_mExperimentalsve

Negate Arm’s documentation

svneg_s16_xExperimentalsve

Negate Arm’s documentation

svneg_s16_zExperimentalsve

Negate Arm’s documentation

svneg_s32_mExperimentalsve

Negate Arm’s documentation

svneg_s32_xExperimentalsve

Negate Arm’s documentation

svneg_s32_zExperimentalsve

Negate Arm’s documentation

svneg_s64_mExperimentalsve

Negate Arm’s documentation

svneg_s64_xExperimentalsve

Negate Arm’s documentation

svneg_s64_zExperimentalsve

Negate Arm’s documentation

svnmad_f32_mExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmad_f32_xExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmad_f32_zExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmad_f64_mExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmad_f64_xExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmad_f64_zExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmad_n_f32_mExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmad_n_f32_xExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmad_n_f32_zExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmad_n_f64_mExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmad_n_f64_xExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmad_n_f64_zExperimentalsve

Negated multiply-add, multiplicand first Arm’s documentation

svnmatch_s8Experimentalsve and sve2

Detect no matching elements Arm’s documentation

svnmatch_s16Experimentalsve and sve2

Detect no matching elements Arm’s documentation

svnmatch_u8Experimentalsve and sve2

Detect no matching elements Arm’s documentation

svnmatch_u16Experimentalsve and sve2

Detect no matching elements Arm’s documentation

svnmla_f32_mExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmla_f32_xExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmla_f32_zExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmla_f64_mExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmla_f64_xExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmla_f64_zExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmla_n_f32_mExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmla_n_f32_xExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmla_n_f32_zExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmla_n_f64_mExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmla_n_f64_xExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmla_n_f64_zExperimentalsve

Negated multiply-add, addend first Arm’s documentation

svnmls_f32_mExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmls_f32_xExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmls_f32_zExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmls_f64_mExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmls_f64_xExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmls_f64_zExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmls_n_f32_mExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmls_n_f32_xExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmls_n_f32_zExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmls_n_f64_mExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmls_n_f64_xExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmls_n_f64_zExperimentalsve

Negated multiply-subtract, minuend first Arm’s documentation

svnmsb_f32_mExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnmsb_f32_xExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnmsb_f32_zExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnmsb_f64_mExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnmsb_f64_xExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnmsb_f64_zExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnmsb_n_f32_mExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnmsb_n_f32_xExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnmsb_n_f32_zExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnmsb_n_f64_mExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnmsb_n_f64_xExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnmsb_n_f64_zExperimentalsve

Negated multiply-subtract, multiplicand first Arm’s documentation

svnor_b_zExperimentalsve

Bitwise NOR Arm’s documentation

svnot_b_zExperimentalsve

Bitwise invert Arm’s documentation

svnot_s8_mExperimentalsve

Bitwise invert Arm’s documentation

svnot_s8_xExperimentalsve

Bitwise invert Arm’s documentation

svnot_s8_zExperimentalsve

Bitwise invert Arm’s documentation

svnot_s16_mExperimentalsve

Bitwise invert Arm’s documentation

svnot_s16_xExperimentalsve

Bitwise invert Arm’s documentation

svnot_s16_zExperimentalsve

Bitwise invert Arm’s documentation

svnot_s32_mExperimentalsve

Bitwise invert Arm’s documentation

svnot_s32_xExperimentalsve

Bitwise invert Arm’s documentation

svnot_s32_zExperimentalsve

Bitwise invert Arm’s documentation

svnot_s64_mExperimentalsve

Bitwise invert Arm’s documentation

svnot_s64_xExperimentalsve

Bitwise invert Arm’s documentation

svnot_s64_zExperimentalsve

Bitwise invert Arm’s documentation

svnot_u8_mExperimentalsve

Bitwise invert Arm’s documentation

svnot_u8_xExperimentalsve

Bitwise invert Arm’s documentation

svnot_u8_zExperimentalsve

Bitwise invert Arm’s documentation

svnot_u16_mExperimentalsve

Bitwise invert Arm’s documentation

svnot_u16_xExperimentalsve

Bitwise invert Arm’s documentation

svnot_u16_zExperimentalsve

Bitwise invert Arm’s documentation

svnot_u32_mExperimentalsve

Bitwise invert Arm’s documentation

svnot_u32_xExperimentalsve

Bitwise invert Arm’s documentation

svnot_u32_zExperimentalsve

Bitwise invert Arm’s documentation

svnot_u64_mExperimentalsve

Bitwise invert Arm’s documentation

svnot_u64_xExperimentalsve

Bitwise invert Arm’s documentation

svnot_u64_zExperimentalsve

Bitwise invert Arm’s documentation

svorn_b_zExperimentalsve

Bitwise inclusive OR, inverting second argument Arm’s documentation

svorr_b_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s8_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s8_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s8_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s16_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s16_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s16_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s32_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s32_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s32_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s64_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s64_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_s64_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u8_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u8_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u8_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u16_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u16_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u16_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u32_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u32_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u32_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u64_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u64_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_n_u64_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s8_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s8_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s8_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s16_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s16_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s16_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s32_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s32_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s32_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s64_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s64_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_s64_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u8_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u8_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u8_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u16_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u16_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u16_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u32_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u32_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u32_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u64_mExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u64_xExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorr_u64_zExperimentalsve

Bitwise inclusive OR Arm’s documentation

svorv_s8Experimentalsve

Bitwise inclusive OR reduction to scalar Arm’s documentation

svorv_s16Experimentalsve

Bitwise inclusive OR reduction to scalar Arm’s documentation

svorv_s32Experimentalsve

Bitwise inclusive OR reduction to scalar Arm’s documentation

svorv_s64Experimentalsve

Bitwise inclusive OR reduction to scalar Arm’s documentation

svorv_u8Experimentalsve

Bitwise inclusive OR reduction to scalar Arm’s documentation

svorv_u16Experimentalsve

Bitwise inclusive OR reduction to scalar Arm’s documentation

svorv_u32Experimentalsve

Bitwise inclusive OR reduction to scalar Arm’s documentation

svorv_u64Experimentalsve

Bitwise inclusive OR reduction to scalar Arm’s documentation

svpfalse_bExperimentalsve

Set all predicate elements to false Arm’s documentation

svpfirst_bExperimentalsve

Set the first active predicate element to true Arm’s documentation

svpmul_n_u8Experimentalsve and sve2

Polynomial multiply Arm’s documentation

svpmul_u8Experimentalsve and sve2

Polynomial multiply Arm’s documentation

svpmullb_n_u16Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (bottom) Arm’s documentation

svpmullb_n_u64Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (bottom) Arm’s documentation

svpmullb_pair_n_u8Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (bottom) Arm’s documentation

svpmullb_pair_n_u32Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (bottom) Arm’s documentation

svpmullb_pair_n_u64Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (bottom) Arm’s documentation

svpmullb_pair_u8Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (bottom) Arm’s documentation

svpmullb_pair_u32Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (bottom) Arm’s documentation

svpmullb_pair_u64Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (bottom) Arm’s documentation

svpmullb_u16Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (bottom) Arm’s documentation

svpmullb_u64Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (bottom) Arm’s documentation

svpmullt_n_u16Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (top) Arm’s documentation

svpmullt_n_u64Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (top) Arm’s documentation

svpmullt_pair_n_u8Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (top) Arm’s documentation

svpmullt_pair_n_u32Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (top) Arm’s documentation

svpmullt_pair_n_u64Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (top) Arm’s documentation

svpmullt_pair_u8Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (top) Arm’s documentation

svpmullt_pair_u32Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (top) Arm’s documentation

svpmullt_pair_u64Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (top) Arm’s documentation

svpmullt_u16Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (top) Arm’s documentation

svpmullt_u64Experimentalsve and sve2 and sve2-aes

Polynomial multiply long (top) Arm’s documentation

svpnext_b8Experimentalsve

Find next active predicate Arm’s documentation

svpnext_b16Experimentalsve

Find next active predicate Arm’s documentation

svpnext_b32Experimentalsve

Find next active predicate Arm’s documentation

svpnext_b64Experimentalsve

Find next active predicate Arm’s documentation

svprfb^⚠Experimentalsve

Prefetch bytes Arm’s documentation

svprfb_gather_s32offset^⚠Experimentalsve

Prefetch bytes Arm’s documentation

svprfb_gather_s64offset^⚠Experimentalsve

Prefetch bytes Arm’s documentation

svprfb_gather_u32base^⚠Experimentalsve

Prefetch bytes Arm’s documentation

svprfb_gather_u32base_offset^⚠Experimentalsve

Prefetch bytes Arm’s documentation

svprfb_gather_u32offset^⚠Experimentalsve

Prefetch bytes Arm’s documentation

svprfb_gather_u64base^⚠Experimentalsve

Prefetch bytes Arm’s documentation

svprfb_gather_u64base_offset^⚠Experimentalsve

Prefetch bytes Arm’s documentation

svprfb_gather_u64offset^⚠Experimentalsve

Prefetch bytes Arm’s documentation

svprfb_vnum^⚠Experimentalsve

Prefetch bytes Arm’s documentation

svprfd^⚠Experimentalsve

Prefetch doublewords Arm’s documentation

svprfd_gather_s32index^⚠Experimentalsve

Prefetch doublewords Arm’s documentation

svprfd_gather_s64index^⚠Experimentalsve

Prefetch doublewords Arm’s documentation

svprfd_gather_u32base^⚠Experimentalsve

Prefetch doublewords Arm’s documentation

svprfd_gather_u32base_index^⚠Experimentalsve

Prefetch doublewords Arm’s documentation

svprfd_gather_u32index^⚠Experimentalsve

Prefetch doublewords Arm’s documentation

svprfd_gather_u64base^⚠Experimentalsve

Prefetch doublewords Arm’s documentation

svprfd_gather_u64base_index^⚠Experimentalsve

Prefetch doublewords Arm’s documentation

svprfd_gather_u64index^⚠Experimentalsve

Prefetch doublewords Arm’s documentation

svprfd_vnum^⚠Experimentalsve

Prefetch doublewords Arm’s documentation

svprfh^⚠Experimentalsve

Prefetch halfwords Arm’s documentation

svprfh_gather_s32index^⚠Experimentalsve

Prefetch halfwords Arm’s documentation

svprfh_gather_s64index^⚠Experimentalsve

Prefetch halfwords Arm’s documentation

svprfh_gather_u32base^⚠Experimentalsve

Prefetch halfwords Arm’s documentation

svprfh_gather_u32base_index^⚠Experimentalsve

Prefetch halfwords Arm’s documentation

svprfh_gather_u32index^⚠Experimentalsve

Prefetch halfwords Arm’s documentation

svprfh_gather_u64base^⚠Experimentalsve

Prefetch halfwords Arm’s documentation

svprfh_gather_u64base_index^⚠Experimentalsve

Prefetch halfwords Arm’s documentation

svprfh_gather_u64index^⚠Experimentalsve

Prefetch halfwords Arm’s documentation

svprfh_vnum^⚠Experimentalsve

Prefetch halfwords Arm’s documentation

svprfw^⚠Experimentalsve

Prefetch words Arm’s documentation

svprfw_gather_s32index^⚠Experimentalsve

Prefetch words Arm’s documentation

svprfw_gather_s64index^⚠Experimentalsve

Prefetch words Arm’s documentation

svprfw_gather_u32base^⚠Experimentalsve

Prefetch words Arm’s documentation

svprfw_gather_u32base_index^⚠Experimentalsve

Prefetch words Arm’s documentation

svprfw_gather_u32index^⚠Experimentalsve

Prefetch words Arm’s documentation

svprfw_gather_u64base^⚠Experimentalsve

Prefetch words Arm’s documentation

svprfw_gather_u64base_index^⚠Experimentalsve

Prefetch words Arm’s documentation

svprfw_gather_u64index^⚠Experimentalsve

Prefetch words Arm’s documentation

svprfw_vnum^⚠Experimentalsve

Prefetch words Arm’s documentation

svptest_anyExperimentalsve

Test whether any active element is true Arm’s documentation

svptest_firstExperimentalsve

Test whether first active element is true Arm’s documentation

svptest_lastExperimentalsve

Test whether last active element is true Arm’s documentation

svptrue_b8Experimentalsve

Set predicate elements to true Arm’s documentation

svptrue_b16Experimentalsve

Set predicate elements to true Arm’s documentation

svptrue_b32Experimentalsve

Set predicate elements to true Arm’s documentation

svptrue_b64Experimentalsve

Set predicate elements to true Arm’s documentation

svptrue_pat_b8Experimentalsve

Set predicate elements to true Arm’s documentation

svptrue_pat_b16Experimentalsve

Set predicate elements to true Arm’s documentation

svptrue_pat_b32Experimentalsve

Set predicate elements to true Arm’s documentation

svptrue_pat_b64Experimentalsve

Set predicate elements to true Arm’s documentation

svqabs_s8_mExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqabs_s8_xExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqabs_s8_zExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqabs_s16_mExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqabs_s16_xExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqabs_s16_zExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqabs_s32_mExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqabs_s32_xExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqabs_s32_zExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqabs_s64_mExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqabs_s64_xExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqabs_s64_zExperimentalsve and sve2

Saturating absolute value Arm’s documentation

svqadd_n_s8Experimentalsve

Saturating add Arm’s documentation

svqadd_n_s8_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_s8_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_s8_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_s16Experimentalsve

Saturating add Arm’s documentation

svqadd_n_s32Experimentalsve

Saturating add Arm’s documentation

svqadd_n_s64Experimentalsve

Saturating add Arm’s documentation

svqadd_n_s16_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_s16_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_s16_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_s32_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_s32_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_s32_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_s64_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_s64_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_s64_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u8Experimentalsve

Saturating add Arm’s documentation

svqadd_n_u8_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u8_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u8_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u16Experimentalsve

Saturating add Arm’s documentation

svqadd_n_u32Experimentalsve

Saturating add Arm’s documentation

svqadd_n_u64Experimentalsve

Saturating add Arm’s documentation

svqadd_n_u16_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u16_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u16_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u32_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u32_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u32_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u64_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u64_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_n_u64_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s8Experimentalsve

Saturating add Arm’s documentation

svqadd_s8_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s8_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s8_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s16Experimentalsve

Saturating add Arm’s documentation

svqadd_s32Experimentalsve

Saturating add Arm’s documentation

svqadd_s64Experimentalsve

Saturating add Arm’s documentation

svqadd_s16_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s16_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s16_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s32_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s32_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s32_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s64_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s64_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_s64_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u8Experimentalsve

Saturating add Arm’s documentation

svqadd_u8_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u8_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u8_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u16Experimentalsve

Saturating add Arm’s documentation

svqadd_u32Experimentalsve

Saturating add Arm’s documentation

svqadd_u64Experimentalsve

Saturating add Arm’s documentation

svqadd_u16_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u16_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u16_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u32_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u32_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u32_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u64_mExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u64_xExperimentalsve and sve2

Saturating add Arm’s documentation

svqadd_u64_zExperimentalsve and sve2

Saturating add Arm’s documentation

svqcadd_s8Experimentalsve and sve2

Saturating complex add with rotate Arm’s documentation

svqcadd_s16Experimentalsve and sve2

Saturating complex add with rotate Arm’s documentation

svqcadd_s32Experimentalsve and sve2

Saturating complex add with rotate Arm’s documentation

svqcadd_s64Experimentalsve and sve2

Saturating complex add with rotate Arm’s documentation

svqdecb_n_s32Experimentalsve

Saturating decrement by number of byte elements Arm’s documentation

svqdecb_n_s64Experimentalsve

Saturating decrement by number of byte elements Arm’s documentation

svqdecb_n_u32Experimentalsve

Saturating decrement by number of byte elements Arm’s documentation

svqdecb_n_u64Experimentalsve

Saturating decrement by number of byte elements Arm’s documentation

svqdecb_pat_n_s32Experimentalsve

Saturating decrement by number of byte elements Arm’s documentation

svqdecb_pat_n_s64Experimentalsve

Saturating decrement by number of byte elements Arm’s documentation

svqdecb_pat_n_u32Experimentalsve

Saturating decrement by number of byte elements Arm’s documentation

svqdecb_pat_n_u64Experimentalsve

Saturating decrement by number of byte elements Arm’s documentation

svqdecd_n_s32Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdecd_n_s64Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdecd_n_u32Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdecd_n_u64Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdecd_pat_n_s32Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdecd_pat_n_s64Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdecd_pat_n_u32Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdecd_pat_n_u64Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdecd_pat_s64Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdecd_pat_u64Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdecd_s64Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdecd_u64Experimentalsve

Saturating decrement by number of doubleword elements Arm’s documentation

svqdech_n_s32Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdech_n_s64Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdech_n_u32Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdech_n_u64Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdech_pat_n_s32Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdech_pat_n_s64Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdech_pat_n_u32Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdech_pat_n_u64Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdech_pat_s16Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdech_pat_u16Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdech_s16Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdech_u16Experimentalsve

Saturating decrement by number of halfword elements Arm’s documentation

svqdecp_n_s32_b8Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_s32_b16Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_s32_b32Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_s32_b64Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_s64_b8Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_s64_b16Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_s64_b32Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_s64_b64Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_u32_b8Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_u32_b16Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_u32_b32Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_u32_b64Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_u64_b8Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_u64_b16Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_u64_b32Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_n_u64_b64Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_s16Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_s32Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_s64Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_u16Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_u32Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecp_u64Experimentalsve

Saturating decrement by active element count Arm’s documentation

svqdecw_n_s32Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdecw_n_s64Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdecw_n_u32Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdecw_n_u64Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdecw_pat_n_s32Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdecw_pat_n_s64Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdecw_pat_n_u32Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdecw_pat_n_u64Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdecw_pat_s32Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdecw_pat_u32Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdecw_s32Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdecw_u32Experimentalsve

Saturating decrement by number of word elements Arm’s documentation

svqdmlalb_lane_s32Experimentalsve and sve2

Saturating doubling multiply-add long (bottom) Arm’s documentation

svqdmlalb_lane_s64Experimentalsve and sve2

Saturating doubling multiply-add long (bottom) Arm’s documentation

svqdmlalb_n_s16Experimentalsve and sve2

Saturating doubling multiply-add long (bottom) Arm’s documentation

svqdmlalb_n_s32Experimentalsve and sve2

Saturating doubling multiply-add long (bottom) Arm’s documentation

svqdmlalb_n_s64Experimentalsve and sve2

Saturating doubling multiply-add long (bottom) Arm’s documentation

svqdmlalb_s16Experimentalsve and sve2

Saturating doubling multiply-add long (bottom) Arm’s documentation

svqdmlalb_s32Experimentalsve and sve2

Saturating doubling multiply-add long (bottom) Arm’s documentation

svqdmlalb_s64Experimentalsve and sve2

Saturating doubling multiply-add long (bottom) Arm’s documentation

svqdmlalbt_n_s16Experimentalsve and sve2

Saturating doubling multiply-add long (bottom × top) Arm’s documentation

svqdmlalbt_n_s32Experimentalsve and sve2

Saturating doubling multiply-add long (bottom × top) Arm’s documentation

svqdmlalbt_n_s64Experimentalsve and sve2

Saturating doubling multiply-add long (bottom × top) Arm’s documentation

svqdmlalbt_s16Experimentalsve and sve2

Saturating doubling multiply-add long (bottom × top) Arm’s documentation

svqdmlalbt_s32Experimentalsve and sve2

Saturating doubling multiply-add long (bottom × top) Arm’s documentation

svqdmlalbt_s64Experimentalsve and sve2

Saturating doubling multiply-add long (bottom × top) Arm’s documentation

svqdmlalt_lane_s32Experimentalsve and sve2

Saturating doubling multiply-add long (top) Arm’s documentation

svqdmlalt_lane_s64Experimentalsve and sve2

Saturating doubling multiply-add long (top) Arm’s documentation

svqdmlalt_n_s16Experimentalsve and sve2

Saturating doubling multiply-add long (top) Arm’s documentation

svqdmlalt_n_s32Experimentalsve and sve2

Saturating doubling multiply-add long (top) Arm’s documentation

svqdmlalt_n_s64Experimentalsve and sve2

Saturating doubling multiply-add long (top) Arm’s documentation

svqdmlalt_s16Experimentalsve and sve2

Saturating doubling multiply-add long (top) Arm’s documentation

svqdmlalt_s32Experimentalsve and sve2

Saturating doubling multiply-add long (top) Arm’s documentation

svqdmlalt_s64Experimentalsve and sve2

Saturating doubling multiply-add long (top) Arm’s documentation

svqdmlslb_lane_s32Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom) Arm’s documentation

svqdmlslb_lane_s64Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom) Arm’s documentation

svqdmlslb_n_s16Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom) Arm’s documentation

svqdmlslb_n_s32Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom) Arm’s documentation

svqdmlslb_n_s64Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom) Arm’s documentation

svqdmlslb_s16Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom) Arm’s documentation

svqdmlslb_s32Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom) Arm’s documentation

svqdmlslb_s64Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom) Arm’s documentation

svqdmlslbt_n_s16Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation

svqdmlslbt_n_s32Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation

svqdmlslbt_n_s64Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation

svqdmlslbt_s16Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation

svqdmlslbt_s32Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation

svqdmlslbt_s64Experimentalsve and sve2

Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation

svqdmlslt_lane_s32Experimentalsve and sve2

Saturating doubling multiply-subtract long (top) Arm’s documentation

svqdmlslt_lane_s64Experimentalsve and sve2

Saturating doubling multiply-subtract long (top) Arm’s documentation

svqdmlslt_n_s16Experimentalsve and sve2

Saturating doubling multiply-subtract long (top) Arm’s documentation

svqdmlslt_n_s32Experimentalsve and sve2

Saturating doubling multiply-subtract long (top) Arm’s documentation

svqdmlslt_n_s64Experimentalsve and sve2

Saturating doubling multiply-subtract long (top) Arm’s documentation

svqdmlslt_s16Experimentalsve and sve2

Saturating doubling multiply-subtract long (top) Arm’s documentation

svqdmlslt_s32Experimentalsve and sve2

Saturating doubling multiply-subtract long (top) Arm’s documentation

svqdmlslt_s64Experimentalsve and sve2

Saturating doubling multiply-subtract long (top) Arm’s documentation

svqdmulh_lane_s16Experimentalsve and sve2

Saturating doubling multiply high Arm’s documentation

svqdmulh_lane_s32Experimentalsve and sve2

Saturating doubling multiply high Arm’s documentation

svqdmulh_lane_s64Experimentalsve and sve2

Saturating doubling multiply high Arm’s documentation

svqdmulh_n_s8Experimentalsve and sve2

Saturating doubling multiply high Arm’s documentation

svqdmulh_n_s16Experimentalsve and sve2

Saturating doubling multiply high Arm’s documentation

svqdmulh_n_s32Experimentalsve and sve2

Saturating doubling multiply high Arm’s documentation

svqdmulh_n_s64Experimentalsve and sve2

Saturating doubling multiply high Arm’s documentation

svqdmulh_s8Experimentalsve and sve2

Saturating doubling multiply high Arm’s documentation

svqdmulh_s16Experimentalsve and sve2

Saturating doubling multiply high Arm’s documentation

svqdmulh_s32Experimentalsve and sve2

Saturating doubling multiply high Arm’s documentation

svqdmulh_s64Experimentalsve and sve2

Saturating doubling multiply high Arm’s documentation

svqdmullb_lane_s32Experimentalsve and sve2

Saturating doubling multiply long (bottom) Arm’s documentation

svqdmullb_lane_s64Experimentalsve and sve2

Saturating doubling multiply long (bottom) Arm’s documentation

svqdmullb_n_s16Experimentalsve and sve2

Saturating doubling multiply long (bottom) Arm’s documentation

svqdmullb_n_s32Experimentalsve and sve2

Saturating doubling multiply long (bottom) Arm’s documentation

svqdmullb_n_s64Experimentalsve and sve2

Saturating doubling multiply long (bottom) Arm’s documentation

svqdmullb_s16Experimentalsve and sve2

Saturating doubling multiply long (bottom) Arm’s documentation

svqdmullb_s32Experimentalsve and sve2

Saturating doubling multiply long (bottom) Arm’s documentation

svqdmullb_s64Experimentalsve and sve2

Saturating doubling multiply long (bottom) Arm’s documentation

svqdmullt_lane_s32Experimentalsve and sve2

Saturating doubling multiply long (top) Arm’s documentation

svqdmullt_lane_s64Experimentalsve and sve2

Saturating doubling multiply long (top) Arm’s documentation

svqdmullt_n_s16Experimentalsve and sve2

Saturating doubling multiply long (top) Arm’s documentation

svqdmullt_n_s32Experimentalsve and sve2

Saturating doubling multiply long (top) Arm’s documentation

svqdmullt_n_s64Experimentalsve and sve2

Saturating doubling multiply long (top) Arm’s documentation

svqdmullt_s16Experimentalsve and sve2

Saturating doubling multiply long (top) Arm’s documentation

svqdmullt_s32Experimentalsve and sve2

Saturating doubling multiply long (top) Arm’s documentation

svqdmullt_s64Experimentalsve and sve2

Saturating doubling multiply long (top) Arm’s documentation

svqincb_n_s32Experimentalsve

Saturating increment by number of byte elements Arm’s documentation

svqincb_n_s64Experimentalsve

Saturating increment by number of byte elements Arm’s documentation

svqincb_n_u32Experimentalsve

Saturating increment by number of byte elements Arm’s documentation

svqincb_n_u64Experimentalsve

Saturating increment by number of byte elements Arm’s documentation

svqincb_pat_n_s32Experimentalsve

Saturating increment by number of byte elements Arm’s documentation

svqincb_pat_n_s64Experimentalsve

Saturating increment by number of byte elements Arm’s documentation

svqincb_pat_n_u32Experimentalsve

Saturating increment by number of byte elements Arm’s documentation

svqincb_pat_n_u64Experimentalsve

Saturating increment by number of byte elements Arm’s documentation

svqincd_n_s32Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqincd_n_s64Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqincd_n_u32Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqincd_n_u64Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqincd_pat_n_s32Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqincd_pat_n_s64Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqincd_pat_n_u32Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqincd_pat_n_u64Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqincd_pat_s64Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqincd_pat_u64Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqincd_s64Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqincd_u64Experimentalsve

Saturating increment by number of doubleword elements Arm’s documentation

svqinch_n_s32Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqinch_n_s64Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqinch_n_u32Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqinch_n_u64Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqinch_pat_n_s32Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqinch_pat_n_s64Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqinch_pat_n_u32Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqinch_pat_n_u64Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqinch_pat_s16Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqinch_pat_u16Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqinch_s16Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqinch_u16Experimentalsve

Saturating increment by number of halfword elements Arm’s documentation

svqincp_n_s32_b8Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_s32_b16Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_s32_b32Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_s32_b64Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_s64_b8Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_s64_b16Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_s64_b32Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_s64_b64Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_u32_b8Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_u32_b16Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_u32_b32Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_u32_b64Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_u64_b8Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_u64_b16Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_u64_b32Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_n_u64_b64Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_s16Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_s32Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_s64Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_u16Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_u32Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincp_u64Experimentalsve

Saturating increment by active element count Arm’s documentation

svqincw_n_s32Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqincw_n_s64Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqincw_n_u32Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqincw_n_u64Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqincw_pat_n_s32Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqincw_pat_n_s64Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqincw_pat_n_u32Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqincw_pat_n_u64Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqincw_pat_s32Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqincw_pat_u32Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqincw_s32Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqincw_u32Experimentalsve

Saturating increment by number of word elements Arm’s documentation

svqneg_s8_mExperimentalsve and sve2

Saturating negate Arm’s documentation

svqneg_s8_xExperimentalsve and sve2

Saturating negate Arm’s documentation

svqneg_s8_zExperimentalsve and sve2

Saturating negate Arm’s documentation

svqneg_s16_mExperimentalsve and sve2

Saturating negate Arm’s documentation

svqneg_s16_xExperimentalsve and sve2

Saturating negate Arm’s documentation

svqneg_s16_zExperimentalsve and sve2

Saturating negate Arm’s documentation

svqneg_s32_mExperimentalsve and sve2

Saturating negate Arm’s documentation

svqneg_s32_xExperimentalsve and sve2

Saturating negate Arm’s documentation

svqneg_s32_zExperimentalsve and sve2

Saturating negate Arm’s documentation

svqneg_s64_mExperimentalsve and sve2

Saturating negate Arm’s documentation

svqneg_s64_xExperimentalsve and sve2

Saturating negate Arm’s documentation

svqneg_s64_zExperimentalsve and sve2

Saturating negate Arm’s documentation

svqrdcmlah_lane_s16Experimentalsve and sve2

Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation

svqrdcmlah_lane_s32Experimentalsve and sve2

Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation

svqrdcmlah_s8Experimentalsve and sve2

Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation

svqrdcmlah_s16Experimentalsve and sve2

Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation

svqrdcmlah_s32Experimentalsve and sve2

Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation

svqrdcmlah_s64Experimentalsve and sve2

Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation

svqrdmlah_lane_s16Experimentalsve and sve2

Saturating rounding doubling multiply-add high Arm’s documentation

svqrdmlah_lane_s32Experimentalsve and sve2

Saturating rounding doubling multiply-add high Arm’s documentation

svqrdmlah_lane_s64Experimentalsve and sve2

Saturating rounding doubling multiply-add high Arm’s documentation

svqrdmlah_n_s8Experimentalsve and sve2

Saturating rounding doubling multiply-add high Arm’s documentation

svqrdmlah_n_s16Experimentalsve and sve2

Saturating rounding doubling multiply-add high Arm’s documentation

svqrdmlah_n_s32Experimentalsve and sve2

Saturating rounding doubling multiply-add high Arm’s documentation

svqrdmlah_n_s64Experimentalsve and sve2

Saturating rounding doubling multiply-add high Arm’s documentation

svqrdmlah_s8Experimentalsve and sve2

Saturating rounding doubling multiply-add high Arm’s documentation

svqrdmlah_s16Experimentalsve and sve2

Saturating rounding doubling multiply-add high Arm’s documentation

svqrdmlah_s32Experimentalsve and sve2

Saturating rounding doubling multiply-add high Arm’s documentation

svqrdmlah_s64Experimentalsve and sve2

Saturating rounding doubling multiply-add high Arm’s documentation

svqrdmlsh_lane_s16Experimentalsve and sve2

Saturating rounding doubling multiply-subtract high Arm’s documentation

svqrdmlsh_lane_s32Experimentalsve and sve2

Saturating rounding doubling multiply-subtract high Arm’s documentation

svqrdmlsh_lane_s64Experimentalsve and sve2

Saturating rounding doubling multiply-subtract high Arm’s documentation

svqrdmlsh_n_s8Experimentalsve and sve2

Saturating rounding doubling multiply-subtract high Arm’s documentation

svqrdmlsh_n_s16Experimentalsve and sve2

Saturating rounding doubling multiply-subtract high Arm’s documentation

svqrdmlsh_n_s32Experimentalsve and sve2

Saturating rounding doubling multiply-subtract high Arm’s documentation

svqrdmlsh_n_s64Experimentalsve and sve2

Saturating rounding doubling multiply-subtract high Arm’s documentation

svqrdmlsh_s8Experimentalsve and sve2

Saturating rounding doubling multiply-subtract high Arm’s documentation

svqrdmlsh_s16Experimentalsve and sve2

Saturating rounding doubling multiply-subtract high Arm’s documentation

svqrdmlsh_s32Experimentalsve and sve2

Saturating rounding doubling multiply-subtract high Arm’s documentation

svqrdmlsh_s64Experimentalsve and sve2

Saturating rounding doubling multiply-subtract high Arm’s documentation

svqrdmulh_lane_s16Experimentalsve and sve2

Saturating rounding doubling multiply high Arm’s documentation

svqrdmulh_lane_s32Experimentalsve and sve2

Saturating rounding doubling multiply high Arm’s documentation

svqrdmulh_lane_s64Experimentalsve and sve2

Saturating rounding doubling multiply high Arm’s documentation

svqrdmulh_n_s8Experimentalsve and sve2

Saturating rounding doubling multiply high Arm’s documentation

svqrdmulh_n_s16Experimentalsve and sve2

Saturating rounding doubling multiply high Arm’s documentation

svqrdmulh_n_s32Experimentalsve and sve2

Saturating rounding doubling multiply high Arm’s documentation

svqrdmulh_n_s64Experimentalsve and sve2

Saturating rounding doubling multiply high Arm’s documentation

svqrdmulh_s8Experimentalsve and sve2

Saturating rounding doubling multiply high Arm’s documentation

svqrdmulh_s16Experimentalsve and sve2

Saturating rounding doubling multiply high Arm’s documentation

svqrdmulh_s32Experimentalsve and sve2

Saturating rounding doubling multiply high Arm’s documentation

svqrdmulh_s64Experimentalsve and sve2

Saturating rounding doubling multiply high Arm’s documentation

svqrshl_n_s8_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_s8_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_s8_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_s16_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_s16_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_s16_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_s32_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_s32_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_s32_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_s64_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_s64_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_s64_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u8_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u8_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u8_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u16_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u16_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u16_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u32_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u32_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u32_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u64_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u64_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_n_u64_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s8_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s8_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s8_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s16_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s16_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s16_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s32_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s32_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s32_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s64_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s64_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_s64_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u8_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u8_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u8_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u16_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u16_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u16_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u32_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u32_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u32_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u64_mExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u64_xExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshl_u64_zExperimentalsve and sve2

Saturating rounding shift left Arm’s documentation

svqrshrnb_n_s16Experimentalsve and sve2

Saturating rounding shift right narrow (bottom) Arm’s documentation

svqrshrnb_n_s32Experimentalsve and sve2

Saturating rounding shift right narrow (bottom) Arm’s documentation

svqrshrnb_n_s64Experimentalsve and sve2

Saturating rounding shift right narrow (bottom) Arm’s documentation

svqrshrnb_n_u16Experimentalsve and sve2

Saturating rounding shift right narrow (bottom) Arm’s documentation

svqrshrnb_n_u32Experimentalsve and sve2

Saturating rounding shift right narrow (bottom) Arm’s documentation

svqrshrnb_n_u64Experimentalsve and sve2

Saturating rounding shift right narrow (bottom) Arm’s documentation

svqrshrnt_n_s16Experimentalsve and sve2

Saturating rounding shift right narrow (top) Arm’s documentation

svqrshrnt_n_s32Experimentalsve and sve2

Saturating rounding shift right narrow (top) Arm’s documentation

svqrshrnt_n_s64Experimentalsve and sve2

Saturating rounding shift right narrow (top) Arm’s documentation

svqrshrnt_n_u16Experimentalsve and sve2

Saturating rounding shift right narrow (top) Arm’s documentation

svqrshrnt_n_u32Experimentalsve and sve2

Saturating rounding shift right narrow (top) Arm’s documentation

svqrshrnt_n_u64Experimentalsve and sve2

Saturating rounding shift right narrow (top) Arm’s documentation

svqrshrunb_n_s16Experimentalsve and sve2

Saturating rounding shift right unsigned narrow (bottom) Arm’s documentation

svqrshrunb_n_s32Experimentalsve and sve2

Saturating rounding shift right unsigned narrow (bottom) Arm’s documentation

svqrshrunb_n_s64Experimentalsve and sve2

Saturating rounding shift right unsigned narrow (bottom) Arm’s documentation

svqrshrunt_n_s16Experimentalsve and sve2

Saturating rounding shift right unsigned narrow (top) Arm’s documentation

svqrshrunt_n_s32Experimentalsve and sve2

Saturating rounding shift right unsigned narrow (top) Arm’s documentation

svqrshrunt_n_s64Experimentalsve and sve2

Saturating rounding shift right unsigned narrow (top) Arm’s documentation

svqshl_n_s8_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_s8_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_s8_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_s16_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_s16_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_s16_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_s32_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_s32_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_s32_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_s64_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_s64_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_s64_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u8_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u8_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u8_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u16_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u16_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u16_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u32_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u32_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u32_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u64_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u64_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_n_u64_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s8_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s8_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s8_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s16_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s16_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s16_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s32_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s32_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s32_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s64_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s64_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_s64_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u8_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u8_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u8_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u16_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u16_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u16_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u32_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u32_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u32_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u64_mExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u64_xExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshl_u64_zExperimentalsve and sve2

Saturating shift left Arm’s documentation

svqshlu_n_s8_mExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshlu_n_s8_xExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshlu_n_s8_zExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshlu_n_s16_mExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshlu_n_s16_xExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshlu_n_s16_zExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshlu_n_s32_mExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshlu_n_s32_xExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshlu_n_s32_zExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshlu_n_s64_mExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshlu_n_s64_xExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshlu_n_s64_zExperimentalsve and sve2

Saturating shift left unsigned Arm’s documentation

svqshrnb_n_s16Experimentalsve and sve2

Saturating shift right narrow (bottom) Arm’s documentation

svqshrnb_n_s32Experimentalsve and sve2

Saturating shift right narrow (bottom) Arm’s documentation

svqshrnb_n_s64Experimentalsve and sve2

Saturating shift right narrow (bottom) Arm’s documentation

svqshrnb_n_u16Experimentalsve and sve2

Saturating shift right narrow (bottom) Arm’s documentation

svqshrnb_n_u32Experimentalsve and sve2

Saturating shift right narrow (bottom) Arm’s documentation

svqshrnb_n_u64Experimentalsve and sve2

Saturating shift right narrow (bottom) Arm’s documentation

svqshrnt_n_s16Experimentalsve and sve2

Saturating shift right narrow (top) Arm’s documentation

svqshrnt_n_s32Experimentalsve and sve2

Saturating shift right narrow (top) Arm’s documentation

svqshrnt_n_s64Experimentalsve and sve2

Saturating shift right narrow (top) Arm’s documentation

svqshrnt_n_u16Experimentalsve and sve2

Saturating shift right narrow (top) Arm’s documentation

svqshrnt_n_u32Experimentalsve and sve2

Saturating shift right narrow (top) Arm’s documentation

svqshrnt_n_u64Experimentalsve and sve2

Saturating shift right narrow (top) Arm’s documentation

svqshrunb_n_s16Experimentalsve and sve2

Saturating shift right unsigned narrow (bottom) Arm’s documentation

svqshrunb_n_s32Experimentalsve and sve2

Saturating shift right unsigned narrow (bottom) Arm’s documentation

svqshrunb_n_s64Experimentalsve and sve2

Saturating shift right unsigned narrow (bottom) Arm’s documentation

svqshrunt_n_s16Experimentalsve and sve2

Saturating shift right unsigned narrow (top) Arm’s documentation

svqshrunt_n_s32Experimentalsve and sve2

Saturating shift right unsigned narrow (top) Arm’s documentation

svqshrunt_n_s64Experimentalsve and sve2

Saturating shift right unsigned narrow (top) Arm’s documentation

svqsub_n_s8Experimentalsve

Saturating subtract Arm’s documentation

svqsub_n_s8_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_s8_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_s8_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_s16Experimentalsve

Saturating subtract Arm’s documentation

svqsub_n_s32Experimentalsve

Saturating subtract Arm’s documentation

svqsub_n_s64Experimentalsve

Saturating subtract Arm’s documentation

svqsub_n_s16_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_s16_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_s16_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_s32_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_s32_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_s32_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_s64_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_s64_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_s64_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u8Experimentalsve

Saturating subtract Arm’s documentation

svqsub_n_u8_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u8_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u8_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u16Experimentalsve

Saturating subtract Arm’s documentation

svqsub_n_u32Experimentalsve

Saturating subtract Arm’s documentation

svqsub_n_u64Experimentalsve

Saturating subtract Arm’s documentation

svqsub_n_u16_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u16_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u16_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u32_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u32_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u32_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u64_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u64_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_n_u64_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s8Experimentalsve

Saturating subtract Arm’s documentation

svqsub_s8_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s8_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s8_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s16Experimentalsve

Saturating subtract Arm’s documentation

svqsub_s32Experimentalsve

Saturating subtract Arm’s documentation

svqsub_s64Experimentalsve

Saturating subtract Arm’s documentation

svqsub_s16_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s16_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s16_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s32_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s32_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s32_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s64_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s64_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_s64_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u8Experimentalsve

Saturating subtract Arm’s documentation

svqsub_u8_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u8_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u8_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u16Experimentalsve

Saturating subtract Arm’s documentation

svqsub_u32Experimentalsve

Saturating subtract Arm’s documentation

svqsub_u64Experimentalsve

Saturating subtract Arm’s documentation

svqsub_u16_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u16_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u16_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u32_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u32_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u32_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u64_mExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u64_xExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsub_u64_zExperimentalsve and sve2

Saturating subtract Arm’s documentation

svqsubr_n_s8_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_s8_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_s8_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_s16_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_s16_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_s16_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_s32_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_s32_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_s32_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_s64_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_s64_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_s64_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u8_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u8_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u8_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u16_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u16_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u16_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u32_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u32_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u32_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u64_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u64_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_n_u64_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s8_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s8_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s8_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s16_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s16_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s16_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s32_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s32_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s32_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s64_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s64_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_s64_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u8_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u8_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u8_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u16_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u16_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u16_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u32_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u32_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u32_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u64_mExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u64_xExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqsubr_u64_zExperimentalsve and sve2

Saturating subtract reversed Arm’s documentation

svqxtnb_s16Experimentalsve and sve2

Saturating extract narrow (bottom) Arm’s documentation

svqxtnb_s32Experimentalsve and sve2

Saturating extract narrow (bottom) Arm’s documentation

svqxtnb_s64Experimentalsve and sve2

Saturating extract narrow (bottom) Arm’s documentation

svqxtnb_u16Experimentalsve and sve2

Saturating extract narrow (bottom) Arm’s documentation

svqxtnb_u32Experimentalsve and sve2

Saturating extract narrow (bottom) Arm’s documentation

svqxtnb_u64Experimentalsve and sve2

Saturating extract narrow (bottom) Arm’s documentation

svqxtnt_s16Experimentalsve and sve2

Saturating extract narrow (top) Arm’s documentation

svqxtnt_s32Experimentalsve and sve2

Saturating extract narrow (top) Arm’s documentation

svqxtnt_s64Experimentalsve and sve2

Saturating extract narrow (top) Arm’s documentation

svqxtnt_u16Experimentalsve and sve2

Saturating extract narrow (top) Arm’s documentation

svqxtnt_u32Experimentalsve and sve2

Saturating extract narrow (top) Arm’s documentation

svqxtnt_u64Experimentalsve and sve2

Saturating extract narrow (top) Arm’s documentation

svqxtunb_s16Experimentalsve and sve2

Saturating extract unsigned narrow (bottom) Arm’s documentation

svqxtunb_s32Experimentalsve and sve2

Saturating extract unsigned narrow (bottom) Arm’s documentation

svqxtunb_s64Experimentalsve and sve2

Saturating extract unsigned narrow (bottom) Arm’s documentation

svqxtunt_s16Experimentalsve and sve2

Saturating extract unsigned narrow (top) Arm’s documentation

svqxtunt_s32Experimentalsve and sve2

Saturating extract unsigned narrow (top) Arm’s documentation

svqxtunt_s64Experimentalsve and sve2

Saturating extract unsigned narrow (top) Arm’s documentation

svraddhnb_n_s16Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnb_n_s32Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnb_n_s64Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnb_n_u16Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnb_n_u32Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnb_n_u64Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnb_s16Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnb_s32Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnb_s64Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnb_u16Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnb_u32Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnb_u64Experimentalsve and sve2

Rounding add narrow high part (bottom) Arm’s documentation

svraddhnt_n_s16Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svraddhnt_n_s32Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svraddhnt_n_s64Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svraddhnt_n_u16Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svraddhnt_n_u32Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svraddhnt_n_u64Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svraddhnt_s16Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svraddhnt_s32Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svraddhnt_s64Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svraddhnt_u16Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svraddhnt_u32Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svraddhnt_u64Experimentalsve and sve2

Rounding add narrow high part (top) Arm’s documentation

svrax1_s64Experimentalsve and sve2 and sve2-sha3

Bitwise rotate left by 1 and exclusive OR Arm’s documentation

svrax1_u64Experimentalsve and sve2 and sve2-sha3

Bitwise rotate left by 1 and exclusive OR Arm’s documentation

svrbit_s8_mExperimentalsve

Reverse bits Arm’s documentation

svrbit_s8_xExperimentalsve

Reverse bits Arm’s documentation

svrbit_s8_zExperimentalsve

Reverse bits Arm’s documentation

svrbit_s16_mExperimentalsve

Reverse bits Arm’s documentation

svrbit_s16_xExperimentalsve

Reverse bits Arm’s documentation

svrbit_s16_zExperimentalsve

Reverse bits Arm’s documentation

svrbit_s32_mExperimentalsve

Reverse bits Arm’s documentation

svrbit_s32_xExperimentalsve

Reverse bits Arm’s documentation

svrbit_s32_zExperimentalsve

Reverse bits Arm’s documentation

svrbit_s64_mExperimentalsve

Reverse bits Arm’s documentation

svrbit_s64_xExperimentalsve

Reverse bits Arm’s documentation

svrbit_s64_zExperimentalsve

Reverse bits Arm’s documentation

svrbit_u8_mExperimentalsve

Reverse bits Arm’s documentation

svrbit_u8_xExperimentalsve

Reverse bits Arm’s documentation

svrbit_u8_zExperimentalsve

Reverse bits Arm’s documentation

svrbit_u16_mExperimentalsve

Reverse bits Arm’s documentation

svrbit_u16_xExperimentalsve

Reverse bits Arm’s documentation

svrbit_u16_zExperimentalsve

Reverse bits Arm’s documentation

svrbit_u32_mExperimentalsve

Reverse bits Arm’s documentation

svrbit_u32_xExperimentalsve

Reverse bits Arm’s documentation

svrbit_u32_zExperimentalsve

Reverse bits Arm’s documentation

svrbit_u64_mExperimentalsve

Reverse bits Arm’s documentation

svrbit_u64_xExperimentalsve

Reverse bits Arm’s documentation

svrbit_u64_zExperimentalsve

Reverse bits Arm’s documentation

svrdffrExperimentalsve

Read FFR, returning predicate of succesfully loaded elements Arm’s documentation

svrdffr_zExperimentalsve

Read FFR, returning predicate of succesfully loaded elements Arm’s documentation

svrecpe_f32Experimentalsve

Reciprocal estimate Arm’s documentation

svrecpe_f64Experimentalsve

Reciprocal estimate Arm’s documentation

svrecpe_u32_mExperimentalsve and sve2

Reciprocal estimate Arm’s documentation

svrecpe_u32_xExperimentalsve and sve2

Reciprocal estimate Arm’s documentation

svrecpe_u32_zExperimentalsve and sve2

Reciprocal estimate Arm’s documentation

svrecps_f32Experimentalsve

Reciprocal step Arm’s documentation

svrecps_f64Experimentalsve

Reciprocal step Arm’s documentation

svrecpx_f32_mExperimentalsve

Reciprocal exponent Arm’s documentation

svrecpx_f32_xExperimentalsve

Reciprocal exponent Arm’s documentation

svrecpx_f32_zExperimentalsve

Reciprocal exponent Arm’s documentation

svrecpx_f64_mExperimentalsve

Reciprocal exponent Arm’s documentation

svrecpx_f64_xExperimentalsve

Reciprocal exponent Arm’s documentation

svrecpx_f64_zExperimentalsve

Reciprocal exponent Arm’s documentation

svreinterpret_f32_f32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f32_f64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f32_s8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f32_s16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f32_s32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f32_s64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f32_u8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f32_u16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f32_u32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f32_u64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f64_f32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f64_f64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f64_s8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f64_s16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f64_s32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f64_s64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f64_u8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f64_u16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f64_u32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_f64_u64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s8_f32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s8_f64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s8_s8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s8_s16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s8_s32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s8_s64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s8_u8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s8_u16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s8_u32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s8_u64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s16_f32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s16_f64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s16_s8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s16_s16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s16_s32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s16_s64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s16_u8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s16_u16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s16_u32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s16_u64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s32_f32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s32_f64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s32_s8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s32_s16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s32_s32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s32_s64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s32_u8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s32_u16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s32_u32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s32_u64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s64_f32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s64_f64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s64_s8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s64_s16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s64_s32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s64_s64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s64_u8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s64_u16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s64_u32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_s64_u64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u8_f32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u8_f64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u8_s8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u8_s16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u8_s32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u8_s64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u8_u8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u8_u16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u8_u32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u8_u64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u16_f32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u16_f64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u16_s8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u16_s16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u16_s32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u16_s64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u16_u8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u16_u16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u16_u32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u16_u64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u32_f32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u32_f64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u32_s8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u32_s16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u32_s32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u32_s64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u32_u8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u32_u16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u32_u32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u32_u64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u64_f32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u64_f64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u64_s8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u64_s16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u64_s32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u64_s64Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u64_u8Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u64_u16Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u64_u32Experimentalsve

Reinterpret vector contents Arm’s documentation

svreinterpret_u64_u64Experimentalsve

Reinterpret vector contents Arm’s documentation

svrev_b8Experimentalsve

Reverse all elements Arm’s documentation

svrev_b16Experimentalsve

Reverse all elements Arm’s documentation

svrev_b32Experimentalsve

Reverse all elements Arm’s documentation

svrev_b64Experimentalsve

Reverse all elements Arm’s documentation

svrev_f32Experimentalsve

Reverse all elements Arm’s documentation

svrev_f64Experimentalsve

Reverse all elements Arm’s documentation

svrev_s8Experimentalsve

Reverse all elements Arm’s documentation

svrev_s16Experimentalsve

Reverse all elements Arm’s documentation

svrev_s32Experimentalsve

Reverse all elements Arm’s documentation

svrev_s64Experimentalsve

Reverse all elements Arm’s documentation

svrev_u8Experimentalsve

Reverse all elements Arm’s documentation

svrev_u16Experimentalsve

Reverse all elements Arm’s documentation

svrev_u32Experimentalsve

Reverse all elements Arm’s documentation

svrev_u64Experimentalsve

Reverse all elements Arm’s documentation

svrevb_s16_mExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_s16_xExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_s16_zExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_s32_mExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_s32_xExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_s32_zExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_s64_mExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_s64_xExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_s64_zExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_u16_mExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_u16_xExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_u16_zExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_u32_mExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_u32_xExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_u32_zExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_u64_mExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_u64_xExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevb_u64_zExperimentalsve

Reverse bytes within elements Arm’s documentation

svrevh_s32_mExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevh_s32_xExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevh_s32_zExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevh_s64_mExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevh_s64_xExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevh_s64_zExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevh_u32_mExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevh_u32_xExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevh_u32_zExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevh_u64_mExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevh_u64_xExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevh_u64_zExperimentalsve

Reverse halfwords within elements Arm’s documentation

svrevw_s64_mExperimentalsve

Reverse words within elements Arm’s documentation

svrevw_s64_xExperimentalsve

Reverse words within elements Arm’s documentation

svrevw_s64_zExperimentalsve

Reverse words within elements Arm’s documentation

svrevw_u64_mExperimentalsve

Reverse words within elements Arm’s documentation

svrevw_u64_xExperimentalsve

Reverse words within elements Arm’s documentation

svrevw_u64_zExperimentalsve

Reverse words within elements Arm’s documentation

svrhadd_n_s8_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_s8_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_s8_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_s16_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_s16_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_s16_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_s32_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_s32_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_s32_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_s64_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_s64_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_s64_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u8_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u8_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u8_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u16_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u16_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u16_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u32_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u32_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u32_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u64_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u64_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_n_u64_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s8_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s8_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s8_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s16_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s16_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s16_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s32_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s32_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s32_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s64_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s64_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_s64_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u8_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u8_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u8_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u16_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u16_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u16_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u32_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u32_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u32_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u64_mExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u64_xExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrhadd_u64_zExperimentalsve and sve2

Rounding halving add Arm’s documentation

svrinta_f32_mExperimentalsve

Round to nearest, ties away from zero Arm’s documentation

svrinta_f32_xExperimentalsve

Round to nearest, ties away from zero Arm’s documentation

svrinta_f32_zExperimentalsve

Round to nearest, ties away from zero Arm’s documentation

svrinta_f64_mExperimentalsve

Round to nearest, ties away from zero Arm’s documentation

svrinta_f64_xExperimentalsve

Round to nearest, ties away from zero Arm’s documentation

svrinta_f64_zExperimentalsve

Round to nearest, ties away from zero Arm’s documentation

svrinti_f32_mExperimentalsve

Round using current rounding mode (inexact) Arm’s documentation

svrinti_f32_xExperimentalsve

Round using current rounding mode (inexact) Arm’s documentation

svrinti_f32_zExperimentalsve

Round using current rounding mode (inexact) Arm’s documentation

svrinti_f64_mExperimentalsve

Round using current rounding mode (inexact) Arm’s documentation

svrinti_f64_xExperimentalsve

Round using current rounding mode (inexact) Arm’s documentation

svrinti_f64_zExperimentalsve

Round using current rounding mode (inexact) Arm’s documentation

svrintm_f32_mExperimentalsve

Round towards -∞ Arm’s documentation

svrintm_f32_xExperimentalsve

Round towards -∞ Arm’s documentation

svrintm_f32_zExperimentalsve

Round towards -∞ Arm’s documentation

svrintm_f64_mExperimentalsve

Round towards -∞ Arm’s documentation

svrintm_f64_xExperimentalsve

Round towards -∞ Arm’s documentation

svrintm_f64_zExperimentalsve

Round towards -∞ Arm’s documentation

svrintn_f32_mExperimentalsve

Round to nearest, ties to even Arm’s documentation

svrintn_f32_xExperimentalsve

Round to nearest, ties to even Arm’s documentation

svrintn_f32_zExperimentalsve

Round to nearest, ties to even Arm’s documentation

svrintn_f64_mExperimentalsve

Round to nearest, ties to even Arm’s documentation

svrintn_f64_xExperimentalsve

Round to nearest, ties to even Arm’s documentation

svrintn_f64_zExperimentalsve

Round to nearest, ties to even Arm’s documentation

svrintp_f32_mExperimentalsve

Round towards +∞ Arm’s documentation

svrintp_f32_xExperimentalsve

Round towards +∞ Arm’s documentation

svrintp_f32_zExperimentalsve

Round towards +∞ Arm’s documentation

svrintp_f64_mExperimentalsve

Round towards +∞ Arm’s documentation

svrintp_f64_xExperimentalsve

Round towards +∞ Arm’s documentation

svrintp_f64_zExperimentalsve

Round towards +∞ Arm’s documentation

svrintx_f32_mExperimentalsve

Round using current rounding mode (exact) Arm’s documentation

svrintx_f32_xExperimentalsve

Round using current rounding mode (exact) Arm’s documentation

svrintx_f32_zExperimentalsve

Round using current rounding mode (exact) Arm’s documentation

svrintx_f64_mExperimentalsve

Round using current rounding mode (exact) Arm’s documentation

svrintx_f64_xExperimentalsve

Round using current rounding mode (exact) Arm’s documentation

svrintx_f64_zExperimentalsve

Round using current rounding mode (exact) Arm’s documentation

svrintz_f32_mExperimentalsve

Round towards zero Arm’s documentation

svrintz_f32_xExperimentalsve

Round towards zero Arm’s documentation

svrintz_f32_zExperimentalsve

Round towards zero Arm’s documentation

svrintz_f64_mExperimentalsve

Round towards zero Arm’s documentation

svrintz_f64_xExperimentalsve

Round towards zero Arm’s documentation

svrintz_f64_zExperimentalsve

Round towards zero Arm’s documentation

svrshl_n_s8_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_s8_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_s8_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_s16_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_s16_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_s16_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_s32_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_s32_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_s32_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_s64_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_s64_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_s64_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u8_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u8_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u8_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u16_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u16_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u16_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u32_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u32_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u32_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u64_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u64_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_n_u64_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s8_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s8_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s8_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s16_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s16_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s16_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s32_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s32_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s32_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s64_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s64_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_s64_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u8_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u8_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u8_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u16_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u16_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u16_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u32_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u32_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u32_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u64_mExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u64_xExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshl_u64_zExperimentalsve and sve2

Rounding shift left Arm’s documentation

svrshr_n_s8_mExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_s8_xExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_s8_zExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_s16_mExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_s16_xExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_s16_zExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_s32_mExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_s32_xExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_s32_zExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_s64_mExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_s64_xExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_s64_zExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u8_mExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u8_xExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u8_zExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u16_mExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u16_xExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u16_zExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u32_mExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u32_xExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u32_zExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u64_mExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u64_xExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshr_n_u64_zExperimentalsve and sve2

Rounding shift right Arm’s documentation

svrshrnb_n_s16Experimentalsve and sve2

Rounding shift right narrow (bottom) Arm’s documentation

svrshrnb_n_s32Experimentalsve and sve2

Rounding shift right narrow (bottom) Arm’s documentation

svrshrnb_n_s64Experimentalsve and sve2

Rounding shift right narrow (bottom) Arm’s documentation

svrshrnb_n_u16Experimentalsve and sve2

Rounding shift right narrow (bottom) Arm’s documentation

svrshrnb_n_u32Experimentalsve and sve2

Rounding shift right narrow (bottom) Arm’s documentation

svrshrnb_n_u64Experimentalsve and sve2

Rounding shift right narrow (bottom) Arm’s documentation

svrshrnt_n_s16Experimentalsve and sve2

Rounding shift right narrow (top) Arm’s documentation

svrshrnt_n_s32Experimentalsve and sve2

Rounding shift right narrow (top) Arm’s documentation

svrshrnt_n_s64Experimentalsve and sve2

Rounding shift right narrow (top) Arm’s documentation

svrshrnt_n_u16Experimentalsve and sve2

Rounding shift right narrow (top) Arm’s documentation

svrshrnt_n_u32Experimentalsve and sve2

Rounding shift right narrow (top) Arm’s documentation

svrshrnt_n_u64Experimentalsve and sve2

Rounding shift right narrow (top) Arm’s documentation

svrsqrte_f32Experimentalsve

Reciprocal square root estimate Arm’s documentation

svrsqrte_f64Experimentalsve

Reciprocal square root estimate Arm’s documentation

svrsqrte_u32_mExperimentalsve and sve2

Reciprocal square root estimate Arm’s documentation

svrsqrte_u32_xExperimentalsve and sve2

Reciprocal square root estimate Arm’s documentation

svrsqrte_u32_zExperimentalsve and sve2

Reciprocal square root estimate Arm’s documentation

svrsqrts_f32Experimentalsve

Reciprocal square root step Arm’s documentation

svrsqrts_f64Experimentalsve

Reciprocal square root step Arm’s documentation

svrsra_n_s8Experimentalsve and sve2

Rounding shift right and accumulate Arm’s documentation

svrsra_n_s16Experimentalsve and sve2

Rounding shift right and accumulate Arm’s documentation

svrsra_n_s32Experimentalsve and sve2

Rounding shift right and accumulate Arm’s documentation

svrsra_n_s64Experimentalsve and sve2

Rounding shift right and accumulate Arm’s documentation

svrsra_n_u8Experimentalsve and sve2

Rounding shift right and accumulate Arm’s documentation

svrsra_n_u16Experimentalsve and sve2

Rounding shift right and accumulate Arm’s documentation

svrsra_n_u32Experimentalsve and sve2

Rounding shift right and accumulate Arm’s documentation

svrsra_n_u64Experimentalsve and sve2

Rounding shift right and accumulate Arm’s documentation

svrsubhnb_n_s16Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnb_n_s32Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnb_n_s64Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnb_n_u16Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnb_n_u32Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnb_n_u64Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnb_s16Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnb_s32Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnb_s64Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnb_u16Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnb_u32Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnb_u64Experimentalsve and sve2

Rounding subtract narrow high part (bottom) Arm’s documentation

svrsubhnt_n_s16Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svrsubhnt_n_s32Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svrsubhnt_n_s64Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svrsubhnt_n_u16Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svrsubhnt_n_u32Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svrsubhnt_n_u64Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svrsubhnt_s16Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svrsubhnt_s32Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svrsubhnt_s64Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svrsubhnt_u16Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svrsubhnt_u32Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svrsubhnt_u64Experimentalsve and sve2

Rounding subtract narrow high part (top) Arm’s documentation

svsbclb_n_u32Experimentalsve and sve2

Subtract with borrow long (bottom) Arm’s documentation

svsbclb_n_u64Experimentalsve and sve2

Subtract with borrow long (bottom) Arm’s documentation

svsbclb_u32Experimentalsve and sve2

Subtract with borrow long (bottom) Arm’s documentation

svsbclb_u64Experimentalsve and sve2

Subtract with borrow long (bottom) Arm’s documentation

svsbclt_n_u32Experimentalsve and sve2

Subtract with borrow long (top) Arm’s documentation

svsbclt_n_u64Experimentalsve and sve2

Subtract with borrow long (top) Arm’s documentation

svsbclt_u32Experimentalsve and sve2

Subtract with borrow long (top) Arm’s documentation

svsbclt_u64Experimentalsve and sve2

Subtract with borrow long (top) Arm’s documentation

svscale_f32_mExperimentalsve

Adjust exponent Arm’s documentation

svscale_f32_xExperimentalsve

Adjust exponent Arm’s documentation

svscale_f32_zExperimentalsve

Adjust exponent Arm’s documentation

svscale_f64_mExperimentalsve

Adjust exponent Arm’s documentation

svscale_f64_xExperimentalsve

Adjust exponent Arm’s documentation

svscale_f64_zExperimentalsve

Adjust exponent Arm’s documentation

svscale_n_f32_mExperimentalsve

Adjust exponent Arm’s documentation

svscale_n_f32_xExperimentalsve

Adjust exponent Arm’s documentation

svscale_n_f32_zExperimentalsve

Adjust exponent Arm’s documentation

svscale_n_f64_mExperimentalsve

Adjust exponent Arm’s documentation

svscale_n_f64_xExperimentalsve

Adjust exponent Arm’s documentation

svscale_n_f64_zExperimentalsve

Adjust exponent Arm’s documentation

svsel_bExperimentalsve

Conditionally select elements Arm’s documentation

svsel_f32Experimentalsve

Conditionally select elements Arm’s documentation

svsel_f64Experimentalsve

Conditionally select elements Arm’s documentation

svsel_s8Experimentalsve

Conditionally select elements Arm’s documentation

svsel_s16Experimentalsve

Conditionally select elements Arm’s documentation

svsel_s32Experimentalsve

Conditionally select elements Arm’s documentation

svsel_s64Experimentalsve

Conditionally select elements Arm’s documentation

svsel_u8Experimentalsve

Conditionally select elements Arm’s documentation

svsel_u16Experimentalsve

Conditionally select elements Arm’s documentation

svsel_u32Experimentalsve

Conditionally select elements Arm’s documentation

svsel_u64Experimentalsve

Conditionally select elements Arm’s documentation

svset2_f32Experimentalsve

Change one vector in a tuple of two vectors Arm’s documentation

svset2_f64Experimentalsve

Change one vector in a tuple of two vectors Arm’s documentation

svset2_s8Experimentalsve

Change one vector in a tuple of two vectors Arm’s documentation

svset2_s16Experimentalsve

Change one vector in a tuple of two vectors Arm’s documentation

svset2_s32Experimentalsve

Change one vector in a tuple of two vectors Arm’s documentation

svset2_s64Experimentalsve

Change one vector in a tuple of two vectors Arm’s documentation

svset2_u8Experimentalsve

Change one vector in a tuple of two vectors Arm’s documentation

svset2_u16Experimentalsve

Change one vector in a tuple of two vectors Arm’s documentation

svset2_u32Experimentalsve

Change one vector in a tuple of two vectors Arm’s documentation

svset2_u64Experimentalsve

Change one vector in a tuple of two vectors Arm’s documentation

svset3_f32Experimentalsve

Change one vector in a tuple of three vectors Arm’s documentation

svset3_f64Experimentalsve

Change one vector in a tuple of three vectors Arm’s documentation

svset3_s8Experimentalsve

Change one vector in a tuple of three vectors Arm’s documentation

svset3_s16Experimentalsve

Change one vector in a tuple of three vectors Arm’s documentation

svset3_s32Experimentalsve

Change one vector in a tuple of three vectors Arm’s documentation

svset3_s64Experimentalsve

Change one vector in a tuple of three vectors Arm’s documentation

svset3_u8Experimentalsve

Change one vector in a tuple of three vectors Arm’s documentation

svset3_u16Experimentalsve

Change one vector in a tuple of three vectors Arm’s documentation

svset3_u32Experimentalsve

Change one vector in a tuple of three vectors Arm’s documentation

svset3_u64Experimentalsve

Change one vector in a tuple of three vectors Arm’s documentation

svset4_f32Experimentalsve

Change one vector in a tuple of four vectors Arm’s documentation

svset4_f64Experimentalsve

Change one vector in a tuple of four vectors Arm’s documentation

svset4_s8Experimentalsve

Change one vector in a tuple of four vectors Arm’s documentation

svset4_s16Experimentalsve

Change one vector in a tuple of four vectors Arm’s documentation

svset4_s32Experimentalsve

Change one vector in a tuple of four vectors Arm’s documentation

svset4_s64Experimentalsve

Change one vector in a tuple of four vectors Arm’s documentation

svset4_u8Experimentalsve

Change one vector in a tuple of four vectors Arm’s documentation

svset4_u16Experimentalsve

Change one vector in a tuple of four vectors Arm’s documentation

svset4_u32Experimentalsve

Change one vector in a tuple of four vectors Arm’s documentation

svset4_u64Experimentalsve

Change one vector in a tuple of four vectors Arm’s documentation

svsetffrExperimentalsve

Initialize the first-fault register to all-true Arm’s documentation

svshllb_n_s16Experimentalsve and sve2

Shift left long (bottom) Arm’s documentation

svshllb_n_s32Experimentalsve and sve2

Shift left long (bottom) Arm’s documentation

svshllb_n_s64Experimentalsve and sve2

Shift left long (bottom) Arm’s documentation

svshllb_n_u16Experimentalsve and sve2

Shift left long (bottom) Arm’s documentation

svshllb_n_u32Experimentalsve and sve2

Shift left long (bottom) Arm’s documentation

svshllb_n_u64Experimentalsve and sve2

Shift left long (bottom) Arm’s documentation

svshllt_n_s16Experimentalsve and sve2

Shift left long (top) Arm’s documentation

svshllt_n_s32Experimentalsve and sve2

Shift left long (top) Arm’s documentation

svshllt_n_s64Experimentalsve and sve2

Shift left long (top) Arm’s documentation

svshllt_n_u16Experimentalsve and sve2

Shift left long (top) Arm’s documentation

svshllt_n_u32Experimentalsve and sve2

Shift left long (top) Arm’s documentation

svshllt_n_u64Experimentalsve and sve2

Shift left long (top) Arm’s documentation

svshrnb_n_s16Experimentalsve and sve2

Shift right narrow (bottom) Arm’s documentation

svshrnb_n_s32Experimentalsve and sve2

Shift right narrow (bottom) Arm’s documentation

svshrnb_n_s64Experimentalsve and sve2

Shift right narrow (bottom) Arm’s documentation

svshrnb_n_u16Experimentalsve and sve2

Shift right narrow (bottom) Arm’s documentation

svshrnb_n_u32Experimentalsve and sve2

Shift right narrow (bottom) Arm’s documentation

svshrnb_n_u64Experimentalsve and sve2

Shift right narrow (bottom) Arm’s documentation

svshrnt_n_s16Experimentalsve and sve2

Shift right narrow (top) Arm’s documentation

svshrnt_n_s32Experimentalsve and sve2

Shift right narrow (top) Arm’s documentation

svshrnt_n_s64Experimentalsve and sve2

Shift right narrow (top) Arm’s documentation

svshrnt_n_u16Experimentalsve and sve2

Shift right narrow (top) Arm’s documentation

svshrnt_n_u32Experimentalsve and sve2

Shift right narrow (top) Arm’s documentation

svshrnt_n_u64Experimentalsve and sve2

Shift right narrow (top) Arm’s documentation

svsli_n_s8Experimentalsve and sve2

Shift left and insert Arm’s documentation

svsli_n_s16Experimentalsve and sve2

Shift left and insert Arm’s documentation

svsli_n_s32Experimentalsve and sve2

Shift left and insert Arm’s documentation

svsli_n_s64Experimentalsve and sve2

Shift left and insert Arm’s documentation

svsli_n_u8Experimentalsve and sve2

Shift left and insert Arm’s documentation

svsli_n_u16Experimentalsve and sve2

Shift left and insert Arm’s documentation

svsli_n_u32Experimentalsve and sve2

Shift left and insert Arm’s documentation

svsli_n_u64Experimentalsve and sve2

Shift left and insert Arm’s documentation

svsm4e_u32Experimentalsve and sve2 and sve2-sm4

SM4 encryption and decryption Arm’s documentation

svsm4ekey_u32Experimentalsve and sve2 and sve2-sm4

SM4 key updates Arm’s documentation

svsplice_f32Experimentalsve

Splice two vectors under predicate control Arm’s documentation

svsplice_f64Experimentalsve

Splice two vectors under predicate control Arm’s documentation

svsplice_s8Experimentalsve

Splice two vectors under predicate control Arm’s documentation

svsplice_s16Experimentalsve

Splice two vectors under predicate control Arm’s documentation

svsplice_s32Experimentalsve

Splice two vectors under predicate control Arm’s documentation

svsplice_s64Experimentalsve

Splice two vectors under predicate control Arm’s documentation

svsplice_u8Experimentalsve

Splice two vectors under predicate control Arm’s documentation

svsplice_u16Experimentalsve

Splice two vectors under predicate control Arm’s documentation

svsplice_u32Experimentalsve

Splice two vectors under predicate control Arm’s documentation

svsplice_u64Experimentalsve

Splice two vectors under predicate control Arm’s documentation

svsqadd_n_u8_mExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_n_u8_xExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_n_u8_zExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_n_u16_mExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_n_u16_xExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_n_u16_zExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_n_u32_mExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_n_u32_xExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_n_u32_zExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_n_u64_mExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_n_u64_xExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_n_u64_zExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u8_mExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u8_xExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u8_zExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u16_mExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u16_xExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u16_zExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u32_mExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u32_xExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u32_zExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u64_mExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u64_xExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqadd_u64_zExperimentalsve and sve2

Saturating add with signed addend Arm’s documentation

svsqrt_f32_mExperimentalsve

Square root Arm’s documentation

svsqrt_f32_xExperimentalsve

Square root Arm’s documentation

svsqrt_f32_zExperimentalsve

Square root Arm’s documentation

svsqrt_f64_mExperimentalsve

Square root Arm’s documentation

svsqrt_f64_xExperimentalsve

Square root Arm’s documentation

svsqrt_f64_zExperimentalsve

Square root Arm’s documentation

svsra_n_s8Experimentalsve and sve2

Shift right and accumulate Arm’s documentation

svsra_n_s16Experimentalsve and sve2

Shift right and accumulate Arm’s documentation

svsra_n_s32Experimentalsve and sve2

Shift right and accumulate Arm’s documentation

svsra_n_s64Experimentalsve and sve2

Shift right and accumulate Arm’s documentation

svsra_n_u8Experimentalsve and sve2

Shift right and accumulate Arm’s documentation

svsra_n_u16Experimentalsve and sve2

Shift right and accumulate Arm’s documentation

svsra_n_u32Experimentalsve and sve2

Shift right and accumulate Arm’s documentation

svsra_n_u64Experimentalsve and sve2

Shift right and accumulate Arm’s documentation

svsri_n_s8Experimentalsve and sve2

Shift right and insert Arm’s documentation

svsri_n_s16Experimentalsve and sve2

Shift right and insert Arm’s documentation

svsri_n_s32Experimentalsve and sve2

Shift right and insert Arm’s documentation

svsri_n_s64Experimentalsve and sve2

Shift right and insert Arm’s documentation

svsri_n_u8Experimentalsve and sve2

Shift right and insert Arm’s documentation

svsri_n_u16Experimentalsve and sve2

Shift right and insert Arm’s documentation

svsri_n_u32Experimentalsve and sve2

Shift right and insert Arm’s documentation

svsri_n_u64Experimentalsve and sve2

Shift right and insert Arm’s documentation

svst1_f32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_f64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_s8^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_s16^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_s32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_s64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s32index_f32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s32index_s32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s32index_u32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s32offset_f32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s32offset_s32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s32offset_u32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s64index_f64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s64index_s64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s64index_u64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s64offset_f64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s64offset_s64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_s64offset_u64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32base_f32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32base_index_f32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32base_index_s32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32base_index_u32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32base_offset_f32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32base_offset_s32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32base_offset_u32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32base_s32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32base_u32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32index_f32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32index_s32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32index_u32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32offset_f32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32offset_s32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u32offset_u32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64base_f64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64base_index_f64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64base_index_s64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64base_index_u64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64base_offset_f64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64base_offset_s64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64base_offset_u64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64base_s64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64base_u64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64index_f64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64index_s64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64index_u64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64offset_f64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64offset_s64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_scatter_u64offset_u64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_u8^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_u16^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_u32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_u64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_vnum_f32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_vnum_f64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_vnum_s8^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_vnum_s16^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_vnum_s32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_vnum_s64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_vnum_u8^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_vnum_u16^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_vnum_u32^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1_vnum_u64^⚠Experimentalsve

Non-truncating store Arm’s documentation

svst1b_s16^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_s32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_s64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_s32offset_s32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_s32offset_u32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_s64offset_s64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_s64offset_u64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u32base_offset_s32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u32base_offset_u32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u32base_s32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u32base_u32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u32offset_s32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u32offset_u32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u64base_offset_s64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u64base_offset_u64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u64base_s64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u64base_u64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u64offset_s64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_scatter_u64offset_u64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_u16^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_u32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_u64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_vnum_s16^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_vnum_s32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_vnum_s64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_vnum_u16^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_vnum_u32^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1b_vnum_u64^⚠Experimentalsve

Truncate to 8 bits and store Arm’s documentation

svst1h_s32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_s64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_s32index_s32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_s32index_u32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_s32offset_s32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_s32offset_u32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_s64index_s64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_s64index_u64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_s64offset_s64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_s64offset_u64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u32base_index_s32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u32base_index_u32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u32base_offset_s32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u32base_offset_u32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u32base_s32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u32base_u32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u32index_s32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u32index_u32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u32offset_s32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u32offset_u32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u64base_index_s64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u64base_index_u64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u64base_offset_s64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u64base_offset_u64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u64base_s64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u64base_u64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u64index_s64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u64index_u64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u64offset_s64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_scatter_u64offset_u64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_u32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_u64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_vnum_s32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_vnum_s64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_vnum_u32^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1h_vnum_u64^⚠Experimentalsve

Truncate to 16 bits and store Arm’s documentation

svst1w_s64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_s64index_s64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_s64index_u64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_s64offset_s64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_s64offset_u64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_u64base_index_s64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_u64base_index_u64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_u64base_offset_s64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_u64base_offset_u64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_u64base_s64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_u64base_u64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_u64index_s64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_u64index_u64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_u64offset_s64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_scatter_u64offset_u64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_u64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_vnum_s64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst1w_vnum_u64^⚠Experimentalsve

Truncate to 32 bits and store Arm’s documentation

svst2_f32^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_f64^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_s8^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_s16^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_s32^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_s64^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_u8^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_u16^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_u32^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_u64^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_vnum_f32^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_vnum_f64^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_vnum_s8^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_vnum_s16^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_vnum_s32^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_vnum_s64^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_vnum_u8^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_vnum_u16^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_vnum_u32^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst2_vnum_u64^⚠Experimentalsve

Store two vectors into two-element tuples Arm’s documentation

svst3_f32^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_f64^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_s8^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_s16^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_s32^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_s64^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_u8^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_u16^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_u32^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_u64^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_vnum_f32^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_vnum_f64^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_vnum_s8^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_vnum_s16^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_vnum_s32^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_vnum_s64^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_vnum_u8^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_vnum_u16^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_vnum_u32^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst3_vnum_u64^⚠Experimentalsve

Store three vectors into three-element tuples Arm’s documentation

svst4_f32^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_f64^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_s8^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_s16^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_s32^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_s64^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_u8^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_u16^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_u32^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_u64^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_vnum_f32^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_vnum_f64^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_vnum_s8^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_vnum_s16^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_vnum_s32^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_vnum_s64^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_vnum_u8^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_vnum_u16^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_vnum_u32^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svst4_vnum_u64^⚠Experimentalsve

Store four vectors into four-element tuples Arm’s documentation

svstnt1_f32^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_f64^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_s8^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_s16^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_s32^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_s64^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_s64index_f64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_s64index_s64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_s64index_u64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_s64offset_f64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_s64offset_s64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_s64offset_u64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32base_f32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32base_index_f32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32base_index_s32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32base_index_u32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32base_offset_f32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32base_offset_s32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32base_offset_u32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32base_s32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32base_u32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32offset_f32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32offset_s32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u32offset_u32^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64base_f64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64base_index_f64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64base_index_s64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64base_index_u64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64base_offset_f64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64base_offset_s64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64base_offset_u64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64base_s64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64base_u64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64index_f64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64index_s64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64index_u64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64offset_f64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64offset_s64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_scatter_u64offset_u64^⚠Experimentalsve and sve2

Non-truncating store, non-temporal Arm’s documentation

svstnt1_u8^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_u16^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_u32^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_u64^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_vnum_f32^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_vnum_f64^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_vnum_s8^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_vnum_s16^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_vnum_s32^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_vnum_s64^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_vnum_u8^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_vnum_u16^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_vnum_u32^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1_vnum_u64^⚠Experimentalsve

Non-truncating store, non-temporal Arm’s documentation

svstnt1b_scatter_s64offset_s64^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_s64offset_u64^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u32base_offset_s32^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u32base_offset_u32^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u32base_s32^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u32base_u32^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u32offset_s32^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u32offset_u32^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u64base_offset_s64^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u64base_offset_u64^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u64base_s64^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u64base_u64^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u64offset_s64^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1b_scatter_u64offset_u64^⚠Experimentalsve and sve2

Truncate to 8 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_s64index_s64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_s64index_u64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_s64offset_s64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_s64offset_u64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u32base_index_s32^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u32base_index_u32^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u32base_offset_s32^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u32base_offset_u32^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u32base_s32^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u32base_u32^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u32offset_s32^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u32offset_u32^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u64base_index_s64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u64base_index_u64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u64base_offset_s64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u64base_offset_u64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u64base_s64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u64base_u64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u64index_s64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u64index_u64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u64offset_s64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1h_scatter_u64offset_u64^⚠Experimentalsve and sve2

Truncate to 16 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_s64index_s64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_s64index_u64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_s64offset_s64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_s64offset_u64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_u64base_index_s64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_u64base_index_u64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_u64base_offset_s64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_u64base_offset_u64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_u64base_s64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_u64base_u64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_u64index_s64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_u64index_u64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_u64offset_s64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svstnt1w_scatter_u64offset_u64^⚠Experimentalsve and sve2

Truncate to 32 bits and store, non-temporal Arm’s documentation

svsub_f32_mExperimentalsve

Subtract Arm’s documentation

svsub_f32_xExperimentalsve

Subtract Arm’s documentation

svsub_f32_zExperimentalsve

Subtract Arm’s documentation

svsub_f64_mExperimentalsve

Subtract Arm’s documentation

svsub_f64_xExperimentalsve

Subtract Arm’s documentation

svsub_f64_zExperimentalsve

Subtract Arm’s documentation

svsub_n_f32_mExperimentalsve

Subtract Arm’s documentation

svsub_n_f32_xExperimentalsve

Subtract Arm’s documentation

svsub_n_f32_zExperimentalsve

Subtract Arm’s documentation

svsub_n_f64_mExperimentalsve

Subtract Arm’s documentation

svsub_n_f64_xExperimentalsve

Subtract Arm’s documentation

svsub_n_f64_zExperimentalsve

Subtract Arm’s documentation

svsub_n_s8_mExperimentalsve

Subtract Arm’s documentation

svsub_n_s8_xExperimentalsve

Subtract Arm’s documentation

svsub_n_s8_zExperimentalsve

Subtract Arm’s documentation

svsub_n_s16_mExperimentalsve

Subtract Arm’s documentation

svsub_n_s16_xExperimentalsve

Subtract Arm’s documentation

svsub_n_s16_zExperimentalsve

Subtract Arm’s documentation

svsub_n_s32_mExperimentalsve

Subtract Arm’s documentation

svsub_n_s32_xExperimentalsve

Subtract Arm’s documentation

svsub_n_s32_zExperimentalsve

Subtract Arm’s documentation

svsub_n_s64_mExperimentalsve

Subtract Arm’s documentation

svsub_n_s64_xExperimentalsve

Subtract Arm’s documentation

svsub_n_s64_zExperimentalsve

Subtract Arm’s documentation

svsub_n_u8_mExperimentalsve

Subtract Arm’s documentation

svsub_n_u8_xExperimentalsve

Subtract Arm’s documentation

svsub_n_u8_zExperimentalsve

Subtract Arm’s documentation

svsub_n_u16_mExperimentalsve

Subtract Arm’s documentation

svsub_n_u16_xExperimentalsve

Subtract Arm’s documentation

svsub_n_u16_zExperimentalsve

Subtract Arm’s documentation

svsub_n_u32_mExperimentalsve

Subtract Arm’s documentation

svsub_n_u32_xExperimentalsve

Subtract Arm’s documentation

svsub_n_u32_zExperimentalsve

Subtract Arm’s documentation

svsub_n_u64_mExperimentalsve

Subtract Arm’s documentation

svsub_n_u64_xExperimentalsve

Subtract Arm’s documentation

svsub_n_u64_zExperimentalsve

Subtract Arm’s documentation

svsub_s8_mExperimentalsve

Subtract Arm’s documentation

svsub_s8_xExperimentalsve

Subtract Arm’s documentation

svsub_s8_zExperimentalsve

Subtract Arm’s documentation

svsub_s16_mExperimentalsve

Subtract Arm’s documentation

svsub_s16_xExperimentalsve

Subtract Arm’s documentation

svsub_s16_zExperimentalsve

Subtract Arm’s documentation

svsub_s32_mExperimentalsve

Subtract Arm’s documentation

svsub_s32_xExperimentalsve

Subtract Arm’s documentation

svsub_s32_zExperimentalsve

Subtract Arm’s documentation

svsub_s64_mExperimentalsve

Subtract Arm’s documentation

svsub_s64_xExperimentalsve

Subtract Arm’s documentation

svsub_s64_zExperimentalsve

Subtract Arm’s documentation

svsub_u8_mExperimentalsve

Subtract Arm’s documentation

svsub_u8_xExperimentalsve

Subtract Arm’s documentation

svsub_u8_zExperimentalsve

Subtract Arm’s documentation

svsub_u16_mExperimentalsve

Subtract Arm’s documentation

svsub_u16_xExperimentalsve

Subtract Arm’s documentation

svsub_u16_zExperimentalsve

Subtract Arm’s documentation

svsub_u32_mExperimentalsve

Subtract Arm’s documentation

svsub_u32_xExperimentalsve

Subtract Arm’s documentation

svsub_u32_zExperimentalsve

Subtract Arm’s documentation

svsub_u64_mExperimentalsve

Subtract Arm’s documentation

svsub_u64_xExperimentalsve

Subtract Arm’s documentation

svsub_u64_zExperimentalsve

Subtract Arm’s documentation

svsubhnb_n_s16Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnb_n_s32Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnb_n_s64Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnb_n_u16Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnb_n_u32Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnb_n_u64Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnb_s16Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnb_s32Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnb_s64Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnb_u16Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnb_u32Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnb_u64Experimentalsve and sve2

Subtract narrow high part (bottom) Arm’s documentation

svsubhnt_n_s16Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsubhnt_n_s32Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsubhnt_n_s64Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsubhnt_n_u16Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsubhnt_n_u32Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsubhnt_n_u64Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsubhnt_s16Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsubhnt_s32Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsubhnt_s64Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsubhnt_u16Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsubhnt_u32Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsubhnt_u64Experimentalsve and sve2

Subtract narrow high part (top) Arm’s documentation

svsublb_n_s16Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublb_n_s32Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublb_n_s64Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublb_n_u16Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublb_n_u32Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublb_n_u64Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublb_s16Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublb_s32Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublb_s64Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublb_u16Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublb_u32Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublb_u64Experimentalsve and sve2

Subtract long (bottom) Arm’s documentation

svsublbt_n_s16Experimentalsve and sve2

Subtract long (bottom - top) Arm’s documentation

svsublbt_n_s32Experimentalsve and sve2

Subtract long (bottom - top) Arm’s documentation

svsublbt_n_s64Experimentalsve and sve2

Subtract long (bottom - top) Arm’s documentation

svsublbt_s16Experimentalsve and sve2

Subtract long (bottom - top) Arm’s documentation

svsublbt_s32Experimentalsve and sve2

Subtract long (bottom - top) Arm’s documentation

svsublbt_s64Experimentalsve and sve2

Subtract long (bottom - top) Arm’s documentation

svsublt_n_s16Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsublt_n_s32Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsublt_n_s64Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsublt_n_u16Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsublt_n_u32Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsublt_n_u64Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsublt_s16Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsublt_s32Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsublt_s64Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsublt_u16Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsublt_u32Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsublt_u64Experimentalsve and sve2

Subtract long (top) Arm’s documentation

svsubltb_n_s16Experimentalsve and sve2

Subtract long (top - bottom) Arm’s documentation

svsubltb_n_s32Experimentalsve and sve2

Subtract long (top - bottom) Arm’s documentation

svsubltb_n_s64Experimentalsve and sve2

Subtract long (top - bottom) Arm’s documentation

svsubltb_s16Experimentalsve and sve2

Subtract long (top - bottom) Arm’s documentation

svsubltb_s32Experimentalsve and sve2

Subtract long (top - bottom) Arm’s documentation

svsubltb_s64Experimentalsve and sve2

Subtract long (top - bottom) Arm’s documentation

svsubr_f32_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_f32_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_f32_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_f64_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_f64_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_f64_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_f32_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_f32_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_f32_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_f64_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_f64_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_f64_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s8_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s8_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s8_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s16_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s16_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s16_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s32_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s32_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s32_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s64_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s64_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_s64_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_u8_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_u8_xExperimentalsve

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svsubr_n_u8_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_u16_mExperimentalsve

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svsubr_n_u16_xExperimentalsve

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svsubr_n_u16_zExperimentalsve

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svsubr_n_u32_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_u32_xExperimentalsve

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svsubr_n_u32_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_u64_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_u64_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_n_u64_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_s8_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_s8_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_s8_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_s16_mExperimentalsve

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svsubr_s16_xExperimentalsve

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svsubr_s16_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_s32_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_s32_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_s32_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_s64_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_s64_xExperimentalsve

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svsubr_s64_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_u8_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_u8_xExperimentalsve

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svsubr_u8_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_u16_mExperimentalsve

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svsubr_u16_xExperimentalsve

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svsubr_u16_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_u32_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_u32_xExperimentalsve

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svsubr_u32_zExperimentalsve

Subtract reversed Arm’s documentation

svsubr_u64_mExperimentalsve

Subtract reversed Arm’s documentation

svsubr_u64_xExperimentalsve

Subtract reversed Arm’s documentation

svsubr_u64_zExperimentalsve

Subtract reversed Arm’s documentation

svsubwb_n_s16Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwb_n_s32Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwb_n_s64Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwb_n_u16Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwb_n_u32Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwb_n_u64Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwb_s16Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwb_s32Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwb_s64Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwb_u16Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwb_u32Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwb_u64Experimentalsve and sve2

Subtract wide (bottom) Arm’s documentation

svsubwt_n_s16Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsubwt_n_s32Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsubwt_n_s64Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsubwt_n_u16Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsubwt_n_u32Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsubwt_n_u64Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsubwt_s16Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsubwt_s32Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsubwt_s64Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsubwt_u16Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsubwt_u32Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsubwt_u64Experimentalsve and sve2

Subtract wide (top) Arm’s documentation

svsudot_lane_s32Experimentalsve and i8mm

Dot product (signed × unsigned) Arm’s documentation

svsudot_n_s32Experimentalsve and i8mm

Dot product (signed × unsigned) Arm’s documentation

svsudot_s32Experimentalsve and i8mm

Dot product (signed × unsigned) Arm’s documentation

svtbl2_f32Experimentalsve and sve2

Table lookup in two-vector table Arm’s documentation

svtbl2_f64Experimentalsve and sve2

Table lookup in two-vector table Arm’s documentation

svtbl2_s8Experimentalsve and sve2

Table lookup in two-vector table Arm’s documentation

svtbl2_s16Experimentalsve and sve2

Table lookup in two-vector table Arm’s documentation

svtbl2_s32Experimentalsve and sve2

Table lookup in two-vector table Arm’s documentation

svtbl2_s64Experimentalsve and sve2

Table lookup in two-vector table Arm’s documentation

svtbl2_u8Experimentalsve and sve2

Table lookup in two-vector table Arm’s documentation

svtbl2_u16Experimentalsve and sve2

Table lookup in two-vector table Arm’s documentation

svtbl2_u32Experimentalsve and sve2

Table lookup in two-vector table Arm’s documentation

svtbl2_u64Experimentalsve and sve2

Table lookup in two-vector table Arm’s documentation

svtbl_f32Experimentalsve

Table lookup in single-vector table Arm’s documentation

svtbl_f64Experimentalsve

Table lookup in single-vector table Arm’s documentation

svtbl_s8Experimentalsve

Table lookup in single-vector table Arm’s documentation

svtbl_s16Experimentalsve

Table lookup in single-vector table Arm’s documentation

svtbl_s32Experimentalsve

Table lookup in single-vector table Arm’s documentation

svtbl_s64Experimentalsve

Table lookup in single-vector table Arm’s documentation

svtbl_u8Experimentalsve

Table lookup in single-vector table Arm’s documentation

svtbl_u16Experimentalsve

Table lookup in single-vector table Arm’s documentation

svtbl_u32Experimentalsve

Table lookup in single-vector table Arm’s documentation

svtbl_u64Experimentalsve

Table lookup in single-vector table Arm’s documentation

svtbx_f32Experimentalsve and sve2

Table lookup in single-vector table (merging) Arm’s documentation

svtbx_f64Experimentalsve and sve2

Table lookup in single-vector table (merging) Arm’s documentation

svtbx_s8Experimentalsve and sve2

Table lookup in single-vector table (merging) Arm’s documentation

svtbx_s16Experimentalsve and sve2

Table lookup in single-vector table (merging) Arm’s documentation

svtbx_s32Experimentalsve and sve2

Table lookup in single-vector table (merging) Arm’s documentation

svtbx_s64Experimentalsve and sve2

Table lookup in single-vector table (merging) Arm’s documentation

svtbx_u8Experimentalsve and sve2

Table lookup in single-vector table (merging) Arm’s documentation

svtbx_u16Experimentalsve and sve2

Table lookup in single-vector table (merging) Arm’s documentation

svtbx_u32Experimentalsve and sve2

Table lookup in single-vector table (merging) Arm’s documentation

svtbx_u64Experimentalsve and sve2

Table lookup in single-vector table (merging) Arm’s documentation

svtmad_f32Experimentalsve

Trigonometric multiply-add coefficient Arm’s documentation

svtmad_f64Experimentalsve

Trigonometric multiply-add coefficient Arm’s documentation

svtrn1_b8Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_b16Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_b32Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_b64Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_f32Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_f64Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_s8Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_s16Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_s32Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_s64Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_u8Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_u16Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_u32Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1_u64Experimentalsve

Interleave even elements from two inputs Arm’s documentation

svtrn1q_f32Experimentalsve and f64mm

Interleave even quadwords from two inputs Arm’s documentation

svtrn1q_f64Experimentalsve and f64mm

Interleave even quadwords from two inputs Arm’s documentation

svtrn1q_s8Experimentalsve and f64mm

Interleave even quadwords from two inputs Arm’s documentation

svtrn1q_s16Experimentalsve and f64mm

Interleave even quadwords from two inputs Arm’s documentation

svtrn1q_s32Experimentalsve and f64mm

Interleave even quadwords from two inputs Arm’s documentation

svtrn1q_s64Experimentalsve and f64mm

Interleave even quadwords from two inputs Arm’s documentation

svtrn1q_u8Experimentalsve and f64mm

Interleave even quadwords from two inputs Arm’s documentation

svtrn1q_u16Experimentalsve and f64mm

Interleave even quadwords from two inputs Arm’s documentation

svtrn1q_u32Experimentalsve and f64mm

Interleave even quadwords from two inputs Arm’s documentation

svtrn1q_u64Experimentalsve and f64mm

Interleave even quadwords from two inputs Arm’s documentation

svtrn2_b8Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_b16Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_b32Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_b64Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_f32Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_f64Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_s8Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_s16Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_s32Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_s64Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_u8Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_u16Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_u32Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2_u64Experimentalsve

Interleave odd elements from two inputs Arm’s documentation

svtrn2q_f32Experimentalsve and f64mm

Interleave odd quadwords from two inputs Arm’s documentation

svtrn2q_f64Experimentalsve and f64mm

Interleave odd quadwords from two inputs Arm’s documentation

svtrn2q_s8Experimentalsve and f64mm

Interleave odd quadwords from two inputs Arm’s documentation

svtrn2q_s16Experimentalsve and f64mm

Interleave odd quadwords from two inputs Arm’s documentation

svtrn2q_s32Experimentalsve and f64mm

Interleave odd quadwords from two inputs Arm’s documentation

svtrn2q_s64Experimentalsve and f64mm

Interleave odd quadwords from two inputs Arm’s documentation

svtrn2q_u8Experimentalsve and f64mm

Interleave odd quadwords from two inputs Arm’s documentation

svtrn2q_u16Experimentalsve and f64mm

Interleave odd quadwords from two inputs Arm’s documentation

svtrn2q_u32Experimentalsve and f64mm

Interleave odd quadwords from two inputs Arm’s documentation

svtrn2q_u64Experimentalsve and f64mm

Interleave odd quadwords from two inputs Arm’s documentation

svtsmul_f32Experimentalsve

Trigonometric starting value Arm’s documentation

svtsmul_f64Experimentalsve

Trigonometric starting value Arm’s documentation

svtssel_f32Experimentalsve

Trigonometric select coefficient Arm’s documentation

svtssel_f64Experimentalsve

Trigonometric select coefficient Arm’s documentation

svundef2_f32^⚠Experimentalsve

Create an uninitialized tuple of two vectors Arm’s documentation

svundef2_f64^⚠Experimentalsve

Create an uninitialized tuple of two vectors Arm’s documentation

svundef2_s8^⚠Experimentalsve

Create an uninitialized tuple of two vectors Arm’s documentation

svundef2_s16^⚠Experimentalsve

Create an uninitialized tuple of two vectors Arm’s documentation

svundef2_s32^⚠Experimentalsve

Create an uninitialized tuple of two vectors Arm’s documentation

svundef2_s64^⚠Experimentalsve

Create an uninitialized tuple of two vectors Arm’s documentation

svundef2_u8^⚠Experimentalsve

Create an uninitialized tuple of two vectors Arm’s documentation

svundef2_u16^⚠Experimentalsve

Create an uninitialized tuple of two vectors Arm’s documentation

svundef2_u32^⚠Experimentalsve

Create an uninitialized tuple of two vectors Arm’s documentation

svundef2_u64^⚠Experimentalsve

Create an uninitialized tuple of two vectors Arm’s documentation

svundef3_f32^⚠Experimentalsve

Create an uninitialized tuple of three vectors Arm’s documentation

svundef3_f64^⚠Experimentalsve

Create an uninitialized tuple of three vectors Arm’s documentation

svundef3_s8^⚠Experimentalsve

Create an uninitialized tuple of three vectors Arm’s documentation

svundef3_s16^⚠Experimentalsve

Create an uninitialized tuple of three vectors Arm’s documentation

svundef3_s32^⚠Experimentalsve

Create an uninitialized tuple of three vectors Arm’s documentation

svundef3_s64^⚠Experimentalsve

Create an uninitialized tuple of three vectors Arm’s documentation

svundef3_u8^⚠Experimentalsve

Create an uninitialized tuple of three vectors Arm’s documentation

svundef3_u16^⚠Experimentalsve

Create an uninitialized tuple of three vectors Arm’s documentation

svundef3_u32^⚠Experimentalsve

Create an uninitialized tuple of three vectors Arm’s documentation

svundef3_u64^⚠Experimentalsve

Create an uninitialized tuple of three vectors Arm’s documentation

svundef4_f32^⚠Experimentalsve

Create an uninitialized tuple of four vectors Arm’s documentation

svundef4_f64^⚠Experimentalsve

Create an uninitialized tuple of four vectors Arm’s documentation

svundef4_s8^⚠Experimentalsve

Create an uninitialized tuple of four vectors Arm’s documentation

svundef4_s16^⚠Experimentalsve

Create an uninitialized tuple of four vectors Arm’s documentation

svundef4_s32^⚠Experimentalsve

Create an uninitialized tuple of four vectors Arm’s documentation

svundef4_s64^⚠Experimentalsve

Create an uninitialized tuple of four vectors Arm’s documentation

svundef4_u8^⚠Experimentalsve

Create an uninitialized tuple of four vectors Arm’s documentation

svundef4_u16^⚠Experimentalsve

Create an uninitialized tuple of four vectors Arm’s documentation

svundef4_u32^⚠Experimentalsve

Create an uninitialized tuple of four vectors Arm’s documentation

svundef4_u64^⚠Experimentalsve

Create an uninitialized tuple of four vectors Arm’s documentation

svundef_f32^⚠Experimentalsve

Create an uninitialized vector Arm’s documentation

svundef_f64^⚠Experimentalsve

Create an uninitialized vector Arm’s documentation

svundef_s8^⚠Experimentalsve

Create an uninitialized vector Arm’s documentation

svundef_s16^⚠Experimentalsve

Create an uninitialized vector Arm’s documentation

svundef_s32^⚠Experimentalsve

Create an uninitialized vector Arm’s documentation

svundef_s64^⚠Experimentalsve

Create an uninitialized vector Arm’s documentation

svundef_u8^⚠Experimentalsve

Create an uninitialized vector Arm’s documentation

svundef_u16^⚠Experimentalsve

Create an uninitialized vector Arm’s documentation

svundef_u32^⚠Experimentalsve

Create an uninitialized vector Arm’s documentation

svundef_u64^⚠Experimentalsve

Create an uninitialized vector Arm’s documentation

svunpkhi_bExperimentalsve and sve2

Unpack and extend high half Arm’s documentation

svunpkhi_s16Experimentalsve and sve2

Unpack and extend high half Arm’s documentation

svunpkhi_s32Experimentalsve and sve2

Unpack and extend high half Arm’s documentation

svunpkhi_s64Experimentalsve and sve2

Unpack and extend high half Arm’s documentation

svunpkhi_u16Experimentalsve and sve2

Unpack and extend high half Arm’s documentation

svunpkhi_u32Experimentalsve and sve2

Unpack and extend high half Arm’s documentation

svunpkhi_u64Experimentalsve and sve2

Unpack and extend high half Arm’s documentation

svunpklo_bExperimentalsve and sve2

Unpack and extend low half Arm’s documentation

svunpklo_s16Experimentalsve and sve2

Unpack and extend low half Arm’s documentation

svunpklo_s32Experimentalsve and sve2

Unpack and extend low half Arm’s documentation

svunpklo_s64Experimentalsve and sve2

Unpack and extend low half Arm’s documentation

svunpklo_u16Experimentalsve and sve2

Unpack and extend low half Arm’s documentation

svunpklo_u32Experimentalsve and sve2

Unpack and extend low half Arm’s documentation

svunpklo_u64Experimentalsve and sve2

Unpack and extend low half Arm’s documentation

svuqadd_n_s8_mExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_n_s8_xExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_n_s8_zExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_n_s16_mExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_n_s16_xExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_n_s16_zExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_n_s32_mExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_n_s32_xExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_n_s32_zExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_n_s64_mExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_n_s64_xExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_n_s64_zExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s8_mExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s8_xExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s8_zExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s16_mExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s16_xExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s16_zExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s32_mExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s32_xExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s32_zExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s64_mExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s64_xExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svuqadd_s64_zExperimentalsve and sve2

Saturating add with unsigned addend Arm’s documentation

svusdot_lane_s32Experimentalsve and i8mm

Dot product (unsigned × signed) Arm’s documentation

svusdot_n_s32Experimentalsve and i8mm

Dot product (unsigned × signed) Arm’s documentation

svusdot_s32Experimentalsve and i8mm

Dot product (unsigned × signed) Arm’s documentation

svusmmla_s32Experimentalsve and i8mm

Matrix multiply-accumulate (unsigned × signed) Arm’s documentation

svuzp1_b8Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_b16Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_b32Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_b64Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_f32Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_f64Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_s8Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_s16Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_s32Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_s64Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_u8Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_u16Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_u32Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1_u64Experimentalsve

Concatenate even elements from two inputs Arm’s documentation

svuzp1q_f32Experimentalsve and f64mm

Concatenate even quadwords from two inputs Arm’s documentation

svuzp1q_f64Experimentalsve and f64mm

Concatenate even quadwords from two inputs Arm’s documentation

svuzp1q_s8Experimentalsve and f64mm

Concatenate even quadwords from two inputs Arm’s documentation

svuzp1q_s16Experimentalsve and f64mm

Concatenate even quadwords from two inputs Arm’s documentation

svuzp1q_s32Experimentalsve and f64mm

Concatenate even quadwords from two inputs Arm’s documentation

svuzp1q_s64Experimentalsve and f64mm

Concatenate even quadwords from two inputs Arm’s documentation

svuzp1q_u8Experimentalsve and f64mm

Concatenate even quadwords from two inputs Arm’s documentation

svuzp1q_u16Experimentalsve and f64mm

Concatenate even quadwords from two inputs Arm’s documentation

svuzp1q_u32Experimentalsve and f64mm

Concatenate even quadwords from two inputs Arm’s documentation

svuzp1q_u64Experimentalsve and f64mm

Concatenate even quadwords from two inputs Arm’s documentation

svuzp2_b8Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_b16Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_b32Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_b64Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_f32Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_f64Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_s8Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_s16Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_s32Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_s64Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_u8Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_u16Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_u32Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2_u64Experimentalsve

Concatenate odd elements from two inputs Arm’s documentation

svuzp2q_f32Experimentalsve and f64mm

Concatenate odd quadwords from two inputs Arm’s documentation

svuzp2q_f64Experimentalsve and f64mm

Concatenate odd quadwords from two inputs Arm’s documentation

svuzp2q_s8Experimentalsve and f64mm

Concatenate odd quadwords from two inputs Arm’s documentation

svuzp2q_s16Experimentalsve and f64mm

Concatenate odd quadwords from two inputs Arm’s documentation

svuzp2q_s32Experimentalsve and f64mm

Concatenate odd quadwords from two inputs Arm’s documentation

svuzp2q_s64Experimentalsve and f64mm

Concatenate odd quadwords from two inputs Arm’s documentation

svuzp2q_u8Experimentalsve and f64mm

Concatenate odd quadwords from two inputs Arm’s documentation

svuzp2q_u16Experimentalsve and f64mm

Concatenate odd quadwords from two inputs Arm’s documentation

svuzp2q_u32Experimentalsve and f64mm

Concatenate odd quadwords from two inputs Arm’s documentation

svuzp2q_u64Experimentalsve and f64mm

Concatenate odd quadwords from two inputs Arm’s documentation

svwhilege_b8_s32Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b8_s64Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b8_u32Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b8_u64Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b16_s32Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b16_s64Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b16_u32Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b16_u64Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b32_s32Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b32_s64Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b32_u32Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b32_u64Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b64_s32Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b64_s64Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b64_u32Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilege_b64_u64Experimentalsve and sve2

While decrementing scalar is greater than or equal to Arm’s documentation

svwhilegt_b8_s32Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b8_s64Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b8_u32Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b8_u64Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b16_s32Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b16_s64Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b16_u32Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b16_u64Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b32_s32Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b32_s64Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b32_u32Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b32_u64Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b64_s32Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b64_s64Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b64_u32Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilegt_b64_u64Experimentalsve and sve2

While decrementing scalar is greater than Arm’s documentation

svwhilele_b8_s32Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b8_s64Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b8_u32Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b8_u64Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b16_s32Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b16_s64Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b16_u32Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b16_u64Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b32_s32Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b32_s64Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b32_u32Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b32_u64Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b64_s32Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b64_s64Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b64_u32Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilele_b64_u64Experimentalsve

While incrementing scalar is less than or equal to Arm’s documentation

svwhilelt_b8_s32Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b8_s64Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b8_u32Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b8_u64Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b16_s32Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b16_s64Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b16_u32Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b16_u64Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b32_s32Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b32_s64Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b32_u32Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b32_u64Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b64_s32Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b64_s64Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b64_u32Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilelt_b64_u64Experimentalsve

While incrementing scalar is less than Arm’s documentation

svwhilerw_f32^⚠Experimentalsve and sve2

While free of read-after-write conflicts Arm’s documentation

svwhilerw_f64^⚠Experimentalsve and sve2

While free of read-after-write conflicts Arm’s documentation

svwhilerw_s8^⚠Experimentalsve and sve2

While free of read-after-write conflicts Arm’s documentation

svwhilerw_s16^⚠Experimentalsve and sve2

While free of read-after-write conflicts Arm’s documentation

svwhilerw_s32^⚠Experimentalsve and sve2

While free of read-after-write conflicts Arm’s documentation

svwhilerw_s64^⚠Experimentalsve and sve2

While free of read-after-write conflicts Arm’s documentation

svwhilerw_u8^⚠Experimentalsve and sve2

While free of read-after-write conflicts Arm’s documentation

svwhilerw_u16^⚠Experimentalsve and sve2

While free of read-after-write conflicts Arm’s documentation

svwhilerw_u32^⚠Experimentalsve and sve2

While free of read-after-write conflicts Arm’s documentation

svwhilerw_u64^⚠Experimentalsve and sve2

While free of read-after-write conflicts Arm’s documentation

svwhilewr_f32^⚠Experimentalsve and sve2

While free of write-after-read conflicts Arm’s documentation

svwhilewr_f64^⚠Experimentalsve and sve2

While free of write-after-read conflicts Arm’s documentation

svwhilewr_s8^⚠Experimentalsve and sve2

While free of write-after-read conflicts Arm’s documentation

svwhilewr_s16^⚠Experimentalsve and sve2

While free of write-after-read conflicts Arm’s documentation

svwhilewr_s32^⚠Experimentalsve and sve2

While free of write-after-read conflicts Arm’s documentation

svwhilewr_s64^⚠Experimentalsve and sve2

While free of write-after-read conflicts Arm’s documentation

svwhilewr_u8^⚠Experimentalsve and sve2

While free of write-after-read conflicts Arm’s documentation

svwhilewr_u16^⚠Experimentalsve and sve2

While free of write-after-read conflicts Arm’s documentation

svwhilewr_u32^⚠Experimentalsve and sve2

While free of write-after-read conflicts Arm’s documentation

svwhilewr_u64^⚠Experimentalsve and sve2

While free of write-after-read conflicts Arm’s documentation

svwrffrExperimentalsve

Write to the first-fault register Arm’s documentation

svxar_n_s8Experimentalsve and sve2

Bitwise exclusive OR and rotate right Arm’s documentation

svxar_n_s16Experimentalsve and sve2

Bitwise exclusive OR and rotate right Arm’s documentation

svxar_n_s32Experimentalsve and sve2

Bitwise exclusive OR and rotate right Arm’s documentation

svxar_n_s64Experimentalsve and sve2

Bitwise exclusive OR and rotate right Arm’s documentation

svxar_n_u8Experimentalsve and sve2

Bitwise exclusive OR and rotate right Arm’s documentation

svxar_n_u16Experimentalsve and sve2

Bitwise exclusive OR and rotate right Arm’s documentation

svxar_n_u32Experimentalsve and sve2

Bitwise exclusive OR and rotate right Arm’s documentation

svxar_n_u64Experimentalsve and sve2

Bitwise exclusive OR and rotate right Arm’s documentation

svzip1_b8Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_b16Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_b32Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_b64Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_f32Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_f64Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_s8Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_s16Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_s32Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_s64Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_u8Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_u16Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_u32Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1_u64Experimentalsve

Interleave elements from low halves of two inputs Arm’s documentation

svzip1q_f32Experimentalsve and f64mm

Interleave quadwords from low halves of two inputs Arm’s documentation

svzip1q_f64Experimentalsve and f64mm

Interleave quadwords from low halves of two inputs Arm’s documentation

svzip1q_s8Experimentalsve and f64mm

Interleave quadwords from low halves of two inputs Arm’s documentation

svzip1q_s16Experimentalsve and f64mm

Interleave quadwords from low halves of two inputs Arm’s documentation

svzip1q_s32Experimentalsve and f64mm

Interleave quadwords from low halves of two inputs Arm’s documentation

svzip1q_s64Experimentalsve and f64mm

Interleave quadwords from low halves of two inputs Arm’s documentation

svzip1q_u8Experimentalsve and f64mm

Interleave quadwords from low halves of two inputs Arm’s documentation

svzip1q_u16Experimentalsve and f64mm

Interleave quadwords from low halves of two inputs Arm’s documentation

svzip1q_u32Experimentalsve and f64mm

Interleave quadwords from low halves of two inputs Arm’s documentation

svzip1q_u64Experimentalsve and f64mm

Interleave quadwords from low halves of two inputs Arm’s documentation

svzip2_b8Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_b16Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_b32Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_b64Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_f32Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_f64Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_s8Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_s16Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_s32Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_s64Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_u8Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_u16Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_u32Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2_u64Experimentalsve

Interleave elements from high halves of two inputs Arm’s documentation

svzip2q_f32Experimentalsve and f64mm

Interleave quadwords from high halves of two inputs Arm’s documentation

svzip2q_f64Experimentalsve and f64mm

Interleave quadwords from high halves of two inputs Arm’s documentation

svzip2q_s8Experimentalsve and f64mm

Interleave quadwords from high halves of two inputs Arm’s documentation

svzip2q_s16Experimentalsve and f64mm

Interleave quadwords from high halves of two inputs Arm’s documentation

svzip2q_s32Experimentalsve and f64mm

Interleave quadwords from high halves of two inputs Arm’s documentation

svzip2q_s64Experimentalsve and f64mm

Interleave quadwords from high halves of two inputs Arm’s documentation

svzip2q_u8Experimentalsve and f64mm

Interleave quadwords from high halves of two inputs Arm’s documentation

svzip2q_u16Experimentalsve and f64mm

Interleave quadwords from high halves of two inputs Arm’s documentation

svzip2q_u32Experimentalsve and f64mm

Interleave quadwords from high halves of two inputs Arm’s documentation

svzip2q_u64Experimentalsve and f64mm

Interleave quadwords from high halves of two inputs Arm’s documentation

vabdh_f16Experimentalneon and fp16

Floating-point absolute difference Arm’s documentation

vabsh_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Floating-point absolute value Arm’s documentation

vaddh_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Add Arm’s documentation

vamax_f16Experimentalneon and faminmax

Multi-vector floating-point absolute maximum Arm’s documentation

vamax_f32Experimentalneon and faminmax

Multi-vector floating-point absolute maximum Arm’s documentation

vamaxq_f16Experimentalneon and faminmax

Multi-vector floating-point absolute maximum Arm’s documentation

vamaxq_f32Experimentalneon and faminmax

Multi-vector floating-point absolute maximum Arm’s documentation

vamaxq_f64Experimentalneon and faminmax

Multi-vector floating-point absolute maximum Arm’s documentation

vamin_f16Experimentalneon and faminmax

Multi-vector floating-point absolute minimum Arm’s documentation

vamin_f32Experimentalneon and faminmax

Multi-vector floating-point absolute minimum Arm’s documentation

vaminq_f16Experimentalneon and faminmax

Multi-vector floating-point absolute minimum Arm’s documentation

vaminq_f32Experimentalneon and faminmax

Multi-vector floating-point absolute minimum Arm’s documentation

vaminq_f64Experimentalneon and faminmax

Multi-vector floating-point absolute minimum Arm’s documentation

vcadd_rot90_f16Experimentalneon and fp16 and fcma

Floating-point complex add Arm’s documentation

vcadd_rot90_f32Experimentalneon and fcma

Floating-point complex add Arm’s documentation

vcadd_rot270_f16Experimentalneon and fp16 and fcma

Floating-point complex add Arm’s documentation

vcadd_rot270_f32Experimentalneon and fcma

Floating-point complex add Arm’s documentation

vcaddq_rot90_f16Experimentalneon and fp16 and fcma

Floating-point complex add Arm’s documentation

vcaddq_rot90_f32Experimentalneon and fcma

Floating-point complex add Arm’s documentation

vcaddq_rot90_f64Experimentalneon and fcma

Floating-point complex add Arm’s documentation

vcaddq_rot270_f16Experimentalneon and fp16 and fcma

Floating-point complex add Arm’s documentation

vcaddq_rot270_f32Experimentalneon and fcma

Floating-point complex add Arm’s documentation

vcaddq_rot270_f64Experimentalneon and fcma

Floating-point complex add Arm’s documentation

vcageh_f16Experimentalneon and fp16

Floating-point absolute compare greater than or equal Arm’s documentation

vcagth_f16Experimentalneon and fp16

Floating-point absolute compare greater than Arm’s documentation

vcaleh_f16Experimentalneon and fp16

Floating-point absolute compare less than or equal Arm’s documentation

vcalth_f16Experimentalneon and fp16

Floating-point absolute compare less than Arm’s documentation

vceqh_f16Experimentalneon and fp16

Floating-point compare equal Arm’s documentation

vceqzh_f16Experimentalneon and fp16

Floating-point compare bitwise equal to zero Arm’s documentation

vcgeh_f16Experimentalneon and fp16

Floating-point compare greater than or equal Arm’s documentation

vcgezh_f16Experimentalneon and fp16

Floating-point compare greater than or equal to zero Arm’s documentation

vcgth_f16Experimentalneon and fp16

Floating-point compare greater than Arm’s documentation

vcgtzh_f16Experimentalneon and fp16

Floating-point compare greater than zero Arm’s documentation

vcleh_f16Experimentalneon and fp16

Floating-point compare less than or equal Arm’s documentation

vclezh_f16Experimentalneon and fp16

Floating-point compare less than or equal to zero Arm’s documentation

vclth_f16Experimentalneon and fp16

Floating-point compare less than Arm’s documentation

vcltzh_f16Experimentalneon and fp16

Floating-point compare less than zero Arm’s documentation

vcmla_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmla_lane_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_lane_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmla_laneq_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_laneq_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot90_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot90_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot90_lane_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot90_lane_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot90_laneq_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot90_laneq_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot180_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot180_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot180_lane_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot180_lane_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot180_laneq_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot180_laneq_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot270_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot270_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot270_lane_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot270_lane_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot270_laneq_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmla_rot270_laneq_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_f64Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_lane_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_lane_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_laneq_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_laneq_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot90_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot90_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot90_f64Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot90_lane_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot90_lane_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot90_laneq_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot90_laneq_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot180_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot180_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot180_f64Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot180_lane_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot180_lane_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot180_laneq_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot180_laneq_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot270_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot270_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot270_f64Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot270_lane_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot270_lane_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot270_laneq_f16Experimentalneon and fcma and fp16

Floating-point complex multiply accumulate Arm’s documentation

vcmlaq_rot270_laneq_f32Experimentalneon and fcma

Floating-point complex multiply accumulate Arm’s documentation

vcvtah_s16_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation

vcvtah_s32_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation

vcvtah_s64_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation

vcvtah_u16_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation

vcvtah_u32_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation

vcvtah_u64_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation

vcvth_f16_s16Experimentalneon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvth_f16_s32Experimentalneon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvth_f16_s64Experimentalneon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvth_f16_u16Experimentalneon and fp16

Unsigned fixed-point convert to floating-point Arm’s documentation

vcvth_f16_u32Experimentalneon and fp16

Unsigned fixed-point convert to floating-point Arm’s documentation

vcvth_f16_u64Experimentalneon and fp16

Unsigned fixed-point convert to floating-point Arm’s documentation

vcvth_n_f16_s16Experimentalneon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvth_n_f16_s32Experimentalneon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvth_n_f16_s64Experimentalneon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvth_n_f16_u16Experimentalneon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvth_n_f16_u32Experimentalneon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvth_n_f16_u64Experimentalneon and fp16

Fixed-point convert to floating-point Arm’s documentation

vcvth_n_s16_f16Experimentalneon and fp16

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvth_n_s32_f16Experimentalneon and fp16

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvth_n_s64_f16Experimentalneon and fp16

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvth_n_u16_f16Experimentalneon and fp16

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvth_n_u32_f16Experimentalneon and fp16

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvth_n_u64_f16Experimentalneon and fp16

Floating-point convert to fixed-point, rounding toward zero Arm’s documentation

vcvth_s16_f16Experimentalneon and fp16

Floating-point convert to signed fixed-point Arm’s documentation

vcvth_s32_f16Experimentalneon and fp16

Floating-point convert to signed fixed-point Arm’s documentation

vcvth_s64_f16Experimentalneon and fp16

Floating-point convert to signed fixed-point Arm’s documentation

vcvth_u16_f16Experimentalneon and fp16

Floating-point convert to unsigned fixed-point Arm’s documentation

vcvth_u32_f16Experimentalneon and fp16

Floating-point convert to unsigned fixed-point Arm’s documentation

vcvth_u64_f16Experimentalneon and fp16

Floating-point convert to unsigned fixed-point Arm’s documentation

vcvtmh_s16_f16Experimentalneon and fp16

Floating-point convert to integer, rounding towards minus infinity Arm’s documentation

vcvtmh_s32_f16Experimentalneon and fp16

Floating-point convert to integer, rounding towards minus infinity Arm’s documentation

vcvtmh_s64_f16Experimentalneon and fp16

Floating-point convert to integer, rounding towards minus infinity Arm’s documentation

vcvtmh_u16_f16Experimentalneon and fp16

Floating-point convert to integer, rounding towards minus infinity Arm’s documentation

vcvtmh_u32_f16Experimentalneon and fp16

Floating-point convert to unsigned integer, rounding towards minus infinity Arm’s documentation

vcvtmh_u64_f16Experimentalneon and fp16

Floating-point convert to unsigned integer, rounding towards minus infinity Arm’s documentation

vcvtnh_s16_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to nearest with ties to even Arm’s documentation

vcvtnh_s32_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to nearest with ties to even Arm’s documentation

vcvtnh_s64_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to nearest with ties to even Arm’s documentation

vcvtnh_u16_f16Experimentalneon and fp16

Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation

vcvtnh_u32_f16Experimentalneon and fp16

Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation

vcvtnh_u64_f16Experimentalneon and fp16

Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation

vcvtph_s16_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to plus infinity Arm’s documentation

vcvtph_s32_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to plus infinity Arm’s documentation

vcvtph_s64_f16Experimentalneon and fp16

Floating-point convert to integer, rounding to plus infinity Arm’s documentation

vcvtph_u16_f16Experimentalneon and fp16

Floating-point convert to unsigned integer, rounding to plus infinity Arm’s documentation

vcvtph_u32_f16Experimentalneon and fp16

Floating-point convert to unsigned integer, rounding to plus infinity Arm’s documentation

vcvtph_u64_f16Experimentalneon and fp16

Floating-point convert to unsigned integer, rounding to plus infinity Arm’s documentation

vdivh_f16Experimentalneon and fp16

Divide Arm’s documentation

vdot_lane_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and dotprod

Dot product arithmetic (indexed) Arm’s documentation

vdot_lane_u32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and dotprod

Dot product arithmetic (indexed) Arm’s documentation

vdot_laneq_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and dotprod

Dot product arithmetic (indexed) Arm’s documentation

vdot_laneq_u32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and dotprod

Dot product arithmetic (indexed) Arm’s documentation

vdot_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and dotprod

Dot product arithmetic (vector) Arm’s documentation

vdot_u32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and dotprod

Dot product arithmetic (vector) Arm’s documentation

vdotq_lane_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and dotprod

Dot product arithmetic (indexed) Arm’s documentation

vdotq_lane_u32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and dotprod

Dot product arithmetic (indexed) Arm’s documentation

vdotq_laneq_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and dotprod

Dot product arithmetic (indexed) Arm’s documentation

vdotq_laneq_u32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and dotprod

Dot product arithmetic (indexed) Arm’s documentation

vdotq_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and dotprod

Dot product arithmetic (vector) Arm’s documentation

vdotq_u32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and dotprod

Dot product arithmetic (vector) Arm’s documentation

vdup_n_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Create a new vector with all lanes set to a value Arm’s documentation

vduph_lane_f16Experimentalneon and fp16

Set all vector lanes to the same value Arm’s documentation

vduph_laneq_f16Experimentalneon and fp16

Extract an element from a vector Arm’s documentation

vdupq_n_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Create a new vector with all lanes set to a value Arm’s documentation

vfma_n_f16Experimentalneon and fp16

Floating-point fused Multiply-Subtract from accumulator. Arm’s documentation

vfmah_f16Experimentalneon and fp16

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmah_lane_f16Experimentalneon and fp16

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmah_laneq_f16Experimentalneon and fp16

Floating-point fused multiply-add to accumulator Arm’s documentation

vfmaq_n_f16Experimentalneon and fp16

Floating-point fused Multiply-Subtract from accumulator. Arm’s documentation

vfms_n_f16Experimentalneon and fp16

Floating-point fused Multiply-Subtract from accumulator. Arm’s documentation

vfmsh_f16Experimentalneon and fp16

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfmsh_lane_f16Experimentalneon and fp16

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfmsh_laneq_f16Experimentalneon and fp16

Floating-point fused multiply-subtract from accumulator Arm’s documentation

vfmsq_n_f16Experimentalneon and fp16

Floating-point fused Multiply-Subtract from accumulator. Arm’s documentation

vget_lane_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Duplicate vector element to scalar Arm’s documentation

vgetq_lane_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Duplicate vector element to scalar Arm’s documentation

vld1_dup_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Load one single-element structure and replicate to all lanes of one register Arm’s documentation

vld1_f16^⚠Experimentalneon and fp16

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_f16_x2^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_f16_x3^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_f16_x4^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Load one single-element structure to one lane of one register Arm’s documentation

vld1q_dup_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Load one single-element structure and replicate to all lanes of one register Arm’s documentation

vld1q_f16^⚠Experimentalneon and fp16

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_f16_x2^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_f16_x3^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_f16_x4^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Load multiple single-element structures to one, two, three, or four registers Arm’s documentation

vld1q_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Load one single-element structure to one lane of one register Arm’s documentation

vld2_dup_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld2q_dup_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation

vld2q_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load multiple 2-element structures to two registers Arm’s documentation

vld3_dup_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load single 3-element structure and replicate to all lanes of two registers Arm’s documentation

vld3_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load single 3-element structure and replicate to all lanes of two registers Arm’s documentation

vld3_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load multiple 3-element structures to two registers Arm’s documentation

vld3q_dup_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load single 3-element structure and replicate to all lanes of two registers Arm’s documentation

vld3q_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load single 3-element structure and replicate to all lanes of two registers Arm’s documentation

vld3q_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Load multiple 3-element structures to two registers Arm’s documentation

vld4_dup_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Load single 4-element structure and replicate to all lanes of two registers Arm’s documentation

vld4_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Load single 4-element structure and replicate to all lanes of two registers Arm’s documentation

vld4_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Load multiple 4-element structures to two registers Arm’s documentation

vld4q_dup_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Load single 4-element structure and replicate to all lanes of two registers Arm’s documentation

vld4q_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Load single 4-element structure and replicate to all lanes of two registers Arm’s documentation

vld4q_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Load multiple 4-element structures to two registers Arm’s documentation

vldap1_lane_p64^⚠Experimentalneon and rcpc3

Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation

vldap1_lane_s64^⚠Experimentalneon and rcpc3

Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation

vldap1_lane_u64^⚠Experimentalneon and rcpc3

Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation

vldap1q_lane_f64^⚠Experimentalneon and rcpc3

Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation

vldap1q_lane_p64^⚠Experimentalneon and rcpc3

Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation

vldap1q_lane_s64^⚠Experimentalneon and rcpc3

Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation

vldap1q_lane_u64^⚠Experimentalneon and rcpc3

Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation

vluti2_lane_f16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_lane_p8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_lane_p16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_lane_s8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_lane_s16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_lane_u8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_lane_u16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_laneq_f16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_laneq_p8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_laneq_p16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_laneq_s8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_laneq_s16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_laneq_u8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2_laneq_u16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_lane_f16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_lane_p8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_lane_p16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_lane_s8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_lane_s16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_lane_u8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_lane_u16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_laneq_f16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_laneq_p8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_laneq_p16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_laneq_s8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_laneq_s16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_laneq_u8^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti2q_laneq_u16^⚠Experimentalneon and lut

Lookup table read with 2-bit indices Arm’s documentation

vluti4q_lane_f16_x2^⚠Experimentalneon and lut and fp16

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_lane_p8^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_lane_p16_x2^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_lane_s8^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_lane_s16_x2^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_lane_u8^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_lane_u16_x2^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_laneq_f16_x2^⚠Experimentalneon and lut and fp16

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_laneq_p8^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_laneq_p16_x2^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_laneq_s8^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_laneq_s16_x2^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_laneq_u8^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vluti4q_laneq_u16_x2^⚠Experimentalneon and lut

Lookup table read with 4-bit indices Arm’s documentation

vmaxh_f16Experimentalneon and fp16

Maximum (vector) Arm’s documentation

vmaxnmh_f16Experimentalneon and fp16

Floating-point Maximum Number Arm’s documentation

vmaxnmv_f16Experimentalneon and fp16

Floating-point maximum number across vector Arm’s documentation

vmaxnmvq_f16Experimentalneon and fp16

Floating-point maximum number across vector Arm’s documentation

vmaxv_f16Experimentalneon and fp16

Floating-point maximum number across vector Arm’s documentation

vmaxvq_f16Experimentalneon and fp16

Floating-point maximum number across vector Arm’s documentation

vminh_f16Experimentalneon and fp16

Minimum (vector) Arm’s documentation

vminnmh_f16Experimentalneon and fp16

Floating-point Minimum Number Arm’s documentation

vminnmv_f16Experimentalneon and fp16

Floating-point minimum number across vector Arm’s documentation

vminnmvq_f16Experimentalneon and fp16

Floating-point minimum number across vector Arm’s documentation

vminv_f16Experimentalneon and fp16

Floating-point minimum number across vector Arm’s documentation

vminvq_f16Experimentalneon and fp16

Floating-point minimum number across vector Arm’s documentation

vmmlaq_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and i8mm

8-bit integer matrix multiply-accumulate Arm’s documentation

vmmlaq_u32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and i8mm

8-bit integer matrix multiply-accumulate Arm’s documentation

vmov_n_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Duplicate element to vector Arm’s documentation

vmovq_n_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Duplicate element to vector Arm’s documentation

vmul_n_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Vector multiply by scalar Arm’s documentation

vmulh_f16Experimentalneon and fp16

Add Arm’s documentation

vmulh_lane_f16Experimentalneon and fp16

Floating-point multiply Arm’s documentation

vmulh_laneq_f16Experimentalneon and fp16

Floating-point multiply Arm’s documentation

vmulq_n_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Vector multiply by scalar Arm’s documentation

vmulx_n_f16Experimentalneon and fp16

Vector multiply by scalar Arm’s documentation

vmulxh_f16Experimentalneon and fp16

Floating-point multiply extended Arm’s documentation

vmulxh_lane_f16Experimentalneon and fp16

Floating-point multiply extended Arm’s documentation

vmulxh_laneq_f16Experimentalneon and fp16

Floating-point multiply extended Arm’s documentation

vmulxq_n_f16Experimentalneon and fp16

Vector multiply by scalar Arm’s documentation

vnegh_f16Experimentalneon and fp16

Negate Arm’s documentation

vrecpeh_f16Experimentalneon and fp16

Reciprocal estimate. Arm’s documentation

vrecpsh_f16Experimentalneon and fp16

Floating-point reciprocal step Arm’s documentation

vrecpxh_f16Experimentalneon and fp16

Floating-point reciprocal exponent Arm’s documentation

vrnd32x_f32Experimentalneon and frintts

Floating-point round to 32-bit integer, using current rounding mode Arm’s documentation

vrnd32x_f64Experimentalneon and frintts

Floating-point round to 32-bit integer, using current rounding mode Arm’s documentation

vrnd32xq_f32Experimentalneon and frintts

Floating-point round to 32-bit integer, using current rounding mode Arm’s documentation

vrnd32xq_f64Experimentalneon and frintts

Floating-point round to 32-bit integer, using current rounding mode Arm’s documentation

vrnd32z_f32Experimentalneon and frintts

Floating-point round to 32-bit integer toward zero Arm’s documentation

vrnd32z_f64Experimentalneon and frintts

Floating-point round to 32-bit integer toward zero Arm’s documentation

vrnd32zq_f32Experimentalneon and frintts

Floating-point round to 32-bit integer toward zero Arm’s documentation

vrnd32zq_f64Experimentalneon and frintts

Floating-point round to 32-bit integer toward zero Arm’s documentation

vrnd64x_f32Experimentalneon and frintts

Floating-point round to 64-bit integer, using current rounding mode Arm’s documentation

vrnd64x_f64Experimentalneon and frintts

Floating-point round to 64-bit integer, using current rounding mode Arm’s documentation

vrnd64xq_f32Experimentalneon and frintts

Floating-point round to 64-bit integer, using current rounding mode Arm’s documentation

vrnd64xq_f64Experimentalneon and frintts

Floating-point round to 64-bit integer, using current rounding mode Arm’s documentation

vrnd64z_f32Experimentalneon and frintts

Floating-point round to 64-bit integer toward zero Arm’s documentation

vrnd64z_f64Experimentalneon and frintts

Floating-point round to 64-bit integer toward zero Arm’s documentation

vrnd64zq_f32Experimentalneon and frintts

Floating-point round to 64-bit integer toward zero Arm’s documentation

vrnd64zq_f64Experimentalneon and frintts

Floating-point round to 64-bit integer toward zero Arm’s documentation

vrndah_f16Experimentalneon and fp16

Floating-point round to integral, to nearest with ties to away Arm’s documentation

vrndh_f16Experimentalneon and fp16

Floating-point round to integral, to nearest with ties to away Arm’s documentation

vrndih_f16Experimentalneon and fp16

Floating-point round to integral, using current rounding mode Arm’s documentation

vrndmh_f16Experimentalneon and fp16

Floating-point round to integral, toward minus infinity Arm’s documentation

vrndnh_f16Experimentalneon and fp16

Floating-point round to integral, toward minus infinity Arm’s documentation

vrndph_f16Experimentalneon and fp16

Floating-point round to integral, toward plus infinity Arm’s documentation

vrndxh_f16Experimentalneon and fp16

Floating-point round to integral, using current rounding mode Arm’s documentation

vrsqrteh_f16Experimentalneon and fp16

Reciprocal square-root estimate. Arm’s documentation

vrsqrtsh_f16Experimentalneon and fp16

Floating-point reciprocal square root step Arm’s documentation

vscale_f16Experimentalneon and fp8

Multi-vector floating-point adjust exponent Arm’s documentation

vscale_f32Experimentalneon and fp8

Multi-vector floating-point adjust exponent Arm’s documentation

vscaleq_f16Experimentalneon and fp8

Multi-vector floating-point adjust exponent Arm’s documentation

vscaleq_f32Experimentalneon and fp8

Multi-vector floating-point adjust exponent Arm’s documentation

vscaleq_f64Experimentalneon and fp8

Multi-vector floating-point adjust exponent Arm’s documentation

vset_lane_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Insert vector element from another vector element Arm’s documentation

vsetq_lane_f16Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon and fp16

Insert vector element from another vector element Arm’s documentation

vsm3partw1q_u32Experimentalneon and sm4

SM3PARTW1 Arm’s documentation

vsm3partw2q_u32Experimentalneon and sm4

SM3PARTW2 Arm’s documentation

vsm3ss1q_u32Experimentalneon and sm4

SM3SS1 Arm’s documentation

vsm3tt1aq_u32Experimentalneon and sm4

SM3TT1A Arm’s documentation

vsm3tt1bq_u32Experimentalneon and sm4

SM3TT1B Arm’s documentation

vsm3tt2aq_u32Experimentalneon and sm4

SM3TT2A Arm’s documentation

vsm3tt2bq_u32Experimentalneon and sm4

SM3TT2B Arm’s documentation

vsm4ekeyq_u32Experimentalneon and sm4

SM4 key Arm’s documentation

vsm4eq_u32Experimentalneon and sm4

SM4 encode Arm’s documentation

vsqrth_f16Experimentalneon and fp16

Floating-point round to integral, using current rounding mode Arm’s documentation

vst1_f16^⚠Experimentalneon and fp16

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1_f16_x2^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_f16_x3^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_f16_x4^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst1q_f16^⚠Experimentalneon and fp16

Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation

vst1q_f16_x2^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_f16_x3^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_f16_x4^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon and fp16

Store multiple single-element structures to one, two, three, or four registers Arm’s documentation

vst1q_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM64EC and neon

Store multiple single-element structures from one, two, three, or four registers Arm’s documentation

vst2_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst2q_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 2-element structures from two registers Arm’s documentation

vst3_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst3q_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 3-element structures from three registers Arm’s documentation

vst4_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 4-element structures from four registers Arm’s documentation

vst4q_lane_f16^⚠Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and non-ARM and non-ARM64EC and neon

Store multiple 4-element structures from four registers Arm’s documentation

vstl1_lane_f64Experimentalneon and rcpc3

Store-Release a single-element structure from one lane of one register. Arm’s documentation

vstl1_lane_p64Experimentalneon and rcpc3

Store-Release a single-element structure from one lane of one register. Arm’s documentation

vstl1_lane_s64Experimentalneon and rcpc3

Store-Release a single-element structure from one lane of one register. Arm’s documentation

vstl1_lane_u64Experimentalneon and rcpc3

Store-Release a single-element structure from one lane of one register. Arm’s documentation

vstl1q_lane_f64Experimentalneon and rcpc3

Store-Release a single-element structure from one lane of one register. Arm’s documentation

vstl1q_lane_p64Experimentalneon and rcpc3

Store-Release a single-element structure from one lane of one register. Arm’s documentation

vstl1q_lane_s64Experimentalneon and rcpc3

Store-Release a single-element structure from one lane of one register. Arm’s documentation

vstl1q_lane_u64Experimentalneon and rcpc3

Store-Release a single-element structure from one lane of one register. Arm’s documentation

vsubh_f16Experimentalneon and fp16

Subtract Arm’s documentation

vsudot_lane_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and i8mm

Dot product index form with signed and unsigned integers Arm’s documentation

vsudot_laneq_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and i8mm

Dot product index form with signed and unsigned integers Arm’s documentation

vsudotq_lane_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and i8mm

Dot product index form with signed and unsigned integers Arm’s documentation

vsudotq_laneq_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and i8mm

Dot product index form with signed and unsigned integers Arm’s documentation

vusdot_lane_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and i8mm

Dot product index form with unsigned and signed integers Arm’s documentation

vusdot_laneq_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and i8mm

Dot product index form with unsigned and signed integers Arm’s documentation

vusdot_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and i8mm

Dot product vector form with unsigned and signed integers Arm’s documentation

vusdotq_lane_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and i8mm

Dot product index form with unsigned and signed integers Arm’s documentation

vusdotq_laneq_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and little-endian and neon and i8mm

Dot product index form with unsigned and signed integers Arm’s documentation

vusdotq_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and i8mm

Dot product vector form with unsigned and signed integers Arm’s documentation

vusmmlaq_s32Experimental(AArch64 or ARM64EC or v7) and (ARM or AArch64 or ARM64EC) and neon and i8mm

Unsigned and signed 8-bit integer matrix multiply-accumulate Arm’s documentation