/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_NET_GENERATED_TRACERS_H
#define TRACE_HW_NET_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_MII_WRITE_REG_EVENT;
extern TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_MII_READ_REG_EVENT;
extern TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_RECEIVE_EVENT;
extern TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_TRANSMIT_EVENT;
extern TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_RESET_EVENT;
extern TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_SET_LINK_EVENT;
extern TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_SUN8I_EMAC_WRITE_EVENT;
extern TraceEvent _TRACE_LAN9118_PHY_READ_EVENT;
extern TraceEvent _TRACE_LAN9118_PHY_WRITE_EVENT;
extern TraceEvent _TRACE_LAN9118_PHY_UPDATE_LINK_EVENT;
extern TraceEvent _TRACE_LAN9118_PHY_RESET_EVENT;
extern TraceEvent _TRACE_LANCE_MEM_READW_EVENT;
extern TraceEvent _TRACE_LANCE_MEM_WRITEW_EVENT;
extern TraceEvent _TRACE_NE2000_READ_EVENT;
extern TraceEvent _TRACE_NE2000_WRITE_EVENT;
extern TraceEvent _TRACE_NE2000_IOPORT_READ_EVENT;
extern TraceEvent _TRACE_NE2000_IOPORT_WRITE_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_MII_WRITE_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_MII_READ_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_UPDATE_IRQ_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_RECEIVE_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_RECEIVE_MCAST_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_RECEIVE_REJECT_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_RECEIVE_DESC_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_START_XMIT_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_REG_READ_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_REG_WRITE_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_DESC_READ_EVENT;
extern TraceEvent _TRACE_OPEN_ETH_DESC_WRITE_EVENT;
extern TraceEvent _TRACE_PCNET_S_RESET_EVENT;
extern TraceEvent _TRACE_PCNET_USER_INT_EVENT;
extern TraceEvent _TRACE_PCNET_ISR_CHANGE_EVENT;
extern TraceEvent _TRACE_PCNET_INIT_EVENT;
extern TraceEvent _TRACE_PCNET_RLEN_TLEN_EVENT;
extern TraceEvent _TRACE_PCNET_SS32_RDRA_TDRA_EVENT;
extern TraceEvent _TRACE_PCNET_APROM_WRITEB_EVENT;
extern TraceEvent _TRACE_PCNET_APROM_READB_EVENT;
extern TraceEvent _TRACE_PCNET_IOPORT_READ_EVENT;
extern TraceEvent _TRACE_PCNET_IOPORT_WRITE_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_PARSED_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_ENTRY_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_NOT_XXP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_UDP_WITH_NO_CHECKSUM_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_IP4_FRAGMENT_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_CSUM_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_ENTRY_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_UDP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_TCP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_UDP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_TCP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_PH_CSUM_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_CALC_CSUM_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_ENTRY_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_TCP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_NOT_XXP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_IP4_FRAGMENT_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_WITH_NO_CHECKSUM_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L4_CSUM_FIX_CSUM_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_ENTRY_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_NOT_IP4_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_CSUM_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_RSS_IP4_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_RSS_IP4_TCP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_RSS_IP4_UDP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_TCP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_UDP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_EX_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_EX_TCP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_RSS_IP6_EX_UDP_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_RSS_HASH_EVENT;
extern TraceEvent _TRACE_NET_RX_PKT_RSS_ADD_CHUNK_EVENT;
extern TraceEvent _TRACE_E1000_RECEIVER_OVERRUN_EVENT;
extern TraceEvent _TRACE_E1000X_RX_CAN_RECV_DISABLED_EVENT;
extern TraceEvent _TRACE_E1000X_VLAN_IS_VLAN_PKT_EVENT;
extern TraceEvent _TRACE_E1000X_RX_FLT_VLAN_MISMATCH_EVENT;
extern TraceEvent _TRACE_E1000X_RX_FLT_VLAN_MATCH_EVENT;
extern TraceEvent _TRACE_E1000X_RX_FLT_UCAST_MATCH_EVENT;
extern TraceEvent _TRACE_E1000X_RX_FLT_UCAST_MISMATCH_EVENT;
extern TraceEvent _TRACE_E1000X_RX_FLT_INEXACT_MISMATCH_EVENT;
extern TraceEvent _TRACE_E1000X_RX_LINK_DOWN_EVENT;
extern TraceEvent _TRACE_E1000X_RX_DISABLED_EVENT;
extern TraceEvent _TRACE_E1000X_RX_OVERSIZED_EVENT;
extern TraceEvent _TRACE_E1000X_MAC_INDICATE_EVENT;
extern TraceEvent _TRACE_E1000X_LINK_NEGOTIATION_START_EVENT;
extern TraceEvent _TRACE_E1000X_LINK_NEGOTIATION_DONE_EVENT;
extern TraceEvent _TRACE_E1000E_CORE_WRITE_EVENT;
extern TraceEvent _TRACE_E1000E_CORE_READ_EVENT;
extern TraceEvent _TRACE_E1000E_CORE_MDIC_READ_EVENT;
extern TraceEvent _TRACE_E1000E_CORE_MDIC_READ_UNHANDLED_EVENT;
extern TraceEvent _TRACE_E1000E_CORE_MDIC_WRITE_EVENT;
extern TraceEvent _TRACE_E1000E_CORE_MDIC_WRITE_UNHANDLED_EVENT;
extern TraceEvent _TRACE_E1000E_CORE_CTRL_WRITE_EVENT;
extern TraceEvent _TRACE_E1000E_CORE_CTRL_SW_RESET_EVENT;
extern TraceEvent _TRACE_E1000E_CORE_CTRL_PHY_RESET_EVENT;
extern TraceEvent _TRACE_E1000E_LINK_AUTONEG_FLOWCTL_EVENT;
extern TraceEvent _TRACE_E1000E_LINK_SET_PARAMS_EVENT;
extern TraceEvent _TRACE_E1000E_LINK_READ_PARAMS_EVENT;
extern TraceEvent _TRACE_E1000E_LINK_SET_EXT_PARAMS_EVENT;
extern TraceEvent _TRACE_E1000E_LINK_STATUS_EVENT;
extern TraceEvent _TRACE_E1000E_LINK_STATUS_CHANGED_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_REGS_WRITE_RO_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_REGS_WRITE_UNKNOWN_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_REGS_READ_UNKNOWN_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_REGS_READ_TRIVIAL_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_REGS_WRITE_TRIVIAL_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_NO_TS_SUPPORT_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_NO_SNAP_SUPPORT_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_ISCSI_FILTERING_NOT_SUPPORTED_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_NFSW_FILTERING_NOT_SUPPORTED_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_NFSR_FILTERING_NOT_SUPPORTED_EVENT;
extern TraceEvent _TRACE_E1000E_TX_DISABLED_EVENT;
extern TraceEvent _TRACE_E1000E_TX_DESCR_EVENT;
extern TraceEvent _TRACE_E1000E_RING_FREE_SPACE_EVENT;
extern TraceEvent _TRACE_E1000E_RX_CAN_RECV_RINGS_FULL_EVENT;
extern TraceEvent _TRACE_E1000E_RX_CAN_RECV_EVENT;
extern TraceEvent _TRACE_E1000E_RX_HAS_BUFFERS_EVENT;
extern TraceEvent _TRACE_E1000E_RX_NULL_DESCRIPTOR_EVENT;
extern TraceEvent _TRACE_E1000E_RX_DESC_PS_READ_EVENT;
extern TraceEvent _TRACE_E1000E_RX_DESC_PS_WRITE_EVENT;
extern TraceEvent _TRACE_E1000E_RX_DESC_BUFF_SIZES_EVENT;
extern TraceEvent _TRACE_E1000E_RX_DESC_LEN_EVENT;
extern TraceEvent _TRACE_E1000E_RX_DESC_BUFF_WRITE_EVENT;
extern TraceEvent _TRACE_E1000E_RX_DESCR_EVENT;
extern TraceEvent _TRACE_E1000E_RX_SET_RCTL_EVENT;
extern TraceEvent _TRACE_E1000E_RX_RECEIVE_IOV_EVENT;
extern TraceEvent _TRACE_E1000E_RX_FLT_DROPPED_EVENT;
extern TraceEvent _TRACE_E1000E_RX_WRITTEN_TO_GUEST_EVENT;
extern TraceEvent _TRACE_E1000E_RX_NOT_WRITTEN_TO_GUEST_EVENT;
extern TraceEvent _TRACE_E1000E_RX_INTERRUPT_SET_EVENT;
extern TraceEvent _TRACE_E1000E_RX_INTERRUPT_DELAYED_EVENT;
extern TraceEvent _TRACE_E1000E_RX_SET_CSO_EVENT;
extern TraceEvent _TRACE_E1000E_RX_SET_RDT_EVENT;
extern TraceEvent _TRACE_E1000E_RX_SET_RFCTL_EVENT;
extern TraceEvent _TRACE_E1000E_RX_START_RECV_EVENT;
extern TraceEvent _TRACE_E1000E_RX_RSS_STARTED_EVENT;
extern TraceEvent _TRACE_E1000E_RX_RSS_DISABLED_EVENT;
extern TraceEvent _TRACE_E1000E_RX_RSS_TYPE_EVENT;
extern TraceEvent _TRACE_E1000E_RX_RSS_IP4_EVENT;
extern TraceEvent _TRACE_E1000E_RX_RSS_IP6_RFCTL_EVENT;
extern TraceEvent _TRACE_E1000E_RX_RSS_IP6_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_PROTOCOLS_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_VLAN_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_RSS_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_IP_ID_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_ACK_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_PKT_TYPE_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_VIRTHDR_NO_CSUM_INFO_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_L3_CSO_DISABLED_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_L4_CSO_DISABLED_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_L3_CSUM_VALIDATION_FAILED_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_L4_CSUM_VALIDATION_FAILED_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_STATUS_FLAGS_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_IPV6_SUM_DISABLED_EVENT;
extern TraceEvent _TRACE_E1000E_RX_METADATA_IPV6_FILTERING_DISABLED_EVENT;
extern TraceEvent _TRACE_E1000E_VLAN_VET_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_MSI_NOTIFY_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_MSI_NOTIFY_POSTPONED_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_LEGACY_NOTIFY_POSTPONED_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_MSIX_NOTIFY_POSTPONED_VEC_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_LEGACY_NOTIFY_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_MSIX_NOTIFY_VEC_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_POSTPONED_BY_XITR_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_CLEAR_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_SET_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_FIX_ICR_ASSERTED_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_ADD_MSI_OTHER_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_PENDING_INTERRUPTS_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_WRITE_ICS_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_ICR_PROCESS_IAME_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_READ_ICS_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_READ_IMS_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_ICR_CLEAR_NONMSIX_ICR_READ_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_ICR_CLEAR_ZERO_IMS_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_ICR_CLEAR_IAME_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_ICR_CLEAR_ICR_BIT_IMS_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_IAM_CLEAR_EIAME_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_ICR_CLEAR_EIAC_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_IMS_CLEAR_SET_IMC_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_FIRE_DELAYED_INTERRUPTS_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_REARM_TIMER_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_THROTTLING_TIMER_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_RDTR_FPD_RUNNING_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_RDTR_FPD_NOT_RUNNING_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_TIDV_FPD_RUNNING_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_TIDV_FPD_NOT_RUNNING_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_EITR_SET_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_ITR_SET_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_FIRE_ALL_TIMERS_EVENT;
extern TraceEvent _TRACE_E1000E_IRQ_MSIX_PENDING_CLEARING_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_MSIX_VEC_WRONG_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_MSIX_INVALID_EVENT;
extern TraceEvent _TRACE_E1000E_MAC_SET_SW_EVENT;
extern TraceEvent _TRACE_E1000E_VM_STATE_RUNNING_EVENT;
extern TraceEvent _TRACE_E1000E_VM_STATE_STOPPED_EVENT;
extern TraceEvent _TRACE_E1000E_CB_PCI_REALIZE_EVENT;
extern TraceEvent _TRACE_E1000E_CB_PCI_UNINIT_EVENT;
extern TraceEvent _TRACE_E1000E_CB_QDEV_RESET_HOLD_EVENT;
extern TraceEvent _TRACE_E1000E_CB_PRE_SAVE_EVENT;
extern TraceEvent _TRACE_E1000E_CB_POST_LOAD_EVENT;
extern TraceEvent _TRACE_E1000E_IO_WRITE_ADDR_EVENT;
extern TraceEvent _TRACE_E1000E_IO_WRITE_DATA_EVENT;
extern TraceEvent _TRACE_E1000E_IO_READ_ADDR_EVENT;
extern TraceEvent _TRACE_E1000E_IO_READ_DATA_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_IO_WRITE_UNKNOWN_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_IO_READ_UNKNOWN_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_IO_ADDR_UNDEFINED_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_IO_ADDR_FLASH_EVENT;
extern TraceEvent _TRACE_E1000E_WRN_IO_ADDR_UNKNOWN_EVENT;
extern TraceEvent _TRACE_E1000E_MSI_INIT_FAIL_EVENT;
extern TraceEvent _TRACE_E1000E_MSIX_INIT_FAIL_EVENT;
extern TraceEvent _TRACE_E1000E_MSIX_USE_VECTOR_FAIL_EVENT;
extern TraceEvent _TRACE_E1000E_MAC_SET_PERMANENT_EVENT;
extern TraceEvent _TRACE_E1000E_CFG_SUPPORT_VIRTIO_EVENT;
extern TraceEvent _TRACE_IGB_WRITE_CONFIG_EVENT;
extern TraceEvent _TRACE_IGBVF_WRITE_CONFIG_EVENT;
extern TraceEvent _TRACE_IGB_CORE_MDIC_READ_EVENT;
extern TraceEvent _TRACE_IGB_CORE_MDIC_READ_UNHANDLED_EVENT;
extern TraceEvent _TRACE_IGB_CORE_MDIC_WRITE_EVENT;
extern TraceEvent _TRACE_IGB_CORE_MDIC_WRITE_UNHANDLED_EVENT;
extern TraceEvent _TRACE_IGB_CORE_VF_RESET_EVENT;
extern TraceEvent _TRACE_IGB_LINK_SET_EXT_PARAMS_EVENT;
extern TraceEvent _TRACE_IGB_RX_DESC_BUFF_SIZE_EVENT;
extern TraceEvent _TRACE_IGB_RX_DESC_BUFF_WRITE_EVENT;
extern TraceEvent _TRACE_IGB_RX_METADATA_RSS_EVENT;
extern TraceEvent _TRACE_IGB_IRQ_ICR_CLEAR_GPIE_NSICR_EVENT;
extern TraceEvent _TRACE_IGB_IRQ_SET_IAM_EVENT;
extern TraceEvent _TRACE_IGB_IRQ_READ_IAM_EVENT;
extern TraceEvent _TRACE_IGB_IRQ_WRITE_EICS_EVENT;
extern TraceEvent _TRACE_IGB_IRQ_WRITE_EIMS_EVENT;
extern TraceEvent _TRACE_IGB_IRQ_WRITE_EIMC_EVENT;
extern TraceEvent _TRACE_IGB_IRQ_WRITE_EIAC_EVENT;
extern TraceEvent _TRACE_IGB_IRQ_WRITE_EIAM_EVENT;
extern TraceEvent _TRACE_IGB_IRQ_WRITE_EICR_EVENT;
extern TraceEvent _TRACE_IGB_IRQ_EITR_SET_EVENT;
extern TraceEvent _TRACE_IGB_SET_PFMAILBOX_EVENT;
extern TraceEvent _TRACE_IGB_SET_VFMAILBOX_EVENT;
extern TraceEvent _TRACE_IGB_WRN_RX_DESC_MODES_NOT_SUPP_EVENT;
extern TraceEvent _TRACE_IGBVF_WRN_IO_ADDR_UNKNOWN_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_POOL_FOUND_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_FOUND_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_RECEIVE_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_RECEIVE_DMA_COMPLETED_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_RECEIVE_WROTE_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_CREATE_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_PAGE_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_H_ADD_LOGICAL_LAN_BUFFER_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_RXBUFS_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BUF_DESC_EVENT;
extern TraceEvent _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_TOTAL_EVENT;
extern TraceEvent _TRACE_SUNGEM_TX_CHECKSUM_EVENT;
extern TraceEvent _TRACE_SUNGEM_TX_CHECKSUM_OOB_EVENT;
extern TraceEvent _TRACE_SUNGEM_TX_UNFINISHED_EVENT;
extern TraceEvent _TRACE_SUNGEM_TX_OVERFLOW_EVENT;
extern TraceEvent _TRACE_SUNGEM_TX_FINISHED_EVENT;
extern TraceEvent _TRACE_SUNGEM_TX_KICK_EVENT;
extern TraceEvent _TRACE_SUNGEM_TX_DISABLED_EVENT;
extern TraceEvent _TRACE_SUNGEM_TX_PROCESS_EVENT;
extern TraceEvent _TRACE_SUNGEM_TX_DESC_EVENT;
extern TraceEvent _TRACE_SUNGEM_TX_RESET_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_MAC_DISABLED_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_TXDMA_DISABLED_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_CHECK_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_MAC_CHECK_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_MAC_MULTICAST_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_MAC_COMPARE_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_PACKET_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_DISABLED_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_BAD_FRAME_SIZE_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_UNMATCHED_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_PROCESS_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_RINGFULL_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_DESC_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_RESET_EVENT;
extern TraceEvent _TRACE_SUNGEM_RX_KICK_EVENT;
extern TraceEvent _TRACE_SUNGEM_RESET_EVENT;
extern TraceEvent _TRACE_SUNGEM_MII_WRITE_EVENT;
extern TraceEvent _TRACE_SUNGEM_MII_READ_EVENT;
extern TraceEvent _TRACE_SUNGEM_MII_INVALID_SOF_EVENT;
extern TraceEvent _TRACE_SUNGEM_MII_INVALID_OP_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_GREG_WRITE_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_GREG_READ_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_TXDMA_WRITE_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_TXDMA_READ_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_RXDMA_WRITE_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_RXDMA_READ_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_WOL_WRITE_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_WOL_READ_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_MAC_WRITE_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_MAC_READ_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_MIF_WRITE_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_MIF_READ_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_PCS_WRITE_EVENT;
extern TraceEvent _TRACE_SUNGEM_MMIO_PCS_READ_EVENT;
extern TraceEvent _TRACE_SUNHME_SEB_WRITE_EVENT;
extern TraceEvent _TRACE_SUNHME_SEB_READ_EVENT;
extern TraceEvent _TRACE_SUNHME_ETX_WRITE_EVENT;
extern TraceEvent _TRACE_SUNHME_ETX_READ_EVENT;
extern TraceEvent _TRACE_SUNHME_ERX_WRITE_EVENT;
extern TraceEvent _TRACE_SUNHME_ERX_READ_EVENT;
extern TraceEvent _TRACE_SUNHME_MAC_WRITE_EVENT;
extern TraceEvent _TRACE_SUNHME_MAC_READ_EVENT;
extern TraceEvent _TRACE_SUNHME_MII_WRITE_EVENT;
extern TraceEvent _TRACE_SUNHME_MII_READ_EVENT;
extern TraceEvent _TRACE_SUNHME_MIF_WRITE_EVENT;
extern TraceEvent _TRACE_SUNHME_MIF_READ_EVENT;
extern TraceEvent _TRACE_SUNHME_TX_DESC_EVENT;
extern TraceEvent _TRACE_SUNHME_TX_XSUM_ADD_EVENT;
extern TraceEvent _TRACE_SUNHME_TX_XSUM_STUFF_EVENT;
extern TraceEvent _TRACE_SUNHME_TX_DONE_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_INCOMING_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_FILTER_DESTMAC_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_FILTER_LOCAL_MATCH_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_FILTER_BCAST_MATCH_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_FILTER_HASH_NOMATCH_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_FILTER_HASH_MATCH_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_FILTER_PROMISC_MATCH_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_FILTER_REJECT_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_FILTER_ACCEPT_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_DESC_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_XSUM_CALC_EVENT;
extern TraceEvent _TRACE_SUNHME_RX_NORXD_EVENT;
extern TraceEvent _TRACE_SUNHME_UPDATE_IRQ_EVENT;
extern TraceEvent _TRACE_VIRTIO_NET_ANNOUNCE_NOTIFY_EVENT;
extern TraceEvent _TRACE_VIRTIO_NET_ANNOUNCE_TIMER_EVENT;
extern TraceEvent _TRACE_VIRTIO_NET_HANDLE_ANNOUNCE_EVENT;
extern TraceEvent _TRACE_VIRTIO_NET_POST_LOAD_DEVICE_EVENT;
extern TraceEvent _TRACE_VIRTIO_NET_RSS_LOAD_EVENT;
extern TraceEvent _TRACE_VIRTIO_NET_RSS_ATTACH_EBPF_EVENT;
extern TraceEvent _TRACE_VIRTIO_NET_RSS_DISABLE_EVENT;
extern TraceEvent _TRACE_VIRTIO_NET_RSS_ERROR_EVENT;
extern TraceEvent _TRACE_VIRTIO_NET_RSS_ENABLE_EVENT;
extern TraceEvent _TRACE_TULIP_REG_WRITE_EVENT;
extern TraceEvent _TRACE_TULIP_REG_READ_EVENT;
extern TraceEvent _TRACE_TULIP_RECEIVE_EVENT;
extern TraceEvent _TRACE_TULIP_DESCRIPTOR_EVENT;
extern TraceEvent _TRACE_TULIP_RX_STATE_EVENT;
extern TraceEvent _TRACE_TULIP_TX_STATE_EVENT;
extern TraceEvent _TRACE_TULIP_IRQ_EVENT;
extern TraceEvent _TRACE_TULIP_MII_WRITE_EVENT;
extern TraceEvent _TRACE_TULIP_MII_READ_EVENT;
extern TraceEvent _TRACE_TULIP_RESET_EVENT;
extern TraceEvent _TRACE_TULIP_SETUP_FRAME_EVENT;
extern TraceEvent _TRACE_TULIP_SETUP_FILTER_EVENT;
extern TraceEvent _TRACE_LASI_82596_MEM_READW_EVENT;
extern TraceEvent _TRACE_LASI_82596_MEM_WRITEW_EVENT;
extern TraceEvent _TRACE_I82596_S_RESET_EVENT;
extern TraceEvent _TRACE_I82596_TRANSMIT_EVENT;
extern TraceEvent _TRACE_I82596_RECEIVE_ANALYSIS_EVENT;
extern TraceEvent _TRACE_I82596_RECEIVE_QUEUE_FULL_EVENT;
extern TraceEvent _TRACE_I82596_RECEIVE_SUSPENDED_EVENT;
extern TraceEvent _TRACE_I82596_RX_STATE_CHANGE_EVENT;
extern TraceEvent _TRACE_I82596_NEW_MAC_EVENT;
extern TraceEvent _TRACE_I82596_SET_MULTICAST_EVENT;
extern TraceEvent _TRACE_I82596_SCB_COMMAND_EVENT;
extern TraceEvent _TRACE_I82596_DUMP_EVENT;
extern TraceEvent _TRACE_I82596_FLUSH_QUEUE_EVENT;
extern TraceEvent _TRACE_I82596_TX_TFD_EVENT;
extern TraceEvent _TRACE_I82596_TX_TBD_EVENT;
extern TraceEvent _TRACE_I82596_RX_RFD_EVENT;
extern TraceEvent _TRACE_I82596_RX_RBD_EVENT;
extern TraceEvent _TRACE_I82596_RECEIVE_PACKET_EVENT;
extern TraceEvent _TRACE_I82596_RX_SHORT_FRAME_EVENT;
extern TraceEvent _TRACE_I82596_RX_RFD_UPDATE_EVENT;
extern TraceEvent _TRACE_I82596_RX_OUT_OF_RBDS_EVENT;
extern TraceEvent _TRACE_I82596_RX_INCOMPLETE_EVENT;
extern TraceEvent _TRACE_I82596_RX_COMPLETE_EVENT;
extern TraceEvent _TRACE_I82596_RECEIVE_IOV_EVENT;
extern TraceEvent _TRACE_I82596_CA_INIT_EVENT;
extern TraceEvent _TRACE_I82596_IOPORT_WRITE_EVENT;
extern TraceEvent _TRACE_IMX_PHY_READ_NUM_EVENT;
extern TraceEvent _TRACE_IMX_PHY_WRITE_NUM_EVENT;
extern TraceEvent _TRACE_IMX_FEC_READ_BD_EVENT;
extern TraceEvent _TRACE_IMX_ENET_READ_BD_EVENT;
extern TraceEvent _TRACE_IMX_ETH_TX_BD_BUSY_EVENT;
extern TraceEvent _TRACE_IMX_ETH_RX_BD_FULL_EVENT;
extern TraceEvent _TRACE_IMX_ETH_READ_EVENT;
extern TraceEvent _TRACE_IMX_ETH_WRITE_EVENT;
extern TraceEvent _TRACE_IMX_FEC_RECEIVE_EVENT;
extern TraceEvent _TRACE_IMX_FEC_RECEIVE_LEN_EVENT;
extern TraceEvent _TRACE_IMX_FEC_RECEIVE_LAST_EVENT;
extern TraceEvent _TRACE_IMX_ENET_RECEIVE_EVENT;
extern TraceEvent _TRACE_IMX_ENET_RECEIVE_LEN_EVENT;
extern TraceEvent _TRACE_IMX_ENET_RECEIVE_LAST_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_RESET_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_UPDATE_TX_IRQ_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_UPDATE_RX_IRQ_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_SET_MISTA_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_CPU_OWNED_DESC_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_SENT_PACKET_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_TX_DONE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_CAN_RECEIVE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_PACKET_FILTERED_OUT_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_PACKET_DROPPED_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_RECEIVING_PACKET_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_RECEIVED_PACKET_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_RX_DONE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_REG_READ_EVENT;
extern TraceEvent _TRACE_NPCM7XX_EMC_REG_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_REG_READ_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_REG_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_MDIO_ACCESS_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_RESET_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_SET_LINK_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_UPDATE_IRQ_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_PACKET_DESC_READ_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_PACKET_RECEIVE_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_PACKET_RECEIVING_BUFFER_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_PACKET_RECEIVED_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_PACKET_SENT_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_DEBUG_DESC_DATA_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_PACKET_TX_DESC_DATA_EVENT;
extern TraceEvent _TRACE_NPCM_GMAC_TX_DESC_OWNER_EVENT;
extern TraceEvent _TRACE_NPCM_PCS_REG_READ_EVENT;
extern TraceEvent _TRACE_NPCM_PCS_REG_WRITE_EVENT;
extern TraceEvent _TRACE_DP8393X_RAISE_IRQ_EVENT;
extern TraceEvent _TRACE_DP8393X_LOWER_IRQ_EVENT;
extern TraceEvent _TRACE_DP8393X_LOAD_CAM_EVENT;
extern TraceEvent _TRACE_DP8393X_LOAD_CAM_DONE_EVENT;
extern TraceEvent _TRACE_DP8393X_READ_RRA_REGS_EVENT;
extern TraceEvent _TRACE_DP8393X_TRANSMIT_PACKET_EVENT;
extern TraceEvent _TRACE_DP8393X_TRANSMIT_TXLEN_ERROR_EVENT;
extern TraceEvent _TRACE_DP8393X_READ_EVENT;
extern TraceEvent _TRACE_DP8393X_WRITE_EVENT;
extern TraceEvent _TRACE_DP8393X_WRITE_INVALID_EVENT;
extern TraceEvent _TRACE_DP8393X_WRITE_INVALID_DCR_EVENT;
extern TraceEvent _TRACE_DP8393X_RECEIVE_OVERSIZE_EVENT;
extern TraceEvent _TRACE_DP8393X_RECEIVE_NOT_NETCARD_EVENT;
extern TraceEvent _TRACE_DP8393X_RECEIVE_PACKET_EVENT;
extern TraceEvent _TRACE_DP8393X_RECEIVE_WRITE_STATUS_EVENT;
extern TraceEvent _TRACE_XEN_NETDEV_REALIZE_EVENT;
extern TraceEvent _TRACE_XEN_NETDEV_UNREALIZE_EVENT;
extern TraceEvent _TRACE_XEN_NETDEV_CREATE_EVENT;
extern TraceEvent _TRACE_XEN_NETDEV_DESTROY_EVENT;
extern TraceEvent _TRACE_XEN_NETDEV_DISCONNECT_EVENT;
extern TraceEvent _TRACE_XEN_NETDEV_CONNECT_EVENT;
extern TraceEvent _TRACE_XEN_NETDEV_FRONTEND_CHANGED_EVENT;
extern TraceEvent _TRACE_XEN_NETDEV_TX_EVENT;
extern TraceEvent _TRACE_XEN_NETDEV_RX_EVENT;
extern TraceEvent _TRACE_ETHLITE_PKT_LOST_EVENT;
extern TraceEvent _TRACE_ETHLITE_PKT_SIZE_TOO_BIG_EVENT;
extern TraceEvent _TRACE_ETHLITE_PKT_TX_SIZE_TOO_BIG_EVENT;
extern uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_MII_WRITE_REG_DSTATE;
extern uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_MII_READ_REG_DSTATE;
extern uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_RECEIVE_DSTATE;
extern uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_TRANSMIT_DSTATE;
extern uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_RESET_DSTATE;
extern uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_SET_LINK_DSTATE;
extern uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_SUN8I_EMAC_WRITE_DSTATE;
extern uint16_t _TRACE_LAN9118_PHY_READ_DSTATE;
extern uint16_t _TRACE_LAN9118_PHY_WRITE_DSTATE;
extern uint16_t _TRACE_LAN9118_PHY_UPDATE_LINK_DSTATE;
extern uint16_t _TRACE_LAN9118_PHY_RESET_DSTATE;
extern uint16_t _TRACE_LANCE_MEM_READW_DSTATE;
extern uint16_t _TRACE_LANCE_MEM_WRITEW_DSTATE;
extern uint16_t _TRACE_NE2000_READ_DSTATE;
extern uint16_t _TRACE_NE2000_WRITE_DSTATE;
extern uint16_t _TRACE_NE2000_IOPORT_READ_DSTATE;
extern uint16_t _TRACE_NE2000_IOPORT_WRITE_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_MII_WRITE_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_MII_READ_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_UPDATE_IRQ_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_RECEIVE_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_RECEIVE_MCAST_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_RECEIVE_REJECT_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_RECEIVE_DESC_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_START_XMIT_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_REG_READ_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_REG_WRITE_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_DESC_READ_DSTATE;
extern uint16_t _TRACE_OPEN_ETH_DESC_WRITE_DSTATE;
extern uint16_t _TRACE_PCNET_S_RESET_DSTATE;
extern uint16_t _TRACE_PCNET_USER_INT_DSTATE;
extern uint16_t _TRACE_PCNET_ISR_CHANGE_DSTATE;
extern uint16_t _TRACE_PCNET_INIT_DSTATE;
extern uint16_t _TRACE_PCNET_RLEN_TLEN_DSTATE;
extern uint16_t _TRACE_PCNET_SS32_RDRA_TDRA_DSTATE;
extern uint16_t _TRACE_PCNET_APROM_WRITEB_DSTATE;
extern uint16_t _TRACE_PCNET_APROM_READB_DSTATE;
extern uint16_t _TRACE_PCNET_IOPORT_READ_DSTATE;
extern uint16_t _TRACE_PCNET_IOPORT_WRITE_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_PARSED_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_ENTRY_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_NOT_XXP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_UDP_WITH_NO_CHECKSUM_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_IP4_FRAGMENT_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_CSUM_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_ENTRY_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_UDP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_TCP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_UDP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_TCP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_PH_CSUM_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_CALC_CSUM_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_ENTRY_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_TCP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_NOT_XXP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_IP4_FRAGMENT_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_WITH_NO_CHECKSUM_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L4_CSUM_FIX_CSUM_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_ENTRY_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_NOT_IP4_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_CSUM_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_RSS_IP4_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_RSS_IP4_TCP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_RSS_IP4_UDP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_RSS_IP6_TCP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_RSS_IP6_UDP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_RSS_IP6_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_RSS_IP6_EX_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_RSS_IP6_EX_TCP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_RSS_IP6_EX_UDP_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_RSS_HASH_DSTATE;
extern uint16_t _TRACE_NET_RX_PKT_RSS_ADD_CHUNK_DSTATE;
extern uint16_t _TRACE_E1000_RECEIVER_OVERRUN_DSTATE;
extern uint16_t _TRACE_E1000X_RX_CAN_RECV_DISABLED_DSTATE;
extern uint16_t _TRACE_E1000X_VLAN_IS_VLAN_PKT_DSTATE;
extern uint16_t _TRACE_E1000X_RX_FLT_VLAN_MISMATCH_DSTATE;
extern uint16_t _TRACE_E1000X_RX_FLT_VLAN_MATCH_DSTATE;
extern uint16_t _TRACE_E1000X_RX_FLT_UCAST_MATCH_DSTATE;
extern uint16_t _TRACE_E1000X_RX_FLT_UCAST_MISMATCH_DSTATE;
extern uint16_t _TRACE_E1000X_RX_FLT_INEXACT_MISMATCH_DSTATE;
extern uint16_t _TRACE_E1000X_RX_LINK_DOWN_DSTATE;
extern uint16_t _TRACE_E1000X_RX_DISABLED_DSTATE;
extern uint16_t _TRACE_E1000X_RX_OVERSIZED_DSTATE;
extern uint16_t _TRACE_E1000X_MAC_INDICATE_DSTATE;
extern uint16_t _TRACE_E1000X_LINK_NEGOTIATION_START_DSTATE;
extern uint16_t _TRACE_E1000X_LINK_NEGOTIATION_DONE_DSTATE;
extern uint16_t _TRACE_E1000E_CORE_WRITE_DSTATE;
extern uint16_t _TRACE_E1000E_CORE_READ_DSTATE;
extern uint16_t _TRACE_E1000E_CORE_MDIC_READ_DSTATE;
extern uint16_t _TRACE_E1000E_CORE_MDIC_READ_UNHANDLED_DSTATE;
extern uint16_t _TRACE_E1000E_CORE_MDIC_WRITE_DSTATE;
extern uint16_t _TRACE_E1000E_CORE_MDIC_WRITE_UNHANDLED_DSTATE;
extern uint16_t _TRACE_E1000E_CORE_CTRL_WRITE_DSTATE;
extern uint16_t _TRACE_E1000E_CORE_CTRL_SW_RESET_DSTATE;
extern uint16_t _TRACE_E1000E_CORE_CTRL_PHY_RESET_DSTATE;
extern uint16_t _TRACE_E1000E_LINK_AUTONEG_FLOWCTL_DSTATE;
extern uint16_t _TRACE_E1000E_LINK_SET_PARAMS_DSTATE;
extern uint16_t _TRACE_E1000E_LINK_READ_PARAMS_DSTATE;
extern uint16_t _TRACE_E1000E_LINK_SET_EXT_PARAMS_DSTATE;
extern uint16_t _TRACE_E1000E_LINK_STATUS_DSTATE;
extern uint16_t _TRACE_E1000E_LINK_STATUS_CHANGED_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_REGS_WRITE_RO_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_REGS_WRITE_UNKNOWN_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_REGS_READ_UNKNOWN_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_REGS_READ_TRIVIAL_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_REGS_WRITE_TRIVIAL_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_NO_TS_SUPPORT_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_NO_SNAP_SUPPORT_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_ISCSI_FILTERING_NOT_SUPPORTED_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_NFSW_FILTERING_NOT_SUPPORTED_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_NFSR_FILTERING_NOT_SUPPORTED_DSTATE;
extern uint16_t _TRACE_E1000E_TX_DISABLED_DSTATE;
extern uint16_t _TRACE_E1000E_TX_DESCR_DSTATE;
extern uint16_t _TRACE_E1000E_RING_FREE_SPACE_DSTATE;
extern uint16_t _TRACE_E1000E_RX_CAN_RECV_RINGS_FULL_DSTATE;
extern uint16_t _TRACE_E1000E_RX_CAN_RECV_DSTATE;
extern uint16_t _TRACE_E1000E_RX_HAS_BUFFERS_DSTATE;
extern uint16_t _TRACE_E1000E_RX_NULL_DESCRIPTOR_DSTATE;
extern uint16_t _TRACE_E1000E_RX_DESC_PS_READ_DSTATE;
extern uint16_t _TRACE_E1000E_RX_DESC_PS_WRITE_DSTATE;
extern uint16_t _TRACE_E1000E_RX_DESC_BUFF_SIZES_DSTATE;
extern uint16_t _TRACE_E1000E_RX_DESC_LEN_DSTATE;
extern uint16_t _TRACE_E1000E_RX_DESC_BUFF_WRITE_DSTATE;
extern uint16_t _TRACE_E1000E_RX_DESCR_DSTATE;
extern uint16_t _TRACE_E1000E_RX_SET_RCTL_DSTATE;
extern uint16_t _TRACE_E1000E_RX_RECEIVE_IOV_DSTATE;
extern uint16_t _TRACE_E1000E_RX_FLT_DROPPED_DSTATE;
extern uint16_t _TRACE_E1000E_RX_WRITTEN_TO_GUEST_DSTATE;
extern uint16_t _TRACE_E1000E_RX_NOT_WRITTEN_TO_GUEST_DSTATE;
extern uint16_t _TRACE_E1000E_RX_INTERRUPT_SET_DSTATE;
extern uint16_t _TRACE_E1000E_RX_INTERRUPT_DELAYED_DSTATE;
extern uint16_t _TRACE_E1000E_RX_SET_CSO_DSTATE;
extern uint16_t _TRACE_E1000E_RX_SET_RDT_DSTATE;
extern uint16_t _TRACE_E1000E_RX_SET_RFCTL_DSTATE;
extern uint16_t _TRACE_E1000E_RX_START_RECV_DSTATE;
extern uint16_t _TRACE_E1000E_RX_RSS_STARTED_DSTATE;
extern uint16_t _TRACE_E1000E_RX_RSS_DISABLED_DSTATE;
extern uint16_t _TRACE_E1000E_RX_RSS_TYPE_DSTATE;
extern uint16_t _TRACE_E1000E_RX_RSS_IP4_DSTATE;
extern uint16_t _TRACE_E1000E_RX_RSS_IP6_RFCTL_DSTATE;
extern uint16_t _TRACE_E1000E_RX_RSS_IP6_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_PROTOCOLS_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_VLAN_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_RSS_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_IP_ID_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_ACK_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_PKT_TYPE_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_VIRTHDR_NO_CSUM_INFO_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_L3_CSO_DISABLED_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_L4_CSO_DISABLED_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_L3_CSUM_VALIDATION_FAILED_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_L4_CSUM_VALIDATION_FAILED_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_STATUS_FLAGS_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_IPV6_SUM_DISABLED_DSTATE;
extern uint16_t _TRACE_E1000E_RX_METADATA_IPV6_FILTERING_DISABLED_DSTATE;
extern uint16_t _TRACE_E1000E_VLAN_VET_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_MSI_NOTIFY_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_MSI_NOTIFY_POSTPONED_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_LEGACY_NOTIFY_POSTPONED_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_MSIX_NOTIFY_POSTPONED_VEC_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_LEGACY_NOTIFY_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_MSIX_NOTIFY_VEC_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_POSTPONED_BY_XITR_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_CLEAR_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_SET_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_FIX_ICR_ASSERTED_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_ADD_MSI_OTHER_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_PENDING_INTERRUPTS_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_WRITE_ICS_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_ICR_PROCESS_IAME_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_READ_ICS_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_READ_IMS_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_ICR_CLEAR_NONMSIX_ICR_READ_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_ICR_CLEAR_ZERO_IMS_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_ICR_CLEAR_IAME_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_ICR_CLEAR_ICR_BIT_IMS_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_IAM_CLEAR_EIAME_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_ICR_CLEAR_EIAC_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_IMS_CLEAR_SET_IMC_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_FIRE_DELAYED_INTERRUPTS_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_REARM_TIMER_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_THROTTLING_TIMER_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_RDTR_FPD_RUNNING_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_RDTR_FPD_NOT_RUNNING_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_TIDV_FPD_RUNNING_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_TIDV_FPD_NOT_RUNNING_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_EITR_SET_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_ITR_SET_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_FIRE_ALL_TIMERS_DSTATE;
extern uint16_t _TRACE_E1000E_IRQ_MSIX_PENDING_CLEARING_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_MSIX_VEC_WRONG_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_MSIX_INVALID_DSTATE;
extern uint16_t _TRACE_E1000E_MAC_SET_SW_DSTATE;
extern uint16_t _TRACE_E1000E_VM_STATE_RUNNING_DSTATE;
extern uint16_t _TRACE_E1000E_VM_STATE_STOPPED_DSTATE;
extern uint16_t _TRACE_E1000E_CB_PCI_REALIZE_DSTATE;
extern uint16_t _TRACE_E1000E_CB_PCI_UNINIT_DSTATE;
extern uint16_t _TRACE_E1000E_CB_QDEV_RESET_HOLD_DSTATE;
extern uint16_t _TRACE_E1000E_CB_PRE_SAVE_DSTATE;
extern uint16_t _TRACE_E1000E_CB_POST_LOAD_DSTATE;
extern uint16_t _TRACE_E1000E_IO_WRITE_ADDR_DSTATE;
extern uint16_t _TRACE_E1000E_IO_WRITE_DATA_DSTATE;
extern uint16_t _TRACE_E1000E_IO_READ_ADDR_DSTATE;
extern uint16_t _TRACE_E1000E_IO_READ_DATA_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_IO_WRITE_UNKNOWN_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_IO_READ_UNKNOWN_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_IO_ADDR_UNDEFINED_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_IO_ADDR_FLASH_DSTATE;
extern uint16_t _TRACE_E1000E_WRN_IO_ADDR_UNKNOWN_DSTATE;
extern uint16_t _TRACE_E1000E_MSI_INIT_FAIL_DSTATE;
extern uint16_t _TRACE_E1000E_MSIX_INIT_FAIL_DSTATE;
extern uint16_t _TRACE_E1000E_MSIX_USE_VECTOR_FAIL_DSTATE;
extern uint16_t _TRACE_E1000E_MAC_SET_PERMANENT_DSTATE;
extern uint16_t _TRACE_E1000E_CFG_SUPPORT_VIRTIO_DSTATE;
extern uint16_t _TRACE_IGB_WRITE_CONFIG_DSTATE;
extern uint16_t _TRACE_IGBVF_WRITE_CONFIG_DSTATE;
extern uint16_t _TRACE_IGB_CORE_MDIC_READ_DSTATE;
extern uint16_t _TRACE_IGB_CORE_MDIC_READ_UNHANDLED_DSTATE;
extern uint16_t _TRACE_IGB_CORE_MDIC_WRITE_DSTATE;
extern uint16_t _TRACE_IGB_CORE_MDIC_WRITE_UNHANDLED_DSTATE;
extern uint16_t _TRACE_IGB_CORE_VF_RESET_DSTATE;
extern uint16_t _TRACE_IGB_LINK_SET_EXT_PARAMS_DSTATE;
extern uint16_t _TRACE_IGB_RX_DESC_BUFF_SIZE_DSTATE;
extern uint16_t _TRACE_IGB_RX_DESC_BUFF_WRITE_DSTATE;
extern uint16_t _TRACE_IGB_RX_METADATA_RSS_DSTATE;
extern uint16_t _TRACE_IGB_IRQ_ICR_CLEAR_GPIE_NSICR_DSTATE;
extern uint16_t _TRACE_IGB_IRQ_SET_IAM_DSTATE;
extern uint16_t _TRACE_IGB_IRQ_READ_IAM_DSTATE;
extern uint16_t _TRACE_IGB_IRQ_WRITE_EICS_DSTATE;
extern uint16_t _TRACE_IGB_IRQ_WRITE_EIMS_DSTATE;
extern uint16_t _TRACE_IGB_IRQ_WRITE_EIMC_DSTATE;
extern uint16_t _TRACE_IGB_IRQ_WRITE_EIAC_DSTATE;
extern uint16_t _TRACE_IGB_IRQ_WRITE_EIAM_DSTATE;
extern uint16_t _TRACE_IGB_IRQ_WRITE_EICR_DSTATE;
extern uint16_t _TRACE_IGB_IRQ_EITR_SET_DSTATE;
extern uint16_t _TRACE_IGB_SET_PFMAILBOX_DSTATE;
extern uint16_t _TRACE_IGB_SET_VFMAILBOX_DSTATE;
extern uint16_t _TRACE_IGB_WRN_RX_DESC_MODES_NOT_SUPP_DSTATE;
extern uint16_t _TRACE_IGBVF_WRN_IO_ADDR_UNKNOWN_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_POOL_FOUND_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_FOUND_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_RECEIVE_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_RECEIVE_DMA_COMPLETED_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_RECEIVE_WROTE_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_CREATE_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_ADD_RXBUF_TO_PAGE_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_H_ADD_LOGICAL_LAN_BUFFER_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_RXBUFS_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BUF_DESC_DSTATE;
extern uint16_t _TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_TOTAL_DSTATE;
extern uint16_t _TRACE_SUNGEM_TX_CHECKSUM_DSTATE;
extern uint16_t _TRACE_SUNGEM_TX_CHECKSUM_OOB_DSTATE;
extern uint16_t _TRACE_SUNGEM_TX_UNFINISHED_DSTATE;
extern uint16_t _TRACE_SUNGEM_TX_OVERFLOW_DSTATE;
extern uint16_t _TRACE_SUNGEM_TX_FINISHED_DSTATE;
extern uint16_t _TRACE_SUNGEM_TX_KICK_DSTATE;
extern uint16_t _TRACE_SUNGEM_TX_DISABLED_DSTATE;
extern uint16_t _TRACE_SUNGEM_TX_PROCESS_DSTATE;
extern uint16_t _TRACE_SUNGEM_TX_DESC_DSTATE;
extern uint16_t _TRACE_SUNGEM_TX_RESET_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_MAC_DISABLED_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_TXDMA_DISABLED_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_CHECK_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_MAC_CHECK_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_MAC_MULTICAST_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_MAC_COMPARE_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_PACKET_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_DISABLED_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_BAD_FRAME_SIZE_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_UNMATCHED_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_PROCESS_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_RINGFULL_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_DESC_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_RESET_DSTATE;
extern uint16_t _TRACE_SUNGEM_RX_KICK_DSTATE;
extern uint16_t _TRACE_SUNGEM_RESET_DSTATE;
extern uint16_t _TRACE_SUNGEM_MII_WRITE_DSTATE;
extern uint16_t _TRACE_SUNGEM_MII_READ_DSTATE;
extern uint16_t _TRACE_SUNGEM_MII_INVALID_SOF_DSTATE;
extern uint16_t _TRACE_SUNGEM_MII_INVALID_OP_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_GREG_WRITE_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_GREG_READ_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_TXDMA_WRITE_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_TXDMA_READ_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_RXDMA_WRITE_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_RXDMA_READ_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_WOL_WRITE_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_WOL_READ_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_MAC_WRITE_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_MAC_READ_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_MIF_WRITE_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_MIF_READ_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_PCS_WRITE_DSTATE;
extern uint16_t _TRACE_SUNGEM_MMIO_PCS_READ_DSTATE;
extern uint16_t _TRACE_SUNHME_SEB_WRITE_DSTATE;
extern uint16_t _TRACE_SUNHME_SEB_READ_DSTATE;
extern uint16_t _TRACE_SUNHME_ETX_WRITE_DSTATE;
extern uint16_t _TRACE_SUNHME_ETX_READ_DSTATE;
extern uint16_t _TRACE_SUNHME_ERX_WRITE_DSTATE;
extern uint16_t _TRACE_SUNHME_ERX_READ_DSTATE;
extern uint16_t _TRACE_SUNHME_MAC_WRITE_DSTATE;
extern uint16_t _TRACE_SUNHME_MAC_READ_DSTATE;
extern uint16_t _TRACE_SUNHME_MII_WRITE_DSTATE;
extern uint16_t _TRACE_SUNHME_MII_READ_DSTATE;
extern uint16_t _TRACE_SUNHME_MIF_WRITE_DSTATE;
extern uint16_t _TRACE_SUNHME_MIF_READ_DSTATE;
extern uint16_t _TRACE_SUNHME_TX_DESC_DSTATE;
extern uint16_t _TRACE_SUNHME_TX_XSUM_ADD_DSTATE;
extern uint16_t _TRACE_SUNHME_TX_XSUM_STUFF_DSTATE;
extern uint16_t _TRACE_SUNHME_TX_DONE_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_INCOMING_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_FILTER_DESTMAC_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_FILTER_LOCAL_MATCH_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_FILTER_BCAST_MATCH_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_FILTER_HASH_NOMATCH_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_FILTER_HASH_MATCH_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_FILTER_PROMISC_MATCH_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_FILTER_REJECT_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_FILTER_ACCEPT_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_DESC_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_XSUM_CALC_DSTATE;
extern uint16_t _TRACE_SUNHME_RX_NORXD_DSTATE;
extern uint16_t _TRACE_SUNHME_UPDATE_IRQ_DSTATE;
extern uint16_t _TRACE_VIRTIO_NET_ANNOUNCE_NOTIFY_DSTATE;
extern uint16_t _TRACE_VIRTIO_NET_ANNOUNCE_TIMER_DSTATE;
extern uint16_t _TRACE_VIRTIO_NET_HANDLE_ANNOUNCE_DSTATE;
extern uint16_t _TRACE_VIRTIO_NET_POST_LOAD_DEVICE_DSTATE;
extern uint16_t _TRACE_VIRTIO_NET_RSS_LOAD_DSTATE;
extern uint16_t _TRACE_VIRTIO_NET_RSS_ATTACH_EBPF_DSTATE;
extern uint16_t _TRACE_VIRTIO_NET_RSS_DISABLE_DSTATE;
extern uint16_t _TRACE_VIRTIO_NET_RSS_ERROR_DSTATE;
extern uint16_t _TRACE_VIRTIO_NET_RSS_ENABLE_DSTATE;
extern uint16_t _TRACE_TULIP_REG_WRITE_DSTATE;
extern uint16_t _TRACE_TULIP_REG_READ_DSTATE;
extern uint16_t _TRACE_TULIP_RECEIVE_DSTATE;
extern uint16_t _TRACE_TULIP_DESCRIPTOR_DSTATE;
extern uint16_t _TRACE_TULIP_RX_STATE_DSTATE;
extern uint16_t _TRACE_TULIP_TX_STATE_DSTATE;
extern uint16_t _TRACE_TULIP_IRQ_DSTATE;
extern uint16_t _TRACE_TULIP_MII_WRITE_DSTATE;
extern uint16_t _TRACE_TULIP_MII_READ_DSTATE;
extern uint16_t _TRACE_TULIP_RESET_DSTATE;
extern uint16_t _TRACE_TULIP_SETUP_FRAME_DSTATE;
extern uint16_t _TRACE_TULIP_SETUP_FILTER_DSTATE;
extern uint16_t _TRACE_LASI_82596_MEM_READW_DSTATE;
extern uint16_t _TRACE_LASI_82596_MEM_WRITEW_DSTATE;
extern uint16_t _TRACE_I82596_S_RESET_DSTATE;
extern uint16_t _TRACE_I82596_TRANSMIT_DSTATE;
extern uint16_t _TRACE_I82596_RECEIVE_ANALYSIS_DSTATE;
extern uint16_t _TRACE_I82596_RECEIVE_QUEUE_FULL_DSTATE;
extern uint16_t _TRACE_I82596_RECEIVE_SUSPENDED_DSTATE;
extern uint16_t _TRACE_I82596_RX_STATE_CHANGE_DSTATE;
extern uint16_t _TRACE_I82596_NEW_MAC_DSTATE;
extern uint16_t _TRACE_I82596_SET_MULTICAST_DSTATE;
extern uint16_t _TRACE_I82596_SCB_COMMAND_DSTATE;
extern uint16_t _TRACE_I82596_DUMP_DSTATE;
extern uint16_t _TRACE_I82596_FLUSH_QUEUE_DSTATE;
extern uint16_t _TRACE_I82596_TX_TFD_DSTATE;
extern uint16_t _TRACE_I82596_TX_TBD_DSTATE;
extern uint16_t _TRACE_I82596_RX_RFD_DSTATE;
extern uint16_t _TRACE_I82596_RX_RBD_DSTATE;
extern uint16_t _TRACE_I82596_RECEIVE_PACKET_DSTATE;
extern uint16_t _TRACE_I82596_RX_SHORT_FRAME_DSTATE;
extern uint16_t _TRACE_I82596_RX_RFD_UPDATE_DSTATE;
extern uint16_t _TRACE_I82596_RX_OUT_OF_RBDS_DSTATE;
extern uint16_t _TRACE_I82596_RX_INCOMPLETE_DSTATE;
extern uint16_t _TRACE_I82596_RX_COMPLETE_DSTATE;
extern uint16_t _TRACE_I82596_RECEIVE_IOV_DSTATE;
extern uint16_t _TRACE_I82596_CA_INIT_DSTATE;
extern uint16_t _TRACE_I82596_IOPORT_WRITE_DSTATE;
extern uint16_t _TRACE_IMX_PHY_READ_NUM_DSTATE;
extern uint16_t _TRACE_IMX_PHY_WRITE_NUM_DSTATE;
extern uint16_t _TRACE_IMX_FEC_READ_BD_DSTATE;
extern uint16_t _TRACE_IMX_ENET_READ_BD_DSTATE;
extern uint16_t _TRACE_IMX_ETH_TX_BD_BUSY_DSTATE;
extern uint16_t _TRACE_IMX_ETH_RX_BD_FULL_DSTATE;
extern uint16_t _TRACE_IMX_ETH_READ_DSTATE;
extern uint16_t _TRACE_IMX_ETH_WRITE_DSTATE;
extern uint16_t _TRACE_IMX_FEC_RECEIVE_DSTATE;
extern uint16_t _TRACE_IMX_FEC_RECEIVE_LEN_DSTATE;
extern uint16_t _TRACE_IMX_FEC_RECEIVE_LAST_DSTATE;
extern uint16_t _TRACE_IMX_ENET_RECEIVE_DSTATE;
extern uint16_t _TRACE_IMX_ENET_RECEIVE_LEN_DSTATE;
extern uint16_t _TRACE_IMX_ENET_RECEIVE_LAST_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_RESET_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_UPDATE_TX_IRQ_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_UPDATE_RX_IRQ_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_SET_MISTA_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_CPU_OWNED_DESC_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_SENT_PACKET_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_TX_DONE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_CAN_RECEIVE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_PACKET_FILTERED_OUT_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_PACKET_DROPPED_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_RECEIVING_PACKET_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_RECEIVED_PACKET_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_RX_DONE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_REG_READ_DSTATE;
extern uint16_t _TRACE_NPCM7XX_EMC_REG_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_REG_READ_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_REG_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_MDIO_ACCESS_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_RESET_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_SET_LINK_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_UPDATE_IRQ_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_PACKET_DESC_READ_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_PACKET_RECEIVE_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_PACKET_RECEIVING_BUFFER_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_PACKET_RECEIVED_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_PACKET_SENT_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_DEBUG_DESC_DATA_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_PACKET_TX_DESC_DATA_DSTATE;
extern uint16_t _TRACE_NPCM_GMAC_TX_DESC_OWNER_DSTATE;
extern uint16_t _TRACE_NPCM_PCS_REG_READ_DSTATE;
extern uint16_t _TRACE_NPCM_PCS_REG_WRITE_DSTATE;
extern uint16_t _TRACE_DP8393X_RAISE_IRQ_DSTATE;
extern uint16_t _TRACE_DP8393X_LOWER_IRQ_DSTATE;
extern uint16_t _TRACE_DP8393X_LOAD_CAM_DSTATE;
extern uint16_t _TRACE_DP8393X_LOAD_CAM_DONE_DSTATE;
extern uint16_t _TRACE_DP8393X_READ_RRA_REGS_DSTATE;
extern uint16_t _TRACE_DP8393X_TRANSMIT_PACKET_DSTATE;
extern uint16_t _TRACE_DP8393X_TRANSMIT_TXLEN_ERROR_DSTATE;
extern uint16_t _TRACE_DP8393X_READ_DSTATE;
extern uint16_t _TRACE_DP8393X_WRITE_DSTATE;
extern uint16_t _TRACE_DP8393X_WRITE_INVALID_DSTATE;
extern uint16_t _TRACE_DP8393X_WRITE_INVALID_DCR_DSTATE;
extern uint16_t _TRACE_DP8393X_RECEIVE_OVERSIZE_DSTATE;
extern uint16_t _TRACE_DP8393X_RECEIVE_NOT_NETCARD_DSTATE;
extern uint16_t _TRACE_DP8393X_RECEIVE_PACKET_DSTATE;
extern uint16_t _TRACE_DP8393X_RECEIVE_WRITE_STATUS_DSTATE;
extern uint16_t _TRACE_XEN_NETDEV_REALIZE_DSTATE;
extern uint16_t _TRACE_XEN_NETDEV_UNREALIZE_DSTATE;
extern uint16_t _TRACE_XEN_NETDEV_CREATE_DSTATE;
extern uint16_t _TRACE_XEN_NETDEV_DESTROY_DSTATE;
extern uint16_t _TRACE_XEN_NETDEV_DISCONNECT_DSTATE;
extern uint16_t _TRACE_XEN_NETDEV_CONNECT_DSTATE;
extern uint16_t _TRACE_XEN_NETDEV_FRONTEND_CHANGED_DSTATE;
extern uint16_t _TRACE_XEN_NETDEV_TX_DSTATE;
extern uint16_t _TRACE_XEN_NETDEV_RX_DSTATE;
extern uint16_t _TRACE_ETHLITE_PKT_LOST_DSTATE;
extern uint16_t _TRACE_ETHLITE_PKT_SIZE_TOO_BIG_DSTATE;
extern uint16_t _TRACE_ETHLITE_PKT_TX_SIZE_TOO_BIG_DSTATE;
#define TRACE_ALLWINNER_SUN8I_EMAC_MII_WRITE_REG_ENABLED 1
#define TRACE_ALLWINNER_SUN8I_EMAC_MII_READ_REG_ENABLED 1
#define TRACE_ALLWINNER_SUN8I_EMAC_RECEIVE_ENABLED 1
#define TRACE_ALLWINNER_SUN8I_EMAC_TRANSMIT_ENABLED 1
#define TRACE_ALLWINNER_SUN8I_EMAC_RESET_ENABLED 1
#define TRACE_ALLWINNER_SUN8I_EMAC_SET_LINK_ENABLED 1
#define TRACE_ALLWINNER_SUN8I_EMAC_READ_ENABLED 1
#define TRACE_ALLWINNER_SUN8I_EMAC_WRITE_ENABLED 1
#define TRACE_LAN9118_PHY_READ_ENABLED 1
#define TRACE_LAN9118_PHY_WRITE_ENABLED 1
#define TRACE_LAN9118_PHY_UPDATE_LINK_ENABLED 1
#define TRACE_LAN9118_PHY_RESET_ENABLED 1
#define TRACE_LANCE_MEM_READW_ENABLED 1
#define TRACE_LANCE_MEM_WRITEW_ENABLED 1
#define TRACE_NE2000_READ_ENABLED 1
#define TRACE_NE2000_WRITE_ENABLED 1
#define TRACE_NE2000_IOPORT_READ_ENABLED 1
#define TRACE_NE2000_IOPORT_WRITE_ENABLED 1
#define TRACE_OPEN_ETH_MII_WRITE_ENABLED 1
#define TRACE_OPEN_ETH_MII_READ_ENABLED 1
#define TRACE_OPEN_ETH_UPDATE_IRQ_ENABLED 1
#define TRACE_OPEN_ETH_RECEIVE_ENABLED 1
#define TRACE_OPEN_ETH_RECEIVE_MCAST_ENABLED 1
#define TRACE_OPEN_ETH_RECEIVE_REJECT_ENABLED 1
#define TRACE_OPEN_ETH_RECEIVE_DESC_ENABLED 1
#define TRACE_OPEN_ETH_START_XMIT_ENABLED 1
#define TRACE_OPEN_ETH_REG_READ_ENABLED 1
#define TRACE_OPEN_ETH_REG_WRITE_ENABLED 1
#define TRACE_OPEN_ETH_DESC_READ_ENABLED 1
#define TRACE_OPEN_ETH_DESC_WRITE_ENABLED 1
#define TRACE_PCNET_S_RESET_ENABLED 1
#define TRACE_PCNET_USER_INT_ENABLED 1
#define TRACE_PCNET_ISR_CHANGE_ENABLED 1
#define TRACE_PCNET_INIT_ENABLED 1
#define TRACE_PCNET_RLEN_TLEN_ENABLED 1
#define TRACE_PCNET_SS32_RDRA_TDRA_ENABLED 1
#define TRACE_PCNET_APROM_WRITEB_ENABLED 1
#define TRACE_PCNET_APROM_READB_ENABLED 1
#define TRACE_PCNET_IOPORT_READ_ENABLED 1
#define TRACE_PCNET_IOPORT_WRITE_ENABLED 1
#define TRACE_NET_RX_PKT_PARSED_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_ENTRY_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_NOT_XXP_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_UDP_WITH_NO_CHECKSUM_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_IP4_FRAGMENT_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_CSUM_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_CALC_ENTRY_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_UDP_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_TCP_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_UDP_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_TCP_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_CALC_PH_CSUM_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_CALC_CSUM_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_FIX_ENTRY_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_FIX_TCP_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_FIX_NOT_XXP_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_FIX_IP4_FRAGMENT_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_WITH_NO_CHECKSUM_ENABLED 1
#define TRACE_NET_RX_PKT_L4_CSUM_FIX_CSUM_ENABLED 1
#define TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_ENTRY_ENABLED 1
#define TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_NOT_IP4_ENABLED 1
#define TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_CSUM_ENABLED 1
#define TRACE_NET_RX_PKT_RSS_IP4_ENABLED 1
#define TRACE_NET_RX_PKT_RSS_IP4_TCP_ENABLED 1
#define TRACE_NET_RX_PKT_RSS_IP4_UDP_ENABLED 1
#define TRACE_NET_RX_PKT_RSS_IP6_TCP_ENABLED 1
#define TRACE_NET_RX_PKT_RSS_IP6_UDP_ENABLED 1
#define TRACE_NET_RX_PKT_RSS_IP6_ENABLED 1
#define TRACE_NET_RX_PKT_RSS_IP6_EX_ENABLED 1
#define TRACE_NET_RX_PKT_RSS_IP6_EX_TCP_ENABLED 1
#define TRACE_NET_RX_PKT_RSS_IP6_EX_UDP_ENABLED 1
#define TRACE_NET_RX_PKT_RSS_HASH_ENABLED 1
#define TRACE_NET_RX_PKT_RSS_ADD_CHUNK_ENABLED 1
#define TRACE_E1000_RECEIVER_OVERRUN_ENABLED 1
#define TRACE_E1000X_RX_CAN_RECV_DISABLED_ENABLED 1
#define TRACE_E1000X_VLAN_IS_VLAN_PKT_ENABLED 1
#define TRACE_E1000X_RX_FLT_VLAN_MISMATCH_ENABLED 1
#define TRACE_E1000X_RX_FLT_VLAN_MATCH_ENABLED 1
#define TRACE_E1000X_RX_FLT_UCAST_MATCH_ENABLED 1
#define TRACE_E1000X_RX_FLT_UCAST_MISMATCH_ENABLED 1
#define TRACE_E1000X_RX_FLT_INEXACT_MISMATCH_ENABLED 1
#define TRACE_E1000X_RX_LINK_DOWN_ENABLED 1
#define TRACE_E1000X_RX_DISABLED_ENABLED 1
#define TRACE_E1000X_RX_OVERSIZED_ENABLED 1
#define TRACE_E1000X_MAC_INDICATE_ENABLED 1
#define TRACE_E1000X_LINK_NEGOTIATION_START_ENABLED 1
#define TRACE_E1000X_LINK_NEGOTIATION_DONE_ENABLED 1
#define TRACE_E1000E_CORE_WRITE_ENABLED 1
#define TRACE_E1000E_CORE_READ_ENABLED 1
#define TRACE_E1000E_CORE_MDIC_READ_ENABLED 1
#define TRACE_E1000E_CORE_MDIC_READ_UNHANDLED_ENABLED 1
#define TRACE_E1000E_CORE_MDIC_WRITE_ENABLED 1
#define TRACE_E1000E_CORE_MDIC_WRITE_UNHANDLED_ENABLED 1
#define TRACE_E1000E_CORE_CTRL_WRITE_ENABLED 1
#define TRACE_E1000E_CORE_CTRL_SW_RESET_ENABLED 1
#define TRACE_E1000E_CORE_CTRL_PHY_RESET_ENABLED 1
#define TRACE_E1000E_LINK_AUTONEG_FLOWCTL_ENABLED 1
#define TRACE_E1000E_LINK_SET_PARAMS_ENABLED 1
#define TRACE_E1000E_LINK_READ_PARAMS_ENABLED 1
#define TRACE_E1000E_LINK_SET_EXT_PARAMS_ENABLED 1
#define TRACE_E1000E_LINK_STATUS_ENABLED 1
#define TRACE_E1000E_LINK_STATUS_CHANGED_ENABLED 1
#define TRACE_E1000E_WRN_REGS_WRITE_RO_ENABLED 1
#define TRACE_E1000E_WRN_REGS_WRITE_UNKNOWN_ENABLED 1
#define TRACE_E1000E_WRN_REGS_READ_UNKNOWN_ENABLED 1
#define TRACE_E1000E_WRN_REGS_READ_TRIVIAL_ENABLED 1
#define TRACE_E1000E_WRN_REGS_WRITE_TRIVIAL_ENABLED 1
#define TRACE_E1000E_WRN_NO_TS_SUPPORT_ENABLED 1
#define TRACE_E1000E_WRN_NO_SNAP_SUPPORT_ENABLED 1
#define TRACE_E1000E_WRN_ISCSI_FILTERING_NOT_SUPPORTED_ENABLED 1
#define TRACE_E1000E_WRN_NFSW_FILTERING_NOT_SUPPORTED_ENABLED 1
#define TRACE_E1000E_WRN_NFSR_FILTERING_NOT_SUPPORTED_ENABLED 1
#define TRACE_E1000E_TX_DISABLED_ENABLED 1
#define TRACE_E1000E_TX_DESCR_ENABLED 1
#define TRACE_E1000E_RING_FREE_SPACE_ENABLED 1
#define TRACE_E1000E_RX_CAN_RECV_RINGS_FULL_ENABLED 1
#define TRACE_E1000E_RX_CAN_RECV_ENABLED 1
#define TRACE_E1000E_RX_HAS_BUFFERS_ENABLED 1
#define TRACE_E1000E_RX_NULL_DESCRIPTOR_ENABLED 1
#define TRACE_E1000E_RX_DESC_PS_READ_ENABLED 1
#define TRACE_E1000E_RX_DESC_PS_WRITE_ENABLED 1
#define TRACE_E1000E_RX_DESC_BUFF_SIZES_ENABLED 1
#define TRACE_E1000E_RX_DESC_LEN_ENABLED 1
#define TRACE_E1000E_RX_DESC_BUFF_WRITE_ENABLED 1
#define TRACE_E1000E_RX_DESCR_ENABLED 1
#define TRACE_E1000E_RX_SET_RCTL_ENABLED 1
#define TRACE_E1000E_RX_RECEIVE_IOV_ENABLED 1
#define TRACE_E1000E_RX_FLT_DROPPED_ENABLED 1
#define TRACE_E1000E_RX_WRITTEN_TO_GUEST_ENABLED 1
#define TRACE_E1000E_RX_NOT_WRITTEN_TO_GUEST_ENABLED 1
#define TRACE_E1000E_RX_INTERRUPT_SET_ENABLED 1
#define TRACE_E1000E_RX_INTERRUPT_DELAYED_ENABLED 1
#define TRACE_E1000E_RX_SET_CSO_ENABLED 1
#define TRACE_E1000E_RX_SET_RDT_ENABLED 1
#define TRACE_E1000E_RX_SET_RFCTL_ENABLED 1
#define TRACE_E1000E_RX_START_RECV_ENABLED 1
#define TRACE_E1000E_RX_RSS_STARTED_ENABLED 1
#define TRACE_E1000E_RX_RSS_DISABLED_ENABLED 1
#define TRACE_E1000E_RX_RSS_TYPE_ENABLED 1
#define TRACE_E1000E_RX_RSS_IP4_ENABLED 1
#define TRACE_E1000E_RX_RSS_IP6_RFCTL_ENABLED 1
#define TRACE_E1000E_RX_RSS_IP6_ENABLED 1
#define TRACE_E1000E_RX_METADATA_PROTOCOLS_ENABLED 1
#define TRACE_E1000E_RX_METADATA_VLAN_ENABLED 1
#define TRACE_E1000E_RX_METADATA_RSS_ENABLED 1
#define TRACE_E1000E_RX_METADATA_IP_ID_ENABLED 1
#define TRACE_E1000E_RX_METADATA_ACK_ENABLED 1
#define TRACE_E1000E_RX_METADATA_PKT_TYPE_ENABLED 1
#define TRACE_E1000E_RX_METADATA_VIRTHDR_NO_CSUM_INFO_ENABLED 1
#define TRACE_E1000E_RX_METADATA_L3_CSO_DISABLED_ENABLED 1
#define TRACE_E1000E_RX_METADATA_L4_CSO_DISABLED_ENABLED 1
#define TRACE_E1000E_RX_METADATA_L3_CSUM_VALIDATION_FAILED_ENABLED 1
#define TRACE_E1000E_RX_METADATA_L4_CSUM_VALIDATION_FAILED_ENABLED 1
#define TRACE_E1000E_RX_METADATA_STATUS_FLAGS_ENABLED 1
#define TRACE_E1000E_RX_METADATA_IPV6_SUM_DISABLED_ENABLED 1
#define TRACE_E1000E_RX_METADATA_IPV6_FILTERING_DISABLED_ENABLED 1
#define TRACE_E1000E_VLAN_VET_ENABLED 1
#define TRACE_E1000E_IRQ_MSI_NOTIFY_ENABLED 1
#define TRACE_E1000E_IRQ_MSI_NOTIFY_POSTPONED_ENABLED 1
#define TRACE_E1000E_IRQ_LEGACY_NOTIFY_POSTPONED_ENABLED 1
#define TRACE_E1000E_IRQ_MSIX_NOTIFY_POSTPONED_VEC_ENABLED 1
#define TRACE_E1000E_IRQ_LEGACY_NOTIFY_ENABLED 1
#define TRACE_E1000E_IRQ_MSIX_NOTIFY_VEC_ENABLED 1
#define TRACE_E1000E_IRQ_POSTPONED_BY_XITR_ENABLED 1
#define TRACE_E1000E_IRQ_CLEAR_ENABLED 1
#define TRACE_E1000E_IRQ_SET_ENABLED 1
#define TRACE_E1000E_IRQ_FIX_ICR_ASSERTED_ENABLED 1
#define TRACE_E1000E_IRQ_ADD_MSI_OTHER_ENABLED 1
#define TRACE_E1000E_IRQ_PENDING_INTERRUPTS_ENABLED 1
#define TRACE_E1000E_IRQ_WRITE_ICS_ENABLED 1
#define TRACE_E1000E_IRQ_ICR_PROCESS_IAME_ENABLED 1
#define TRACE_E1000E_IRQ_READ_ICS_ENABLED 1
#define TRACE_E1000E_IRQ_READ_IMS_ENABLED 1
#define TRACE_E1000E_IRQ_ICR_CLEAR_NONMSIX_ICR_READ_ENABLED 1
#define TRACE_E1000E_IRQ_ICR_CLEAR_ZERO_IMS_ENABLED 1
#define TRACE_E1000E_IRQ_ICR_CLEAR_IAME_ENABLED 1
#define TRACE_E1000E_IRQ_ICR_CLEAR_ICR_BIT_IMS_ENABLED 1
#define TRACE_E1000E_IRQ_IAM_CLEAR_EIAME_ENABLED 1
#define TRACE_E1000E_IRQ_ICR_CLEAR_EIAC_ENABLED 1
#define TRACE_E1000E_IRQ_IMS_CLEAR_SET_IMC_ENABLED 1
#define TRACE_E1000E_IRQ_FIRE_DELAYED_INTERRUPTS_ENABLED 1
#define TRACE_E1000E_IRQ_REARM_TIMER_ENABLED 1
#define TRACE_E1000E_IRQ_THROTTLING_TIMER_ENABLED 1
#define TRACE_E1000E_IRQ_RDTR_FPD_RUNNING_ENABLED 1
#define TRACE_E1000E_IRQ_RDTR_FPD_NOT_RUNNING_ENABLED 1
#define TRACE_E1000E_IRQ_TIDV_FPD_RUNNING_ENABLED 1
#define TRACE_E1000E_IRQ_TIDV_FPD_NOT_RUNNING_ENABLED 1
#define TRACE_E1000E_IRQ_EITR_SET_ENABLED 1
#define TRACE_E1000E_IRQ_ITR_SET_ENABLED 1
#define TRACE_E1000E_IRQ_FIRE_ALL_TIMERS_ENABLED 1
#define TRACE_E1000E_IRQ_MSIX_PENDING_CLEARING_ENABLED 1
#define TRACE_E1000E_WRN_MSIX_VEC_WRONG_ENABLED 1
#define TRACE_E1000E_WRN_MSIX_INVALID_ENABLED 1
#define TRACE_E1000E_MAC_SET_SW_ENABLED 1
#define TRACE_E1000E_VM_STATE_RUNNING_ENABLED 1
#define TRACE_E1000E_VM_STATE_STOPPED_ENABLED 1
#define TRACE_E1000E_CB_PCI_REALIZE_ENABLED 1
#define TRACE_E1000E_CB_PCI_UNINIT_ENABLED 1
#define TRACE_E1000E_CB_QDEV_RESET_HOLD_ENABLED 1
#define TRACE_E1000E_CB_PRE_SAVE_ENABLED 1
#define TRACE_E1000E_CB_POST_LOAD_ENABLED 1
#define TRACE_E1000E_IO_WRITE_ADDR_ENABLED 1
#define TRACE_E1000E_IO_WRITE_DATA_ENABLED 1
#define TRACE_E1000E_IO_READ_ADDR_ENABLED 1
#define TRACE_E1000E_IO_READ_DATA_ENABLED 1
#define TRACE_E1000E_WRN_IO_WRITE_UNKNOWN_ENABLED 1
#define TRACE_E1000E_WRN_IO_READ_UNKNOWN_ENABLED 1
#define TRACE_E1000E_WRN_IO_ADDR_UNDEFINED_ENABLED 1
#define TRACE_E1000E_WRN_IO_ADDR_FLASH_ENABLED 1
#define TRACE_E1000E_WRN_IO_ADDR_UNKNOWN_ENABLED 1
#define TRACE_E1000E_MSI_INIT_FAIL_ENABLED 1
#define TRACE_E1000E_MSIX_INIT_FAIL_ENABLED 1
#define TRACE_E1000E_MSIX_USE_VECTOR_FAIL_ENABLED 1
#define TRACE_E1000E_MAC_SET_PERMANENT_ENABLED 1
#define TRACE_E1000E_CFG_SUPPORT_VIRTIO_ENABLED 1
#define TRACE_IGB_WRITE_CONFIG_ENABLED 1
#define TRACE_IGBVF_WRITE_CONFIG_ENABLED 1
#define TRACE_IGB_CORE_MDIC_READ_ENABLED 1
#define TRACE_IGB_CORE_MDIC_READ_UNHANDLED_ENABLED 1
#define TRACE_IGB_CORE_MDIC_WRITE_ENABLED 1
#define TRACE_IGB_CORE_MDIC_WRITE_UNHANDLED_ENABLED 1
#define TRACE_IGB_CORE_VF_RESET_ENABLED 1
#define TRACE_IGB_LINK_SET_EXT_PARAMS_ENABLED 1
#define TRACE_IGB_RX_DESC_BUFF_SIZE_ENABLED 1
#define TRACE_IGB_RX_DESC_BUFF_WRITE_ENABLED 1
#define TRACE_IGB_RX_METADATA_RSS_ENABLED 1
#define TRACE_IGB_IRQ_ICR_CLEAR_GPIE_NSICR_ENABLED 1
#define TRACE_IGB_IRQ_SET_IAM_ENABLED 1
#define TRACE_IGB_IRQ_READ_IAM_ENABLED 1
#define TRACE_IGB_IRQ_WRITE_EICS_ENABLED 1
#define TRACE_IGB_IRQ_WRITE_EIMS_ENABLED 1
#define TRACE_IGB_IRQ_WRITE_EIMC_ENABLED 1
#define TRACE_IGB_IRQ_WRITE_EIAC_ENABLED 1
#define TRACE_IGB_IRQ_WRITE_EIAM_ENABLED 1
#define TRACE_IGB_IRQ_WRITE_EICR_ENABLED 1
#define TRACE_IGB_IRQ_EITR_SET_ENABLED 1
#define TRACE_IGB_SET_PFMAILBOX_ENABLED 1
#define TRACE_IGB_SET_VFMAILBOX_ENABLED 1
#define TRACE_IGB_WRN_RX_DESC_MODES_NOT_SUPP_ENABLED 1
#define TRACE_IGBVF_WRN_IO_ADDR_UNKNOWN_ENABLED 1
#define TRACE_SPAPR_VLAN_GET_RX_BD_FROM_POOL_FOUND_ENABLED 1
#define TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_ENABLED 1
#define TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_FOUND_ENABLED 1
#define TRACE_SPAPR_VLAN_RECEIVE_ENABLED 1
#define TRACE_SPAPR_VLAN_RECEIVE_DMA_COMPLETED_ENABLED 1
#define TRACE_SPAPR_VLAN_RECEIVE_WROTE_ENABLED 1
#define TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_CREATE_ENABLED 1
#define TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_ENABLED 1
#define TRACE_SPAPR_VLAN_ADD_RXBUF_TO_PAGE_ENABLED 1
#define TRACE_SPAPR_VLAN_H_ADD_LOGICAL_LAN_BUFFER_ENABLED 1
#define TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_ENABLED 1
#define TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_RXBUFS_ENABLED 1
#define TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BUF_DESC_ENABLED 1
#define TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_TOTAL_ENABLED 1
#define TRACE_SUNGEM_TX_CHECKSUM_ENABLED 1
#define TRACE_SUNGEM_TX_CHECKSUM_OOB_ENABLED 1
#define TRACE_SUNGEM_TX_UNFINISHED_ENABLED 1
#define TRACE_SUNGEM_TX_OVERFLOW_ENABLED 1
#define TRACE_SUNGEM_TX_FINISHED_ENABLED 1
#define TRACE_SUNGEM_TX_KICK_ENABLED 1
#define TRACE_SUNGEM_TX_DISABLED_ENABLED 1
#define TRACE_SUNGEM_TX_PROCESS_ENABLED 1
#define TRACE_SUNGEM_TX_DESC_ENABLED 1
#define TRACE_SUNGEM_TX_RESET_ENABLED 1
#define TRACE_SUNGEM_RX_MAC_DISABLED_ENABLED 1
#define TRACE_SUNGEM_RX_TXDMA_DISABLED_ENABLED 1
#define TRACE_SUNGEM_RX_CHECK_ENABLED 1
#define TRACE_SUNGEM_RX_MAC_CHECK_ENABLED 1
#define TRACE_SUNGEM_RX_MAC_MULTICAST_ENABLED 1
#define TRACE_SUNGEM_RX_MAC_COMPARE_ENABLED 1
#define TRACE_SUNGEM_RX_PACKET_ENABLED 1
#define TRACE_SUNGEM_RX_DISABLED_ENABLED 1
#define TRACE_SUNGEM_RX_BAD_FRAME_SIZE_ENABLED 1
#define TRACE_SUNGEM_RX_UNMATCHED_ENABLED 1
#define TRACE_SUNGEM_RX_PROCESS_ENABLED 1
#define TRACE_SUNGEM_RX_RINGFULL_ENABLED 1
#define TRACE_SUNGEM_RX_DESC_ENABLED 1
#define TRACE_SUNGEM_RX_RESET_ENABLED 1
#define TRACE_SUNGEM_RX_KICK_ENABLED 1
#define TRACE_SUNGEM_RESET_ENABLED 1
#define TRACE_SUNGEM_MII_WRITE_ENABLED 1
#define TRACE_SUNGEM_MII_READ_ENABLED 1
#define TRACE_SUNGEM_MII_INVALID_SOF_ENABLED 1
#define TRACE_SUNGEM_MII_INVALID_OP_ENABLED 1
#define TRACE_SUNGEM_MMIO_GREG_WRITE_ENABLED 1
#define TRACE_SUNGEM_MMIO_GREG_READ_ENABLED 1
#define TRACE_SUNGEM_MMIO_TXDMA_WRITE_ENABLED 1
#define TRACE_SUNGEM_MMIO_TXDMA_READ_ENABLED 1
#define TRACE_SUNGEM_MMIO_RXDMA_WRITE_ENABLED 1
#define TRACE_SUNGEM_MMIO_RXDMA_READ_ENABLED 1
#define TRACE_SUNGEM_MMIO_WOL_WRITE_ENABLED 1
#define TRACE_SUNGEM_MMIO_WOL_READ_ENABLED 1
#define TRACE_SUNGEM_MMIO_MAC_WRITE_ENABLED 1
#define TRACE_SUNGEM_MMIO_MAC_READ_ENABLED 1
#define TRACE_SUNGEM_MMIO_MIF_WRITE_ENABLED 1
#define TRACE_SUNGEM_MMIO_MIF_READ_ENABLED 1
#define TRACE_SUNGEM_MMIO_PCS_WRITE_ENABLED 1
#define TRACE_SUNGEM_MMIO_PCS_READ_ENABLED 1
#define TRACE_SUNHME_SEB_WRITE_ENABLED 1
#define TRACE_SUNHME_SEB_READ_ENABLED 1
#define TRACE_SUNHME_ETX_WRITE_ENABLED 1
#define TRACE_SUNHME_ETX_READ_ENABLED 1
#define TRACE_SUNHME_ERX_WRITE_ENABLED 1
#define TRACE_SUNHME_ERX_READ_ENABLED 1
#define TRACE_SUNHME_MAC_WRITE_ENABLED 1
#define TRACE_SUNHME_MAC_READ_ENABLED 1
#define TRACE_SUNHME_MII_WRITE_ENABLED 1
#define TRACE_SUNHME_MII_READ_ENABLED 1
#define TRACE_SUNHME_MIF_WRITE_ENABLED 1
#define TRACE_SUNHME_MIF_READ_ENABLED 1
#define TRACE_SUNHME_TX_DESC_ENABLED 1
#define TRACE_SUNHME_TX_XSUM_ADD_ENABLED 1
#define TRACE_SUNHME_TX_XSUM_STUFF_ENABLED 1
#define TRACE_SUNHME_TX_DONE_ENABLED 1
#define TRACE_SUNHME_RX_INCOMING_ENABLED 1
#define TRACE_SUNHME_RX_FILTER_DESTMAC_ENABLED 1
#define TRACE_SUNHME_RX_FILTER_LOCAL_MATCH_ENABLED 1
#define TRACE_SUNHME_RX_FILTER_BCAST_MATCH_ENABLED 1
#define TRACE_SUNHME_RX_FILTER_HASH_NOMATCH_ENABLED 1
#define TRACE_SUNHME_RX_FILTER_HASH_MATCH_ENABLED 1
#define TRACE_SUNHME_RX_FILTER_PROMISC_MATCH_ENABLED 1
#define TRACE_SUNHME_RX_FILTER_REJECT_ENABLED 1
#define TRACE_SUNHME_RX_FILTER_ACCEPT_ENABLED 1
#define TRACE_SUNHME_RX_DESC_ENABLED 1
#define TRACE_SUNHME_RX_XSUM_CALC_ENABLED 1
#define TRACE_SUNHME_RX_NORXD_ENABLED 1
#define TRACE_SUNHME_UPDATE_IRQ_ENABLED 1
#define TRACE_VIRTIO_NET_ANNOUNCE_NOTIFY_ENABLED 1
#define TRACE_VIRTIO_NET_ANNOUNCE_TIMER_ENABLED 1
#define TRACE_VIRTIO_NET_HANDLE_ANNOUNCE_ENABLED 1
#define TRACE_VIRTIO_NET_POST_LOAD_DEVICE_ENABLED 1
#define TRACE_VIRTIO_NET_RSS_LOAD_ENABLED 1
#define TRACE_VIRTIO_NET_RSS_ATTACH_EBPF_ENABLED 1
#define TRACE_VIRTIO_NET_RSS_DISABLE_ENABLED 1
#define TRACE_VIRTIO_NET_RSS_ERROR_ENABLED 1
#define TRACE_VIRTIO_NET_RSS_ENABLE_ENABLED 1
#define TRACE_TULIP_REG_WRITE_ENABLED 1
#define TRACE_TULIP_REG_READ_ENABLED 1
#define TRACE_TULIP_RECEIVE_ENABLED 1
#define TRACE_TULIP_DESCRIPTOR_ENABLED 1
#define TRACE_TULIP_RX_STATE_ENABLED 1
#define TRACE_TULIP_TX_STATE_ENABLED 1
#define TRACE_TULIP_IRQ_ENABLED 1
#define TRACE_TULIP_MII_WRITE_ENABLED 1
#define TRACE_TULIP_MII_READ_ENABLED 1
#define TRACE_TULIP_RESET_ENABLED 1
#define TRACE_TULIP_SETUP_FRAME_ENABLED 1
#define TRACE_TULIP_SETUP_FILTER_ENABLED 1
#define TRACE_LASI_82596_MEM_READW_ENABLED 1
#define TRACE_LASI_82596_MEM_WRITEW_ENABLED 1
#define TRACE_I82596_S_RESET_ENABLED 1
#define TRACE_I82596_TRANSMIT_ENABLED 1
#define TRACE_I82596_RECEIVE_ANALYSIS_ENABLED 1
#define TRACE_I82596_RECEIVE_QUEUE_FULL_ENABLED 1
#define TRACE_I82596_RECEIVE_SUSPENDED_ENABLED 1
#define TRACE_I82596_RX_STATE_CHANGE_ENABLED 1
#define TRACE_I82596_NEW_MAC_ENABLED 1
#define TRACE_I82596_SET_MULTICAST_ENABLED 1
#define TRACE_I82596_SCB_COMMAND_ENABLED 1
#define TRACE_I82596_DUMP_ENABLED 1
#define TRACE_I82596_FLUSH_QUEUE_ENABLED 1
#define TRACE_I82596_TX_TFD_ENABLED 1
#define TRACE_I82596_TX_TBD_ENABLED 1
#define TRACE_I82596_RX_RFD_ENABLED 1
#define TRACE_I82596_RX_RBD_ENABLED 1
#define TRACE_I82596_RECEIVE_PACKET_ENABLED 1
#define TRACE_I82596_RX_SHORT_FRAME_ENABLED 1
#define TRACE_I82596_RX_RFD_UPDATE_ENABLED 1
#define TRACE_I82596_RX_OUT_OF_RBDS_ENABLED 1
#define TRACE_I82596_RX_INCOMPLETE_ENABLED 1
#define TRACE_I82596_RX_COMPLETE_ENABLED 1
#define TRACE_I82596_RECEIVE_IOV_ENABLED 1
#define TRACE_I82596_CA_INIT_ENABLED 1
#define TRACE_I82596_IOPORT_WRITE_ENABLED 1
#define TRACE_IMX_PHY_READ_NUM_ENABLED 1
#define TRACE_IMX_PHY_WRITE_NUM_ENABLED 1
#define TRACE_IMX_FEC_READ_BD_ENABLED 1
#define TRACE_IMX_ENET_READ_BD_ENABLED 1
#define TRACE_IMX_ETH_TX_BD_BUSY_ENABLED 1
#define TRACE_IMX_ETH_RX_BD_FULL_ENABLED 1
#define TRACE_IMX_ETH_READ_ENABLED 1
#define TRACE_IMX_ETH_WRITE_ENABLED 1
#define TRACE_IMX_FEC_RECEIVE_ENABLED 1
#define TRACE_IMX_FEC_RECEIVE_LEN_ENABLED 1
#define TRACE_IMX_FEC_RECEIVE_LAST_ENABLED 1
#define TRACE_IMX_ENET_RECEIVE_ENABLED 1
#define TRACE_IMX_ENET_RECEIVE_LEN_ENABLED 1
#define TRACE_IMX_ENET_RECEIVE_LAST_ENABLED 1
#define TRACE_NPCM7XX_EMC_RESET_ENABLED 1
#define TRACE_NPCM7XX_EMC_UPDATE_TX_IRQ_ENABLED 1
#define TRACE_NPCM7XX_EMC_UPDATE_RX_IRQ_ENABLED 1
#define TRACE_NPCM7XX_EMC_SET_MISTA_ENABLED 1
#define TRACE_NPCM7XX_EMC_CPU_OWNED_DESC_ENABLED 1
#define TRACE_NPCM7XX_EMC_SENT_PACKET_ENABLED 1
#define TRACE_NPCM7XX_EMC_TX_DONE_ENABLED 1
#define TRACE_NPCM7XX_EMC_CAN_RECEIVE_ENABLED 1
#define TRACE_NPCM7XX_EMC_PACKET_FILTERED_OUT_ENABLED 1
#define TRACE_NPCM7XX_EMC_PACKET_DROPPED_ENABLED 1
#define TRACE_NPCM7XX_EMC_RECEIVING_PACKET_ENABLED 1
#define TRACE_NPCM7XX_EMC_RECEIVED_PACKET_ENABLED 1
#define TRACE_NPCM7XX_EMC_RX_DONE_ENABLED 1
#define TRACE_NPCM7XX_EMC_REG_READ_ENABLED 1
#define TRACE_NPCM7XX_EMC_REG_WRITE_ENABLED 1
#define TRACE_NPCM_GMAC_REG_READ_ENABLED 1
#define TRACE_NPCM_GMAC_REG_WRITE_ENABLED 1
#define TRACE_NPCM_GMAC_MDIO_ACCESS_ENABLED 1
#define TRACE_NPCM_GMAC_RESET_ENABLED 1
#define TRACE_NPCM_GMAC_SET_LINK_ENABLED 1
#define TRACE_NPCM_GMAC_UPDATE_IRQ_ENABLED 1
#define TRACE_NPCM_GMAC_PACKET_DESC_READ_ENABLED 1
#define TRACE_NPCM_GMAC_PACKET_RECEIVE_ENABLED 1
#define TRACE_NPCM_GMAC_PACKET_RECEIVING_BUFFER_ENABLED 1
#define TRACE_NPCM_GMAC_PACKET_RECEIVED_ENABLED 1
#define TRACE_NPCM_GMAC_PACKET_SENT_ENABLED 1
#define TRACE_NPCM_GMAC_DEBUG_DESC_DATA_ENABLED 1
#define TRACE_NPCM_GMAC_PACKET_TX_DESC_DATA_ENABLED 1
#define TRACE_NPCM_GMAC_TX_DESC_OWNER_ENABLED 1
#define TRACE_NPCM_PCS_REG_READ_ENABLED 1
#define TRACE_NPCM_PCS_REG_WRITE_ENABLED 1
#define TRACE_DP8393X_RAISE_IRQ_ENABLED 1
#define TRACE_DP8393X_LOWER_IRQ_ENABLED 1
#define TRACE_DP8393X_LOAD_CAM_ENABLED 1
#define TRACE_DP8393X_LOAD_CAM_DONE_ENABLED 1
#define TRACE_DP8393X_READ_RRA_REGS_ENABLED 1
#define TRACE_DP8393X_TRANSMIT_PACKET_ENABLED 1
#define TRACE_DP8393X_TRANSMIT_TXLEN_ERROR_ENABLED 1
#define TRACE_DP8393X_READ_ENABLED 1
#define TRACE_DP8393X_WRITE_ENABLED 1
#define TRACE_DP8393X_WRITE_INVALID_ENABLED 1
#define TRACE_DP8393X_WRITE_INVALID_DCR_ENABLED 1
#define TRACE_DP8393X_RECEIVE_OVERSIZE_ENABLED 1
#define TRACE_DP8393X_RECEIVE_NOT_NETCARD_ENABLED 1
#define TRACE_DP8393X_RECEIVE_PACKET_ENABLED 1
#define TRACE_DP8393X_RECEIVE_WRITE_STATUS_ENABLED 1
#define TRACE_XEN_NETDEV_REALIZE_ENABLED 1
#define TRACE_XEN_NETDEV_UNREALIZE_ENABLED 1
#define TRACE_XEN_NETDEV_CREATE_ENABLED 1
#define TRACE_XEN_NETDEV_DESTROY_ENABLED 1
#define TRACE_XEN_NETDEV_DISCONNECT_ENABLED 1
#define TRACE_XEN_NETDEV_CONNECT_ENABLED 1
#define TRACE_XEN_NETDEV_FRONTEND_CHANGED_ENABLED 1
#define TRACE_XEN_NETDEV_TX_ENABLED 1
#define TRACE_XEN_NETDEV_RX_ENABLED 1
#define TRACE_ETHLITE_PKT_LOST_ENABLED 1
#define TRACE_ETHLITE_PKT_SIZE_TOO_BIG_ENABLED 1
#define TRACE_ETHLITE_PKT_TX_SIZE_TOO_BIG_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_ALLWINNER_SUN8I_EMAC_MII_WRITE_REG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SUN8I_EMAC_MII_WRITE_REG) || \
    false)

static inline void trace_allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SUN8I_EMAC_MII_WRITE_REG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 4 "../hw/net/trace-events"
            qemu_log("allwinner_sun8i_emac_mii_write_reg " "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32 "\n", reg, value);
#line 1364 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_ALLWINNER_SUN8I_EMAC_MII_READ_REG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SUN8I_EMAC_MII_READ_REG) || \
    false)

static inline void trace_allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SUN8I_EMAC_MII_READ_REG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../hw/net/trace-events"
            qemu_log("allwinner_sun8i_emac_mii_read_reg " "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32 "\n", reg, value);
#line 1379 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_ALLWINNER_SUN8I_EMAC_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SUN8I_EMAC_RECEIVE) || \
    false)

static inline void trace_allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SUN8I_EMAC_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 6 "../hw/net/trace-events"
            qemu_log("allwinner_sun8i_emac_receive " "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 "\n", desc, paddr, bytes);
#line 1394 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_ALLWINNER_SUN8I_EMAC_TRANSMIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SUN8I_EMAC_TRANSMIT) || \
    false)

static inline void trace_allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SUN8I_EMAC_TRANSMIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 7 "../hw/net/trace-events"
            qemu_log("allwinner_sun8i_emac_transmit " "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 "\n", desc, paddr, bytes);
#line 1409 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_ALLWINNER_SUN8I_EMAC_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SUN8I_EMAC_RESET) || \
    false)

static inline void trace_allwinner_sun8i_emac_reset(void)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SUN8I_EMAC_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 8 "../hw/net/trace-events"
            qemu_log("allwinner_sun8i_emac_reset " "HW reset" "\n");
#line 1424 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_ALLWINNER_SUN8I_EMAC_SET_LINK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SUN8I_EMAC_SET_LINK) || \
    false)

static inline void trace_allwinner_sun8i_emac_set_link(bool active)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SUN8I_EMAC_SET_LINK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 9 "../hw/net/trace-events"
            qemu_log("allwinner_sun8i_emac_set_link " "Set link: active=%u" "\n", active);
#line 1439 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_ALLWINNER_SUN8I_EMAC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SUN8I_EMAC_READ) || \
    false)

static inline void trace_allwinner_sun8i_emac_read(uint64_t offset, uint64_t val)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SUN8I_EMAC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 10 "../hw/net/trace-events"
            qemu_log("allwinner_sun8i_emac_read " "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 "\n", offset, val);
#line 1454 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_ALLWINNER_SUN8I_EMAC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SUN8I_EMAC_WRITE) || \
    false)

static inline void trace_allwinner_sun8i_emac_write(uint64_t offset, uint64_t val)
{
    if (trace_event_get_state(TRACE_ALLWINNER_SUN8I_EMAC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 11 "../hw/net/trace-events"
            qemu_log("allwinner_sun8i_emac_write " "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 "\n", offset, val);
#line 1469 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_LAN9118_PHY_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LAN9118_PHY_READ) || \
    false)

static inline void trace_lan9118_phy_read(uint16_t val, int reg)
{
    if (trace_event_get_state(TRACE_LAN9118_PHY_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../hw/net/trace-events"
            qemu_log("lan9118_phy_read " "[0x%02x] -> 0x%04" PRIx16 "\n", val, reg);
#line 1484 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_LAN9118_PHY_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LAN9118_PHY_WRITE) || \
    false)

static inline void trace_lan9118_phy_write(uint16_t val, int reg)
{
    if (trace_event_get_state(TRACE_LAN9118_PHY_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../hw/net/trace-events"
            qemu_log("lan9118_phy_write " "[0x%02x] <- 0x%04" PRIx16 "\n", val, reg);
#line 1499 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_LAN9118_PHY_UPDATE_LINK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LAN9118_PHY_UPDATE_LINK) || \
    false)

static inline void trace_lan9118_phy_update_link(const char *s)
{
    if (trace_event_get_state(TRACE_LAN9118_PHY_UPDATE_LINK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../hw/net/trace-events"
            qemu_log("lan9118_phy_update_link " "%s" "\n", s);
#line 1514 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_LAN9118_PHY_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LAN9118_PHY_RESET) || \
    false)

static inline void trace_lan9118_phy_reset(void)
{
    if (trace_event_get_state(TRACE_LAN9118_PHY_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 17 "../hw/net/trace-events"
            qemu_log("lan9118_phy_reset " "" "\n");
#line 1529 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_LANCE_MEM_READW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LANCE_MEM_READW) || \
    false)

static inline void trace_lance_mem_readw(uint64_t addr, uint32_t ret)
{
    if (trace_event_get_state(TRACE_LANCE_MEM_READW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../hw/net/trace-events"
            qemu_log("lance_mem_readw " "addr=0x%"PRIx64"val=0x%04x" "\n", addr, ret);
#line 1544 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_LANCE_MEM_WRITEW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LANCE_MEM_WRITEW) || \
    false)

static inline void trace_lance_mem_writew(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_LANCE_MEM_WRITEW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 21 "../hw/net/trace-events"
            qemu_log("lance_mem_writew " "addr=0x%"PRIx64"val=0x%04x" "\n", addr, val);
#line 1559 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NE2000_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NE2000_READ) || \
    false)

static inline void trace_ne2000_read(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_NE2000_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 24 "../hw/net/trace-events"
            qemu_log("ne2000_read " "read addr=0x%" PRIx64 " val=0x%" PRIx64 "\n", addr, val);
#line 1574 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NE2000_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NE2000_WRITE) || \
    false)

static inline void trace_ne2000_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_NE2000_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 25 "../hw/net/trace-events"
            qemu_log("ne2000_write " "write addr=0x%" PRIx64 " val=0x%" PRIx64 "\n", addr, val);
#line 1589 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NE2000_IOPORT_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NE2000_IOPORT_READ) || \
    false)

static inline void trace_ne2000_ioport_read(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_NE2000_IOPORT_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 26 "../hw/net/trace-events"
            qemu_log("ne2000_ioport_read " "io read addr=0x%02" PRIx64 " val=0x%02" PRIx64 "\n", addr, val);
#line 1604 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NE2000_IOPORT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NE2000_IOPORT_WRITE) || \
    false)

static inline void trace_ne2000_ioport_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_NE2000_IOPORT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 27 "../hw/net/trace-events"
            qemu_log("ne2000_ioport_write " "io write addr=0x%02" PRIx64 " val=0x%02" PRIx64 "\n", addr, val);
#line 1619 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_MII_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_MII_WRITE) || \
    false)

static inline void trace_open_eth_mii_write(unsigned idx, uint16_t v)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_MII_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 30 "../hw/net/trace-events"
            qemu_log("open_eth_mii_write " "MII[0x%02x] <- 0x%04x" "\n", idx, v);
#line 1634 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_MII_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_MII_READ) || \
    false)

static inline void trace_open_eth_mii_read(unsigned idx, uint16_t v)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_MII_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 31 "../hw/net/trace-events"
            qemu_log("open_eth_mii_read " "MII[0x%02x] -> 0x%04x" "\n", idx, v);
#line 1649 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_UPDATE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_UPDATE_IRQ) || \
    false)

static inline void trace_open_eth_update_irq(uint32_t v)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_UPDATE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 32 "../hw/net/trace-events"
            qemu_log("open_eth_update_irq " "IRQ <- 0x%x" "\n", v);
#line 1664 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_RECEIVE) || \
    false)

static inline void trace_open_eth_receive(unsigned len)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 33 "../hw/net/trace-events"
            qemu_log("open_eth_receive " "RX: len: %u" "\n", len);
#line 1679 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_RECEIVE_MCAST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_RECEIVE_MCAST) || \
    false)

static inline void trace_open_eth_receive_mcast(unsigned idx, uint32_t h0, uint32_t h1)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_RECEIVE_MCAST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 34 "../hw/net/trace-events"
            qemu_log("open_eth_receive_mcast " "MCAST: idx = %u, hash: %08x:%08x" "\n", idx, h0, h1);
#line 1694 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_RECEIVE_REJECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_RECEIVE_REJECT) || \
    false)

static inline void trace_open_eth_receive_reject(void)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_RECEIVE_REJECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 35 "../hw/net/trace-events"
            qemu_log("open_eth_receive_reject " "RX: rejected" "\n");
#line 1709 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_RECEIVE_DESC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_RECEIVE_DESC) || \
    false)

static inline void trace_open_eth_receive_desc(uint32_t addr, uint32_t len_flags)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_RECEIVE_DESC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 36 "../hw/net/trace-events"
            qemu_log("open_eth_receive_desc " "RX: 0x%08x, len_flags: 0x%08x" "\n", addr, len_flags);
#line 1724 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_START_XMIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_START_XMIT) || \
    false)

static inline void trace_open_eth_start_xmit(uint32_t addr, unsigned len, unsigned tx_len)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_START_XMIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 37 "../hw/net/trace-events"
            qemu_log("open_eth_start_xmit " "TX: 0x%08x, len: %u, tx_len: %u" "\n", addr, len, tx_len);
#line 1739 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_REG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_REG_READ) || \
    false)

static inline void trace_open_eth_reg_read(uint32_t addr, uint32_t v)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_REG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 38 "../hw/net/trace-events"
            qemu_log("open_eth_reg_read " "MAC[0x%02x] -> 0x%08x" "\n", addr, v);
#line 1754 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_REG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_REG_WRITE) || \
    false)

static inline void trace_open_eth_reg_write(uint32_t addr, uint32_t v)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_REG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 39 "../hw/net/trace-events"
            qemu_log("open_eth_reg_write " "MAC[0x%02x] <- 0x%08x" "\n", addr, v);
#line 1769 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_DESC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_DESC_READ) || \
    false)

static inline void trace_open_eth_desc_read(uint32_t addr, uint32_t v)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_DESC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 40 "../hw/net/trace-events"
            qemu_log("open_eth_desc_read " "DESC[0x%04x] -> 0x%08x" "\n", addr, v);
#line 1784 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_OPEN_ETH_DESC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_OPEN_ETH_DESC_WRITE) || \
    false)

static inline void trace_open_eth_desc_write(uint32_t addr, uint32_t v)
{
    if (trace_event_get_state(TRACE_OPEN_ETH_DESC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 41 "../hw/net/trace-events"
            qemu_log("open_eth_desc_write " "DESC[0x%04x] <- 0x%08x" "\n", addr, v);
#line 1799 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_PCNET_S_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCNET_S_RESET) || \
    false)

static inline void trace_pcnet_s_reset(void *s)
{
    if (trace_event_get_state(TRACE_PCNET_S_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 44 "../hw/net/trace-events"
            qemu_log("pcnet_s_reset " "s=%p" "\n", s);
#line 1814 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_PCNET_USER_INT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCNET_USER_INT) || \
    false)

static inline void trace_pcnet_user_int(void *s)
{
    if (trace_event_get_state(TRACE_PCNET_USER_INT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 45 "../hw/net/trace-events"
            qemu_log("pcnet_user_int " "s=%p" "\n", s);
#line 1829 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_PCNET_ISR_CHANGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCNET_ISR_CHANGE) || \
    false)

static inline void trace_pcnet_isr_change(void *s, uint32_t isr, uint32_t isr_old)
{
    if (trace_event_get_state(TRACE_PCNET_ISR_CHANGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 46 "../hw/net/trace-events"
            qemu_log("pcnet_isr_change " "s=%p INTA=%d<=%d" "\n", s, isr, isr_old);
#line 1844 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_PCNET_INIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCNET_INIT) || \
    false)

static inline void trace_pcnet_init(void *s, uint64_t init_addr)
{
    if (trace_event_get_state(TRACE_PCNET_INIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 47 "../hw/net/trace-events"
            qemu_log("pcnet_init " "s=%p init_addr=0x%"PRIx64 "\n", s, init_addr);
#line 1859 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_PCNET_RLEN_TLEN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCNET_RLEN_TLEN) || \
    false)

static inline void trace_pcnet_rlen_tlen(void *s, uint32_t rlen, uint32_t tlen)
{
    if (trace_event_get_state(TRACE_PCNET_RLEN_TLEN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 48 "../hw/net/trace-events"
            qemu_log("pcnet_rlen_tlen " "s=%p rlen=%d tlen=%d" "\n", s, rlen, tlen);
#line 1874 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_PCNET_SS32_RDRA_TDRA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCNET_SS32_RDRA_TDRA) || \
    false)

static inline void trace_pcnet_ss32_rdra_tdra(void *s, uint32_t ss32, uint32_t rdra, uint32_t rcvrl, uint32_t tdra, uint32_t xmtrl)
{
    if (trace_event_get_state(TRACE_PCNET_SS32_RDRA_TDRA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 49 "../hw/net/trace-events"
            qemu_log("pcnet_ss32_rdra_tdra " "s=%p ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]" "\n", s, ss32, rdra, rcvrl, tdra, xmtrl);
#line 1889 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_PCNET_APROM_WRITEB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCNET_APROM_WRITEB) || \
    false)

static inline void trace_pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_PCNET_APROM_WRITEB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 52 "../hw/net/trace-events"
            qemu_log("pcnet_aprom_writeb " "opaque=%p addr=0x%08x val=0x%02x" "\n", opaque, addr, val);
#line 1904 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_PCNET_APROM_READB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCNET_APROM_READB) || \
    false)

static inline void trace_pcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_PCNET_APROM_READB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 53 "../hw/net/trace-events"
            qemu_log("pcnet_aprom_readb " "opaque=%p addr=0x%08x val=0x%02x" "\n", opaque, addr, val);
#line 1919 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_PCNET_IOPORT_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCNET_IOPORT_READ) || \
    false)

static inline void trace_pcnet_ioport_read(void *opaque, uint64_t addr, unsigned size)
{
    if (trace_event_get_state(TRACE_PCNET_IOPORT_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 54 "../hw/net/trace-events"
            qemu_log("pcnet_ioport_read " "opaque=%p addr=0x%"PRIx64" size=%d" "\n", opaque, addr, size);
#line 1934 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_PCNET_IOPORT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCNET_IOPORT_WRITE) || \
    false)

static inline void trace_pcnet_ioport_write(void *opaque, uint64_t addr, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_PCNET_IOPORT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 55 "../hw/net/trace-events"
            qemu_log("pcnet_ioport_write " "opaque=%p addr=0x%"PRIx64" data=0x%"PRIx64" size=%d" "\n", opaque, addr, data, size);
#line 1949 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_PARSED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_PARSED) || \
    false)

static inline void trace_net_rx_pkt_parsed(bool ip4, bool ip6, int l4proto, size_t l3o, size_t l4o, size_t l5o)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_PARSED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 58 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_parsed " "RX packet parsed: ip4: %d, ip6: %d, l4 protocol: %d, l3 offset: %zu, l4 offset: %zu, l5 offset: %zu" "\n", ip4, ip6, l4proto, l3o, l4o, l5o);
#line 1964 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_ENTRY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_ENTRY) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_validate_entry(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_ENTRY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 59 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_validate_entry " "Starting L4 checksum validation" "\n");
#line 1979 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_NOT_XXP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_NOT_XXP) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_validate_not_xxp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_NOT_XXP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 60 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_validate_not_xxp " "Not a TCP/UDP packet" "\n");
#line 1994 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_UDP_WITH_NO_CHECKSUM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_UDP_WITH_NO_CHECKSUM) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_validate_udp_with_no_checksum(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_UDP_WITH_NO_CHECKSUM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 61 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_validate_udp_with_no_checksum " "UDP packet without checksum" "\n");
#line 2009 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_IP4_FRAGMENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_IP4_FRAGMENT) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_validate_ip4_fragment(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_IP4_FRAGMENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 62 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_validate_ip4_fragment " "IP4 fragment" "\n");
#line 2024 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_CSUM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_CSUM) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_validate_csum(bool csum_valid)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_VALIDATE_CSUM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 63 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_validate_csum " "Checksum valid: %d" "\n", csum_valid);
#line 2039 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_CALC_ENTRY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_CALC_ENTRY) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_calc_entry(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_CALC_ENTRY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 65 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_calc_entry " "Starting L4 checksum calculation" "\n");
#line 2054 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_UDP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_UDP) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_calc_ip4_udp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_UDP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 66 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_calc_ip4_udp " "IP4/UDP packet" "\n");
#line 2069 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_TCP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_TCP) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_calc_ip4_tcp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_CALC_IP4_TCP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 67 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_calc_ip4_tcp " "IP4/TCP packet" "\n");
#line 2084 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_UDP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_UDP) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_calc_ip6_udp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_UDP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 68 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_calc_ip6_udp " "IP6/UDP packet" "\n");
#line 2099 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_TCP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_TCP) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_calc_ip6_tcp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_CALC_IP6_TCP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 69 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_calc_ip6_tcp " "IP6/TCP packet" "\n");
#line 2114 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_CALC_PH_CSUM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_CALC_PH_CSUM) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_calc_ph_csum(uint32_t cntr, uint16_t csl)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_CALC_PH_CSUM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 70 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_calc_ph_csum " "Pseudo-header: checksum counter %u, length %u" "\n", cntr, csl);
#line 2129 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_CALC_CSUM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_CALC_CSUM) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_calc_csum(size_t l4hdr_off, uint16_t csl, uint32_t cntr, uint16_t csum)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_CALC_CSUM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 71 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_calc_csum " "L4 Checksum: L4 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X" "\n", l4hdr_off, csl, cntr, csum);
#line 2144 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_FIX_ENTRY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_FIX_ENTRY) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_fix_entry(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_FIX_ENTRY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 73 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_fix_entry " "Starting L4 checksum correction" "\n");
#line 2159 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_FIX_TCP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_FIX_TCP) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_fix_tcp(uint32_t l4_cso)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_FIX_TCP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 74 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_fix_tcp " "TCP packet, L4 cso: %u" "\n", l4_cso);
#line 2174 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_fix_udp(uint32_t l4_cso)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 75 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_fix_udp " "UDP packet, L4 cso: %u" "\n", l4_cso);
#line 2189 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_FIX_NOT_XXP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_FIX_NOT_XXP) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_fix_not_xxp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_FIX_NOT_XXP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 76 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_fix_not_xxp " "Not an IP4 packet" "\n");
#line 2204 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_FIX_IP4_FRAGMENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_FIX_IP4_FRAGMENT) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_fix_ip4_fragment(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_FIX_IP4_FRAGMENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 77 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_fix_ip4_fragment " "IP4 fragment" "\n");
#line 2219 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_WITH_NO_CHECKSUM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_WITH_NO_CHECKSUM) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_fix_udp_with_no_checksum(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_FIX_UDP_WITH_NO_CHECKSUM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 78 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_fix_udp_with_no_checksum " "UDP packet without checksum" "\n");
#line 2234 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L4_CSUM_FIX_CSUM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L4_CSUM_FIX_CSUM) || \
    false)

static inline void trace_net_rx_pkt_l4_csum_fix_csum(uint32_t cso, uint16_t csum)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L4_CSUM_FIX_CSUM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 79 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l4_csum_fix_csum " "L4 Checksum: Offset: %u, value 0x%X" "\n", cso, csum);
#line 2249 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_ENTRY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_ENTRY) || \
    false)

static inline void trace_net_rx_pkt_l3_csum_validate_entry(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_ENTRY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 81 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l3_csum_validate_entry " "Starting L3 checksum validation" "\n");
#line 2264 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_NOT_IP4_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_NOT_IP4) || \
    false)

static inline void trace_net_rx_pkt_l3_csum_validate_not_ip4(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_NOT_IP4)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 82 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l3_csum_validate_not_ip4 " "Not an IP4 packet" "\n");
#line 2279 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_CSUM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_CSUM) || \
    false)

static inline void trace_net_rx_pkt_l3_csum_validate_csum(size_t l3hdr_off, uint32_t csl, uint32_t cntr, uint16_t csum, bool csum_valid)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_L3_CSUM_VALIDATE_CSUM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 83 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_l3_csum_validate_csum " "L3 Checksum: L3 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X, valid: %d" "\n", l3hdr_off, csl, cntr, csum, csum_valid);
#line 2294 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_RSS_IP4_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_RSS_IP4) || \
    false)

static inline void trace_net_rx_pkt_rss_ip4(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_RSS_IP4)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 85 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_rss_ip4 " "Calculating IPv4 RSS  hash" "\n");
#line 2309 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_RSS_IP4_TCP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_RSS_IP4_TCP) || \
    false)

static inline void trace_net_rx_pkt_rss_ip4_tcp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_RSS_IP4_TCP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 86 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_rss_ip4_tcp " "Calculating IPv4/TCP RSS  hash" "\n");
#line 2324 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_RSS_IP4_UDP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_RSS_IP4_UDP) || \
    false)

static inline void trace_net_rx_pkt_rss_ip4_udp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_RSS_IP4_UDP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 87 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_rss_ip4_udp " "Calculating IPv4/UDP RSS  hash" "\n");
#line 2339 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_RSS_IP6_TCP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_RSS_IP6_TCP) || \
    false)

static inline void trace_net_rx_pkt_rss_ip6_tcp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_RSS_IP6_TCP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 88 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_rss_ip6_tcp " "Calculating IPv6/TCP RSS  hash" "\n");
#line 2354 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_RSS_IP6_UDP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_RSS_IP6_UDP) || \
    false)

static inline void trace_net_rx_pkt_rss_ip6_udp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_RSS_IP6_UDP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 89 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_rss_ip6_udp " "Calculating IPv6/UDP RSS  hash" "\n");
#line 2369 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_RSS_IP6_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_RSS_IP6) || \
    false)

static inline void trace_net_rx_pkt_rss_ip6(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_RSS_IP6)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 90 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_rss_ip6 " "Calculating IPv6 RSS  hash" "\n");
#line 2384 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_RSS_IP6_EX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_RSS_IP6_EX) || \
    false)

static inline void trace_net_rx_pkt_rss_ip6_ex(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_RSS_IP6_EX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 91 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_rss_ip6_ex " "Calculating IPv6/EX RSS  hash" "\n");
#line 2399 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_RSS_IP6_EX_TCP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_RSS_IP6_EX_TCP) || \
    false)

static inline void trace_net_rx_pkt_rss_ip6_ex_tcp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_RSS_IP6_EX_TCP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 92 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_rss_ip6_ex_tcp " "Calculating IPv6/EX/TCP RSS  hash" "\n");
#line 2414 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_RSS_IP6_EX_UDP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_RSS_IP6_EX_UDP) || \
    false)

static inline void trace_net_rx_pkt_rss_ip6_ex_udp(void)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_RSS_IP6_EX_UDP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 93 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_rss_ip6_ex_udp " "Calculating IPv6/EX/UDP RSS  hash" "\n");
#line 2429 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_RSS_HASH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_RSS_HASH) || \
    false)

static inline void trace_net_rx_pkt_rss_hash(size_t rss_length, uint32_t rss_hash)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_RSS_HASH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 94 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_rss_hash " "RSS hash for %zu bytes: 0x%X" "\n", rss_length, rss_hash);
#line 2444 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NET_RX_PKT_RSS_ADD_CHUNK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NET_RX_PKT_RSS_ADD_CHUNK) || \
    false)

static inline void trace_net_rx_pkt_rss_add_chunk(void*ptr, size_t size, size_t input_offset)
{
    if (trace_event_get_state(TRACE_NET_RX_PKT_RSS_ADD_CHUNK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 95 "../hw/net/trace-events"
            qemu_log("net_rx_pkt_rss_add_chunk " "Add RSS chunk %p, %zu bytes, RSS input offset %zu bytes" "\n", ptr, size, input_offset);
#line 2459 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000_RECEIVER_OVERRUN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000_RECEIVER_OVERRUN) || \
    false)

static inline void trace_e1000_receiver_overrun(size_t s, uint32_t rdh, uint32_t rdt)
{
    if (trace_event_get_state(TRACE_E1000_RECEIVER_OVERRUN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 98 "../hw/net/trace-events"
            qemu_log("e1000_receiver_overrun " "Receiver overrun: dropped packet of %zu bytes, RDH=%u, RDT=%u" "\n", s, rdh, rdt);
#line 2474 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_RX_CAN_RECV_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_RX_CAN_RECV_DISABLED) || \
    false)

static inline void trace_e1000x_rx_can_recv_disabled(bool link_up, bool rx_enabled, bool pci_master)
{
    if (trace_event_get_state(TRACE_E1000X_RX_CAN_RECV_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 101 "../hw/net/trace-events"
            qemu_log("e1000x_rx_can_recv_disabled " "link_up: %d, rx_enabled %d, pci_master %d" "\n", link_up, rx_enabled, pci_master);
#line 2489 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_VLAN_IS_VLAN_PKT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_VLAN_IS_VLAN_PKT) || \
    false)

static inline void trace_e1000x_vlan_is_vlan_pkt(bool is_vlan_pkt, uint16_t eth_proto, uint16_t vet)
{
    if (trace_event_get_state(TRACE_E1000X_VLAN_IS_VLAN_PKT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 102 "../hw/net/trace-events"
            qemu_log("e1000x_vlan_is_vlan_pkt " "Is VLAN packet: %d, ETH proto: 0x%X, VET: 0x%X" "\n", is_vlan_pkt, eth_proto, vet);
#line 2504 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_RX_FLT_VLAN_MISMATCH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_RX_FLT_VLAN_MISMATCH) || \
    false)

static inline void trace_e1000x_rx_flt_vlan_mismatch(uint16_t vid)
{
    if (trace_event_get_state(TRACE_E1000X_RX_FLT_VLAN_MISMATCH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 103 "../hw/net/trace-events"
            qemu_log("e1000x_rx_flt_vlan_mismatch " "VID mismatch: 0x%X" "\n", vid);
#line 2519 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_RX_FLT_VLAN_MATCH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_RX_FLT_VLAN_MATCH) || \
    false)

static inline void trace_e1000x_rx_flt_vlan_match(uint16_t vid)
{
    if (trace_event_get_state(TRACE_E1000X_RX_FLT_VLAN_MATCH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 104 "../hw/net/trace-events"
            qemu_log("e1000x_rx_flt_vlan_match " "VID match: 0x%X" "\n", vid);
#line 2534 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_RX_FLT_UCAST_MATCH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_RX_FLT_UCAST_MATCH) || \
    false)

static inline void trace_e1000x_rx_flt_ucast_match(uint32_t idx, uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5)
{
    if (trace_event_get_state(TRACE_E1000X_RX_FLT_UCAST_MATCH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 105 "../hw/net/trace-events"
            qemu_log("e1000x_rx_flt_ucast_match " "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x" "\n", idx, b0, b1, b2, b3, b4, b5);
#line 2549 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_RX_FLT_UCAST_MISMATCH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_RX_FLT_UCAST_MISMATCH) || \
    false)

static inline void trace_e1000x_rx_flt_ucast_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5)
{
    if (trace_event_get_state(TRACE_E1000X_RX_FLT_UCAST_MISMATCH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 106 "../hw/net/trace-events"
            qemu_log("e1000x_rx_flt_ucast_mismatch " "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x" "\n", b0, b1, b2, b3, b4, b5);
#line 2564 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_RX_FLT_INEXACT_MISMATCH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_RX_FLT_INEXACT_MISMATCH) || \
    false)

static inline void trace_e1000x_rx_flt_inexact_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint32_t mo, uint32_t mta, uint32_t mta_val)
{
    if (trace_event_get_state(TRACE_E1000X_RX_FLT_INEXACT_MISMATCH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 107 "../hw/net/trace-events"
            qemu_log("e1000x_rx_flt_inexact_mismatch " "inexact mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] 0x%x" "\n", b0, b1, b2, b3, b4, b5, mo, mta, mta_val);
#line 2579 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_RX_LINK_DOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_RX_LINK_DOWN) || \
    false)

static inline void trace_e1000x_rx_link_down(uint32_t status_reg)
{
    if (trace_event_get_state(TRACE_E1000X_RX_LINK_DOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 108 "../hw/net/trace-events"
            qemu_log("e1000x_rx_link_down " "Received packet dropped because the link is down STATUS = %u" "\n", status_reg);
#line 2594 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_RX_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_RX_DISABLED) || \
    false)

static inline void trace_e1000x_rx_disabled(uint32_t rctl_reg)
{
    if (trace_event_get_state(TRACE_E1000X_RX_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 109 "../hw/net/trace-events"
            qemu_log("e1000x_rx_disabled " "Received packet dropped because receive is disabled RCTL = %u" "\n", rctl_reg);
#line 2609 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_RX_OVERSIZED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_RX_OVERSIZED) || \
    false)

static inline void trace_e1000x_rx_oversized(size_t size)
{
    if (trace_event_get_state(TRACE_E1000X_RX_OVERSIZED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 110 "../hw/net/trace-events"
            qemu_log("e1000x_rx_oversized " "Received packet dropped because it was oversized (%zu bytes)" "\n", size);
#line 2624 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_MAC_INDICATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_MAC_INDICATE) || \
    false)

static inline void trace_e1000x_mac_indicate(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5)
{
    if (trace_event_get_state(TRACE_E1000X_MAC_INDICATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 111 "../hw/net/trace-events"
            qemu_log("e1000x_mac_indicate " "Indicating MAC to guest: %02x:%02x:%02x:%02x:%02x:%02x" "\n", b0, b1, b2, b3, b4, b5);
#line 2639 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_LINK_NEGOTIATION_START_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_LINK_NEGOTIATION_START) || \
    false)

static inline void trace_e1000x_link_negotiation_start(void)
{
    if (trace_event_get_state(TRACE_E1000X_LINK_NEGOTIATION_START)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 112 "../hw/net/trace-events"
            qemu_log("e1000x_link_negotiation_start " "Start link auto negotiation" "\n");
#line 2654 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000X_LINK_NEGOTIATION_DONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000X_LINK_NEGOTIATION_DONE) || \
    false)

static inline void trace_e1000x_link_negotiation_done(void)
{
    if (trace_event_get_state(TRACE_E1000X_LINK_NEGOTIATION_DONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 113 "../hw/net/trace-events"
            qemu_log("e1000x_link_negotiation_done " "Auto negotiation is completed" "\n");
#line 2669 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CORE_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CORE_WRITE) || \
    false)

static inline void trace_e1000e_core_write(uint64_t index, uint32_t size, uint64_t val)
{
    if (trace_event_get_state(TRACE_E1000E_CORE_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 116 "../hw/net/trace-events"
            qemu_log("e1000e_core_write " "Write to register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 "\n", index, size, val);
#line 2684 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CORE_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CORE_READ) || \
    false)

static inline void trace_e1000e_core_read(uint64_t index, uint32_t size, uint64_t val)
{
    if (trace_event_get_state(TRACE_E1000E_CORE_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 117 "../hw/net/trace-events"
            qemu_log("e1000e_core_read " "Read from register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 "\n", index, size, val);
#line 2699 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CORE_MDIC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CORE_MDIC_READ) || \
    false)

static inline void trace_e1000e_core_mdic_read(uint8_t page, uint32_t addr, uint32_t data)
{
    if (trace_event_get_state(TRACE_E1000E_CORE_MDIC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 118 "../hw/net/trace-events"
            qemu_log("e1000e_core_mdic_read " "MDIC READ: PHY[%u][%u] = 0x%x" "\n", page, addr, data);
#line 2714 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CORE_MDIC_READ_UNHANDLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CORE_MDIC_READ_UNHANDLED) || \
    false)

static inline void trace_e1000e_core_mdic_read_unhandled(uint8_t page, uint32_t addr)
{
    if (trace_event_get_state(TRACE_E1000E_CORE_MDIC_READ_UNHANDLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 119 "../hw/net/trace-events"
            qemu_log("e1000e_core_mdic_read_unhandled " "MDIC READ: PHY[%u][%u] UNHANDLED" "\n", page, addr);
#line 2729 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CORE_MDIC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CORE_MDIC_WRITE) || \
    false)

static inline void trace_e1000e_core_mdic_write(uint8_t page, uint32_t addr, uint32_t data)
{
    if (trace_event_get_state(TRACE_E1000E_CORE_MDIC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 120 "../hw/net/trace-events"
            qemu_log("e1000e_core_mdic_write " "MDIC WRITE: PHY[%u][%u] = 0x%x" "\n", page, addr, data);
#line 2744 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CORE_MDIC_WRITE_UNHANDLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CORE_MDIC_WRITE_UNHANDLED) || \
    false)

static inline void trace_e1000e_core_mdic_write_unhandled(uint8_t page, uint32_t addr)
{
    if (trace_event_get_state(TRACE_E1000E_CORE_MDIC_WRITE_UNHANDLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 121 "../hw/net/trace-events"
            qemu_log("e1000e_core_mdic_write_unhandled " "MDIC WRITE: PHY[%u][%u] UNHANDLED" "\n", page, addr);
#line 2759 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CORE_CTRL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CORE_CTRL_WRITE) || \
    false)

static inline void trace_e1000e_core_ctrl_write(uint64_t index, uint32_t val)
{
    if (trace_event_get_state(TRACE_E1000E_CORE_CTRL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 122 "../hw/net/trace-events"
            qemu_log("e1000e_core_ctrl_write " "Write CTRL register 0x%"PRIx64", value: 0x%X" "\n", index, val);
#line 2774 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CORE_CTRL_SW_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CORE_CTRL_SW_RESET) || \
    false)

static inline void trace_e1000e_core_ctrl_sw_reset(void)
{
    if (trace_event_get_state(TRACE_E1000E_CORE_CTRL_SW_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 123 "../hw/net/trace-events"
            qemu_log("e1000e_core_ctrl_sw_reset " "Doing SW reset" "\n");
#line 2789 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CORE_CTRL_PHY_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CORE_CTRL_PHY_RESET) || \
    false)

static inline void trace_e1000e_core_ctrl_phy_reset(void)
{
    if (trace_event_get_state(TRACE_E1000E_CORE_CTRL_PHY_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 124 "../hw/net/trace-events"
            qemu_log("e1000e_core_ctrl_phy_reset " "Doing PHY reset" "\n");
#line 2804 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_LINK_AUTONEG_FLOWCTL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_LINK_AUTONEG_FLOWCTL) || \
    false)

static inline void trace_e1000e_link_autoneg_flowctl(bool enabled)
{
    if (trace_event_get_state(TRACE_E1000E_LINK_AUTONEG_FLOWCTL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 126 "../hw/net/trace-events"
            qemu_log("e1000e_link_autoneg_flowctl " "Auto-negotiated flow control state is %d" "\n", enabled);
#line 2819 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_LINK_SET_PARAMS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_LINK_SET_PARAMS) || \
    false)

static inline void trace_e1000e_link_set_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl)
{
    if (trace_event_get_state(TRACE_E1000E_LINK_SET_PARAMS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 127 "../hw/net/trace-events"
            qemu_log("e1000e_link_set_params " "Set link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d" "\n", autodetect, speed, force_spd, force_dplx, rx_fctl, tx_fctl);
#line 2834 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_LINK_READ_PARAMS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_LINK_READ_PARAMS) || \
    false)

static inline void trace_e1000e_link_read_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl)
{
    if (trace_event_get_state(TRACE_E1000E_LINK_READ_PARAMS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 128 "../hw/net/trace-events"
            qemu_log("e1000e_link_read_params " "Get link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d" "\n", autodetect, speed, force_spd, force_dplx, rx_fctl, tx_fctl);
#line 2849 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_LINK_SET_EXT_PARAMS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_LINK_SET_EXT_PARAMS) || \
    false)

static inline void trace_e1000e_link_set_ext_params(bool asd_check, bool speed_select_bypass)
{
    if (trace_event_get_state(TRACE_E1000E_LINK_SET_EXT_PARAMS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 129 "../hw/net/trace-events"
            qemu_log("e1000e_link_set_ext_params " "Set extended link params: ASD check: %d, Speed select bypass: %d" "\n", asd_check, speed_select_bypass);
#line 2864 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_LINK_STATUS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_LINK_STATUS) || \
    false)

static inline void trace_e1000e_link_status(bool link_up, bool full_dplx, uint32_t speed, uint32_t asdv)
{
    if (trace_event_get_state(TRACE_E1000E_LINK_STATUS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 130 "../hw/net/trace-events"
            qemu_log("e1000e_link_status " "Link up: %d, Duplex: %d, Speed: %d, ASDV: %d" "\n", link_up, full_dplx, speed, asdv);
#line 2879 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_LINK_STATUS_CHANGED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_LINK_STATUS_CHANGED) || \
    false)

static inline void trace_e1000e_link_status_changed(bool status)
{
    if (trace_event_get_state(TRACE_E1000E_LINK_STATUS_CHANGED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 131 "../hw/net/trace-events"
            qemu_log("e1000e_link_status_changed " "New link status: %d" "\n", status);
#line 2894 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_REGS_WRITE_RO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_REGS_WRITE_RO) || \
    false)

static inline void trace_e1000e_wrn_regs_write_ro(uint64_t index, uint32_t size, uint64_t val)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_REGS_WRITE_RO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 133 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_regs_write_ro " "WARNING: Write to RO register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 "\n", index, size, val);
#line 2909 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_REGS_WRITE_UNKNOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_REGS_WRITE_UNKNOWN) || \
    false)

static inline void trace_e1000e_wrn_regs_write_unknown(uint64_t index, uint32_t size, uint64_t val)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_REGS_WRITE_UNKNOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 134 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_regs_write_unknown " "WARNING: Write to unknown register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 "\n", index, size, val);
#line 2924 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_REGS_READ_UNKNOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_REGS_READ_UNKNOWN) || \
    false)

static inline void trace_e1000e_wrn_regs_read_unknown(uint64_t index, uint32_t size)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_REGS_READ_UNKNOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 135 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_regs_read_unknown " "WARNING: Read from unknown register 0x%"PRIx64", %d byte(s)" "\n", index, size);
#line 2939 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_REGS_READ_TRIVIAL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_REGS_READ_TRIVIAL) || \
    false)

static inline void trace_e1000e_wrn_regs_read_trivial(uint32_t index)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_REGS_READ_TRIVIAL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 136 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_regs_read_trivial " "WARNING: Reading register at offset: 0x%05x. It is not fully implemented." "\n", index);
#line 2954 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_REGS_WRITE_TRIVIAL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_REGS_WRITE_TRIVIAL) || \
    false)

static inline void trace_e1000e_wrn_regs_write_trivial(uint32_t index)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_REGS_WRITE_TRIVIAL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 137 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_regs_write_trivial " "WARNING: Writing to register at offset: 0x%05x. It is not fully implemented." "\n", index);
#line 2969 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_NO_TS_SUPPORT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_NO_TS_SUPPORT) || \
    false)

static inline void trace_e1000e_wrn_no_ts_support(void)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_NO_TS_SUPPORT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 138 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_no_ts_support " "WARNING: Guest requested TX timestamping which is not supported" "\n");
#line 2984 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_NO_SNAP_SUPPORT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_NO_SNAP_SUPPORT) || \
    false)

static inline void trace_e1000e_wrn_no_snap_support(void)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_NO_SNAP_SUPPORT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 139 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_no_snap_support " "WARNING: Guest requested TX SNAP header update which is not supported" "\n");
#line 2999 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_ISCSI_FILTERING_NOT_SUPPORTED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_ISCSI_FILTERING_NOT_SUPPORTED) || \
    false)

static inline void trace_e1000e_wrn_iscsi_filtering_not_supported(void)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_ISCSI_FILTERING_NOT_SUPPORTED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 140 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_iscsi_filtering_not_supported " "WARNING: Guest requested iSCSI filtering  which is not supported" "\n");
#line 3014 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_NFSW_FILTERING_NOT_SUPPORTED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_NFSW_FILTERING_NOT_SUPPORTED) || \
    false)

static inline void trace_e1000e_wrn_nfsw_filtering_not_supported(void)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_NFSW_FILTERING_NOT_SUPPORTED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 141 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_nfsw_filtering_not_supported " "WARNING: Guest requested NFS write filtering  which is not supported" "\n");
#line 3029 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_NFSR_FILTERING_NOT_SUPPORTED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_NFSR_FILTERING_NOT_SUPPORTED) || \
    false)

static inline void trace_e1000e_wrn_nfsr_filtering_not_supported(void)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_NFSR_FILTERING_NOT_SUPPORTED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 142 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_nfsr_filtering_not_supported " "WARNING: Guest requested NFS read filtering  which is not supported" "\n");
#line 3044 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_TX_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_TX_DISABLED) || \
    false)

static inline void trace_e1000e_tx_disabled(void)
{
    if (trace_event_get_state(TRACE_E1000E_TX_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 144 "../hw/net/trace-events"
            qemu_log("e1000e_tx_disabled " "TX Disabled" "\n");
#line 3059 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_TX_DESCR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_TX_DESCR) || \
    false)

static inline void trace_e1000e_tx_descr(void *addr, uint32_t lower, uint32_t upper)
{
    if (trace_event_get_state(TRACE_E1000E_TX_DESCR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 145 "../hw/net/trace-events"
            qemu_log("e1000e_tx_descr " "%p : %x %x" "\n", addr, lower, upper);
#line 3074 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RING_FREE_SPACE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RING_FREE_SPACE) || \
    false)

static inline void trace_e1000e_ring_free_space(int ridx, uint32_t rdlen, uint32_t rdh, uint32_t rdt)
{
    if (trace_event_get_state(TRACE_E1000E_RING_FREE_SPACE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 147 "../hw/net/trace-events"
            qemu_log("e1000e_ring_free_space " "ring #%d: LEN: %u, DH: %u, DT: %u" "\n", ridx, rdlen, rdh, rdt);
#line 3089 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_CAN_RECV_RINGS_FULL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_CAN_RECV_RINGS_FULL) || \
    false)

static inline void trace_e1000e_rx_can_recv_rings_full(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_CAN_RECV_RINGS_FULL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 149 "../hw/net/trace-events"
            qemu_log("e1000e_rx_can_recv_rings_full " "Cannot receive: all rings are full" "\n");
#line 3104 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_CAN_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_CAN_RECV) || \
    false)

static inline void trace_e1000e_rx_can_recv(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_CAN_RECV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 150 "../hw/net/trace-events"
            qemu_log("e1000e_rx_can_recv " "Can receive" "\n");
#line 3119 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_HAS_BUFFERS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_HAS_BUFFERS) || \
    false)

static inline void trace_e1000e_rx_has_buffers(int ridx, uint32_t free_desc, size_t total_size, uint32_t desc_buf_size)
{
    if (trace_event_get_state(TRACE_E1000E_RX_HAS_BUFFERS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 151 "../hw/net/trace-events"
            qemu_log("e1000e_rx_has_buffers " "ring #%d: free descr: %u, packet size %zu, descr buffer size %u" "\n", ridx, free_desc, total_size, desc_buf_size);
#line 3134 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_NULL_DESCRIPTOR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_NULL_DESCRIPTOR) || \
    false)

static inline void trace_e1000e_rx_null_descriptor(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_NULL_DESCRIPTOR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 152 "../hw/net/trace-events"
            qemu_log("e1000e_rx_null_descriptor " "Null RX descriptor!!" "\n");
#line 3149 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_DESC_PS_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_DESC_PS_READ) || \
    false)

static inline void trace_e1000e_rx_desc_ps_read(uint64_t a0, uint64_t a1, uint64_t a2, uint64_t a3)
{
    if (trace_event_get_state(TRACE_E1000E_RX_DESC_PS_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 153 "../hw/net/trace-events"
            qemu_log("e1000e_rx_desc_ps_read " "buffers: [0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64"]" "\n", a0, a1, a2, a3);
#line 3164 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_DESC_PS_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_DESC_PS_WRITE) || \
    false)

static inline void trace_e1000e_rx_desc_ps_write(uint16_t a0, uint16_t a1, uint16_t a2, uint16_t a3)
{
    if (trace_event_get_state(TRACE_E1000E_RX_DESC_PS_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 154 "../hw/net/trace-events"
            qemu_log("e1000e_rx_desc_ps_write " "bytes written: [%u, %u, %u, %u]" "\n", a0, a1, a2, a3);
#line 3179 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_DESC_BUFF_SIZES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_DESC_BUFF_SIZES) || \
    false)

static inline void trace_e1000e_rx_desc_buff_sizes(uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3)
{
    if (trace_event_get_state(TRACE_E1000E_RX_DESC_BUFF_SIZES)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 155 "../hw/net/trace-events"
            qemu_log("e1000e_rx_desc_buff_sizes " "buffer sizes: [%u, %u, %u, %u]" "\n", b0, b1, b2, b3);
#line 3194 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_DESC_LEN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_DESC_LEN) || \
    false)

static inline void trace_e1000e_rx_desc_len(uint8_t rx_desc_len)
{
    if (trace_event_get_state(TRACE_E1000E_RX_DESC_LEN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 156 "../hw/net/trace-events"
            qemu_log("e1000e_rx_desc_len " "RX descriptor length: %u" "\n", rx_desc_len);
#line 3209 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_DESC_BUFF_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_DESC_BUFF_WRITE) || \
    false)

static inline void trace_e1000e_rx_desc_buff_write(uint8_t idx, uint64_t addr, uint16_t offset, const void*source, uint32_t len)
{
    if (trace_event_get_state(TRACE_E1000E_RX_DESC_BUFF_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 157 "../hw/net/trace-events"
            qemu_log("e1000e_rx_desc_buff_write " "buffer #%u, addr: 0x%"PRIx64", offset: %u, from: %p, length: %u" "\n", idx, addr, offset, source, len);
#line 3224 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_DESCR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_DESCR) || \
    false)

static inline void trace_e1000e_rx_descr(int ridx, uint64_t base, uint8_t len)
{
    if (trace_event_get_state(TRACE_E1000E_RX_DESCR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 158 "../hw/net/trace-events"
            qemu_log("e1000e_rx_descr " "Next RX descriptor: ring #%d, PA: 0x%"PRIx64", length: %u" "\n", ridx, base, len);
#line 3239 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_SET_RCTL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_SET_RCTL) || \
    false)

static inline void trace_e1000e_rx_set_rctl(uint32_t rctl)
{
    if (trace_event_get_state(TRACE_E1000E_RX_SET_RCTL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 159 "../hw/net/trace-events"
            qemu_log("e1000e_rx_set_rctl " "RCTL = 0x%x" "\n", rctl);
#line 3254 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_RECEIVE_IOV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_RECEIVE_IOV) || \
    false)

static inline void trace_e1000e_rx_receive_iov(int iovcnt)
{
    if (trace_event_get_state(TRACE_E1000E_RX_RECEIVE_IOV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 160 "../hw/net/trace-events"
            qemu_log("e1000e_rx_receive_iov " "Received vector of %d fragments" "\n", iovcnt);
#line 3269 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_FLT_DROPPED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_FLT_DROPPED) || \
    false)

static inline void trace_e1000e_rx_flt_dropped(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_FLT_DROPPED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 161 "../hw/net/trace-events"
            qemu_log("e1000e_rx_flt_dropped " "Received packet dropped by RX filter" "\n");
#line 3284 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_WRITTEN_TO_GUEST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_WRITTEN_TO_GUEST) || \
    false)

static inline void trace_e1000e_rx_written_to_guest(int queue_idx)
{
    if (trace_event_get_state(TRACE_E1000E_RX_WRITTEN_TO_GUEST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 162 "../hw/net/trace-events"
            qemu_log("e1000e_rx_written_to_guest " "Received packet written to guest (queue %d)" "\n", queue_idx);
#line 3299 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_NOT_WRITTEN_TO_GUEST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_NOT_WRITTEN_TO_GUEST) || \
    false)

static inline void trace_e1000e_rx_not_written_to_guest(int queue_idx)
{
    if (trace_event_get_state(TRACE_E1000E_RX_NOT_WRITTEN_TO_GUEST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 163 "../hw/net/trace-events"
            qemu_log("e1000e_rx_not_written_to_guest " "Received packet NOT written to guest (queue %d)" "\n", queue_idx);
#line 3314 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_INTERRUPT_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_INTERRUPT_SET) || \
    false)

static inline void trace_e1000e_rx_interrupt_set(uint32_t causes)
{
    if (trace_event_get_state(TRACE_E1000E_RX_INTERRUPT_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 164 "../hw/net/trace-events"
            qemu_log("e1000e_rx_interrupt_set " "Receive interrupt set (ICR causes %u)" "\n", causes);
#line 3329 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_INTERRUPT_DELAYED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_INTERRUPT_DELAYED) || \
    false)

static inline void trace_e1000e_rx_interrupt_delayed(uint32_t causes)
{
    if (trace_event_get_state(TRACE_E1000E_RX_INTERRUPT_DELAYED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 165 "../hw/net/trace-events"
            qemu_log("e1000e_rx_interrupt_delayed " "Receive interrupt delayed (ICR causes %u)" "\n", causes);
#line 3344 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_SET_CSO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_SET_CSO) || \
    false)

static inline void trace_e1000e_rx_set_cso(int cso_state)
{
    if (trace_event_get_state(TRACE_E1000E_RX_SET_CSO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 166 "../hw/net/trace-events"
            qemu_log("e1000e_rx_set_cso " "RX CSO state set to %d" "\n", cso_state);
#line 3359 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_SET_RDT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_SET_RDT) || \
    false)

static inline void trace_e1000e_rx_set_rdt(int queue_idx, uint32_t val)
{
    if (trace_event_get_state(TRACE_E1000E_RX_SET_RDT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 167 "../hw/net/trace-events"
            qemu_log("e1000e_rx_set_rdt " "Setting RDT[%d] = %u" "\n", queue_idx, val);
#line 3374 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_SET_RFCTL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_SET_RFCTL) || \
    false)

static inline void trace_e1000e_rx_set_rfctl(uint32_t val)
{
    if (trace_event_get_state(TRACE_E1000E_RX_SET_RFCTL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 168 "../hw/net/trace-events"
            qemu_log("e1000e_rx_set_rfctl " "Setting RFCTL = 0x%X" "\n", val);
#line 3389 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_START_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_START_RECV) || \
    false)

static inline void trace_e1000e_rx_start_recv(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_START_RECV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 169 "../hw/net/trace-events"
            qemu_log("e1000e_rx_start_recv "  "\n");
#line 3404 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_RSS_STARTED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_RSS_STARTED) || \
    false)

static inline void trace_e1000e_rx_rss_started(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_RSS_STARTED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 171 "../hw/net/trace-events"
            qemu_log("e1000e_rx_rss_started " "Starting RSS processing" "\n");
#line 3419 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_RSS_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_RSS_DISABLED) || \
    false)

static inline void trace_e1000e_rx_rss_disabled(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_RSS_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 172 "../hw/net/trace-events"
            qemu_log("e1000e_rx_rss_disabled " "RSS is disabled" "\n");
#line 3434 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_RSS_TYPE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_RSS_TYPE) || \
    false)

static inline void trace_e1000e_rx_rss_type(uint32_t type)
{
    if (trace_event_get_state(TRACE_E1000E_RX_RSS_TYPE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 173 "../hw/net/trace-events"
            qemu_log("e1000e_rx_rss_type " "RSS type is %u" "\n", type);
#line 3449 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_RSS_IP4_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_RSS_IP4) || \
    false)

static inline void trace_e1000e_rx_rss_ip4(int l4hdr_proto, uint32_t mrqc, bool tcpipv4_enabled, bool ipv4_enabled)
{
    if (trace_event_get_state(TRACE_E1000E_RX_RSS_IP4)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 174 "../hw/net/trace-events"
            qemu_log("e1000e_rx_rss_ip4 " "RSS IPv4: L4 header protocol %d, mrqc 0x%X, tcpipv4 enabled %d, ipv4 enabled %d" "\n", l4hdr_proto, mrqc, tcpipv4_enabled, ipv4_enabled);
#line 3464 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_RSS_IP6_RFCTL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_RSS_IP6_RFCTL) || \
    false)

static inline void trace_e1000e_rx_rss_ip6_rfctl(uint32_t rfctl)
{
    if (trace_event_get_state(TRACE_E1000E_RX_RSS_IP6_RFCTL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 175 "../hw/net/trace-events"
            qemu_log("e1000e_rx_rss_ip6_rfctl " "RSS IPv6: rfctl 0x%X" "\n", rfctl);
#line 3479 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_RSS_IP6_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_RSS_IP6) || \
    false)

static inline void trace_e1000e_rx_rss_ip6(bool ex_dis, bool new_ex_dis, int l4hdr_proto, bool has_ext_headers, bool ex_dst_valid, bool ex_src_valid, uint32_t mrqc, bool tcpipv6ex_enabled, bool ipv6ex_enabled, bool ipv6_enabled)
{
    if (trace_event_get_state(TRACE_E1000E_RX_RSS_IP6)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 176 "../hw/net/trace-events"
            qemu_log("e1000e_rx_rss_ip6 " "RSS IPv6: ex_dis: %d, new_ex_dis: %d, L4 header protocol %d, has_ext_headers %d, ex_dst_valid %d, ex_src_valid %d, mrqc 0x%X, tcpipv6ex enabled %d, ipv6ex enabled %d, ipv6 enabled %d" "\n", ex_dis, new_ex_dis, l4hdr_proto, has_ext_headers, ex_dst_valid, ex_src_valid, mrqc, tcpipv6ex_enabled, ipv6ex_enabled, ipv6_enabled);
#line 3494 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_PROTOCOLS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_PROTOCOLS) || \
    false)

static inline void trace_e1000e_rx_metadata_protocols(bool hasip4, bool hasip6, int l4hdr_protocol)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_PROTOCOLS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 178 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_protocols " "protocols: ip4: %d, ip6: %d, l4hdr: %d" "\n", hasip4, hasip6, l4hdr_protocol);
#line 3509 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_VLAN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_VLAN) || \
    false)

static inline void trace_e1000e_rx_metadata_vlan(uint16_t vlan_tag)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_VLAN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 179 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_vlan " "VLAN tag is 0x%X" "\n", vlan_tag);
#line 3524 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_RSS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_RSS) || \
    false)

static inline void trace_e1000e_rx_metadata_rss(uint32_t rss, uint32_t mrq)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_RSS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 180 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_rss " "RSS data: rss: 0x%X, mrq: 0x%X" "\n", rss, mrq);
#line 3539 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_IP_ID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_IP_ID) || \
    false)

static inline void trace_e1000e_rx_metadata_ip_id(uint16_t ip_id)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_IP_ID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 181 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_ip_id " "the IPv4 ID is 0x%X" "\n", ip_id);
#line 3554 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_ACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_ACK) || \
    false)

static inline void trace_e1000e_rx_metadata_ack(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_ACK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 182 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_ack " "the packet is TCP ACK" "\n");
#line 3569 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_PKT_TYPE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_PKT_TYPE) || \
    false)

static inline void trace_e1000e_rx_metadata_pkt_type(uint32_t pkt_type)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_PKT_TYPE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 183 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_pkt_type " "the packet type is %u" "\n", pkt_type);
#line 3584 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_VIRTHDR_NO_CSUM_INFO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_VIRTHDR_NO_CSUM_INFO) || \
    false)

static inline void trace_e1000e_rx_metadata_virthdr_no_csum_info(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_VIRTHDR_NO_CSUM_INFO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 184 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_virthdr_no_csum_info " "virt-header does not contain checksum info" "\n");
#line 3599 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_L3_CSO_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_L3_CSO_DISABLED) || \
    false)

static inline void trace_e1000e_rx_metadata_l3_cso_disabled(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_L3_CSO_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 185 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_l3_cso_disabled " "IP4 CSO is disabled" "\n");
#line 3614 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_L4_CSO_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_L4_CSO_DISABLED) || \
    false)

static inline void trace_e1000e_rx_metadata_l4_cso_disabled(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_L4_CSO_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 186 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_l4_cso_disabled " "TCP/UDP CSO is disabled" "\n");
#line 3629 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_L3_CSUM_VALIDATION_FAILED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_L3_CSUM_VALIDATION_FAILED) || \
    false)

static inline void trace_e1000e_rx_metadata_l3_csum_validation_failed(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_L3_CSUM_VALIDATION_FAILED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 187 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_l3_csum_validation_failed " "Cannot validate L3 checksum" "\n");
#line 3644 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_L4_CSUM_VALIDATION_FAILED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_L4_CSUM_VALIDATION_FAILED) || \
    false)

static inline void trace_e1000e_rx_metadata_l4_csum_validation_failed(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_L4_CSUM_VALIDATION_FAILED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 188 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_l4_csum_validation_failed " "Cannot validate L4 checksum" "\n");
#line 3659 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_STATUS_FLAGS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_STATUS_FLAGS) || \
    false)

static inline void trace_e1000e_rx_metadata_status_flags(uint32_t status_flags)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_STATUS_FLAGS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 189 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_status_flags " "status_flags is 0x%X" "\n", status_flags);
#line 3674 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_IPV6_SUM_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_IPV6_SUM_DISABLED) || \
    false)

static inline void trace_e1000e_rx_metadata_ipv6_sum_disabled(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_IPV6_SUM_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 190 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_ipv6_sum_disabled " "IPv6 RX checksummimg disabled by RFCTL" "\n");
#line 3689 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_RX_METADATA_IPV6_FILTERING_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_RX_METADATA_IPV6_FILTERING_DISABLED) || \
    false)

static inline void trace_e1000e_rx_metadata_ipv6_filtering_disabled(void)
{
    if (trace_event_get_state(TRACE_E1000E_RX_METADATA_IPV6_FILTERING_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 191 "../hw/net/trace-events"
            qemu_log("e1000e_rx_metadata_ipv6_filtering_disabled " "IPv6 RX filtering disabled by RFCTL" "\n");
#line 3704 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_VLAN_VET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_VLAN_VET) || \
    false)

static inline void trace_e1000e_vlan_vet(uint16_t vet)
{
    if (trace_event_get_state(TRACE_E1000E_VLAN_VET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 193 "../hw/net/trace-events"
            qemu_log("e1000e_vlan_vet " "Setting VLAN ethernet type 0x%X" "\n", vet);
#line 3719 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_MSI_NOTIFY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_MSI_NOTIFY) || \
    false)

static inline void trace_e1000e_irq_msi_notify(uint32_t cause)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_MSI_NOTIFY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 195 "../hw/net/trace-events"
            qemu_log("e1000e_irq_msi_notify " "MSI notify 0x%x" "\n", cause);
#line 3734 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_MSI_NOTIFY_POSTPONED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_MSI_NOTIFY_POSTPONED) || \
    false)

static inline void trace_e1000e_irq_msi_notify_postponed(void)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_MSI_NOTIFY_POSTPONED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 196 "../hw/net/trace-events"
            qemu_log("e1000e_irq_msi_notify_postponed " "Sending MSI postponed by ITR" "\n");
#line 3749 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_LEGACY_NOTIFY_POSTPONED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_LEGACY_NOTIFY_POSTPONED) || \
    false)

static inline void trace_e1000e_irq_legacy_notify_postponed(void)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_LEGACY_NOTIFY_POSTPONED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 197 "../hw/net/trace-events"
            qemu_log("e1000e_irq_legacy_notify_postponed " "Raising legacy IRQ postponed by ITR" "\n");
#line 3764 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_MSIX_NOTIFY_POSTPONED_VEC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_MSIX_NOTIFY_POSTPONED_VEC) || \
    false)

static inline void trace_e1000e_irq_msix_notify_postponed_vec(int idx)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_MSIX_NOTIFY_POSTPONED_VEC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 198 "../hw/net/trace-events"
            qemu_log("e1000e_irq_msix_notify_postponed_vec " "Sending MSI-X postponed by EITR[%d]" "\n", idx);
#line 3779 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_LEGACY_NOTIFY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_LEGACY_NOTIFY) || \
    false)

static inline void trace_e1000e_irq_legacy_notify(bool level)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_LEGACY_NOTIFY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 199 "../hw/net/trace-events"
            qemu_log("e1000e_irq_legacy_notify " "IRQ line state: %d" "\n", level);
#line 3794 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_MSIX_NOTIFY_VEC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_MSIX_NOTIFY_VEC) || \
    false)

static inline void trace_e1000e_irq_msix_notify_vec(uint32_t vector)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_MSIX_NOTIFY_VEC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 200 "../hw/net/trace-events"
            qemu_log("e1000e_irq_msix_notify_vec " "MSI-X notify vector 0x%x" "\n", vector);
#line 3809 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_POSTPONED_BY_XITR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_POSTPONED_BY_XITR) || \
    false)

static inline void trace_e1000e_irq_postponed_by_xitr(uint32_t reg)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_POSTPONED_BY_XITR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 201 "../hw/net/trace-events"
            qemu_log("e1000e_irq_postponed_by_xitr " "Interrupt postponed by [E]ITR register 0x%x" "\n", reg);
#line 3824 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_CLEAR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_CLEAR) || \
    false)

static inline void trace_e1000e_irq_clear(uint32_t offset, uint32_t old, uint32_t new)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_CLEAR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 202 "../hw/net/trace-events"
            qemu_log("e1000e_irq_clear " "Clearing interrupt register 0x%x: 0x%x --> 0x%x" "\n", offset, old, new);
#line 3839 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_SET) || \
    false)

static inline void trace_e1000e_irq_set(uint32_t offset, uint32_t old, uint32_t new)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 203 "../hw/net/trace-events"
            qemu_log("e1000e_irq_set " "Setting interrupt register 0x%x: 0x%x --> 0x%x" "\n", offset, old, new);
#line 3854 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_FIX_ICR_ASSERTED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_FIX_ICR_ASSERTED) || \
    false)

static inline void trace_e1000e_irq_fix_icr_asserted(uint32_t new_val)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_FIX_ICR_ASSERTED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 204 "../hw/net/trace-events"
            qemu_log("e1000e_irq_fix_icr_asserted " "ICR_ASSERTED bit fixed: 0x%x" "\n", new_val);
#line 3869 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_ADD_MSI_OTHER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_ADD_MSI_OTHER) || \
    false)

static inline void trace_e1000e_irq_add_msi_other(uint32_t new_val)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_ADD_MSI_OTHER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 205 "../hw/net/trace-events"
            qemu_log("e1000e_irq_add_msi_other " "ICR_OTHER bit added: 0x%x" "\n", new_val);
#line 3884 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_PENDING_INTERRUPTS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_PENDING_INTERRUPTS) || \
    false)

static inline void trace_e1000e_irq_pending_interrupts(uint32_t pending, uint32_t icr, uint32_t ims)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_PENDING_INTERRUPTS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 206 "../hw/net/trace-events"
            qemu_log("e1000e_irq_pending_interrupts " "ICR PENDING: 0x%x (ICR: 0x%x, IMS: 0x%x)" "\n", pending, icr, ims);
#line 3899 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_WRITE_ICS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_WRITE_ICS) || \
    false)

static inline void trace_e1000e_irq_write_ics(uint32_t val)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_WRITE_ICS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 207 "../hw/net/trace-events"
            qemu_log("e1000e_irq_write_ics " "Adding ICR bits 0x%x" "\n", val);
#line 3914 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_ICR_PROCESS_IAME_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_ICR_PROCESS_IAME) || \
    false)

static inline void trace_e1000e_irq_icr_process_iame(void)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_ICR_PROCESS_IAME)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 208 "../hw/net/trace-events"
            qemu_log("e1000e_irq_icr_process_iame " "Clearing IMS bits due to IAME" "\n");
#line 3929 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_READ_ICS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_READ_ICS) || \
    false)

static inline void trace_e1000e_irq_read_ics(uint32_t ics)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_READ_ICS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 209 "../hw/net/trace-events"
            qemu_log("e1000e_irq_read_ics " "Current ICS: 0x%x" "\n", ics);
#line 3944 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_READ_IMS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_READ_IMS) || \
    false)

static inline void trace_e1000e_irq_read_ims(uint32_t ims)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_READ_IMS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 210 "../hw/net/trace-events"
            qemu_log("e1000e_irq_read_ims " "Current IMS: 0x%x" "\n", ims);
#line 3959 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_ICR_CLEAR_NONMSIX_ICR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_ICR_CLEAR_NONMSIX_ICR_READ) || \
    false)

static inline void trace_e1000e_irq_icr_clear_nonmsix_icr_read(void)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_ICR_CLEAR_NONMSIX_ICR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 211 "../hw/net/trace-events"
            qemu_log("e1000e_irq_icr_clear_nonmsix_icr_read " "Clearing ICR on read due to non MSI-X int" "\n");
#line 3974 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_ICR_CLEAR_ZERO_IMS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_ICR_CLEAR_ZERO_IMS) || \
    false)

static inline void trace_e1000e_irq_icr_clear_zero_ims(void)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_ICR_CLEAR_ZERO_IMS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 212 "../hw/net/trace-events"
            qemu_log("e1000e_irq_icr_clear_zero_ims " "Clearing ICR on read due to zero IMS" "\n");
#line 3989 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_ICR_CLEAR_IAME_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_ICR_CLEAR_IAME) || \
    false)

static inline void trace_e1000e_irq_icr_clear_iame(void)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_ICR_CLEAR_IAME)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 213 "../hw/net/trace-events"
            qemu_log("e1000e_irq_icr_clear_iame " "Clearing ICR on read due to IAME" "\n");
#line 4004 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_ICR_CLEAR_ICR_BIT_IMS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_ICR_CLEAR_ICR_BIT_IMS) || \
    false)

static inline void trace_e1000e_irq_icr_clear_icr_bit_ims(uint32_t icr, uint32_t ims)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_ICR_CLEAR_ICR_BIT_IMS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 214 "../hw/net/trace-events"
            qemu_log("e1000e_irq_icr_clear_icr_bit_ims " "Clearing ICR on read due corresponding IMS bit: 0x%x & 0x%x" "\n", icr, ims);
#line 4019 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_IAM_CLEAR_EIAME_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_IAM_CLEAR_EIAME) || \
    false)

static inline void trace_e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_IAM_CLEAR_EIAME)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 215 "../hw/net/trace-events"
            qemu_log("e1000e_irq_iam_clear_eiame " "Clearing IMS due to EIAME, IAM: 0x%X, cause: 0x%X" "\n", iam, cause);
#line 4034 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_ICR_CLEAR_EIAC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_ICR_CLEAR_EIAC) || \
    false)

static inline void trace_e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_ICR_CLEAR_EIAC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 216 "../hw/net/trace-events"
            qemu_log("e1000e_irq_icr_clear_eiac " "Clearing ICR bits due to EIAC, ICR: 0x%X, EIAC: 0x%X" "\n", icr, eiac);
#line 4049 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_IMS_CLEAR_SET_IMC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_IMS_CLEAR_SET_IMC) || \
    false)

static inline void trace_e1000e_irq_ims_clear_set_imc(uint32_t val)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_IMS_CLEAR_SET_IMC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 217 "../hw/net/trace-events"
            qemu_log("e1000e_irq_ims_clear_set_imc " "Clearing IMS bits due to IMC write 0x%x" "\n", val);
#line 4064 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_FIRE_DELAYED_INTERRUPTS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_FIRE_DELAYED_INTERRUPTS) || \
    false)

static inline void trace_e1000e_irq_fire_delayed_interrupts(void)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_FIRE_DELAYED_INTERRUPTS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 218 "../hw/net/trace-events"
            qemu_log("e1000e_irq_fire_delayed_interrupts " "Firing delayed interrupts" "\n");
#line 4079 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_REARM_TIMER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_REARM_TIMER) || \
    false)

static inline void trace_e1000e_irq_rearm_timer(uint32_t reg, int64_t delay_ns)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_REARM_TIMER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 219 "../hw/net/trace-events"
            qemu_log("e1000e_irq_rearm_timer " "Mitigation timer armed for register 0x%X, delay %"PRId64" ns" "\n", reg, delay_ns);
#line 4094 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_THROTTLING_TIMER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_THROTTLING_TIMER) || \
    false)

static inline void trace_e1000e_irq_throttling_timer(uint32_t reg)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_THROTTLING_TIMER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 220 "../hw/net/trace-events"
            qemu_log("e1000e_irq_throttling_timer " "Mitigation timer shot for register 0x%X" "\n", reg);
#line 4109 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_RDTR_FPD_RUNNING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_RDTR_FPD_RUNNING) || \
    false)

static inline void trace_e1000e_irq_rdtr_fpd_running(void)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_RDTR_FPD_RUNNING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 221 "../hw/net/trace-events"
            qemu_log("e1000e_irq_rdtr_fpd_running " "FPD written while RDTR was running" "\n");
#line 4124 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_RDTR_FPD_NOT_RUNNING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_RDTR_FPD_NOT_RUNNING) || \
    false)

static inline void trace_e1000e_irq_rdtr_fpd_not_running(void)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_RDTR_FPD_NOT_RUNNING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 222 "../hw/net/trace-events"
            qemu_log("e1000e_irq_rdtr_fpd_not_running " "FPD written while RDTR was not running" "\n");
#line 4139 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_TIDV_FPD_RUNNING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_TIDV_FPD_RUNNING) || \
    false)

static inline void trace_e1000e_irq_tidv_fpd_running(void)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_TIDV_FPD_RUNNING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 223 "../hw/net/trace-events"
            qemu_log("e1000e_irq_tidv_fpd_running " "FPD written while TIDV was running" "\n");
#line 4154 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_TIDV_FPD_NOT_RUNNING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_TIDV_FPD_NOT_RUNNING) || \
    false)

static inline void trace_e1000e_irq_tidv_fpd_not_running(void)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_TIDV_FPD_NOT_RUNNING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 224 "../hw/net/trace-events"
            qemu_log("e1000e_irq_tidv_fpd_not_running " "FPD written while TIDV was not running" "\n");
#line 4169 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_EITR_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_EITR_SET) || \
    false)

static inline void trace_e1000e_irq_eitr_set(uint32_t eitr_num, uint32_t val)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_EITR_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 225 "../hw/net/trace-events"
            qemu_log("e1000e_irq_eitr_set " "EITR[%u] = %u" "\n", eitr_num, val);
#line 4184 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_ITR_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_ITR_SET) || \
    false)

static inline void trace_e1000e_irq_itr_set(uint32_t val)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_ITR_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 226 "../hw/net/trace-events"
            qemu_log("e1000e_irq_itr_set " "ITR = %u" "\n", val);
#line 4199 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_FIRE_ALL_TIMERS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_FIRE_ALL_TIMERS) || \
    false)

static inline void trace_e1000e_irq_fire_all_timers(uint32_t val)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_FIRE_ALL_TIMERS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 227 "../hw/net/trace-events"
            qemu_log("e1000e_irq_fire_all_timers " "Firing all delay/throttling timers on all interrupts enable (0x%X written to IMS)" "\n", val);
#line 4214 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IRQ_MSIX_PENDING_CLEARING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IRQ_MSIX_PENDING_CLEARING) || \
    false)

static inline void trace_e1000e_irq_msix_pending_clearing(uint32_t cause, uint32_t int_cfg, uint32_t vec)
{
    if (trace_event_get_state(TRACE_E1000E_IRQ_MSIX_PENDING_CLEARING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 228 "../hw/net/trace-events"
            qemu_log("e1000e_irq_msix_pending_clearing " "Clearing MSI-X pending bit for cause 0x%x, IVAR config 0x%x, vector %u" "\n", cause, int_cfg, vec);
#line 4229 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_MSIX_VEC_WRONG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_MSIX_VEC_WRONG) || \
    false)

static inline void trace_e1000e_wrn_msix_vec_wrong(uint32_t cause, uint32_t cfg)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_MSIX_VEC_WRONG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 230 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_msix_vec_wrong " "Invalid configuration for cause 0x%x: 0x%x" "\n", cause, cfg);
#line 4244 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_MSIX_INVALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_MSIX_INVALID) || \
    false)

static inline void trace_e1000e_wrn_msix_invalid(uint32_t cause, uint32_t cfg)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_MSIX_INVALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 231 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_msix_invalid " "Invalid entry for cause 0x%x: 0x%x" "\n", cause, cfg);
#line 4259 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_MAC_SET_SW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_MAC_SET_SW) || \
    false)

static inline void trace_e1000e_mac_set_sw(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5)
{
    if (trace_event_get_state(TRACE_E1000E_MAC_SET_SW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 233 "../hw/net/trace-events"
            qemu_log("e1000e_mac_set_sw " "Set SW MAC: %02x:%02x:%02x:%02x:%02x:%02x" "\n", b0, b1, b2, b3, b4, b5);
#line 4274 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_VM_STATE_RUNNING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_VM_STATE_RUNNING) || \
    false)

static inline void trace_e1000e_vm_state_running(void)
{
    if (trace_event_get_state(TRACE_E1000E_VM_STATE_RUNNING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 235 "../hw/net/trace-events"
            qemu_log("e1000e_vm_state_running " "VM state is running" "\n");
#line 4289 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_VM_STATE_STOPPED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_VM_STATE_STOPPED) || \
    false)

static inline void trace_e1000e_vm_state_stopped(void)
{
    if (trace_event_get_state(TRACE_E1000E_VM_STATE_STOPPED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 236 "../hw/net/trace-events"
            qemu_log("e1000e_vm_state_stopped " "VM state is stopped" "\n");
#line 4304 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CB_PCI_REALIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CB_PCI_REALIZE) || \
    false)

static inline void trace_e1000e_cb_pci_realize(void)
{
    if (trace_event_get_state(TRACE_E1000E_CB_PCI_REALIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 239 "../hw/net/trace-events"
            qemu_log("e1000e_cb_pci_realize " "E1000E PCI realize entry" "\n");
#line 4319 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CB_PCI_UNINIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CB_PCI_UNINIT) || \
    false)

static inline void trace_e1000e_cb_pci_uninit(void)
{
    if (trace_event_get_state(TRACE_E1000E_CB_PCI_UNINIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 240 "../hw/net/trace-events"
            qemu_log("e1000e_cb_pci_uninit " "E1000E PCI unit entry" "\n");
#line 4334 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CB_QDEV_RESET_HOLD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CB_QDEV_RESET_HOLD) || \
    false)

static inline void trace_e1000e_cb_qdev_reset_hold(void)
{
    if (trace_event_get_state(TRACE_E1000E_CB_QDEV_RESET_HOLD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 241 "../hw/net/trace-events"
            qemu_log("e1000e_cb_qdev_reset_hold " "E1000E qdev reset hold" "\n");
#line 4349 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CB_PRE_SAVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CB_PRE_SAVE) || \
    false)

static inline void trace_e1000e_cb_pre_save(void)
{
    if (trace_event_get_state(TRACE_E1000E_CB_PRE_SAVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 242 "../hw/net/trace-events"
            qemu_log("e1000e_cb_pre_save " "E1000E pre save entry" "\n");
#line 4364 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CB_POST_LOAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CB_POST_LOAD) || \
    false)

static inline void trace_e1000e_cb_post_load(void)
{
    if (trace_event_get_state(TRACE_E1000E_CB_POST_LOAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 243 "../hw/net/trace-events"
            qemu_log("e1000e_cb_post_load " "E1000E post load entry" "\n");
#line 4379 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IO_WRITE_ADDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IO_WRITE_ADDR) || \
    false)

static inline void trace_e1000e_io_write_addr(uint64_t addr)
{
    if (trace_event_get_state(TRACE_E1000E_IO_WRITE_ADDR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 245 "../hw/net/trace-events"
            qemu_log("e1000e_io_write_addr " "IOADDR write 0x%"PRIx64 "\n", addr);
#line 4394 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IO_WRITE_DATA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IO_WRITE_DATA) || \
    false)

static inline void trace_e1000e_io_write_data(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_E1000E_IO_WRITE_DATA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 246 "../hw/net/trace-events"
            qemu_log("e1000e_io_write_data " "IODATA write 0x%"PRIx64", value: 0x%"PRIx64 "\n", addr, val);
#line 4409 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IO_READ_ADDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IO_READ_ADDR) || \
    false)

static inline void trace_e1000e_io_read_addr(uint64_t addr)
{
    if (trace_event_get_state(TRACE_E1000E_IO_READ_ADDR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 247 "../hw/net/trace-events"
            qemu_log("e1000e_io_read_addr " "IOADDR read 0x%"PRIx64 "\n", addr);
#line 4424 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_IO_READ_DATA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_IO_READ_DATA) || \
    false)

static inline void trace_e1000e_io_read_data(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_E1000E_IO_READ_DATA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 248 "../hw/net/trace-events"
            qemu_log("e1000e_io_read_data " "IODATA read 0x%"PRIx64", value: 0x%"PRIx64 "\n", addr, val);
#line 4439 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_IO_WRITE_UNKNOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_IO_WRITE_UNKNOWN) || \
    false)

static inline void trace_e1000e_wrn_io_write_unknown(uint64_t addr)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_IO_WRITE_UNKNOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 249 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_io_write_unknown " "IO write unknown address 0x%"PRIx64 "\n", addr);
#line 4454 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_IO_READ_UNKNOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_IO_READ_UNKNOWN) || \
    false)

static inline void trace_e1000e_wrn_io_read_unknown(uint64_t addr)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_IO_READ_UNKNOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 250 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_io_read_unknown " "IO read unknown address 0x%"PRIx64 "\n", addr);
#line 4469 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_IO_ADDR_UNDEFINED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_IO_ADDR_UNDEFINED) || \
    false)

static inline void trace_e1000e_wrn_io_addr_undefined(uint64_t addr)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_IO_ADDR_UNDEFINED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 251 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_io_addr_undefined " "IO undefined register 0x%"PRIx64 "\n", addr);
#line 4484 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_IO_ADDR_FLASH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_IO_ADDR_FLASH) || \
    false)

static inline void trace_e1000e_wrn_io_addr_flash(uint64_t addr)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_IO_ADDR_FLASH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 252 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_io_addr_flash " "IO flash access (0x%"PRIx64") not implemented" "\n", addr);
#line 4499 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_WRN_IO_ADDR_UNKNOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_WRN_IO_ADDR_UNKNOWN) || \
    false)

static inline void trace_e1000e_wrn_io_addr_unknown(uint64_t addr)
{
    if (trace_event_get_state(TRACE_E1000E_WRN_IO_ADDR_UNKNOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 253 "../hw/net/trace-events"
            qemu_log("e1000e_wrn_io_addr_unknown " "IO unknown register 0x%"PRIx64 "\n", addr);
#line 4514 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_MSI_INIT_FAIL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_MSI_INIT_FAIL) || \
    false)

static inline void trace_e1000e_msi_init_fail(int32_t res)
{
    if (trace_event_get_state(TRACE_E1000E_MSI_INIT_FAIL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 255 "../hw/net/trace-events"
            qemu_log("e1000e_msi_init_fail " "Failed to initialize MSI, error %d" "\n", res);
#line 4529 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_MSIX_INIT_FAIL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_MSIX_INIT_FAIL) || \
    false)

static inline void trace_e1000e_msix_init_fail(int32_t res)
{
    if (trace_event_get_state(TRACE_E1000E_MSIX_INIT_FAIL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 256 "../hw/net/trace-events"
            qemu_log("e1000e_msix_init_fail " "Failed to initialize MSI-X, error %d" "\n", res);
#line 4544 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_MSIX_USE_VECTOR_FAIL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_MSIX_USE_VECTOR_FAIL) || \
    false)

static inline void trace_e1000e_msix_use_vector_fail(uint32_t vec, int32_t res)
{
    if (trace_event_get_state(TRACE_E1000E_MSIX_USE_VECTOR_FAIL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 257 "../hw/net/trace-events"
            qemu_log("e1000e_msix_use_vector_fail " "Failed to use MSI-X vector %d, error %d" "\n", vec, res);
#line 4559 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_MAC_SET_PERMANENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_MAC_SET_PERMANENT) || \
    false)

static inline void trace_e1000e_mac_set_permanent(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5)
{
    if (trace_event_get_state(TRACE_E1000E_MAC_SET_PERMANENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 259 "../hw/net/trace-events"
            qemu_log("e1000e_mac_set_permanent " "Set permanent MAC: %02x:%02x:%02x:%02x:%02x:%02x" "\n", b0, b1, b2, b3, b4, b5);
#line 4574 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_E1000E_CFG_SUPPORT_VIRTIO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_E1000E_CFG_SUPPORT_VIRTIO) || \
    false)

static inline void trace_e1000e_cfg_support_virtio(bool support)
{
    if (trace_event_get_state(TRACE_E1000E_CFG_SUPPORT_VIRTIO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 260 "../hw/net/trace-events"
            qemu_log("e1000e_cfg_support_virtio " "Virtio header supported: %d" "\n", support);
#line 4589 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_WRITE_CONFIG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_WRITE_CONFIG) || \
    false)

static inline void trace_igb_write_config(uint32_t address, uint32_t val, int len)
{
    if (trace_event_get_state(TRACE_IGB_WRITE_CONFIG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 263 "../hw/net/trace-events"
            qemu_log("igb_write_config " "CONFIG write 0x%"PRIx32", value: 0x%"PRIx32", len: %"PRId32 "\n", address, val, len);
#line 4604 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGBVF_WRITE_CONFIG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGBVF_WRITE_CONFIG) || \
    false)

static inline void trace_igbvf_write_config(uint32_t address, uint32_t val, int len)
{
    if (trace_event_get_state(TRACE_IGBVF_WRITE_CONFIG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 264 "../hw/net/trace-events"
            qemu_log("igbvf_write_config " "CONFIG write 0x%"PRIx32", value: 0x%"PRIx32", len: %"PRId32 "\n", address, val, len);
#line 4619 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_CORE_MDIC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_CORE_MDIC_READ) || \
    false)

static inline void trace_igb_core_mdic_read(uint32_t addr, uint32_t data)
{
    if (trace_event_get_state(TRACE_IGB_CORE_MDIC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 267 "../hw/net/trace-events"
            qemu_log("igb_core_mdic_read " "MDIC READ: PHY[%u] = 0x%x" "\n", addr, data);
#line 4634 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_CORE_MDIC_READ_UNHANDLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_CORE_MDIC_READ_UNHANDLED) || \
    false)

static inline void trace_igb_core_mdic_read_unhandled(uint32_t addr)
{
    if (trace_event_get_state(TRACE_IGB_CORE_MDIC_READ_UNHANDLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 268 "../hw/net/trace-events"
            qemu_log("igb_core_mdic_read_unhandled " "MDIC READ: PHY[%u] UNHANDLED" "\n", addr);
#line 4649 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_CORE_MDIC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_CORE_MDIC_WRITE) || \
    false)

static inline void trace_igb_core_mdic_write(uint32_t addr, uint32_t data)
{
    if (trace_event_get_state(TRACE_IGB_CORE_MDIC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 269 "../hw/net/trace-events"
            qemu_log("igb_core_mdic_write " "MDIC WRITE: PHY[%u] = 0x%x" "\n", addr, data);
#line 4664 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_CORE_MDIC_WRITE_UNHANDLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_CORE_MDIC_WRITE_UNHANDLED) || \
    false)

static inline void trace_igb_core_mdic_write_unhandled(uint32_t addr)
{
    if (trace_event_get_state(TRACE_IGB_CORE_MDIC_WRITE_UNHANDLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 270 "../hw/net/trace-events"
            qemu_log("igb_core_mdic_write_unhandled " "MDIC WRITE: PHY[%u] UNHANDLED" "\n", addr);
#line 4679 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_CORE_VF_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_CORE_VF_RESET) || \
    false)

static inline void trace_igb_core_vf_reset(uint16_t vfn)
{
    if (trace_event_get_state(TRACE_IGB_CORE_VF_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 271 "../hw/net/trace-events"
            qemu_log("igb_core_vf_reset " "VF%d" "\n", vfn);
#line 4694 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_LINK_SET_EXT_PARAMS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_LINK_SET_EXT_PARAMS) || \
    false)

static inline void trace_igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, bool pfrstd)
{
    if (trace_event_get_state(TRACE_IGB_LINK_SET_EXT_PARAMS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 273 "../hw/net/trace-events"
            qemu_log("igb_link_set_ext_params " "Set extended link params: ASD check: %d, Speed select bypass: %d, PF reset done: %d" "\n", asd_check, speed_select_bypass, pfrstd);
#line 4709 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_RX_DESC_BUFF_SIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_RX_DESC_BUFF_SIZE) || \
    false)

static inline void trace_igb_rx_desc_buff_size(uint32_t b)
{
    if (trace_event_get_state(TRACE_IGB_RX_DESC_BUFF_SIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 275 "../hw/net/trace-events"
            qemu_log("igb_rx_desc_buff_size " "buffer size: %u" "\n", b);
#line 4724 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_RX_DESC_BUFF_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_RX_DESC_BUFF_WRITE) || \
    false)

static inline void trace_igb_rx_desc_buff_write(uint8_t idx, uint64_t addr, uint16_t offset, const void*source, uint32_t len)
{
    if (trace_event_get_state(TRACE_IGB_RX_DESC_BUFF_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 276 "../hw/net/trace-events"
            qemu_log("igb_rx_desc_buff_write " "buffer %u, addr: 0x%"PRIx64", offset: %u, from: %p, length: %u" "\n", idx, addr, offset, source, len);
#line 4739 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_RX_METADATA_RSS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_RX_METADATA_RSS) || \
    false)

static inline void trace_igb_rx_metadata_rss(uint32_t rss, uint16_t rss_pkt_type)
{
    if (trace_event_get_state(TRACE_IGB_RX_METADATA_RSS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 278 "../hw/net/trace-events"
            qemu_log("igb_rx_metadata_rss " "RSS data: rss: 0x%X, rss_pkt_type: 0x%X" "\n", rss, rss_pkt_type);
#line 4754 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_IRQ_ICR_CLEAR_GPIE_NSICR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_IRQ_ICR_CLEAR_GPIE_NSICR) || \
    false)

static inline void trace_igb_irq_icr_clear_gpie_nsicr(void)
{
    if (trace_event_get_state(TRACE_IGB_IRQ_ICR_CLEAR_GPIE_NSICR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 280 "../hw/net/trace-events"
            qemu_log("igb_irq_icr_clear_gpie_nsicr " "Clearing ICR on read due to GPIE.NSICR enabled" "\n");
#line 4769 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_IRQ_SET_IAM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_IRQ_SET_IAM) || \
    false)

static inline void trace_igb_irq_set_iam(uint32_t icr)
{
    if (trace_event_get_state(TRACE_IGB_IRQ_SET_IAM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 281 "../hw/net/trace-events"
            qemu_log("igb_irq_set_iam " "Update IAM: 0x%x" "\n", icr);
#line 4784 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_IRQ_READ_IAM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_IRQ_READ_IAM) || \
    false)

static inline void trace_igb_irq_read_iam(uint32_t icr)
{
    if (trace_event_get_state(TRACE_IGB_IRQ_READ_IAM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 282 "../hw/net/trace-events"
            qemu_log("igb_irq_read_iam " "Current IAM: 0x%x" "\n", icr);
#line 4799 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_IRQ_WRITE_EICS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_IRQ_WRITE_EICS) || \
    false)

static inline void trace_igb_irq_write_eics(uint32_t val, bool msix)
{
    if (trace_event_get_state(TRACE_IGB_IRQ_WRITE_EICS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 283 "../hw/net/trace-events"
            qemu_log("igb_irq_write_eics " "Update EICS: 0x%x MSI-X: %d" "\n", val, msix);
#line 4814 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_IRQ_WRITE_EIMS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_IRQ_WRITE_EIMS) || \
    false)

static inline void trace_igb_irq_write_eims(uint32_t val, bool msix)
{
    if (trace_event_get_state(TRACE_IGB_IRQ_WRITE_EIMS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 284 "../hw/net/trace-events"
            qemu_log("igb_irq_write_eims " "Update EIMS: 0x%x MSI-X: %d" "\n", val, msix);
#line 4829 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_IRQ_WRITE_EIMC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_IRQ_WRITE_EIMC) || \
    false)

static inline void trace_igb_irq_write_eimc(uint32_t val, bool msix)
{
    if (trace_event_get_state(TRACE_IGB_IRQ_WRITE_EIMC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 285 "../hw/net/trace-events"
            qemu_log("igb_irq_write_eimc " "Update EIMC: 0x%x MSI-X: %d" "\n", val, msix);
#line 4844 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_IRQ_WRITE_EIAC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_IRQ_WRITE_EIAC) || \
    false)

static inline void trace_igb_irq_write_eiac(uint32_t val)
{
    if (trace_event_get_state(TRACE_IGB_IRQ_WRITE_EIAC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 286 "../hw/net/trace-events"
            qemu_log("igb_irq_write_eiac " "Update EIAC: 0x%x" "\n", val);
#line 4859 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_IRQ_WRITE_EIAM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_IRQ_WRITE_EIAM) || \
    false)

static inline void trace_igb_irq_write_eiam(uint32_t val, bool msix)
{
    if (trace_event_get_state(TRACE_IGB_IRQ_WRITE_EIAM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 287 "../hw/net/trace-events"
            qemu_log("igb_irq_write_eiam " "Update EIAM: 0x%x MSI-X: %d" "\n", val, msix);
#line 4874 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_IRQ_WRITE_EICR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_IRQ_WRITE_EICR) || \
    false)

static inline void trace_igb_irq_write_eicr(uint32_t val, bool msix)
{
    if (trace_event_get_state(TRACE_IGB_IRQ_WRITE_EICR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 288 "../hw/net/trace-events"
            qemu_log("igb_irq_write_eicr " "Update EICR: 0x%x MSI-X: %d" "\n", val, msix);
#line 4889 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_IRQ_EITR_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_IRQ_EITR_SET) || \
    false)

static inline void trace_igb_irq_eitr_set(uint32_t eitr_num, uint32_t val)
{
    if (trace_event_get_state(TRACE_IGB_IRQ_EITR_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 289 "../hw/net/trace-events"
            qemu_log("igb_irq_eitr_set " "EITR[%u] = 0x%x" "\n", eitr_num, val);
#line 4904 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_SET_PFMAILBOX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_SET_PFMAILBOX) || \
    false)

static inline void trace_igb_set_pfmailbox(uint32_t vf_num, uint32_t val)
{
    if (trace_event_get_state(TRACE_IGB_SET_PFMAILBOX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 290 "../hw/net/trace-events"
            qemu_log("igb_set_pfmailbox " "PFMailbox[%d]: 0x%x" "\n", vf_num, val);
#line 4919 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_SET_VFMAILBOX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_SET_VFMAILBOX) || \
    false)

static inline void trace_igb_set_vfmailbox(uint32_t vf_num, uint32_t val)
{
    if (trace_event_get_state(TRACE_IGB_SET_VFMAILBOX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 291 "../hw/net/trace-events"
            qemu_log("igb_set_vfmailbox " "VFMailbox[%d]: 0x%x" "\n", vf_num, val);
#line 4934 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGB_WRN_RX_DESC_MODES_NOT_SUPP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGB_WRN_RX_DESC_MODES_NOT_SUPP) || \
    false)

static inline void trace_igb_wrn_rx_desc_modes_not_supp(int desc_type)
{
    if (trace_event_get_state(TRACE_IGB_WRN_RX_DESC_MODES_NOT_SUPP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 293 "../hw/net/trace-events"
            qemu_log("igb_wrn_rx_desc_modes_not_supp " "Not supported descriptor type: %d" "\n", desc_type);
#line 4949 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IGBVF_WRN_IO_ADDR_UNKNOWN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IGBVF_WRN_IO_ADDR_UNKNOWN) || \
    false)

static inline void trace_igbvf_wrn_io_addr_unknown(uint64_t addr)
{
    if (trace_event_get_state(TRACE_IGBVF_WRN_IO_ADDR_UNKNOWN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 296 "../hw/net/trace-events"
            qemu_log("igbvf_wrn_io_addr_unknown " "IO unknown register 0x%"PRIx64 "\n", addr);
#line 4964 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_GET_RX_BD_FROM_POOL_FOUND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_GET_RX_BD_FROM_POOL_FOUND) || \
    false)

static inline void trace_spapr_vlan_get_rx_bd_from_pool_found(int pool, int32_t count, uint32_t rx_bufs)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_GET_RX_BD_FROM_POOL_FOUND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 299 "../hw/net/trace-events"
            qemu_log("spapr_vlan_get_rx_bd_from_pool_found " "pool=%d count=%"PRId32" rxbufs=%"PRIu32 "\n", pool, count, rx_bufs);
#line 4979 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE) || \
    false)

static inline void trace_spapr_vlan_get_rx_bd_from_page(int buf_ptr, uint64_t bd)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 300 "../hw/net/trace-events"
            qemu_log("spapr_vlan_get_rx_bd_from_page " "use_buf_ptr=%d bd=0x%016"PRIx64 "\n", buf_ptr, bd);
#line 4994 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_FOUND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_FOUND) || \
    false)

static inline void trace_spapr_vlan_get_rx_bd_from_page_found(uint32_t use_buf_ptr, uint32_t rx_bufs)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_GET_RX_BD_FROM_PAGE_FOUND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 301 "../hw/net/trace-events"
            qemu_log("spapr_vlan_get_rx_bd_from_page_found " "ptr=%"PRIu32" rxbufs=%"PRIu32 "\n", use_buf_ptr, rx_bufs);
#line 5009 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_RECEIVE) || \
    false)

static inline void trace_spapr_vlan_receive(const char *id, uint32_t rx_bufs)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 302 "../hw/net/trace-events"
            qemu_log("spapr_vlan_receive " "[%s] rx_bufs=%"PRIu32 "\n", id, rx_bufs);
#line 5024 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_RECEIVE_DMA_COMPLETED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_RECEIVE_DMA_COMPLETED) || \
    false)

static inline void trace_spapr_vlan_receive_dma_completed(void)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_RECEIVE_DMA_COMPLETED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 303 "../hw/net/trace-events"
            qemu_log("spapr_vlan_receive_dma_completed " "DMA write completed" "\n");
#line 5039 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_RECEIVE_WROTE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_RECEIVE_WROTE) || \
    false)

static inline void trace_spapr_vlan_receive_wrote(uint64_t ptr, uint64_t hi, uint64_t lo)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_RECEIVE_WROTE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 304 "../hw/net/trace-events"
            qemu_log("spapr_vlan_receive_wrote " "rxq entry (ptr=0x%"PRIx64"): 0x%016"PRIx64" 0x%016"PRIx64 "\n", ptr, hi, lo);
#line 5054 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_CREATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_CREATE) || \
    false)

static inline void trace_spapr_vlan_add_rxbuf_to_pool_create(int pool, uint64_t len)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_CREATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 305 "../hw/net/trace-events"
            qemu_log("spapr_vlan_add_rxbuf_to_pool_create " "created RX pool %d for size %"PRIu64 "\n", pool, len);
#line 5069 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL) || \
    false)

static inline void trace_spapr_vlan_add_rxbuf_to_pool(int pool, uint64_t len, int32_t count)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_ADD_RXBUF_TO_POOL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 306 "../hw/net/trace-events"
            qemu_log("spapr_vlan_add_rxbuf_to_pool " "add buf using pool %d (size %"PRIu64", count=%"PRId32")" "\n", pool, len, count);
#line 5084 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_ADD_RXBUF_TO_PAGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_ADD_RXBUF_TO_PAGE) || \
    false)

static inline void trace_spapr_vlan_add_rxbuf_to_page(uint32_t ptr, uint32_t rx_bufs, uint64_t bd)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_ADD_RXBUF_TO_PAGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 307 "../hw/net/trace-events"
            qemu_log("spapr_vlan_add_rxbuf_to_page " "added buf ptr=%"PRIu32"  rx_bufs=%"PRIu32" bd=0x%016"PRIx64 "\n", ptr, rx_bufs, bd);
#line 5099 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_H_ADD_LOGICAL_LAN_BUFFER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_H_ADD_LOGICAL_LAN_BUFFER) || \
    false)

static inline void trace_spapr_vlan_h_add_logical_lan_buffer(uint64_t reg, uint64_t buf)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_H_ADD_LOGICAL_LAN_BUFFER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 308 "../hw/net/trace-events"
            qemu_log("spapr_vlan_h_add_logical_lan_buffer " "H_ADD_LOGICAL_LAN_BUFFER(0x%"PRIx64", 0x%"PRIx64")" "\n", reg, buf);
#line 5114 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN) || \
    false)

static inline void trace_spapr_vlan_h_send_logical_lan(uint64_t reg, uint64_t continue_token)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 309 "../hw/net/trace-events"
            qemu_log("spapr_vlan_h_send_logical_lan " "H_SEND_LOGICAL_LAN(0x%"PRIx64", <bufs>, 0x%"PRIx64")" "\n", reg, continue_token);
#line 5129 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_RXBUFS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_RXBUFS) || \
    false)

static inline void trace_spapr_vlan_h_send_logical_lan_rxbufs(uint32_t rx_bufs)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_RXBUFS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 310 "../hw/net/trace-events"
            qemu_log("spapr_vlan_h_send_logical_lan_rxbufs " "rxbufs = %"PRIu32 "\n", rx_bufs);
#line 5144 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BUF_DESC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BUF_DESC) || \
    false)

static inline void trace_spapr_vlan_h_send_logical_lan_buf_desc(uint64_t buf)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_BUF_DESC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 311 "../hw/net/trace-events"
            qemu_log("spapr_vlan_h_send_logical_lan_buf_desc " "   buf desc: 0x%"PRIx64 "\n", buf);
#line 5159 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_TOTAL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_TOTAL) || \
    false)

static inline void trace_spapr_vlan_h_send_logical_lan_total(int nbufs, unsigned total_len)
{
    if (trace_event_get_state(TRACE_SPAPR_VLAN_H_SEND_LOGICAL_LAN_TOTAL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 312 "../hw/net/trace-events"
            qemu_log("spapr_vlan_h_send_logical_lan_total " "%d buffers, total length 0x%x" "\n", nbufs, total_len);
#line 5174 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_TX_CHECKSUM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_TX_CHECKSUM) || \
    false)

static inline void trace_sungem_tx_checksum(uint16_t start, uint16_t off)
{
    if (trace_event_get_state(TRACE_SUNGEM_TX_CHECKSUM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 315 "../hw/net/trace-events"
            qemu_log("sungem_tx_checksum " "TX checksumming from byte %d, inserting at %d" "\n", start, off);
#line 5189 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_TX_CHECKSUM_OOB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_TX_CHECKSUM_OOB) || \
    false)

static inline void trace_sungem_tx_checksum_oob(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_TX_CHECKSUM_OOB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 316 "../hw/net/trace-events"
            qemu_log("sungem_tx_checksum_oob " "TX checksum out of packet bounds" "\n");
#line 5204 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_TX_UNFINISHED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_TX_UNFINISHED) || \
    false)

static inline void trace_sungem_tx_unfinished(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_TX_UNFINISHED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 317 "../hw/net/trace-events"
            qemu_log("sungem_tx_unfinished " "TX packet started without finishing the previous one" "\n");
#line 5219 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_TX_OVERFLOW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_TX_OVERFLOW) || \
    false)

static inline void trace_sungem_tx_overflow(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_TX_OVERFLOW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 318 "../hw/net/trace-events"
            qemu_log("sungem_tx_overflow " "TX packet queue overflow" "\n");
#line 5234 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_TX_FINISHED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_TX_FINISHED) || \
    false)

static inline void trace_sungem_tx_finished(uint32_t size)
{
    if (trace_event_get_state(TRACE_SUNGEM_TX_FINISHED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 319 "../hw/net/trace-events"
            qemu_log("sungem_tx_finished " "TX completing %"PRIu32 " bytes packet" "\n", size);
#line 5249 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_TX_KICK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_TX_KICK) || \
    false)

static inline void trace_sungem_tx_kick(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_TX_KICK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 320 "../hw/net/trace-events"
            qemu_log("sungem_tx_kick " "TX Kick..." "\n");
#line 5264 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_TX_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_TX_DISABLED) || \
    false)

static inline void trace_sungem_tx_disabled(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_TX_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 321 "../hw/net/trace-events"
            qemu_log("sungem_tx_disabled " "TX not enabled" "\n");
#line 5279 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_TX_PROCESS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_TX_PROCESS) || \
    false)

static inline void trace_sungem_tx_process(uint32_t comp, uint32_t kick, uint32_t size)
{
    if (trace_event_get_state(TRACE_SUNGEM_TX_PROCESS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 322 "../hw/net/trace-events"
            qemu_log("sungem_tx_process " "TX processing comp=%"PRIu32", kick=%"PRIu32" out of %"PRIu32 "\n", comp, kick, size);
#line 5294 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_TX_DESC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_TX_DESC) || \
    false)

static inline void trace_sungem_tx_desc(uint32_t comp, uint64_t control, uint64_t buffer)
{
    if (trace_event_get_state(TRACE_SUNGEM_TX_DESC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 323 "../hw/net/trace-events"
            qemu_log("sungem_tx_desc " "TX desc %"PRIu32 ": 0x%"PRIx64" 0x%"PRIx64 "\n", comp, control, buffer);
#line 5309 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_TX_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_TX_RESET) || \
    false)

static inline void trace_sungem_tx_reset(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_TX_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 324 "../hw/net/trace-events"
            qemu_log("sungem_tx_reset " "TX reset" "\n");
#line 5324 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_MAC_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_MAC_DISABLED) || \
    false)

static inline void trace_sungem_rx_mac_disabled(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_MAC_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 325 "../hw/net/trace-events"
            qemu_log("sungem_rx_mac_disabled " "Check RX MAC disabled" "\n");
#line 5339 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_TXDMA_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_TXDMA_DISABLED) || \
    false)

static inline void trace_sungem_rx_txdma_disabled(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_TXDMA_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 326 "../hw/net/trace-events"
            qemu_log("sungem_rx_txdma_disabled " "Check RX TXDMA disabled" "\n");
#line 5354 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_CHECK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_CHECK) || \
    false)

static inline void trace_sungem_rx_check(bool full, uint32_t kick, uint32_t done)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_CHECK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 327 "../hw/net/trace-events"
            qemu_log("sungem_rx_check " "Check RX %d (kick=%"PRIu32", done=%"PRIu32")" "\n", full, kick, done);
#line 5369 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_MAC_CHECK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_MAC_CHECK) || \
    false)

static inline void trace_sungem_rx_mac_check(uint32_t mac0, uint32_t mac1, uint32_t mac2)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_MAC_CHECK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 328 "../hw/net/trace-events"
            qemu_log("sungem_rx_mac_check " "Word MAC: 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32 "\n", mac0, mac1, mac2);
#line 5384 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_MAC_MULTICAST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_MAC_MULTICAST) || \
    false)

static inline void trace_sungem_rx_mac_multicast(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_MAC_MULTICAST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 329 "../hw/net/trace-events"
            qemu_log("sungem_rx_mac_multicast " "Multicast" "\n");
#line 5399 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_MAC_COMPARE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_MAC_COMPARE) || \
    false)

static inline void trace_sungem_rx_mac_compare(uint32_t mac0, uint32_t mac1, uint32_t mac2)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_MAC_COMPARE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 330 "../hw/net/trace-events"
            qemu_log("sungem_rx_mac_compare " "Compare MAC to 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32".." "\n", mac0, mac1, mac2);
#line 5414 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_PACKET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_PACKET) || \
    false)

static inline void trace_sungem_rx_packet(size_t size)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_PACKET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 331 "../hw/net/trace-events"
            qemu_log("sungem_rx_packet " "RX got %zu bytes packet" "\n", size);
#line 5429 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_DISABLED) || \
    false)

static inline void trace_sungem_rx_disabled(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_DISABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 332 "../hw/net/trace-events"
            qemu_log("sungem_rx_disabled " "RX not enabled" "\n");
#line 5444 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_BAD_FRAME_SIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_BAD_FRAME_SIZE) || \
    false)

static inline void trace_sungem_rx_bad_frame_size(size_t size)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_BAD_FRAME_SIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 333 "../hw/net/trace-events"
            qemu_log("sungem_rx_bad_frame_size " "RX bad frame size %zu, dropped" "\n", size);
#line 5459 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_UNMATCHED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_UNMATCHED) || \
    false)

static inline void trace_sungem_rx_unmatched(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_UNMATCHED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 334 "../hw/net/trace-events"
            qemu_log("sungem_rx_unmatched " "No match, dropped" "\n");
#line 5474 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_PROCESS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_PROCESS) || \
    false)

static inline void trace_sungem_rx_process(uint32_t done, uint32_t kick, uint32_t size)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_PROCESS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 335 "../hw/net/trace-events"
            qemu_log("sungem_rx_process " "RX processing done=%"PRIu32", kick=%"PRIu32" out of %"PRIu32 "\n", done, kick, size);
#line 5489 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_RINGFULL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_RINGFULL) || \
    false)

static inline void trace_sungem_rx_ringfull(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_RINGFULL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 336 "../hw/net/trace-events"
            qemu_log("sungem_rx_ringfull " "RX ring full" "\n");
#line 5504 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_DESC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_DESC) || \
    false)

static inline void trace_sungem_rx_desc(uint64_t control, uint64_t buffer)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_DESC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 337 "../hw/net/trace-events"
            qemu_log("sungem_rx_desc " "RX desc: 0x%"PRIx64" 0x%"PRIx64 "\n", control, buffer);
#line 5519 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_RESET) || \
    false)

static inline void trace_sungem_rx_reset(void)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 338 "../hw/net/trace-events"
            qemu_log("sungem_rx_reset " "RX reset" "\n");
#line 5534 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RX_KICK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RX_KICK) || \
    false)

static inline void trace_sungem_rx_kick(uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_RX_KICK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 339 "../hw/net/trace-events"
            qemu_log("sungem_rx_kick " "RXDMA_KICK written to %"PRIu64 "\n", val);
#line 5549 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_RESET) || \
    false)

static inline void trace_sungem_reset(bool pci_reset)
{
    if (trace_event_get_state(TRACE_SUNGEM_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 340 "../hw/net/trace-events"
            qemu_log("sungem_reset " "Full reset (PCI:%d)" "\n", pci_reset);
#line 5564 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MII_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MII_WRITE) || \
    false)

static inline void trace_sungem_mii_write(uint8_t phy_addr, uint8_t reg_addr, uint16_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MII_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 341 "../hw/net/trace-events"
            qemu_log("sungem_mii_write " "MII write addr 0x%x reg 0x%02x val 0x%04x" "\n", phy_addr, reg_addr, val);
#line 5579 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MII_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MII_READ) || \
    false)

static inline void trace_sungem_mii_read(uint8_t phy_addr, uint8_t reg_addr, uint16_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MII_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 342 "../hw/net/trace-events"
            qemu_log("sungem_mii_read " "MII read addr 0x%x reg 0x%02x val 0x%04x" "\n", phy_addr, reg_addr, val);
#line 5594 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MII_INVALID_SOF_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MII_INVALID_SOF) || \
    false)

static inline void trace_sungem_mii_invalid_sof(uint32_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MII_INVALID_SOF)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 343 "../hw/net/trace-events"
            qemu_log("sungem_mii_invalid_sof " "MII op, invalid SOF field 0x%"PRIx32 "\n", val);
#line 5609 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MII_INVALID_OP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MII_INVALID_OP) || \
    false)

static inline void trace_sungem_mii_invalid_op(uint8_t op)
{
    if (trace_event_get_state(TRACE_SUNGEM_MII_INVALID_OP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 344 "../hw/net/trace-events"
            qemu_log("sungem_mii_invalid_op " "MII op, invalid op field 0x%x" "\n", op);
#line 5624 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_GREG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_GREG_WRITE) || \
    false)

static inline void trace_sungem_mmio_greg_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_GREG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 345 "../hw/net/trace-events"
            qemu_log("sungem_mmio_greg_write " "MMIO greg write to 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5639 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_GREG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_GREG_READ) || \
    false)

static inline void trace_sungem_mmio_greg_read(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_GREG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 346 "../hw/net/trace-events"
            qemu_log("sungem_mmio_greg_read " "MMIO greg read from 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5654 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_TXDMA_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_TXDMA_WRITE) || \
    false)

static inline void trace_sungem_mmio_txdma_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_TXDMA_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 347 "../hw/net/trace-events"
            qemu_log("sungem_mmio_txdma_write " "MMIO txdma write to 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5669 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_TXDMA_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_TXDMA_READ) || \
    false)

static inline void trace_sungem_mmio_txdma_read(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_TXDMA_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 348 "../hw/net/trace-events"
            qemu_log("sungem_mmio_txdma_read " "MMIO txdma read from 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5684 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_RXDMA_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_RXDMA_WRITE) || \
    false)

static inline void trace_sungem_mmio_rxdma_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_RXDMA_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 349 "../hw/net/trace-events"
            qemu_log("sungem_mmio_rxdma_write " "MMIO rxdma write to 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5699 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_RXDMA_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_RXDMA_READ) || \
    false)

static inline void trace_sungem_mmio_rxdma_read(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_RXDMA_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 350 "../hw/net/trace-events"
            qemu_log("sungem_mmio_rxdma_read " "MMIO rxdma read from 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5714 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_WOL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_WOL_WRITE) || \
    false)

static inline void trace_sungem_mmio_wol_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_WOL_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 351 "../hw/net/trace-events"
            qemu_log("sungem_mmio_wol_write " "MMIO wol write to 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5729 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_WOL_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_WOL_READ) || \
    false)

static inline void trace_sungem_mmio_wol_read(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_WOL_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 352 "../hw/net/trace-events"
            qemu_log("sungem_mmio_wol_read " "MMIO wol read from 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5744 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_MAC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_MAC_WRITE) || \
    false)

static inline void trace_sungem_mmio_mac_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_MAC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 353 "../hw/net/trace-events"
            qemu_log("sungem_mmio_mac_write " "MMIO mac write to 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5759 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_MAC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_MAC_READ) || \
    false)

static inline void trace_sungem_mmio_mac_read(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_MAC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 354 "../hw/net/trace-events"
            qemu_log("sungem_mmio_mac_read " "MMIO mac read from 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5774 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_MIF_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_MIF_WRITE) || \
    false)

static inline void trace_sungem_mmio_mif_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_MIF_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 355 "../hw/net/trace-events"
            qemu_log("sungem_mmio_mif_write " "MMIO mif write to 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5789 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_MIF_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_MIF_READ) || \
    false)

static inline void trace_sungem_mmio_mif_read(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_MIF_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 356 "../hw/net/trace-events"
            qemu_log("sungem_mmio_mif_read " "MMIO mif read from 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5804 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_PCS_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_PCS_WRITE) || \
    false)

static inline void trace_sungem_mmio_pcs_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_PCS_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 357 "../hw/net/trace-events"
            qemu_log("sungem_mmio_pcs_write " "MMIO pcs write to 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5819 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNGEM_MMIO_PCS_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNGEM_MMIO_PCS_READ) || \
    false)

static inline void trace_sungem_mmio_pcs_read(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SUNGEM_MMIO_PCS_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 358 "../hw/net/trace-events"
            qemu_log("sungem_mmio_pcs_read " "MMIO pcs read from 0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val);
#line 5834 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_SEB_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_SEB_WRITE) || \
    false)

static inline void trace_sunhme_seb_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_SEB_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 361 "../hw/net/trace-events"
            qemu_log("sunhme_seb_write " "addr 0x%"PRIx64" value 0x%"PRIx64 "\n", addr, value);
#line 5849 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_SEB_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_SEB_READ) || \
    false)

static inline void trace_sunhme_seb_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_SEB_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 362 "../hw/net/trace-events"
            qemu_log("sunhme_seb_read " "addr 0x%"PRIx64" value 0x%"PRIx64 "\n", addr, value);
#line 5864 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_ETX_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_ETX_WRITE) || \
    false)

static inline void trace_sunhme_etx_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_ETX_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 363 "../hw/net/trace-events"
            qemu_log("sunhme_etx_write " "addr 0x%"PRIx64" value 0x%"PRIx64 "\n", addr, value);
#line 5879 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_ETX_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_ETX_READ) || \
    false)

static inline void trace_sunhme_etx_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_ETX_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 364 "../hw/net/trace-events"
            qemu_log("sunhme_etx_read " "addr 0x%"PRIx64" value 0x%"PRIx64 "\n", addr, value);
#line 5894 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_ERX_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_ERX_WRITE) || \
    false)

static inline void trace_sunhme_erx_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_ERX_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 365 "../hw/net/trace-events"
            qemu_log("sunhme_erx_write " "addr 0x%"PRIx64" value 0x%"PRIx64 "\n", addr, value);
#line 5909 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_ERX_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_ERX_READ) || \
    false)

static inline void trace_sunhme_erx_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_ERX_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 366 "../hw/net/trace-events"
            qemu_log("sunhme_erx_read " "addr 0x%"PRIx64" value 0x%"PRIx64 "\n", addr, value);
#line 5924 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_MAC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_MAC_WRITE) || \
    false)

static inline void trace_sunhme_mac_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_MAC_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 367 "../hw/net/trace-events"
            qemu_log("sunhme_mac_write " "addr 0x%"PRIx64" value 0x%"PRIx64 "\n", addr, value);
#line 5939 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_MAC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_MAC_READ) || \
    false)

static inline void trace_sunhme_mac_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_MAC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 368 "../hw/net/trace-events"
            qemu_log("sunhme_mac_read " "addr 0x%"PRIx64" value 0x%"PRIx64 "\n", addr, value);
#line 5954 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_MII_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_MII_WRITE) || \
    false)

static inline void trace_sunhme_mii_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_MII_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 369 "../hw/net/trace-events"
            qemu_log("sunhme_mii_write " "addr 0x%"PRIx64" value 0x%"PRIx64 "\n", addr, value);
#line 5969 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_MII_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_MII_READ) || \
    false)

static inline void trace_sunhme_mii_read(uint8_t addr, uint16_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_MII_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 370 "../hw/net/trace-events"
            qemu_log("sunhme_mii_read " "addr 0x%x value 0x%x" "\n", addr, value);
#line 5984 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_MIF_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_MIF_WRITE) || \
    false)

static inline void trace_sunhme_mif_write(uint8_t addr, uint16_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_MIF_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 371 "../hw/net/trace-events"
            qemu_log("sunhme_mif_write " "addr 0x%x value 0x%x" "\n", addr, value);
#line 5999 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_MIF_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_MIF_READ) || \
    false)

static inline void trace_sunhme_mif_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_SUNHME_MIF_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 372 "../hw/net/trace-events"
            qemu_log("sunhme_mif_read " "addr 0x%"PRIx64" value 0x%"PRIx64 "\n", addr, value);
#line 6014 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_TX_DESC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_TX_DESC) || \
    false)

static inline void trace_sunhme_tx_desc(uint64_t buffer, uint32_t status, int cr, int nr)
{
    if (trace_event_get_state(TRACE_SUNHME_TX_DESC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 373 "../hw/net/trace-events"
            qemu_log("sunhme_tx_desc " "addr 0x%"PRIx64" status 0x%"PRIx32 " (ring %d/%d)" "\n", buffer, status, cr, nr);
#line 6029 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_TX_XSUM_ADD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_TX_XSUM_ADD) || \
    false)

static inline void trace_sunhme_tx_xsum_add(int offset, int len)
{
    if (trace_event_get_state(TRACE_SUNHME_TX_XSUM_ADD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 374 "../hw/net/trace-events"
            qemu_log("sunhme_tx_xsum_add " "adding xsum at offset %d, len %d" "\n", offset, len);
#line 6044 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_TX_XSUM_STUFF_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_TX_XSUM_STUFF) || \
    false)

static inline void trace_sunhme_tx_xsum_stuff(uint16_t xsum, int offset)
{
    if (trace_event_get_state(TRACE_SUNHME_TX_XSUM_STUFF)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 375 "../hw/net/trace-events"
            qemu_log("sunhme_tx_xsum_stuff " "stuffing xsum 0x%x at offset %d" "\n", xsum, offset);
#line 6059 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_TX_DONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_TX_DONE) || \
    false)

static inline void trace_sunhme_tx_done(int len)
{
    if (trace_event_get_state(TRACE_SUNHME_TX_DONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 376 "../hw/net/trace-events"
            qemu_log("sunhme_tx_done " "successfully transmitted frame with len %d" "\n", len);
#line 6074 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_INCOMING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_INCOMING) || \
    false)

static inline void trace_sunhme_rx_incoming(size_t len)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_INCOMING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 377 "../hw/net/trace-events"
            qemu_log("sunhme_rx_incoming " "received incoming frame with len %zu" "\n", len);
#line 6089 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_FILTER_DESTMAC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_FILTER_DESTMAC) || \
    false)

static inline void trace_sunhme_rx_filter_destmac(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_FILTER_DESTMAC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 378 "../hw/net/trace-events"
            qemu_log("sunhme_rx_filter_destmac " "received frame for MAC: %02x:%02x:%02x:%02x:%02x:%02x" "\n", b0, b1, b2, b3, b4, b5);
#line 6104 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_FILTER_LOCAL_MATCH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_FILTER_LOCAL_MATCH) || \
    false)

static inline void trace_sunhme_rx_filter_local_match(void)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_FILTER_LOCAL_MATCH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 379 "../hw/net/trace-events"
            qemu_log("sunhme_rx_filter_local_match " "incoming frame matches local MAC address" "\n");
#line 6119 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_FILTER_BCAST_MATCH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_FILTER_BCAST_MATCH) || \
    false)

static inline void trace_sunhme_rx_filter_bcast_match(void)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_FILTER_BCAST_MATCH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 380 "../hw/net/trace-events"
            qemu_log("sunhme_rx_filter_bcast_match " "incoming frame matches broadcast MAC address" "\n");
#line 6134 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_FILTER_HASH_NOMATCH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_FILTER_HASH_NOMATCH) || \
    false)

static inline void trace_sunhme_rx_filter_hash_nomatch(void)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_FILTER_HASH_NOMATCH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 381 "../hw/net/trace-events"
            qemu_log("sunhme_rx_filter_hash_nomatch " "incoming MAC address not in hash table" "\n");
#line 6149 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_FILTER_HASH_MATCH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_FILTER_HASH_MATCH) || \
    false)

static inline void trace_sunhme_rx_filter_hash_match(void)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_FILTER_HASH_MATCH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 382 "../hw/net/trace-events"
            qemu_log("sunhme_rx_filter_hash_match " "incoming MAC address found in hash table" "\n");
#line 6164 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_FILTER_PROMISC_MATCH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_FILTER_PROMISC_MATCH) || \
    false)

static inline void trace_sunhme_rx_filter_promisc_match(void)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_FILTER_PROMISC_MATCH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 383 "../hw/net/trace-events"
            qemu_log("sunhme_rx_filter_promisc_match " "incoming frame accepted due to promiscuous mode" "\n");
#line 6179 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_FILTER_REJECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_FILTER_REJECT) || \
    false)

static inline void trace_sunhme_rx_filter_reject(void)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_FILTER_REJECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 384 "../hw/net/trace-events"
            qemu_log("sunhme_rx_filter_reject " "rejecting incoming frame" "\n");
#line 6194 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_FILTER_ACCEPT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_FILTER_ACCEPT) || \
    false)

static inline void trace_sunhme_rx_filter_accept(void)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_FILTER_ACCEPT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 385 "../hw/net/trace-events"
            qemu_log("sunhme_rx_filter_accept " "accepting incoming frame" "\n");
#line 6209 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_DESC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_DESC) || \
    false)

static inline void trace_sunhme_rx_desc(uint32_t addr, int offset, uint32_t status, int len, int cr, int nr)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_DESC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 386 "../hw/net/trace-events"
            qemu_log("sunhme_rx_desc " "addr 0x%"PRIx32"(+0x%x) status 0x%"PRIx32 " len %d (ring %d/%d)" "\n", addr, offset, status, len, cr, nr);
#line 6224 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_XSUM_CALC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_XSUM_CALC) || \
    false)

static inline void trace_sunhme_rx_xsum_calc(uint16_t xsum)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_XSUM_CALC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 387 "../hw/net/trace-events"
            qemu_log("sunhme_rx_xsum_calc " "calculated incoming xsum as 0x%x" "\n", xsum);
#line 6239 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_RX_NORXD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_RX_NORXD) || \
    false)

static inline void trace_sunhme_rx_norxd(void)
{
    if (trace_event_get_state(TRACE_SUNHME_RX_NORXD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 388 "../hw/net/trace-events"
            qemu_log("sunhme_rx_norxd " "no free rx descriptors available" "\n");
#line 6254 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_SUNHME_UPDATE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SUNHME_UPDATE_IRQ) || \
    false)

static inline void trace_sunhme_update_irq(uint32_t mifmask, uint32_t mif, uint32_t sebmask, uint32_t seb, int level)
{
    if (trace_event_get_state(TRACE_SUNHME_UPDATE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 389 "../hw/net/trace-events"
            qemu_log("sunhme_update_irq " "mifmask: 0x%x  mif: 0x%x  sebmask: 0x%x  seb: 0x%x  level: %d" "\n", mifmask, mif, sebmask, seb, level);
#line 6269 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_VIRTIO_NET_ANNOUNCE_NOTIFY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_NET_ANNOUNCE_NOTIFY) || \
    false)

static inline void trace_virtio_net_announce_notify(void)
{
    if (trace_event_get_state(TRACE_VIRTIO_NET_ANNOUNCE_NOTIFY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 392 "../hw/net/trace-events"
            qemu_log("virtio_net_announce_notify " "" "\n");
#line 6284 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_VIRTIO_NET_ANNOUNCE_TIMER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_NET_ANNOUNCE_TIMER) || \
    false)

static inline void trace_virtio_net_announce_timer(int round)
{
    if (trace_event_get_state(TRACE_VIRTIO_NET_ANNOUNCE_TIMER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 393 "../hw/net/trace-events"
            qemu_log("virtio_net_announce_timer " "%d" "\n", round);
#line 6299 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_VIRTIO_NET_HANDLE_ANNOUNCE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_NET_HANDLE_ANNOUNCE) || \
    false)

static inline void trace_virtio_net_handle_announce(int round)
{
    if (trace_event_get_state(TRACE_VIRTIO_NET_HANDLE_ANNOUNCE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 394 "../hw/net/trace-events"
            qemu_log("virtio_net_handle_announce " "%d" "\n", round);
#line 6314 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_VIRTIO_NET_POST_LOAD_DEVICE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_NET_POST_LOAD_DEVICE) || \
    false)

static inline void trace_virtio_net_post_load_device(void)
{
    if (trace_event_get_state(TRACE_VIRTIO_NET_POST_LOAD_DEVICE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 395 "../hw/net/trace-events"
            qemu_log("virtio_net_post_load_device "  "\n");
#line 6329 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_VIRTIO_NET_RSS_LOAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_NET_RSS_LOAD) || \
    false)

static inline void trace_virtio_net_rss_load(void *nic, size_t nfds, void *fds)
{
    if (trace_event_get_state(TRACE_VIRTIO_NET_RSS_LOAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 396 "../hw/net/trace-events"
            qemu_log("virtio_net_rss_load " "nic=%p nfds=%zu fds=%p" "\n", nic, nfds, fds);
#line 6344 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_VIRTIO_NET_RSS_ATTACH_EBPF_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_NET_RSS_ATTACH_EBPF) || \
    false)

static inline void trace_virtio_net_rss_attach_ebpf(void *nic, int prog_fd)
{
    if (trace_event_get_state(TRACE_VIRTIO_NET_RSS_ATTACH_EBPF)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 397 "../hw/net/trace-events"
            qemu_log("virtio_net_rss_attach_ebpf " "nic=%p prog-fd=%d" "\n", nic, prog_fd);
#line 6359 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_VIRTIO_NET_RSS_DISABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_NET_RSS_DISABLE) || \
    false)

static inline void trace_virtio_net_rss_disable(void *nic)
{
    if (trace_event_get_state(TRACE_VIRTIO_NET_RSS_DISABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 398 "../hw/net/trace-events"
            qemu_log("virtio_net_rss_disable " "nic=%p" "\n", nic);
#line 6374 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_VIRTIO_NET_RSS_ERROR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_NET_RSS_ERROR) || \
    false)

static inline void trace_virtio_net_rss_error(void *nic, const char *msg, uint32_t value)
{
    if (trace_event_get_state(TRACE_VIRTIO_NET_RSS_ERROR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 399 "../hw/net/trace-events"
            qemu_log("virtio_net_rss_error " "nic=%p msg=%s, value 0x%08x" "\n", nic, msg, value);
#line 6389 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_VIRTIO_NET_RSS_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_NET_RSS_ENABLE) || \
    false)

static inline void trace_virtio_net_rss_enable(void *nic, uint32_t p1, uint16_t p2, uint8_t p3)
{
    if (trace_event_get_state(TRACE_VIRTIO_NET_RSS_ENABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 400 "../hw/net/trace-events"
            qemu_log("virtio_net_rss_enable " "nic=%p hashes 0x%x, table of %d, key of %d" "\n", nic, p1, p2, p3);
#line 6404 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_REG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_REG_WRITE) || \
    false)

static inline void trace_tulip_reg_write(uint64_t addr, const char *name, int size, uint64_t val)
{
    if (trace_event_get_state(TRACE_TULIP_REG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 403 "../hw/net/trace-events"
            qemu_log("tulip_reg_write " "addr 0x%02"PRIx64" (%s) size %d value 0x%08"PRIx64 "\n", addr, name, size, val);
#line 6419 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_REG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_REG_READ) || \
    false)

static inline void trace_tulip_reg_read(uint64_t addr, const char *name, int size, uint64_t val)
{
    if (trace_event_get_state(TRACE_TULIP_REG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 404 "../hw/net/trace-events"
            qemu_log("tulip_reg_read " "addr 0x%02"PRIx64" (%s) size %d value 0x%08"PRIx64 "\n", addr, name, size, val);
#line 6434 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_RECEIVE) || \
    false)

static inline void trace_tulip_receive(const uint8_t *buf, size_t len)
{
    if (trace_event_get_state(TRACE_TULIP_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 405 "../hw/net/trace-events"
            qemu_log("tulip_receive " "buf %p size %zu" "\n", buf, len);
#line 6449 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_DESCRIPTOR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_DESCRIPTOR) || \
    false)

static inline void trace_tulip_descriptor(const char *prefix, uint32_t addr, uint32_t status, uint32_t control, uint32_t len1, uint32_t len2, uint32_t buf1, uint32_t buf2)
{
    if (trace_event_get_state(TRACE_TULIP_DESCRIPTOR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 406 "../hw/net/trace-events"
            qemu_log("tulip_descriptor " "%s 0x%08x: status 0x%08x control 0x%03x len1 %4d len2 %4d buf1 0x%08x buf2 0x%08x" "\n", prefix, addr, status, control, len1, len2, buf1, buf2);
#line 6464 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_RX_STATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_RX_STATE) || \
    false)

static inline void trace_tulip_rx_state(const char *state)
{
    if (trace_event_get_state(TRACE_TULIP_RX_STATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 407 "../hw/net/trace-events"
            qemu_log("tulip_rx_state " "RX %s" "\n", state);
#line 6479 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_TX_STATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_TX_STATE) || \
    false)

static inline void trace_tulip_tx_state(const char *state)
{
    if (trace_event_get_state(TRACE_TULIP_TX_STATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 408 "../hw/net/trace-events"
            qemu_log("tulip_tx_state " "TX %s" "\n", state);
#line 6494 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_IRQ) || \
    false)

static inline void trace_tulip_irq(uint32_t mask, uint32_t en, const char *state)
{
    if (trace_event_get_state(TRACE_TULIP_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 409 "../hw/net/trace-events"
            qemu_log("tulip_irq " "mask 0x%08x ie 0x%08x %s" "\n", mask, en, state);
#line 6509 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_MII_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_MII_WRITE) || \
    false)

static inline void trace_tulip_mii_write(int phy, int reg, uint16_t data)
{
    if (trace_event_get_state(TRACE_TULIP_MII_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 410 "../hw/net/trace-events"
            qemu_log("tulip_mii_write " "phy 0x%x reg 0x%x data 0x%04x" "\n", phy, reg, data);
#line 6524 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_MII_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_MII_READ) || \
    false)

static inline void trace_tulip_mii_read(int phy, int reg, uint16_t data)
{
    if (trace_event_get_state(TRACE_TULIP_MII_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 411 "../hw/net/trace-events"
            qemu_log("tulip_mii_read " "phy 0x%x, reg 0x%x data 0x%04x" "\n", phy, reg, data);
#line 6539 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_RESET) || \
    false)

static inline void trace_tulip_reset(void)
{
    if (trace_event_get_state(TRACE_TULIP_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 412 "../hw/net/trace-events"
            qemu_log("tulip_reset " "" "\n");
#line 6554 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_SETUP_FRAME_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_SETUP_FRAME) || \
    false)

static inline void trace_tulip_setup_frame(void)
{
    if (trace_event_get_state(TRACE_TULIP_SETUP_FRAME)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 413 "../hw/net/trace-events"
            qemu_log("tulip_setup_frame " "" "\n");
#line 6569 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_TULIP_SETUP_FILTER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TULIP_SETUP_FILTER) || \
    false)

static inline void trace_tulip_setup_filter(int n, uint8_t a, uint8_t b, uint8_t c, uint8_t d, uint8_t e, uint8_t f)
{
    if (trace_event_get_state(TRACE_TULIP_SETUP_FILTER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 414 "../hw/net/trace-events"
            qemu_log("tulip_setup_filter " "%d: %02x:%02x:%02x:%02x:%02x:%02x" "\n", n, a, b, c, d, e, f);
#line 6584 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_LASI_82596_MEM_READW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LASI_82596_MEM_READW) || \
    false)

static inline void trace_lasi_82596_mem_readw(uint64_t addr, uint32_t ret)
{
    if (trace_event_get_state(TRACE_LASI_82596_MEM_READW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 417 "../hw/net/trace-events"
            qemu_log("lasi_82596_mem_readw " "addr=0x%"PRIx64" val=0x%04x" "\n", addr, ret);
#line 6599 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_LASI_82596_MEM_WRITEW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_LASI_82596_MEM_WRITEW) || \
    false)

static inline void trace_lasi_82596_mem_writew(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_LASI_82596_MEM_WRITEW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 418 "../hw/net/trace-events"
            qemu_log("lasi_82596_mem_writew " "addr=0x%"PRIx64" val=0x%04x" "\n", addr, val);
#line 6614 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_S_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_S_RESET) || \
    false)

static inline void trace_i82596_s_reset(void *s)
{
    if (trace_event_get_state(TRACE_I82596_S_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 421 "../hw/net/trace-events"
            qemu_log("i82596_s_reset " "%p Reset chip" "\n", s);
#line 6629 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_TRANSMIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_TRANSMIT) || \
    false)

static inline void trace_i82596_transmit(uint32_t size, uint32_t addr)
{
    if (trace_event_get_state(TRACE_I82596_TRANSMIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 422 "../hw/net/trace-events"
            qemu_log("i82596_transmit " "size %u from addr 0x%04x" "\n", size, addr);
#line 6644 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RECEIVE_ANALYSIS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RECEIVE_ANALYSIS) || \
    false)

static inline void trace_i82596_receive_analysis(const char *s)
{
    if (trace_event_get_state(TRACE_I82596_RECEIVE_ANALYSIS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 423 "../hw/net/trace-events"
            qemu_log("i82596_receive_analysis " "%s" "\n", s);
#line 6659 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RECEIVE_QUEUE_FULL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RECEIVE_QUEUE_FULL) || \
    false)

static inline void trace_i82596_receive_queue_full(void)
{
    if (trace_event_get_state(TRACE_I82596_RECEIVE_QUEUE_FULL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 424 "../hw/net/trace-events"
            qemu_log("i82596_receive_queue_full " "Packet queue full, dropping packet" "\n");
#line 6674 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RECEIVE_SUSPENDED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RECEIVE_SUSPENDED) || \
    false)

static inline void trace_i82596_receive_suspended(void)
{
    if (trace_event_get_state(TRACE_I82596_RECEIVE_SUSPENDED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 425 "../hw/net/trace-events"
            qemu_log("i82596_receive_suspended " "RX unit suspended, queueing packet" "\n");
#line 6689 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RX_STATE_CHANGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RX_STATE_CHANGE) || \
    false)

static inline void trace_i82596_rx_state_change(uint8_t old_state, uint8_t new_state)
{
    if (trace_event_get_state(TRACE_I82596_RX_STATE_CHANGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 426 "../hw/net/trace-events"
            qemu_log("i82596_rx_state_change " "RX state changed from %d to %d" "\n", old_state, new_state);
#line 6704 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_NEW_MAC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_NEW_MAC) || \
    false)

static inline void trace_i82596_new_mac(const char *id_with_mac)
{
    if (trace_event_get_state(TRACE_I82596_NEW_MAC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 427 "../hw/net/trace-events"
            qemu_log("i82596_new_mac " "New MAC for: %s" "\n", id_with_mac);
#line 6719 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_SET_MULTICAST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_SET_MULTICAST) || \
    false)

static inline void trace_i82596_set_multicast(uint16_t count)
{
    if (trace_event_get_state(TRACE_I82596_SET_MULTICAST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 428 "../hw/net/trace-events"
            qemu_log("i82596_set_multicast " "Added %d multicast entries" "\n", count);
#line 6734 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_SCB_COMMAND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_SCB_COMMAND) || \
    false)

static inline void trace_i82596_scb_command(uint8_t cuc, uint8_t ruc)
{
    if (trace_event_get_state(TRACE_I82596_SCB_COMMAND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 429 "../hw/net/trace-events"
            qemu_log("i82596_scb_command " "SCB command CUC=0x%02x RUC=0x%02x" "\n", cuc, ruc);
#line 6749 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_DUMP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_DUMP) || \
    false)

static inline void trace_i82596_dump(uint32_t addr)
{
    if (trace_event_get_state(TRACE_I82596_DUMP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 430 "../hw/net/trace-events"
            qemu_log("i82596_dump " "Dump command to addr 0x%08x" "\n", addr);
#line 6764 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_FLUSH_QUEUE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_FLUSH_QUEUE) || \
    false)

static inline void trace_i82596_flush_queue(int count)
{
    if (trace_event_get_state(TRACE_I82596_FLUSH_QUEUE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 431 "../hw/net/trace-events"
            qemu_log("i82596_flush_queue " "Flushing %d packets from queue" "\n", count);
#line 6779 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_TX_TFD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_TX_TFD) || \
    false)

static inline void trace_i82596_tx_tfd(uint64_t addr, uint16_t status, uint16_t cmd, uint32_t link, uint32_t tbd)
{
    if (trace_event_get_state(TRACE_I82596_TX_TFD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 432 "../hw/net/trace-events"
            qemu_log("i82596_tx_tfd " "TFD @0x%"PRIx64": status=0x%04x cmd=0x%04x link=0x%08x tbd=0x%08x" "\n", addr, status, cmd, link, tbd);
#line 6794 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_TX_TBD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_TX_TBD) || \
    false)

static inline void trace_i82596_tx_tbd(uint64_t addr, uint16_t size, uint32_t buf)
{
    if (trace_event_get_state(TRACE_I82596_TX_TBD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 433 "../hw/net/trace-events"
            qemu_log("i82596_tx_tbd " "TBD @0x%"PRIx64": size=%d buf=0x%08x" "\n", addr, size, buf);
#line 6809 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RX_RFD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RX_RFD) || \
    false)

static inline void trace_i82596_rx_rfd(uint64_t addr, uint16_t status, uint16_t cmd, uint32_t link, uint32_t rbd)
{
    if (trace_event_get_state(TRACE_I82596_RX_RFD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 434 "../hw/net/trace-events"
            qemu_log("i82596_rx_rfd " "RFD @0x%"PRIx64": status=0x%04x cmd=0x%04x link=0x%08x rbd=0x%08x" "\n", addr, status, cmd, link, rbd);
#line 6824 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RX_RBD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RX_RBD) || \
    false)

static inline void trace_i82596_rx_rbd(uint64_t addr, uint16_t count, uint32_t buf, uint16_t size)
{
    if (trace_event_get_state(TRACE_I82596_RX_RBD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 435 "../hw/net/trace-events"
            qemu_log("i82596_rx_rbd " "RBD @0x%"PRIx64": count=%d buf=0x%08x size=%d" "\n", addr, count, buf, size);
#line 6839 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RECEIVE_PACKET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RECEIVE_PACKET) || \
    false)

static inline void trace_i82596_receive_packet(const uint8_t *buf, size_t size)
{
    if (trace_event_get_state(TRACE_I82596_RECEIVE_PACKET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 436 "../hw/net/trace-events"
            qemu_log("i82596_receive_packet " "RX packet %p size %zu" "\n", buf, size);
#line 6854 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RX_SHORT_FRAME_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RX_SHORT_FRAME) || \
    false)

static inline void trace_i82596_rx_short_frame(size_t size)
{
    if (trace_event_get_state(TRACE_I82596_RX_SHORT_FRAME)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 437 "../hw/net/trace-events"
            qemu_log("i82596_rx_short_frame " "RX: Frame too short (%zu bytes)" "\n", size);
#line 6869 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RX_RFD_UPDATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RX_RFD_UPDATE) || \
    false)

static inline void trace_i82596_rx_rfd_update(uint32_t addr, uint32_t next_rfd)
{
    if (trace_event_get_state(TRACE_I82596_RX_RFD_UPDATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 438 "../hw/net/trace-events"
            qemu_log("i82596_rx_rfd_update " "RX: Updating RFD 0x%08x to point to 0x%08x" "\n", addr, next_rfd);
#line 6884 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RX_OUT_OF_RBDS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RX_OUT_OF_RBDS) || \
    false)

static inline void trace_i82596_rx_out_of_rbds(void)
{
    if (trace_event_get_state(TRACE_I82596_RX_OUT_OF_RBDS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 439 "../hw/net/trace-events"
            qemu_log("i82596_rx_out_of_rbds " "RX: Out of RBDs mid-frame" "\n");
#line 6899 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RX_INCOMPLETE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RX_INCOMPLETE) || \
    false)

static inline void trace_i82596_rx_incomplete(size_t copied, size_t total)
{
    if (trace_event_get_state(TRACE_I82596_RX_INCOMPLETE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 440 "../hw/net/trace-events"
            qemu_log("i82596_rx_incomplete " "RX: Incomplete copy (%zu/%zu bytes)" "\n", copied, total);
#line 6914 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RX_COMPLETE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RX_COMPLETE) || \
    false)

static inline void trace_i82596_rx_complete(uint32_t crc, uint32_t align, uint32_t resource)
{
    if (trace_event_get_state(TRACE_I82596_RX_COMPLETE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 441 "../hw/net/trace-events"
            qemu_log("i82596_rx_complete " "RX: Complete (errors: CRC=%d align=%d res=%d)" "\n", crc, align, resource);
#line 6929 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_RECEIVE_IOV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_RECEIVE_IOV) || \
    false)

static inline void trace_i82596_receive_iov(size_t size, int iovcnt)
{
    if (trace_event_get_state(TRACE_I82596_RECEIVE_IOV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 442 "../hw/net/trace-events"
            qemu_log("i82596_receive_iov " "RX IOV: %zu bytes in %d vectors" "\n", size, iovcnt);
#line 6944 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_CA_INIT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_CA_INIT) || \
    false)

static inline void trace_i82596_ca_init(uint32_t scb, uint8_t mode, uint32_t base)
{
    if (trace_event_get_state(TRACE_I82596_CA_INIT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 443 "../hw/net/trace-events"
            qemu_log("i82596_ca_init " "CA: Init - SCB=0x%08x mode=%d base=0x%08x" "\n", scb, mode, base);
#line 6959 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_I82596_IOPORT_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I82596_IOPORT_WRITE) || \
    false)

static inline void trace_i82596_ioport_write(uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_I82596_IOPORT_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 444 "../hw/net/trace-events"
            qemu_log("i82596_ioport_write " "IO write addr=0x%08x val=0x%08x" "\n", addr, val);
#line 6974 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_PHY_READ_NUM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_PHY_READ_NUM) || \
    false)

static inline void trace_imx_phy_read_num(int phy, int configured)
{
    if (trace_event_get_state(TRACE_IMX_PHY_READ_NUM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 447 "../hw/net/trace-events"
            qemu_log("imx_phy_read_num " "read request from unconfigured phy %d (configured %d)" "\n", phy, configured);
#line 6989 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_PHY_WRITE_NUM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_PHY_WRITE_NUM) || \
    false)

static inline void trace_imx_phy_write_num(int phy, int configured)
{
    if (trace_event_get_state(TRACE_IMX_PHY_WRITE_NUM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 448 "../hw/net/trace-events"
            qemu_log("imx_phy_write_num " "write request to unconfigured phy %d (configured %d)" "\n", phy, configured);
#line 7004 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_FEC_READ_BD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_FEC_READ_BD) || \
    false)

static inline void trace_imx_fec_read_bd(uint64_t addr, int flags, int len, int data)
{
    if (trace_event_get_state(TRACE_IMX_FEC_READ_BD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 449 "../hw/net/trace-events"
            qemu_log("imx_fec_read_bd " "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" "\n", addr, flags, len, data);
#line 7019 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_ENET_READ_BD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_ENET_READ_BD) || \
    false)

static inline void trace_imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status)
{
    if (trace_event_get_state(TRACE_IMX_ENET_READ_BD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 450 "../hw/net/trace-events"
            qemu_log("imx_enet_read_bd " "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" "\n", addr, flags, len, data, options, status);
#line 7034 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_ETH_TX_BD_BUSY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_ETH_TX_BD_BUSY) || \
    false)

static inline void trace_imx_eth_tx_bd_busy(void)
{
    if (trace_event_get_state(TRACE_IMX_ETH_TX_BD_BUSY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 451 "../hw/net/trace-events"
            qemu_log("imx_eth_tx_bd_busy " "tx_bd ran out of descriptors to transmit" "\n");
#line 7049 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_ETH_RX_BD_FULL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_ETH_RX_BD_FULL) || \
    false)

static inline void trace_imx_eth_rx_bd_full(void)
{
    if (trace_event_get_state(TRACE_IMX_ETH_RX_BD_FULL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 452 "../hw/net/trace-events"
            qemu_log("imx_eth_rx_bd_full " "RX buffer is full" "\n");
#line 7064 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_ETH_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_ETH_READ) || \
    false)

static inline void trace_imx_eth_read(int reg, const char *reg_name, uint32_t value)
{
    if (trace_event_get_state(TRACE_IMX_ETH_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 453 "../hw/net/trace-events"
            qemu_log("imx_eth_read " "reg[%d:%s] => 0x%08"PRIx32 "\n", reg, reg_name, value);
#line 7079 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_ETH_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_ETH_WRITE) || \
    false)

static inline void trace_imx_eth_write(int reg, const char *reg_name, uint64_t value)
{
    if (trace_event_get_state(TRACE_IMX_ETH_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 454 "../hw/net/trace-events"
            qemu_log("imx_eth_write " "reg[%d:%s] <= 0x%08"PRIx64 "\n", reg, reg_name, value);
#line 7094 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_FEC_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_FEC_RECEIVE) || \
    false)

static inline void trace_imx_fec_receive(size_t size)
{
    if (trace_event_get_state(TRACE_IMX_FEC_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 455 "../hw/net/trace-events"
            qemu_log("imx_fec_receive " "len %zu" "\n", size);
#line 7109 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_FEC_RECEIVE_LEN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_FEC_RECEIVE_LEN) || \
    false)

static inline void trace_imx_fec_receive_len(uint64_t addr, int len)
{
    if (trace_event_get_state(TRACE_IMX_FEC_RECEIVE_LEN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 456 "../hw/net/trace-events"
            qemu_log("imx_fec_receive_len " "rx_bd 0x%"PRIx64" length %d" "\n", addr, len);
#line 7124 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_FEC_RECEIVE_LAST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_FEC_RECEIVE_LAST) || \
    false)

static inline void trace_imx_fec_receive_last(int last)
{
    if (trace_event_get_state(TRACE_IMX_FEC_RECEIVE_LAST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 457 "../hw/net/trace-events"
            qemu_log("imx_fec_receive_last " "rx frame flags 0x%04x" "\n", last);
#line 7139 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_ENET_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_ENET_RECEIVE) || \
    false)

static inline void trace_imx_enet_receive(size_t size)
{
    if (trace_event_get_state(TRACE_IMX_ENET_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 458 "../hw/net/trace-events"
            qemu_log("imx_enet_receive " "len %zu" "\n", size);
#line 7154 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_ENET_RECEIVE_LEN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_ENET_RECEIVE_LEN) || \
    false)

static inline void trace_imx_enet_receive_len(uint64_t addr, int len)
{
    if (trace_event_get_state(TRACE_IMX_ENET_RECEIVE_LEN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 459 "../hw/net/trace-events"
            qemu_log("imx_enet_receive_len " "rx_bd 0x%"PRIx64" length %d" "\n", addr, len);
#line 7169 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_IMX_ENET_RECEIVE_LAST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IMX_ENET_RECEIVE_LAST) || \
    false)

static inline void trace_imx_enet_receive_last(int last)
{
    if (trace_event_get_state(TRACE_IMX_ENET_RECEIVE_LAST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 460 "../hw/net/trace-events"
            qemu_log("imx_enet_receive_last " "rx frame flags 0x%04x" "\n", last);
#line 7184 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_RESET) || \
    false)

static inline void trace_npcm7xx_emc_reset(int emc_num)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 463 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_reset " "Resetting emc%d" "\n", emc_num);
#line 7199 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_UPDATE_TX_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_UPDATE_TX_IRQ) || \
    false)

static inline void trace_npcm7xx_emc_update_tx_irq(int level)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_UPDATE_TX_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 464 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_update_tx_irq " "Setting tx irq to %d" "\n", level);
#line 7214 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_UPDATE_RX_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_UPDATE_RX_IRQ) || \
    false)

static inline void trace_npcm7xx_emc_update_rx_irq(int level)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_UPDATE_RX_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 465 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_update_rx_irq " "Setting rx irq to %d" "\n", level);
#line 7229 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_SET_MISTA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_SET_MISTA) || \
    false)

static inline void trace_npcm7xx_emc_set_mista(uint32_t flags)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_SET_MISTA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 466 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_set_mista " "ORing 0x%x into MISTA" "\n", flags);
#line 7244 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_CPU_OWNED_DESC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_CPU_OWNED_DESC) || \
    false)

static inline void trace_npcm7xx_emc_cpu_owned_desc(uint32_t addr)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_CPU_OWNED_DESC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 467 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_cpu_owned_desc " "Can't process cpu-owned descriptor @0x%x" "\n", addr);
#line 7259 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_SENT_PACKET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_SENT_PACKET) || \
    false)

static inline void trace_npcm7xx_emc_sent_packet(uint32_t len)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_SENT_PACKET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 468 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_sent_packet " "Sent %u byte packet" "\n", len);
#line 7274 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_TX_DONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_TX_DONE) || \
    false)

static inline void trace_npcm7xx_emc_tx_done(uint32_t ctxdsa)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_TX_DONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 469 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_tx_done " "TX done, CTXDSA=0x%x" "\n", ctxdsa);
#line 7289 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_CAN_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_CAN_RECEIVE) || \
    false)

static inline void trace_npcm7xx_emc_can_receive(int can_receive)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_CAN_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 470 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_can_receive " "Can receive: %d" "\n", can_receive);
#line 7304 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_PACKET_FILTERED_OUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_PACKET_FILTERED_OUT) || \
    false)

static inline void trace_npcm7xx_emc_packet_filtered_out(const char*fail_reason)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_PACKET_FILTERED_OUT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 471 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_packet_filtered_out " "Packet filtered out: %s" "\n", fail_reason);
#line 7319 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_PACKET_DROPPED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_PACKET_DROPPED) || \
    false)

static inline void trace_npcm7xx_emc_packet_dropped(uint32_t len)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_PACKET_DROPPED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 472 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_packet_dropped " "%u byte packet dropped" "\n", len);
#line 7334 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_RECEIVING_PACKET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_RECEIVING_PACKET) || \
    false)

static inline void trace_npcm7xx_emc_receiving_packet(uint32_t len)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_RECEIVING_PACKET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 473 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_receiving_packet " "Receiving %u byte packet" "\n", len);
#line 7349 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_RECEIVED_PACKET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_RECEIVED_PACKET) || \
    false)

static inline void trace_npcm7xx_emc_received_packet(uint32_t len)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_RECEIVED_PACKET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 474 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_received_packet " "Received %u byte packet" "\n", len);
#line 7364 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_RX_DONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_RX_DONE) || \
    false)

static inline void trace_npcm7xx_emc_rx_done(uint32_t crxdsa)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_RX_DONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 475 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_rx_done " "RX done, CRXDSA=0x%x" "\n", crxdsa);
#line 7379 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_REG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_REG_READ) || \
    false)

static inline void trace_npcm7xx_emc_reg_read(int emc_num, uint32_t result, const char *name, int regno)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_REG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 476 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_reg_read " "emc%d: 0x%x = reg[%s/%d]" "\n", emc_num, result, name, regno);
#line 7394 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM7XX_EMC_REG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_EMC_REG_WRITE) || \
    false)

static inline void trace_npcm7xx_emc_reg_write(int emc_num, const char *name, int regno, uint32_t value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_EMC_REG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 477 "../hw/net/trace-events"
            qemu_log("npcm7xx_emc_reg_write " "emc%d: reg[%s/%d] = 0x%x" "\n", emc_num, name, regno, value);
#line 7409 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_REG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_REG_READ) || \
    false)

static inline void trace_npcm_gmac_reg_read(const char *name, uint64_t offset, uint32_t value)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_REG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 480 "../hw/net/trace-events"
            qemu_log("npcm_gmac_reg_read " "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx32 "\n", name, offset, value);
#line 7424 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_REG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_REG_WRITE) || \
    false)

static inline void trace_npcm_gmac_reg_write(const char *name, uint64_t offset, uint32_t value)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_REG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 481 "../hw/net/trace-events"
            qemu_log("npcm_gmac_reg_write " "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx32 "\n", name, offset, value);
#line 7439 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_MDIO_ACCESS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_MDIO_ACCESS) || \
    false)

static inline void trace_npcm_gmac_mdio_access(const char *name, uint8_t is_write, uint8_t pa, uint8_t gr, uint16_t val)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_MDIO_ACCESS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 482 "../hw/net/trace-events"
            qemu_log("npcm_gmac_mdio_access " "%s: is_write: %" PRIu8 " pa: %" PRIu8 " gr: %" PRIu8 " val: 0x%04" PRIx16 "\n", name, is_write, pa, gr, val);
#line 7454 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_RESET) || \
    false)

static inline void trace_npcm_gmac_reset(const char *name, uint16_t value)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 483 "../hw/net/trace-events"
            qemu_log("npcm_gmac_reset " "%s: phy_regs[0][1]: 0x%04" PRIx16 "\n", name, value);
#line 7469 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_SET_LINK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_SET_LINK) || \
    false)

static inline void trace_npcm_gmac_set_link(bool active)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_SET_LINK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 484 "../hw/net/trace-events"
            qemu_log("npcm_gmac_set_link " "Set link: active=%u" "\n", active);
#line 7484 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_UPDATE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_UPDATE_IRQ) || \
    false)

static inline void trace_npcm_gmac_update_irq(const char *name, uint32_t status, uint32_t intr_en, int level)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_UPDATE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 485 "../hw/net/trace-events"
            qemu_log("npcm_gmac_update_irq " "%s: Status Reg: 0x%04" PRIX32 " Interrupt Enable Reg: 0x%04" PRIX32 " IRQ Set: %d" "\n", name, status, intr_en, level);
#line 7499 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_PACKET_DESC_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_PACKET_DESC_READ) || \
    false)

static inline void trace_npcm_gmac_packet_desc_read(const char*name, uint32_t desc_addr)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_PACKET_DESC_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 486 "../hw/net/trace-events"
            qemu_log("npcm_gmac_packet_desc_read " "%s: attempting to read descriptor @0x%04" PRIX32 "\n", name, desc_addr);
#line 7514 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_PACKET_RECEIVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_PACKET_RECEIVE) || \
    false)

static inline void trace_npcm_gmac_packet_receive(const char*name, uint32_t len)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_PACKET_RECEIVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 487 "../hw/net/trace-events"
            qemu_log("npcm_gmac_packet_receive " "%s: RX packet length: 0x%04" PRIX32 "\n", name, len);
#line 7529 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_PACKET_RECEIVING_BUFFER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_PACKET_RECEIVING_BUFFER) || \
    false)

static inline void trace_npcm_gmac_packet_receiving_buffer(const char*name, uint32_t buf_len, uint32_t rx_buf_addr)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_PACKET_RECEIVING_BUFFER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 488 "../hw/net/trace-events"
            qemu_log("npcm_gmac_packet_receiving_buffer " "%s: Receiving into Buffer size: 0x%04" PRIX32 " at address 0x%04" PRIX32 "\n", name, buf_len, rx_buf_addr);
#line 7544 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_PACKET_RECEIVED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_PACKET_RECEIVED) || \
    false)

static inline void trace_npcm_gmac_packet_received(const char*name, uint32_t len)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_PACKET_RECEIVED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 489 "../hw/net/trace-events"
            qemu_log("npcm_gmac_packet_received " "%s: Reception finished, packet left: 0x%04" PRIX32 "\n", name, len);
#line 7559 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_PACKET_SENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_PACKET_SENT) || \
    false)

static inline void trace_npcm_gmac_packet_sent(const char*name, uint16_t len)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_PACKET_SENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 490 "../hw/net/trace-events"
            qemu_log("npcm_gmac_packet_sent " "%s: TX packet sent!, length: 0x%04" PRIX16 "\n", name, len);
#line 7574 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_DEBUG_DESC_DATA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_DEBUG_DESC_DATA) || \
    false)

static inline void trace_npcm_gmac_debug_desc_data(const char*name, void*addr, uint32_t des0, uint32_t des1, uint32_t des2, uint32_t des3)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_DEBUG_DESC_DATA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 491 "../hw/net/trace-events"
            qemu_log("npcm_gmac_debug_desc_data " "%s: Address: %p Descriptor 0: 0x%04" PRIX32 " Descriptor 1: 0x%04" PRIX32 "Descriptor 2: 0x%04" PRIX32 " Descriptor 3: 0x%04" PRIX32 "\n", name, addr, des0, des1, des2, des3);
#line 7589 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_PACKET_TX_DESC_DATA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_PACKET_TX_DESC_DATA) || \
    false)

static inline void trace_npcm_gmac_packet_tx_desc_data(const char*name, uint32_t tdes0, uint32_t tdes1)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_PACKET_TX_DESC_DATA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 492 "../hw/net/trace-events"
            qemu_log("npcm_gmac_packet_tx_desc_data " "%s: Tdes0: 0x%04" PRIX32 " Tdes1: 0x%04" PRIX32 "\n", name, tdes0, tdes1);
#line 7604 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_GMAC_TX_DESC_OWNER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_GMAC_TX_DESC_OWNER) || \
    false)

static inline void trace_npcm_gmac_tx_desc_owner(const char*name, uint32_t desc_addr)
{
    if (trace_event_get_state(TRACE_NPCM_GMAC_TX_DESC_OWNER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 493 "../hw/net/trace-events"
            qemu_log("npcm_gmac_tx_desc_owner " "%s: TX Descriptor @0x%04" PRIX32 " is owned by software" "\n", name, desc_addr);
#line 7619 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_PCS_REG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_PCS_REG_READ) || \
    false)

static inline void trace_npcm_pcs_reg_read(const char *name, uint16_t indirect_access_base, uint64_t offset, uint16_t value)
{
    if (trace_event_get_state(TRACE_NPCM_PCS_REG_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 496 "../hw/net/trace-events"
            qemu_log("npcm_pcs_reg_read " "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 "\n", name, indirect_access_base, offset, value);
#line 7634 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_NPCM_PCS_REG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM_PCS_REG_WRITE) || \
    false)

static inline void trace_npcm_pcs_reg_write(const char *name, uint16_t indirect_access_base, uint64_t offset, uint16_t value)
{
    if (trace_event_get_state(TRACE_NPCM_PCS_REG_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 497 "../hw/net/trace-events"
            qemu_log("npcm_pcs_reg_write " "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 "\n", name, indirect_access_base, offset, value);
#line 7649 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_RAISE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_RAISE_IRQ) || \
    false)

static inline void trace_dp8393x_raise_irq(int isr)
{
    if (trace_event_get_state(TRACE_DP8393X_RAISE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 500 "../hw/net/trace-events"
            qemu_log("dp8393x_raise_irq " "raise irq, isr is 0x%04x" "\n", isr);
#line 7664 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_LOWER_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_LOWER_IRQ) || \
    false)

static inline void trace_dp8393x_lower_irq(void)
{
    if (trace_event_get_state(TRACE_DP8393X_LOWER_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 501 "../hw/net/trace-events"
            qemu_log("dp8393x_lower_irq " "lower irq" "\n");
#line 7679 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_LOAD_CAM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_LOAD_CAM) || \
    false)

static inline void trace_dp8393x_load_cam(int idx, int cam0, int cam1, int cam2, int cam3, int cam4, int cam5)
{
    if (trace_event_get_state(TRACE_DP8393X_LOAD_CAM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 502 "../hw/net/trace-events"
            qemu_log("dp8393x_load_cam " "load cam[%d] with 0x%02x0x%02x0x%02x0x%02x0x%02x0x%02x" "\n", idx, cam0, cam1, cam2, cam3, cam4, cam5);
#line 7694 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_LOAD_CAM_DONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_LOAD_CAM_DONE) || \
    false)

static inline void trace_dp8393x_load_cam_done(int cen)
{
    if (trace_event_get_state(TRACE_DP8393X_LOAD_CAM_DONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 503 "../hw/net/trace-events"
            qemu_log("dp8393x_load_cam_done " "load cam done. cam enable mask 0x%04x" "\n", cen);
#line 7709 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_READ_RRA_REGS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_READ_RRA_REGS) || \
    false)

static inline void trace_dp8393x_read_rra_regs(int crba0, int crba1, int rbwc0, int rbwc1)
{
    if (trace_event_get_state(TRACE_DP8393X_READ_RRA_REGS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 504 "../hw/net/trace-events"
            qemu_log("dp8393x_read_rra_regs " "CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x" "\n", crba0, crba1, rbwc0, rbwc1);
#line 7724 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_TRANSMIT_PACKET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_TRANSMIT_PACKET) || \
    false)

static inline void trace_dp8393x_transmit_packet(int ttda)
{
    if (trace_event_get_state(TRACE_DP8393X_TRANSMIT_PACKET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 505 "../hw/net/trace-events"
            qemu_log("dp8393x_transmit_packet " "Transmit packet at 0x%"PRIx32 "\n", ttda);
#line 7739 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_TRANSMIT_TXLEN_ERROR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_TRANSMIT_TXLEN_ERROR) || \
    false)

static inline void trace_dp8393x_transmit_txlen_error(int len)
{
    if (trace_event_get_state(TRACE_DP8393X_TRANSMIT_TXLEN_ERROR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 506 "../hw/net/trace-events"
            qemu_log("dp8393x_transmit_txlen_error " "tx_len is %d" "\n", len);
#line 7754 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_READ) || \
    false)

static inline void trace_dp8393x_read(int reg, const char *name, int val, int size)
{
    if (trace_event_get_state(TRACE_DP8393X_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 507 "../hw/net/trace-events"
            qemu_log("dp8393x_read " "reg=0x%x [%s] val=0x%04x size=%d" "\n", reg, name, val, size);
#line 7769 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_WRITE) || \
    false)

static inline void trace_dp8393x_write(int reg, const char *name, int val, int size)
{
    if (trace_event_get_state(TRACE_DP8393X_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 508 "../hw/net/trace-events"
            qemu_log("dp8393x_write " "reg=0x%x [%s] val=0x%04x size=%d" "\n", reg, name, val, size);
#line 7784 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_WRITE_INVALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_WRITE_INVALID) || \
    false)

static inline void trace_dp8393x_write_invalid(int reg)
{
    if (trace_event_get_state(TRACE_DP8393X_WRITE_INVALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 509 "../hw/net/trace-events"
            qemu_log("dp8393x_write_invalid " "writing to reg %d invalid" "\n", reg);
#line 7799 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_WRITE_INVALID_DCR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_WRITE_INVALID_DCR) || \
    false)

static inline void trace_dp8393x_write_invalid_dcr(const char *name)
{
    if (trace_event_get_state(TRACE_DP8393X_WRITE_INVALID_DCR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 510 "../hw/net/trace-events"
            qemu_log("dp8393x_write_invalid_dcr " "writing to %s invalid" "\n", name);
#line 7814 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_RECEIVE_OVERSIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_RECEIVE_OVERSIZE) || \
    false)

static inline void trace_dp8393x_receive_oversize(int size)
{
    if (trace_event_get_state(TRACE_DP8393X_RECEIVE_OVERSIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 511 "../hw/net/trace-events"
            qemu_log("dp8393x_receive_oversize " "oversize packet, pkt_size is %d" "\n", size);
#line 7829 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_RECEIVE_NOT_NETCARD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_RECEIVE_NOT_NETCARD) || \
    false)

static inline void trace_dp8393x_receive_not_netcard(void)
{
    if (trace_event_get_state(TRACE_DP8393X_RECEIVE_NOT_NETCARD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 512 "../hw/net/trace-events"
            qemu_log("dp8393x_receive_not_netcard " "packet not for netcard" "\n");
#line 7844 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_RECEIVE_PACKET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_RECEIVE_PACKET) || \
    false)

static inline void trace_dp8393x_receive_packet(int crba)
{
    if (trace_event_get_state(TRACE_DP8393X_RECEIVE_PACKET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 513 "../hw/net/trace-events"
            qemu_log("dp8393x_receive_packet " "Receive packet at 0x%"PRIx32 "\n", crba);
#line 7859 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_DP8393X_RECEIVE_WRITE_STATUS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DP8393X_RECEIVE_WRITE_STATUS) || \
    false)

static inline void trace_dp8393x_receive_write_status(int crba)
{
    if (trace_event_get_state(TRACE_DP8393X_RECEIVE_WRITE_STATUS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 514 "../hw/net/trace-events"
            qemu_log("dp8393x_receive_write_status " "Write status at 0x%"PRIx32 "\n", crba);
#line 7874 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_XEN_NETDEV_REALIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_NETDEV_REALIZE) || \
    false)

static inline void trace_xen_netdev_realize(int dev, const char *info, const char *peer)
{
    if (trace_event_get_state(TRACE_XEN_NETDEV_REALIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 517 "../hw/net/trace-events"
            qemu_log("xen_netdev_realize " "vif%u info '%s' peer '%s'" "\n", dev, info, peer);
#line 7889 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_XEN_NETDEV_UNREALIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_NETDEV_UNREALIZE) || \
    false)

static inline void trace_xen_netdev_unrealize(int dev)
{
    if (trace_event_get_state(TRACE_XEN_NETDEV_UNREALIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 518 "../hw/net/trace-events"
            qemu_log("xen_netdev_unrealize " "vif%u" "\n", dev);
#line 7904 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_XEN_NETDEV_CREATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_NETDEV_CREATE) || \
    false)

static inline void trace_xen_netdev_create(int dev)
{
    if (trace_event_get_state(TRACE_XEN_NETDEV_CREATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 519 "../hw/net/trace-events"
            qemu_log("xen_netdev_create " "vif%u" "\n", dev);
#line 7919 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_XEN_NETDEV_DESTROY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_NETDEV_DESTROY) || \
    false)

static inline void trace_xen_netdev_destroy(int dev)
{
    if (trace_event_get_state(TRACE_XEN_NETDEV_DESTROY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 520 "../hw/net/trace-events"
            qemu_log("xen_netdev_destroy " "vif%u" "\n", dev);
#line 7934 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_XEN_NETDEV_DISCONNECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_NETDEV_DISCONNECT) || \
    false)

static inline void trace_xen_netdev_disconnect(int dev)
{
    if (trace_event_get_state(TRACE_XEN_NETDEV_DISCONNECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 521 "../hw/net/trace-events"
            qemu_log("xen_netdev_disconnect " "vif%u" "\n", dev);
#line 7949 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_XEN_NETDEV_CONNECT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_NETDEV_CONNECT) || \
    false)

static inline void trace_xen_netdev_connect(int dev, unsigned int tx, unsigned int rx, int port)
{
    if (trace_event_get_state(TRACE_XEN_NETDEV_CONNECT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 522 "../hw/net/trace-events"
            qemu_log("xen_netdev_connect " "vif%u tx %u rx %u port %u" "\n", dev, tx, rx, port);
#line 7964 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_XEN_NETDEV_FRONTEND_CHANGED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_NETDEV_FRONTEND_CHANGED) || \
    false)

static inline void trace_xen_netdev_frontend_changed(const char *dev, int state)
{
    if (trace_event_get_state(TRACE_XEN_NETDEV_FRONTEND_CHANGED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 523 "../hw/net/trace-events"
            qemu_log("xen_netdev_frontend_changed " "vif%s state %d" "\n", dev, state);
#line 7979 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_XEN_NETDEV_TX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_NETDEV_TX) || \
    false)

static inline void trace_xen_netdev_tx(int dev, int ref, int off, int len, unsigned int flags, const char *c, const char *d, const char *m, const char *e)
{
    if (trace_event_get_state(TRACE_XEN_NETDEV_TX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 524 "../hw/net/trace-events"
            qemu_log("xen_netdev_tx " "vif%u ref %u off %u len %u flags 0x%x%s%s%s%s" "\n", dev, ref, off, len, flags, c, d, m, e);
#line 7994 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_XEN_NETDEV_RX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_XEN_NETDEV_RX) || \
    false)

static inline void trace_xen_netdev_rx(int dev, int idx, int status, int flags)
{
    if (trace_event_get_state(TRACE_XEN_NETDEV_RX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 525 "../hw/net/trace-events"
            qemu_log("xen_netdev_rx " "vif%u idx %d status %d flags 0x%x" "\n", dev, idx, status, flags);
#line 8009 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_ETHLITE_PKT_LOST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ETHLITE_PKT_LOST) || \
    false)

static inline void trace_ethlite_pkt_lost(uint32_t rx_ctrl)
{
    if (trace_event_get_state(TRACE_ETHLITE_PKT_LOST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 528 "../hw/net/trace-events"
            qemu_log("ethlite_pkt_lost " "rx_ctrl:0x%" PRIx32 "\n", rx_ctrl);
#line 8024 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_ETHLITE_PKT_SIZE_TOO_BIG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ETHLITE_PKT_SIZE_TOO_BIG) || \
    false)

static inline void trace_ethlite_pkt_size_too_big(uint64_t size)
{
    if (trace_event_get_state(TRACE_ETHLITE_PKT_SIZE_TOO_BIG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 529 "../hw/net/trace-events"
            qemu_log("ethlite_pkt_size_too_big " "size:0x%" PRIx64 "\n", size);
#line 8039 "trace/trace-hw_net.h"
        }
    }
}

#define TRACE_ETHLITE_PKT_TX_SIZE_TOO_BIG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ETHLITE_PKT_TX_SIZE_TOO_BIG) || \
    false)

static inline void trace_ethlite_pkt_tx_size_too_big(uint64_t size)
{
    if (trace_event_get_state(TRACE_ETHLITE_PKT_TX_SIZE_TOO_BIG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 530 "../hw/net/trace-events"
            qemu_log("ethlite_pkt_tx_size_too_big " "size:0x%" PRIx64 "\n", size);
#line 8054 "trace/trace-hw_net.h"
        }
    }
}
#endif /* TRACE_HW_NET_GENERATED_TRACERS_H */
