/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_NVME_GENERATED_TRACERS_H
#define TRACE_HW_NVME_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_PCI_NVME_IRQ_MSIX_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IRQ_PIN_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IRQ_MASKED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DMA_READ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DBBUF_CONFIG_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MAP_ADDR_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MAP_ADDR_CMB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MAP_PRP_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MAP_SGL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IO_CMD_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ADMIN_CMD_EVENT;
extern TraceEvent _TRACE_PCI_NVME_FLUSH_NS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_FORMAT_SET_EVENT;
extern TraceEvent _TRACE_PCI_NVME_READ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_WRITE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_RW_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MISC_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_RW_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_RW_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_RW_MDATA_IN_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_RW_MDATA_OUT_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_RW_CHECK_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC16_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC64_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_CHECK_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC16_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC64_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC16_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC64_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_APPTAG_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC16_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC64_EVENT;
extern TraceEvent _TRACE_PCI_NVME_COPY_EVENT;
extern TraceEvent _TRACE_PCI_NVME_COPY_SOURCE_RANGE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_COPY_OUT_EVENT;
extern TraceEvent _TRACE_PCI_NVME_VERIFY_EVENT;
extern TraceEvent _TRACE_PCI_NVME_VERIFY_MDATA_IN_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_VERIFY_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_RW_COMPLETE_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_BLOCK_STATUS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DSM_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DSM_DEALLOCATE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DSM_SINGLE_RANGE_LIMIT_EXCEEDED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_COMPARE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_COMPARE_DATA_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_COMPARE_MDATA_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_AIO_DISCARD_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_AIO_COPY_IN_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_AIO_FLUSH_CB_EVENT;
extern TraceEvent _TRACE_PCI_NVME_CREATE_SQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_CREATE_CQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DEL_SQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_DEL_CQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_CTRL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_CTRL_CSI_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_NS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_NS_IND_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_CTRL_LIST_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_PRI_CTRL_CAP_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_SEC_CTRL_LIST_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_NS_CSI_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_NSLIST_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_NSLIST_CSI_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_CMD_SET_EVENT;
extern TraceEvent _TRACE_PCI_NVME_IDENTIFY_NS_DESCR_LIST_EVENT;
extern TraceEvent _TRACE_PCI_NVME_GET_LOG_EVENT;
extern TraceEvent _TRACE_PCI_NVME_GETFEAT_EVENT;
extern TraceEvent _TRACE_PCI_NVME_SETFEAT_EVENT;
extern TraceEvent _TRACE_PCI_NVME_GETFEAT_VWCACHE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_GETFEAT_NUMQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_SETFEAT_NUMQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_SETFEAT_TIMESTAMP_EVENT;
extern TraceEvent _TRACE_PCI_NVME_GETFEAT_TIMESTAMP_EVENT;
extern TraceEvent _TRACE_PCI_NVME_PROCESS_AERS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_AER_EVENT;
extern TraceEvent _TRACE_PCI_NVME_AER_AERL_EXCEEDED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_AER_MASKED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_AER_POST_CQE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_NS_ATTACHMENT_EVENT;
extern TraceEvent _TRACE_PCI_NVME_NS_ATTACHMENT_ATTACH_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ENQUEUE_EVENT_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ENQUEUE_EVENT_NOQUEUE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ENQUEUE_EVENT_MASKED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_NO_OUTSTANDING_AERS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ENQUEUE_REQ_COMPLETION_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UPDATE_CQ_EVENTIDX_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UPDATE_SQ_EVENTIDX_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_READ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_WRITE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_DOORBELL_CQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_DOORBELL_SQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_INTM_SET_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_INTM_CLR_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_CFG_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_AQATTR_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_ASQADDR_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_ACQADDR_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_ASQADDR_HI_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_ACQADDR_HI_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_START_SUCCESS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_STOPPED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_SHUTDOWN_SET_EVENT;
extern TraceEvent _TRACE_PCI_NVME_MMIO_SHUTDOWN_CLEARED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UPDATE_CQ_HEAD_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UPDATE_SQ_TAIL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_OPEN_ZONE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_CLOSE_ZONE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_FINISH_ZONE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_RESET_ZONE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ZNS_ZONE_RESET_EVENT;
extern TraceEvent _TRACE_PCI_NVME_OFFLINE_ZONE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_SET_DESCRIPTOR_EXTENSION_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ZD_EXTENSION_SET_EVENT;
extern TraceEvent _TRACE_PCI_NVME_CLEAR_NS_CLOSE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_CLEAR_NS_RESET_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ZONED_ZRWA_IMPLICIT_FLUSH_EVENT;
extern TraceEvent _TRACE_PCI_NVME_PCI_RESET_EVENT;
extern TraceEvent _TRACE_PCI_NVME_VIRT_MNGMT_EVENT;
extern TraceEvent _TRACE_PCI_NVME_FDP_RUH_CHANGE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_MDTS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_ZASL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_REQ_STATUS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_ADDR_READ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_ADDR_WRITE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_CFS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_AIO_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_COPY_INVALID_FORMAT_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_SGLD_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_NUM_SGLD_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_SGL_EXCESS_LENGTH_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_DMA_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_PRPLIST_ENT_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_PRP2_ALIGN_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_OPC_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_ADMIN_OPC_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_LBA_RANGE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_OFFSET_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_CMB_INVALID_CBA_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_CMB_NOT_ENABLED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_UNALIGNED_ZONE_CMD_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_ZONE_STATE_TRANSITION_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_WRITE_NOT_AT_WP_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_APPEND_NOT_AT_START_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_ZONE_IS_FULL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_ZONE_IS_READ_ONLY_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_ZONE_IS_OFFLINE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_ZONE_BOUNDARY_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_ZONE_INVALID_WRITE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_ZONE_WRITE_NOT_OK_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_ZONE_READ_NOT_OK_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INSUFF_ACTIVE_RES_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INSUFF_OPEN_RES_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_ZD_EXTENSION_MAP_ERROR_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_IOCSCI_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_DEL_SQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_CQID_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SQID_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SIZE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_ADDR_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_QFLAGS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_CQID_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_NOTEMPTY_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_CQID_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_SIZE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ADDR_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_VECTOR_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_QFLAGS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ENTRY_SIZE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_IDENTIFY_CNS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_GETFEAT_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_SETFEAT_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_CQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_SQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_ASQ_MISALIGNED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_ACQ_MISALIGNED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_SMALL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_LARGE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_SMALL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_LARGE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_SMALL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_LARGE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_CSS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_ASQENT_SZ_ZERO_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_ACQENT_SZ_ZERO_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_ZASL_TOO_SMALL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_VIRT_STATE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_INVALID_MGMT_ACTION_EVENT;
extern TraceEvent _TRACE_PCI_NVME_ERR_IGNORED_MMIO_VF_OFFLINE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_MISALIGNED32_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_TOOSMALL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_INTMASK_WITH_MSIX_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_RO_CSTS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_SSRESET_W1C_UNSUPPORTED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_SSRESET_UNSUPPORTED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_CMBLOC_RESERVED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_CMBSZ_READONLY_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_PMRCAP_READONLY_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_PMRSTS_READONLY_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_PMREBS_READONLY_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_PMRSWTP_READONLY_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_INVALID_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIORD_MISALIGNED32_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIORD_TOOSMALL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_MMIORD_INVALID_OFS_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_DB_WR_MISALIGNED_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_DB_WR_INVALID_CQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_DB_WR_INVALID_CQHEAD_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_DB_WR_INVALID_SQ_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_DB_WR_INVALID_SQTAIL_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_UNKNOWN_CSS_VALUE_EVENT;
extern TraceEvent _TRACE_PCI_NVME_UB_TOO_MANY_MAPPINGS_EVENT;
extern uint16_t _TRACE_PCI_NVME_IRQ_MSIX_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IRQ_PIN_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IRQ_MASKED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DMA_READ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DBBUF_CONFIG_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MAP_ADDR_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MAP_ADDR_CMB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MAP_PRP_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MAP_SGL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IO_CMD_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ADMIN_CMD_DSTATE;
extern uint16_t _TRACE_PCI_NVME_FLUSH_NS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_FORMAT_SET_DSTATE;
extern uint16_t _TRACE_PCI_NVME_READ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_WRITE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_RW_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MISC_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_RW_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_RW_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_RW_MDATA_IN_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_RW_MDATA_OUT_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_RW_CHECK_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC16_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC64_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_CHECK_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC16_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC64_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC16_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC64_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_PRCHK_APPTAG_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC16_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC64_DSTATE;
extern uint16_t _TRACE_PCI_NVME_COPY_DSTATE;
extern uint16_t _TRACE_PCI_NVME_COPY_SOURCE_RANGE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_COPY_OUT_DSTATE;
extern uint16_t _TRACE_PCI_NVME_VERIFY_DSTATE;
extern uint16_t _TRACE_PCI_NVME_VERIFY_MDATA_IN_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_VERIFY_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_RW_COMPLETE_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_BLOCK_STATUS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DSM_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DSM_DEALLOCATE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DSM_SINGLE_RANGE_LIMIT_EXCEEDED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_COMPARE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_COMPARE_DATA_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_COMPARE_MDATA_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_AIO_DISCARD_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_AIO_COPY_IN_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_AIO_FLUSH_CB_DSTATE;
extern uint16_t _TRACE_PCI_NVME_CREATE_SQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_CREATE_CQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DEL_SQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_DEL_CQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_CTRL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_CTRL_CSI_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_NS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_NS_IND_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_CTRL_LIST_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_PRI_CTRL_CAP_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_SEC_CTRL_LIST_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_NS_CSI_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_NSLIST_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_NSLIST_CSI_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_CMD_SET_DSTATE;
extern uint16_t _TRACE_PCI_NVME_IDENTIFY_NS_DESCR_LIST_DSTATE;
extern uint16_t _TRACE_PCI_NVME_GET_LOG_DSTATE;
extern uint16_t _TRACE_PCI_NVME_GETFEAT_DSTATE;
extern uint16_t _TRACE_PCI_NVME_SETFEAT_DSTATE;
extern uint16_t _TRACE_PCI_NVME_GETFEAT_VWCACHE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_GETFEAT_NUMQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_SETFEAT_NUMQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_SETFEAT_TIMESTAMP_DSTATE;
extern uint16_t _TRACE_PCI_NVME_GETFEAT_TIMESTAMP_DSTATE;
extern uint16_t _TRACE_PCI_NVME_PROCESS_AERS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_AER_DSTATE;
extern uint16_t _TRACE_PCI_NVME_AER_AERL_EXCEEDED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_AER_MASKED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_AER_POST_CQE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_NS_ATTACHMENT_DSTATE;
extern uint16_t _TRACE_PCI_NVME_NS_ATTACHMENT_ATTACH_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ENQUEUE_EVENT_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ENQUEUE_EVENT_NOQUEUE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ENQUEUE_EVENT_MASKED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_NO_OUTSTANDING_AERS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ENQUEUE_REQ_COMPLETION_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UPDATE_CQ_EVENTIDX_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UPDATE_SQ_EVENTIDX_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_READ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_WRITE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_DOORBELL_CQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_DOORBELL_SQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_INTM_SET_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_INTM_CLR_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_CFG_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_AQATTR_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_ASQADDR_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_ACQADDR_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_ASQADDR_HI_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_ACQADDR_HI_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_START_SUCCESS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_STOPPED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_SHUTDOWN_SET_DSTATE;
extern uint16_t _TRACE_PCI_NVME_MMIO_SHUTDOWN_CLEARED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UPDATE_CQ_HEAD_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UPDATE_SQ_TAIL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_OPEN_ZONE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_CLOSE_ZONE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_FINISH_ZONE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_RESET_ZONE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ZNS_ZONE_RESET_DSTATE;
extern uint16_t _TRACE_PCI_NVME_OFFLINE_ZONE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_SET_DESCRIPTOR_EXTENSION_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ZD_EXTENSION_SET_DSTATE;
extern uint16_t _TRACE_PCI_NVME_CLEAR_NS_CLOSE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_CLEAR_NS_RESET_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ZONED_ZRWA_IMPLICIT_FLUSH_DSTATE;
extern uint16_t _TRACE_PCI_NVME_PCI_RESET_DSTATE;
extern uint16_t _TRACE_PCI_NVME_VIRT_MNGMT_DSTATE;
extern uint16_t _TRACE_PCI_NVME_FDP_RUH_CHANGE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_MDTS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_ZASL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_REQ_STATUS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_ADDR_READ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_ADDR_WRITE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_CFS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_AIO_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_COPY_INVALID_FORMAT_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_SGLD_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_NUM_SGLD_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_SGL_EXCESS_LENGTH_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_DMA_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_PRPLIST_ENT_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_PRP2_ALIGN_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_OPC_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_ADMIN_OPC_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_LBA_RANGE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_OFFSET_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_CMB_INVALID_CBA_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_CMB_NOT_ENABLED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_UNALIGNED_ZONE_CMD_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_ZONE_STATE_TRANSITION_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_WRITE_NOT_AT_WP_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_APPEND_NOT_AT_START_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_ZONE_IS_FULL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_ZONE_IS_READ_ONLY_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_ZONE_IS_OFFLINE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_ZONE_BOUNDARY_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_ZONE_INVALID_WRITE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_ZONE_WRITE_NOT_OK_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_ZONE_READ_NOT_OK_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INSUFF_ACTIVE_RES_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INSUFF_OPEN_RES_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_ZD_EXTENSION_MAP_ERROR_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_IOCSCI_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_DEL_SQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_CQID_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SQID_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SIZE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_ADDR_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_QFLAGS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_CQID_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_NOTEMPTY_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_CQID_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_SIZE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ADDR_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_VECTOR_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_QFLAGS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ENTRY_SIZE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_IDENTIFY_CNS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_GETFEAT_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_SETFEAT_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_CQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_SQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_ASQ_MISALIGNED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_ACQ_MISALIGNED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_SMALL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_LARGE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_SMALL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_LARGE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_SMALL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_LARGE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_CSS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_ASQENT_SZ_ZERO_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_ACQENT_SZ_ZERO_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_ZASL_TOO_SMALL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_VIRT_STATE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_INVALID_MGMT_ACTION_DSTATE;
extern uint16_t _TRACE_PCI_NVME_ERR_IGNORED_MMIO_VF_OFFLINE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_MISALIGNED32_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_TOOSMALL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_INTMASK_WITH_MSIX_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_RO_CSTS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_SSRESET_W1C_UNSUPPORTED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_SSRESET_UNSUPPORTED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_CMBLOC_RESERVED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_CMBSZ_READONLY_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_PMRCAP_READONLY_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_PMRSTS_READONLY_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_PMREBS_READONLY_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_PMRSWTP_READONLY_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIOWR_INVALID_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIORD_MISALIGNED32_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIORD_TOOSMALL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_MMIORD_INVALID_OFS_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_DB_WR_MISALIGNED_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_DB_WR_INVALID_CQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_DB_WR_INVALID_CQHEAD_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_DB_WR_INVALID_SQ_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_DB_WR_INVALID_SQTAIL_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_UNKNOWN_CSS_VALUE_DSTATE;
extern uint16_t _TRACE_PCI_NVME_UB_TOO_MANY_MAPPINGS_DSTATE;
#define TRACE_PCI_NVME_IRQ_MSIX_ENABLED 1
#define TRACE_PCI_NVME_IRQ_PIN_ENABLED 1
#define TRACE_PCI_NVME_IRQ_MASKED_ENABLED 1
#define TRACE_PCI_NVME_DMA_READ_ENABLED 1
#define TRACE_PCI_NVME_DBBUF_CONFIG_ENABLED 1
#define TRACE_PCI_NVME_MAP_ADDR_ENABLED 1
#define TRACE_PCI_NVME_MAP_ADDR_CMB_ENABLED 1
#define TRACE_PCI_NVME_MAP_PRP_ENABLED 1
#define TRACE_PCI_NVME_MAP_SGL_ENABLED 1
#define TRACE_PCI_NVME_IO_CMD_ENABLED 1
#define TRACE_PCI_NVME_ADMIN_CMD_ENABLED 1
#define TRACE_PCI_NVME_FLUSH_NS_ENABLED 1
#define TRACE_PCI_NVME_FORMAT_SET_ENABLED 1
#define TRACE_PCI_NVME_READ_ENABLED 1
#define TRACE_PCI_NVME_WRITE_ENABLED 1
#define TRACE_PCI_NVME_RW_CB_ENABLED 1
#define TRACE_PCI_NVME_MISC_CB_ENABLED 1
#define TRACE_PCI_NVME_DIF_RW_ENABLED 1
#define TRACE_PCI_NVME_DIF_RW_CB_ENABLED 1
#define TRACE_PCI_NVME_DIF_RW_MDATA_IN_CB_ENABLED 1
#define TRACE_PCI_NVME_DIF_RW_MDATA_OUT_CB_ENABLED 1
#define TRACE_PCI_NVME_DIF_RW_CHECK_CB_ENABLED 1
#define TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC16_ENABLED 1
#define TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC64_ENABLED 1
#define TRACE_PCI_NVME_DIF_CHECK_ENABLED 1
#define TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC16_ENABLED 1
#define TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC64_ENABLED 1
#define TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC16_ENABLED 1
#define TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC64_ENABLED 1
#define TRACE_PCI_NVME_DIF_PRCHK_APPTAG_ENABLED 1
#define TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC16_ENABLED 1
#define TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC64_ENABLED 1
#define TRACE_PCI_NVME_COPY_ENABLED 1
#define TRACE_PCI_NVME_COPY_SOURCE_RANGE_ENABLED 1
#define TRACE_PCI_NVME_COPY_OUT_ENABLED 1
#define TRACE_PCI_NVME_VERIFY_ENABLED 1
#define TRACE_PCI_NVME_VERIFY_MDATA_IN_CB_ENABLED 1
#define TRACE_PCI_NVME_VERIFY_CB_ENABLED 1
#define TRACE_PCI_NVME_RW_COMPLETE_CB_ENABLED 1
#define TRACE_PCI_NVME_BLOCK_STATUS_ENABLED 1
#define TRACE_PCI_NVME_DSM_ENABLED 1
#define TRACE_PCI_NVME_DSM_DEALLOCATE_ENABLED 1
#define TRACE_PCI_NVME_DSM_SINGLE_RANGE_LIMIT_EXCEEDED_ENABLED 1
#define TRACE_PCI_NVME_COMPARE_ENABLED 1
#define TRACE_PCI_NVME_COMPARE_DATA_CB_ENABLED 1
#define TRACE_PCI_NVME_COMPARE_MDATA_CB_ENABLED 1
#define TRACE_PCI_NVME_AIO_DISCARD_CB_ENABLED 1
#define TRACE_PCI_NVME_AIO_COPY_IN_CB_ENABLED 1
#define TRACE_PCI_NVME_AIO_FLUSH_CB_ENABLED 1
#define TRACE_PCI_NVME_CREATE_SQ_ENABLED 1
#define TRACE_PCI_NVME_CREATE_CQ_ENABLED 1
#define TRACE_PCI_NVME_DEL_SQ_ENABLED 1
#define TRACE_PCI_NVME_DEL_CQ_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_CTRL_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_CTRL_CSI_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_NS_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_NS_IND_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_CTRL_LIST_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_PRI_CTRL_CAP_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_SEC_CTRL_LIST_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_NS_CSI_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_NSLIST_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_NSLIST_CSI_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_CMD_SET_ENABLED 1
#define TRACE_PCI_NVME_IDENTIFY_NS_DESCR_LIST_ENABLED 1
#define TRACE_PCI_NVME_GET_LOG_ENABLED 1
#define TRACE_PCI_NVME_GETFEAT_ENABLED 1
#define TRACE_PCI_NVME_SETFEAT_ENABLED 1
#define TRACE_PCI_NVME_GETFEAT_VWCACHE_ENABLED 1
#define TRACE_PCI_NVME_GETFEAT_NUMQ_ENABLED 1
#define TRACE_PCI_NVME_SETFEAT_NUMQ_ENABLED 1
#define TRACE_PCI_NVME_SETFEAT_TIMESTAMP_ENABLED 1
#define TRACE_PCI_NVME_GETFEAT_TIMESTAMP_ENABLED 1
#define TRACE_PCI_NVME_PROCESS_AERS_ENABLED 1
#define TRACE_PCI_NVME_AER_ENABLED 1
#define TRACE_PCI_NVME_AER_AERL_EXCEEDED_ENABLED 1
#define TRACE_PCI_NVME_AER_MASKED_ENABLED 1
#define TRACE_PCI_NVME_AER_POST_CQE_ENABLED 1
#define TRACE_PCI_NVME_NS_ATTACHMENT_ENABLED 1
#define TRACE_PCI_NVME_NS_ATTACHMENT_ATTACH_ENABLED 1
#define TRACE_PCI_NVME_ENQUEUE_EVENT_ENABLED 1
#define TRACE_PCI_NVME_ENQUEUE_EVENT_NOQUEUE_ENABLED 1
#define TRACE_PCI_NVME_ENQUEUE_EVENT_MASKED_ENABLED 1
#define TRACE_PCI_NVME_NO_OUTSTANDING_AERS_ENABLED 1
#define TRACE_PCI_NVME_ENQUEUE_REQ_COMPLETION_ENABLED 1
#define TRACE_PCI_NVME_UPDATE_CQ_EVENTIDX_ENABLED 1
#define TRACE_PCI_NVME_UPDATE_SQ_EVENTIDX_ENABLED 1
#define TRACE_PCI_NVME_MMIO_READ_ENABLED 1
#define TRACE_PCI_NVME_MMIO_WRITE_ENABLED 1
#define TRACE_PCI_NVME_MMIO_DOORBELL_CQ_ENABLED 1
#define TRACE_PCI_NVME_MMIO_DOORBELL_SQ_ENABLED 1
#define TRACE_PCI_NVME_MMIO_INTM_SET_ENABLED 1
#define TRACE_PCI_NVME_MMIO_INTM_CLR_ENABLED 1
#define TRACE_PCI_NVME_MMIO_CFG_ENABLED 1
#define TRACE_PCI_NVME_MMIO_AQATTR_ENABLED 1
#define TRACE_PCI_NVME_MMIO_ASQADDR_ENABLED 1
#define TRACE_PCI_NVME_MMIO_ACQADDR_ENABLED 1
#define TRACE_PCI_NVME_MMIO_ASQADDR_HI_ENABLED 1
#define TRACE_PCI_NVME_MMIO_ACQADDR_HI_ENABLED 1
#define TRACE_PCI_NVME_MMIO_START_SUCCESS_ENABLED 1
#define TRACE_PCI_NVME_MMIO_STOPPED_ENABLED 1
#define TRACE_PCI_NVME_MMIO_SHUTDOWN_SET_ENABLED 1
#define TRACE_PCI_NVME_MMIO_SHUTDOWN_CLEARED_ENABLED 1
#define TRACE_PCI_NVME_UPDATE_CQ_HEAD_ENABLED 1
#define TRACE_PCI_NVME_UPDATE_SQ_TAIL_ENABLED 1
#define TRACE_PCI_NVME_OPEN_ZONE_ENABLED 1
#define TRACE_PCI_NVME_CLOSE_ZONE_ENABLED 1
#define TRACE_PCI_NVME_FINISH_ZONE_ENABLED 1
#define TRACE_PCI_NVME_RESET_ZONE_ENABLED 1
#define TRACE_PCI_NVME_ZNS_ZONE_RESET_ENABLED 1
#define TRACE_PCI_NVME_OFFLINE_ZONE_ENABLED 1
#define TRACE_PCI_NVME_SET_DESCRIPTOR_EXTENSION_ENABLED 1
#define TRACE_PCI_NVME_ZD_EXTENSION_SET_ENABLED 1
#define TRACE_PCI_NVME_CLEAR_NS_CLOSE_ENABLED 1
#define TRACE_PCI_NVME_CLEAR_NS_RESET_ENABLED 1
#define TRACE_PCI_NVME_ZONED_ZRWA_IMPLICIT_FLUSH_ENABLED 1
#define TRACE_PCI_NVME_PCI_RESET_ENABLED 1
#define TRACE_PCI_NVME_VIRT_MNGMT_ENABLED 1
#define TRACE_PCI_NVME_FDP_RUH_CHANGE_ENABLED 1
#define TRACE_PCI_NVME_ERR_MDTS_ENABLED 1
#define TRACE_PCI_NVME_ERR_ZASL_ENABLED 1
#define TRACE_PCI_NVME_ERR_REQ_STATUS_ENABLED 1
#define TRACE_PCI_NVME_ERR_ADDR_READ_ENABLED 1
#define TRACE_PCI_NVME_ERR_ADDR_WRITE_ENABLED 1
#define TRACE_PCI_NVME_ERR_CFS_ENABLED 1
#define TRACE_PCI_NVME_ERR_AIO_ENABLED 1
#define TRACE_PCI_NVME_ERR_COPY_INVALID_FORMAT_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_SGLD_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_NUM_SGLD_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_SGL_EXCESS_LENGTH_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_DMA_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_PRPLIST_ENT_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_PRP2_ALIGN_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_OPC_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_ADMIN_OPC_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_LBA_RANGE_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_OFFSET_ENABLED 1
#define TRACE_PCI_NVME_ERR_CMB_INVALID_CBA_ENABLED 1
#define TRACE_PCI_NVME_ERR_CMB_NOT_ENABLED_ENABLED 1
#define TRACE_PCI_NVME_ERR_UNALIGNED_ZONE_CMD_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_ZONE_STATE_TRANSITION_ENABLED 1
#define TRACE_PCI_NVME_ERR_WRITE_NOT_AT_WP_ENABLED 1
#define TRACE_PCI_NVME_ERR_APPEND_NOT_AT_START_ENABLED 1
#define TRACE_PCI_NVME_ERR_ZONE_IS_FULL_ENABLED 1
#define TRACE_PCI_NVME_ERR_ZONE_IS_READ_ONLY_ENABLED 1
#define TRACE_PCI_NVME_ERR_ZONE_IS_OFFLINE_ENABLED 1
#define TRACE_PCI_NVME_ERR_ZONE_BOUNDARY_ENABLED 1
#define TRACE_PCI_NVME_ERR_ZONE_INVALID_WRITE_ENABLED 1
#define TRACE_PCI_NVME_ERR_ZONE_WRITE_NOT_OK_ENABLED 1
#define TRACE_PCI_NVME_ERR_ZONE_READ_NOT_OK_ENABLED 1
#define TRACE_PCI_NVME_ERR_INSUFF_ACTIVE_RES_ENABLED 1
#define TRACE_PCI_NVME_ERR_INSUFF_OPEN_RES_ENABLED 1
#define TRACE_PCI_NVME_ERR_ZD_EXTENSION_MAP_ERROR_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_IOCSCI_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_DEL_SQ_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_CQID_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SQID_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SIZE_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_ADDR_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_QFLAGS_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_CQID_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_NOTEMPTY_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_CQID_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_SIZE_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ADDR_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_VECTOR_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_QFLAGS_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ENTRY_SIZE_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_IDENTIFY_CNS_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_GETFEAT_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_SETFEAT_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_CQ_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_SQ_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_ASQ_MISALIGNED_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_ACQ_MISALIGNED_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_SMALL_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_LARGE_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_SMALL_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_LARGE_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_SMALL_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_LARGE_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_CSS_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_ASQENT_SZ_ZERO_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_ACQENT_SZ_ZERO_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_ZASL_TOO_SMALL_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_ENABLED 1
#define TRACE_PCI_NVME_ERR_STARTFAIL_VIRT_STATE_ENABLED 1
#define TRACE_PCI_NVME_ERR_INVALID_MGMT_ACTION_ENABLED 1
#define TRACE_PCI_NVME_ERR_IGNORED_MMIO_VF_OFFLINE_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_MISALIGNED32_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_TOOSMALL_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_INTMASK_WITH_MSIX_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_RO_CSTS_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_SSRESET_W1C_UNSUPPORTED_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_SSRESET_UNSUPPORTED_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_CMBLOC_RESERVED_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_CMBSZ_READONLY_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_PMRCAP_READONLY_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_PMRSTS_READONLY_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_PMREBS_READONLY_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_PMRSWTP_READONLY_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIOWR_INVALID_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIORD_MISALIGNED32_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIORD_TOOSMALL_ENABLED 1
#define TRACE_PCI_NVME_UB_MMIORD_INVALID_OFS_ENABLED 1
#define TRACE_PCI_NVME_UB_DB_WR_MISALIGNED_ENABLED 1
#define TRACE_PCI_NVME_UB_DB_WR_INVALID_CQ_ENABLED 1
#define TRACE_PCI_NVME_UB_DB_WR_INVALID_CQHEAD_ENABLED 1
#define TRACE_PCI_NVME_UB_DB_WR_INVALID_SQ_ENABLED 1
#define TRACE_PCI_NVME_UB_DB_WR_INVALID_SQTAIL_ENABLED 1
#define TRACE_PCI_NVME_UB_UNKNOWN_CSS_VALUE_ENABLED 1
#define TRACE_PCI_NVME_UB_TOO_MANY_MAPPINGS_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_PCI_NVME_IRQ_MSIX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IRQ_MSIX) || \
    false)

static inline void trace_pci_nvme_irq_msix(uint32_t vector)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IRQ_MSIX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 2 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_irq_msix " "raising MSI-X IRQ vector %u" "\n", vector);
#line 665 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IRQ_PIN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IRQ_PIN) || \
    false)

static inline void trace_pci_nvme_irq_pin(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IRQ_PIN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 3 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_irq_pin " "pulsing IRQ pin" "\n");
#line 680 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IRQ_MASKED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IRQ_MASKED) || \
    false)

static inline void trace_pci_nvme_irq_masked(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IRQ_MASKED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 4 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_irq_masked " "IRQ is masked" "\n");
#line 695 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DMA_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DMA_READ) || \
    false)

static inline void trace_pci_nvme_dma_read(uint64_t prp1, uint64_t prp2)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DMA_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dma_read " "DMA read, prp1=0x%"PRIx64" prp2=0x%"PRIx64"" "\n", prp1, prp2);
#line 710 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DBBUF_CONFIG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DBBUF_CONFIG) || \
    false)

static inline void trace_pci_nvme_dbbuf_config(uint64_t dbs_addr, uint64_t eis_addr)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DBBUF_CONFIG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 6 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dbbuf_config " "dbs_addr=0x%"PRIx64" eis_addr=0x%"PRIx64"" "\n", dbs_addr, eis_addr);
#line 725 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MAP_ADDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MAP_ADDR) || \
    false)

static inline void trace_pci_nvme_map_addr(uint64_t addr, uint64_t len)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MAP_ADDR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 7 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_map_addr " "addr 0x%"PRIx64" len %"PRIu64"" "\n", addr, len);
#line 740 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MAP_ADDR_CMB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MAP_ADDR_CMB) || \
    false)

static inline void trace_pci_nvme_map_addr_cmb(uint64_t addr, uint64_t len)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MAP_ADDR_CMB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 8 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_map_addr_cmb " "addr 0x%"PRIx64" len %"PRIu64"" "\n", addr, len);
#line 755 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MAP_PRP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MAP_PRP) || \
    false)

static inline void trace_pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t prp2, int num_prps)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MAP_PRP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 9 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_map_prp " "trans_len %"PRIu64" len %"PRIu32" prp1 0x%"PRIx64" prp2 0x%"PRIx64" num_prps %d" "\n", trans_len, len, prp1, prp2, num_prps);
#line 770 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MAP_SGL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MAP_SGL) || \
    false)

static inline void trace_pci_nvme_map_sgl(uint8_t typ, uint64_t len)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MAP_SGL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 10 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_map_sgl " "type 0x%"PRIx8" len %"PRIu64"" "\n", typ, len);
#line 785 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IO_CMD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IO_CMD) || \
    false)

static inline void trace_pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode, const char *opname)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IO_CMD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 11 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_io_cmd " "cid %"PRIu16" nsid 0x%"PRIx32" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'" "\n", cid, nsid, sqid, opcode, opname);
#line 800 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ADMIN_CMD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ADMIN_CMD) || \
    false)

static inline void trace_pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char *opname)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ADMIN_CMD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 12 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_admin_cmd " "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'" "\n", cid, sqid, opcode, opname);
#line 815 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_FLUSH_NS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_FLUSH_NS) || \
    false)

static inline void trace_pci_nvme_flush_ns(uint32_t nsid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_FLUSH_NS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 13 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_flush_ns " "nsid 0x%"PRIx32"" "\n", nsid);
#line 830 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_FORMAT_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_FORMAT_SET) || \
    false)

static inline void trace_pci_nvme_format_set(uint32_t nsid, uint8_t lbaf, uint8_t mset, uint8_t pi, uint8_t pil)
{
    if (trace_event_get_state(TRACE_PCI_NVME_FORMAT_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_format_set " "nsid %"PRIu32" lbaf %"PRIu8" mset %"PRIu8" pi %"PRIu8" pil %"PRIu8"" "\n", nsid, lbaf, mset, pi, pil);
#line 845 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_READ) || \
    false)

static inline void trace_pci_nvme_read(uint16_t cid, uint32_t nsid, uint32_t nlb, uint64_t count, uint64_t lba)
{
    if (trace_event_get_state(TRACE_PCI_NVME_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_read " "cid %"PRIu16" nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64"" "\n", cid, nsid, nlb, count, lba);
#line 860 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_WRITE) || \
    false)

static inline void trace_pci_nvme_write(uint16_t cid, const char *verb, uint32_t nsid, uint32_t nlb, uint64_t count, uint64_t lba)
{
    if (trace_event_get_state(TRACE_PCI_NVME_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_write " "cid %"PRIu16" opname '%s' nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64"" "\n", cid, verb, nsid, nlb, count, lba);
#line 875 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_RW_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_RW_CB) || \
    false)

static inline void trace_pci_nvme_rw_cb(uint16_t cid, const char *blkname)
{
    if (trace_event_get_state(TRACE_PCI_NVME_RW_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 17 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_rw_cb " "cid %"PRIu16" blk '%s'" "\n", cid, blkname);
#line 890 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MISC_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MISC_CB) || \
    false)

static inline void trace_pci_nvme_misc_cb(uint16_t cid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MISC_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 18 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_misc_cb " "cid %"PRIu16"" "\n", cid);
#line 905 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_RW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_RW) || \
    false)

static inline void trace_pci_nvme_dif_rw(uint8_t pract, uint8_t prinfo)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_RW)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 19 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_rw " "pract 0x%"PRIx8" prinfo 0x%"PRIx8"" "\n", pract, prinfo);
#line 920 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_RW_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_RW_CB) || \
    false)

static inline void trace_pci_nvme_dif_rw_cb(uint16_t cid, const char *blkname)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_RW_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_rw_cb " "cid %"PRIu16" blk '%s'" "\n", cid, blkname);
#line 935 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_RW_MDATA_IN_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_RW_MDATA_IN_CB) || \
    false)

static inline void trace_pci_nvme_dif_rw_mdata_in_cb(uint16_t cid, const char *blkname)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_RW_MDATA_IN_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 21 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_rw_mdata_in_cb " "cid %"PRIu16" blk '%s'" "\n", cid, blkname);
#line 950 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_RW_MDATA_OUT_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_RW_MDATA_OUT_CB) || \
    false)

static inline void trace_pci_nvme_dif_rw_mdata_out_cb(uint16_t cid, const char *blkname)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_RW_MDATA_OUT_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 22 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_rw_mdata_out_cb " "cid %"PRIu16" blk '%s'" "\n", cid, blkname);
#line 965 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_RW_CHECK_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_RW_CHECK_CB) || \
    false)

static inline void trace_pci_nvme_dif_rw_check_cb(uint16_t cid, uint8_t prinfo, uint16_t apptag, uint16_t appmask, uint32_t reftag)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_RW_CHECK_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 23 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_rw_check_cb " "cid %"PRIu16" prinfo 0x%"PRIx8" apptag 0x%"PRIx16" appmask 0x%"PRIx16" reftag 0x%"PRIx32"" "\n", cid, prinfo, apptag, appmask, reftag);
#line 980 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC16_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC16) || \
    false)

static inline void trace_pci_nvme_dif_pract_generate_dif_crc16(size_t len, size_t lba_size, size_t chksum_len, uint16_t apptag, uint32_t reftag)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC16)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 24 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_pract_generate_dif_crc16 " "len %zu lba_size %zu chksum_len %zu apptag 0x%"PRIx16" reftag 0x%"PRIx32"" "\n", len, lba_size, chksum_len, apptag, reftag);
#line 995 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC64_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC64) || \
    false)

static inline void trace_pci_nvme_dif_pract_generate_dif_crc64(size_t len, size_t lba_size, size_t chksum_len, uint16_t apptag, uint64_t reftag)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC64)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 25 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_pract_generate_dif_crc64 " "len %zu lba_size %zu chksum_len %zu apptag 0x%"PRIx16" reftag 0x%"PRIx64"" "\n", len, lba_size, chksum_len, apptag, reftag);
#line 1010 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_CHECK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_CHECK) || \
    false)

static inline void trace_pci_nvme_dif_check(uint8_t prinfo, uint16_t chksum_len)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_CHECK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 26 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_check " "prinfo 0x%"PRIx8" chksum_len %"PRIu16"" "\n", prinfo, chksum_len);
#line 1025 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC16_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC16) || \
    false)

static inline void trace_pci_nvme_dif_prchk_disabled_crc16(uint16_t apptag, uint32_t reftag)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC16)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 27 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_prchk_disabled_crc16 " "apptag 0x%"PRIx16" reftag 0x%"PRIx32"" "\n", apptag, reftag);
#line 1040 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC64_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC64) || \
    false)

static inline void trace_pci_nvme_dif_prchk_disabled_crc64(uint16_t apptag, uint64_t reftag)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC64)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 28 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_prchk_disabled_crc64 " "apptag 0x%"PRIx16" reftag 0x%"PRIx64"" "\n", apptag, reftag);
#line 1055 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC16_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC16) || \
    false)

static inline void trace_pci_nvme_dif_prchk_guard_crc16(uint16_t guard, uint16_t crc)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC16)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 29 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_prchk_guard_crc16 " "guard 0x%"PRIx16" crc 0x%"PRIx16"" "\n", guard, crc);
#line 1070 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC64_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC64) || \
    false)

static inline void trace_pci_nvme_dif_prchk_guard_crc64(uint64_t guard, uint64_t crc)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC64)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 30 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_prchk_guard_crc64 " "guard 0x%"PRIx64" crc 0x%"PRIx64"" "\n", guard, crc);
#line 1085 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_PRCHK_APPTAG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_PRCHK_APPTAG) || \
    false)

static inline void trace_pci_nvme_dif_prchk_apptag(uint16_t apptag, uint16_t elbat, uint16_t elbatm)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_PRCHK_APPTAG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 31 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_prchk_apptag " "apptag 0x%"PRIx16" elbat 0x%"PRIx16" elbatm 0x%"PRIx16"" "\n", apptag, elbat, elbatm);
#line 1100 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC16_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC16) || \
    false)

static inline void trace_pci_nvme_dif_prchk_reftag_crc16(uint32_t reftag, uint32_t elbrt)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC16)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 32 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_prchk_reftag_crc16 " "reftag 0x%"PRIx32" elbrt 0x%"PRIx32"" "\n", reftag, elbrt);
#line 1115 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC64_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC64) || \
    false)

static inline void trace_pci_nvme_dif_prchk_reftag_crc64(uint64_t reftag, uint64_t elbrt)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC64)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 33 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dif_prchk_reftag_crc64 " "reftag 0x%"PRIx64" elbrt 0x%"PRIx64"" "\n", reftag, elbrt);
#line 1130 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_COPY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_COPY) || \
    false)

static inline void trace_pci_nvme_copy(uint16_t cid, uint32_t nsid, uint16_t nr, uint8_t format)
{
    if (trace_event_get_state(TRACE_PCI_NVME_COPY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 34 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_copy " "cid %"PRIu16" nsid %"PRIu32" nr %"PRIu16" format 0x%"PRIx8"" "\n", cid, nsid, nr, format);
#line 1145 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_COPY_SOURCE_RANGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_COPY_SOURCE_RANGE) || \
    false)

static inline void trace_pci_nvme_copy_source_range(uint64_t slba, uint32_t nlb)
{
    if (trace_event_get_state(TRACE_PCI_NVME_COPY_SOURCE_RANGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 35 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_copy_source_range " "slba 0x%"PRIx64" nlb %"PRIu32"" "\n", slba, nlb);
#line 1160 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_COPY_OUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_COPY_OUT) || \
    false)

static inline void trace_pci_nvme_copy_out(uint64_t slba, uint32_t nlb)
{
    if (trace_event_get_state(TRACE_PCI_NVME_COPY_OUT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 36 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_copy_out " "slba 0x%"PRIx64" nlb %"PRIu32"" "\n", slba, nlb);
#line 1175 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_VERIFY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_VERIFY) || \
    false)

static inline void trace_pci_nvme_verify(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb)
{
    if (trace_event_get_state(TRACE_PCI_NVME_VERIFY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 37 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_verify " "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32"" "\n", cid, nsid, slba, nlb);
#line 1190 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_VERIFY_MDATA_IN_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_VERIFY_MDATA_IN_CB) || \
    false)

static inline void trace_pci_nvme_verify_mdata_in_cb(uint16_t cid, const char *blkname)
{
    if (trace_event_get_state(TRACE_PCI_NVME_VERIFY_MDATA_IN_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 38 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_verify_mdata_in_cb " "cid %"PRIu16" blk '%s'" "\n", cid, blkname);
#line 1205 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_VERIFY_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_VERIFY_CB) || \
    false)

static inline void trace_pci_nvme_verify_cb(uint16_t cid, uint8_t prinfo, uint16_t apptag, uint16_t appmask, uint32_t reftag)
{
    if (trace_event_get_state(TRACE_PCI_NVME_VERIFY_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 39 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_verify_cb " "cid %"PRIu16" prinfo 0x%"PRIx8" apptag 0x%"PRIx16" appmask 0x%"PRIx16" reftag 0x%"PRIx32"" "\n", cid, prinfo, apptag, appmask, reftag);
#line 1220 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_RW_COMPLETE_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_RW_COMPLETE_CB) || \
    false)

static inline void trace_pci_nvme_rw_complete_cb(uint16_t cid, const char *blkname)
{
    if (trace_event_get_state(TRACE_PCI_NVME_RW_COMPLETE_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 40 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_rw_complete_cb " "cid %"PRIu16" blk '%s'" "\n", cid, blkname);
#line 1235 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_BLOCK_STATUS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_BLOCK_STATUS) || \
    false)

static inline void trace_pci_nvme_block_status(int64_t offset, int64_t bytes, int64_t pnum, int ret, bool zeroed)
{
    if (trace_event_get_state(TRACE_PCI_NVME_BLOCK_STATUS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 41 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_block_status " "offset %"PRId64" bytes %"PRId64" pnum %"PRId64" ret 0x%x zeroed %d" "\n", offset, bytes, pnum, ret, zeroed);
#line 1250 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DSM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DSM) || \
    false)

static inline void trace_pci_nvme_dsm(uint32_t nr, uint32_t attr)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DSM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 42 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dsm " "nr %"PRIu32" attr 0x%"PRIx32"" "\n", nr, attr);
#line 1265 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DSM_DEALLOCATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DSM_DEALLOCATE) || \
    false)

static inline void trace_pci_nvme_dsm_deallocate(uint64_t slba, uint32_t nlb)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DSM_DEALLOCATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 43 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dsm_deallocate " "slba %"PRIu64" nlb %"PRIu32"" "\n", slba, nlb);
#line 1280 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DSM_SINGLE_RANGE_LIMIT_EXCEEDED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DSM_SINGLE_RANGE_LIMIT_EXCEEDED) || \
    false)

static inline void trace_pci_nvme_dsm_single_range_limit_exceeded(uint32_t nlb, uint32_t dmrsl)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DSM_SINGLE_RANGE_LIMIT_EXCEEDED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 44 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_dsm_single_range_limit_exceeded " "nlb %"PRIu32" dmrsl %"PRIu32"" "\n", nlb, dmrsl);
#line 1295 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_COMPARE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_COMPARE) || \
    false)

static inline void trace_pci_nvme_compare(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb)
{
    if (trace_event_get_state(TRACE_PCI_NVME_COMPARE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 45 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_compare " "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32"" "\n", cid, nsid, slba, nlb);
#line 1310 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_COMPARE_DATA_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_COMPARE_DATA_CB) || \
    false)

static inline void trace_pci_nvme_compare_data_cb(uint16_t cid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_COMPARE_DATA_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 46 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_compare_data_cb " "cid %"PRIu16"" "\n", cid);
#line 1325 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_COMPARE_MDATA_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_COMPARE_MDATA_CB) || \
    false)

static inline void trace_pci_nvme_compare_mdata_cb(uint16_t cid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_COMPARE_MDATA_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 47 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_compare_mdata_cb " "cid %"PRIu16"" "\n", cid);
#line 1340 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_AIO_DISCARD_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_AIO_DISCARD_CB) || \
    false)

static inline void trace_pci_nvme_aio_discard_cb(uint16_t cid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_AIO_DISCARD_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 48 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_aio_discard_cb " "cid %"PRIu16"" "\n", cid);
#line 1355 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_AIO_COPY_IN_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_AIO_COPY_IN_CB) || \
    false)

static inline void trace_pci_nvme_aio_copy_in_cb(uint16_t cid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_AIO_COPY_IN_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 49 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_aio_copy_in_cb " "cid %"PRIu16"" "\n", cid);
#line 1370 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_AIO_FLUSH_CB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_AIO_FLUSH_CB) || \
    false)

static inline void trace_pci_nvme_aio_flush_cb(uint16_t cid, const char *blkname)
{
    if (trace_event_get_state(TRACE_PCI_NVME_AIO_FLUSH_CB)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 50 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_aio_flush_cb " "cid %"PRIu16" blk '%s'" "\n", cid, blkname);
#line 1385 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_CREATE_SQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_CREATE_SQ) || \
    false)

static inline void trace_pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize, uint16_t qflags)
{
    if (trace_event_get_state(TRACE_PCI_NVME_CREATE_SQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 51 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_create_sq " "create submission queue, addr=0x%"PRIx64", sqid=%"PRIu16", cqid=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16"" "\n", addr, sqid, cqid, qsize, qflags);
#line 1400 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_CREATE_CQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_CREATE_CQ) || \
    false)

static inline void trace_pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t size, uint16_t qflags, int ien)
{
    if (trace_event_get_state(TRACE_PCI_NVME_CREATE_CQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 52 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_create_cq " "create completion queue, addr=0x%"PRIx64", cqid=%"PRIu16", vector=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16", ien=%d" "\n", addr, cqid, vector, size, qflags, ien);
#line 1415 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DEL_SQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DEL_SQ) || \
    false)

static inline void trace_pci_nvme_del_sq(uint16_t qid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DEL_SQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 53 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_del_sq " "deleting submission queue sqid=%"PRIu16"" "\n", qid);
#line 1430 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_DEL_CQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_DEL_CQ) || \
    false)

static inline void trace_pci_nvme_del_cq(uint16_t cqid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_DEL_CQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 54 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_del_cq " "deleted completion queue, cqid=%"PRIu16"" "\n", cqid);
#line 1445 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY) || \
    false)

static inline void trace_pci_nvme_identify(uint16_t cid, uint8_t cns, uint16_t ctrlid, uint8_t csi)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 55 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify " "cid %"PRIu16" cns 0x%"PRIx8" ctrlid %"PRIu16" csi 0x%"PRIx8"" "\n", cid, cns, ctrlid, csi);
#line 1460 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_CTRL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_CTRL) || \
    false)

static inline void trace_pci_nvme_identify_ctrl(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_CTRL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 56 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_ctrl " "identify controller" "\n");
#line 1475 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_CTRL_CSI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_CTRL_CSI) || \
    false)

static inline void trace_pci_nvme_identify_ctrl_csi(uint8_t csi)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_CTRL_CSI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 57 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_ctrl_csi " "identify controller, csi=0x%"PRIx8"" "\n", csi);
#line 1490 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_NS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_NS) || \
    false)

static inline void trace_pci_nvme_identify_ns(uint32_t ns)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_NS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 58 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_ns " "nsid %"PRIu32"" "\n", ns);
#line 1505 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_NS_IND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_NS_IND) || \
    false)

static inline void trace_pci_nvme_identify_ns_ind(uint32_t nsid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_NS_IND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 59 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_ns_ind " "nsid %"PRIu32"" "\n", nsid);
#line 1520 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_CTRL_LIST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_CTRL_LIST) || \
    false)

static inline void trace_pci_nvme_identify_ctrl_list(uint8_t cns, uint16_t cntid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_CTRL_LIST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 60 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_ctrl_list " "cns 0x%"PRIx8" cntid %"PRIu16"" "\n", cns, cntid);
#line 1535 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_PRI_CTRL_CAP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_PRI_CTRL_CAP) || \
    false)

static inline void trace_pci_nvme_identify_pri_ctrl_cap(uint16_t cntlid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_PRI_CTRL_CAP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 61 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_pri_ctrl_cap " "identify primary controller capabilities cntlid=%"PRIu16"" "\n", cntlid);
#line 1550 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_SEC_CTRL_LIST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_SEC_CTRL_LIST) || \
    false)

static inline void trace_pci_nvme_identify_sec_ctrl_list(uint16_t cntlid, uint8_t numcntl)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_SEC_CTRL_LIST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 62 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_sec_ctrl_list " "identify secondary controller list cntlid=%"PRIu16" numcntl=%"PRIu8"" "\n", cntlid, numcntl);
#line 1565 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_NS_CSI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_NS_CSI) || \
    false)

static inline void trace_pci_nvme_identify_ns_csi(uint32_t ns, uint8_t csi)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_NS_CSI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 63 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_ns_csi " "nsid=%"PRIu32", csi=0x%"PRIx8"" "\n", ns, csi);
#line 1580 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_NSLIST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_NSLIST) || \
    false)

static inline void trace_pci_nvme_identify_nslist(uint32_t ns)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_NSLIST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 64 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_nslist " "nsid %"PRIu32"" "\n", ns);
#line 1595 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_NSLIST_CSI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_NSLIST_CSI) || \
    false)

static inline void trace_pci_nvme_identify_nslist_csi(uint16_t ns, uint8_t csi)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_NSLIST_CSI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 65 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_nslist_csi " "nsid=%"PRIu16", csi=0x%"PRIx8"" "\n", ns, csi);
#line 1610 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_CMD_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_CMD_SET) || \
    false)

static inline void trace_pci_nvme_identify_cmd_set(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_CMD_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 66 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_cmd_set " "identify i/o command set" "\n");
#line 1625 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_IDENTIFY_NS_DESCR_LIST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_IDENTIFY_NS_DESCR_LIST) || \
    false)

static inline void trace_pci_nvme_identify_ns_descr_list(uint32_t ns)
{
    if (trace_event_get_state(TRACE_PCI_NVME_IDENTIFY_NS_DESCR_LIST)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 67 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_identify_ns_descr_list " "nsid %"PRIu32"" "\n", ns);
#line 1640 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_GET_LOG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_GET_LOG) || \
    false)

static inline void trace_pci_nvme_get_log(uint16_t cid, uint8_t lid, uint8_t lsp, uint8_t rae, uint32_t len, uint64_t off)
{
    if (trace_event_get_state(TRACE_PCI_NVME_GET_LOG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 68 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_get_log " "cid %"PRIu16" lid 0x%"PRIx8" lsp 0x%"PRIx8" rae 0x%"PRIx8" len %"PRIu32" off %"PRIu64"" "\n", cid, lid, lsp, rae, len, off);
#line 1655 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_GETFEAT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_GETFEAT) || \
    false)

static inline void trace_pci_nvme_getfeat(uint16_t cid, uint32_t nsid, uint8_t fid, uint8_t sel, uint32_t cdw11)
{
    if (trace_event_get_state(TRACE_PCI_NVME_GETFEAT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 69 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_getfeat " "cid %"PRIu16" nsid 0x%"PRIx32" fid 0x%"PRIx8" sel 0x%"PRIx8" cdw11 0x%"PRIx32"" "\n", cid, nsid, fid, sel, cdw11);
#line 1670 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_SETFEAT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_SETFEAT) || \
    false)

static inline void trace_pci_nvme_setfeat(uint16_t cid, uint32_t nsid, uint8_t fid, uint8_t save, uint32_t cdw11)
{
    if (trace_event_get_state(TRACE_PCI_NVME_SETFEAT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 70 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_setfeat " "cid %"PRIu16" nsid 0x%"PRIx32" fid 0x%"PRIx8" save 0x%"PRIx8" cdw11 0x%"PRIx32"" "\n", cid, nsid, fid, save, cdw11);
#line 1685 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_GETFEAT_VWCACHE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_GETFEAT_VWCACHE) || \
    false)

static inline void trace_pci_nvme_getfeat_vwcache(const char*result)
{
    if (trace_event_get_state(TRACE_PCI_NVME_GETFEAT_VWCACHE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 71 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_getfeat_vwcache " "get feature volatile write cache, result=%s" "\n", result);
#line 1700 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_GETFEAT_NUMQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_GETFEAT_NUMQ) || \
    false)

static inline void trace_pci_nvme_getfeat_numq(int result)
{
    if (trace_event_get_state(TRACE_PCI_NVME_GETFEAT_NUMQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 72 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_getfeat_numq " "get feature number of queues, result=%d" "\n", result);
#line 1715 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_SETFEAT_NUMQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_SETFEAT_NUMQ) || \
    false)

static inline void trace_pci_nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq)
{
    if (trace_event_get_state(TRACE_PCI_NVME_SETFEAT_NUMQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 73 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_setfeat_numq " "requested cq_count=%d sq_count=%d, responding with cq_count=%d sq_count=%d" "\n", reqcq, reqsq, gotcq, gotsq);
#line 1730 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_SETFEAT_TIMESTAMP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_SETFEAT_TIMESTAMP) || \
    false)

static inline void trace_pci_nvme_setfeat_timestamp(uint64_t ts)
{
    if (trace_event_get_state(TRACE_PCI_NVME_SETFEAT_TIMESTAMP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 74 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_setfeat_timestamp " "set feature timestamp = 0x%"PRIx64"" "\n", ts);
#line 1745 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_GETFEAT_TIMESTAMP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_GETFEAT_TIMESTAMP) || \
    false)

static inline void trace_pci_nvme_getfeat_timestamp(uint64_t ts)
{
    if (trace_event_get_state(TRACE_PCI_NVME_GETFEAT_TIMESTAMP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 75 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_getfeat_timestamp " "get feature timestamp = 0x%"PRIx64"" "\n", ts);
#line 1760 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_PROCESS_AERS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_PROCESS_AERS) || \
    false)

static inline void trace_pci_nvme_process_aers(int queued)
{
    if (trace_event_get_state(TRACE_PCI_NVME_PROCESS_AERS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 76 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_process_aers " "queued %d" "\n", queued);
#line 1775 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_AER_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_AER) || \
    false)

static inline void trace_pci_nvme_aer(uint16_t cid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_AER)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 77 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_aer " "cid %"PRIu16"" "\n", cid);
#line 1790 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_AER_AERL_EXCEEDED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_AER_AERL_EXCEEDED) || \
    false)

static inline void trace_pci_nvme_aer_aerl_exceeded(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_AER_AERL_EXCEEDED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 78 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_aer_aerl_exceeded " "aerl exceeded" "\n");
#line 1805 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_AER_MASKED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_AER_MASKED) || \
    false)

static inline void trace_pci_nvme_aer_masked(uint8_t type, uint8_t mask)
{
    if (trace_event_get_state(TRACE_PCI_NVME_AER_MASKED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 79 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_aer_masked " "type 0x%"PRIx8" mask 0x%"PRIx8"" "\n", type, mask);
#line 1820 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_AER_POST_CQE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_AER_POST_CQE) || \
    false)

static inline void trace_pci_nvme_aer_post_cqe(uint8_t typ, uint8_t info, uint8_t log_page)
{
    if (trace_event_get_state(TRACE_PCI_NVME_AER_POST_CQE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 80 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_aer_post_cqe " "type 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" "\n", typ, info, log_page);
#line 1835 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_NS_ATTACHMENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_NS_ATTACHMENT) || \
    false)

static inline void trace_pci_nvme_ns_attachment(uint16_t cid, uint8_t sel)
{
    if (trace_event_get_state(TRACE_PCI_NVME_NS_ATTACHMENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 81 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ns_attachment " "cid %"PRIu16", sel=0x%"PRIx8"" "\n", cid, sel);
#line 1850 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_NS_ATTACHMENT_ATTACH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_NS_ATTACHMENT_ATTACH) || \
    false)

static inline void trace_pci_nvme_ns_attachment_attach(uint16_t cntlid, uint32_t nsid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_NS_ATTACHMENT_ATTACH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 82 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ns_attachment_attach " "cntlid=0x%"PRIx16", nsid=0x%"PRIx32"" "\n", cntlid, nsid);
#line 1865 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ENQUEUE_EVENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ENQUEUE_EVENT) || \
    false)

static inline void trace_pci_nvme_enqueue_event(uint8_t typ, uint8_t info, uint8_t log_page)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ENQUEUE_EVENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 83 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_enqueue_event " "type 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" "\n", typ, info, log_page);
#line 1880 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ENQUEUE_EVENT_NOQUEUE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ENQUEUE_EVENT_NOQUEUE) || \
    false)

static inline void trace_pci_nvme_enqueue_event_noqueue(int queued)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ENQUEUE_EVENT_NOQUEUE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 84 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_enqueue_event_noqueue " "queued %d" "\n", queued);
#line 1895 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ENQUEUE_EVENT_MASKED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ENQUEUE_EVENT_MASKED) || \
    false)

static inline void trace_pci_nvme_enqueue_event_masked(uint8_t typ)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ENQUEUE_EVENT_MASKED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 85 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_enqueue_event_masked " "type 0x%"PRIx8"" "\n", typ);
#line 1910 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_NO_OUTSTANDING_AERS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_NO_OUTSTANDING_AERS) || \
    false)

static inline void trace_pci_nvme_no_outstanding_aers(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_NO_OUTSTANDING_AERS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 86 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_no_outstanding_aers " "ignoring event; no outstanding AERs" "\n");
#line 1925 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ENQUEUE_REQ_COMPLETION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ENQUEUE_REQ_COMPLETION) || \
    false)

static inline void trace_pci_nvme_enqueue_req_completion(uint16_t cid, uint16_t cqid, uint32_t dw0, uint32_t dw1, uint16_t status)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ENQUEUE_REQ_COMPLETION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 87 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_enqueue_req_completion " "cid %"PRIu16" cqid %"PRIu16" dw0 0x%"PRIx32" dw1 0x%"PRIx32" status 0x%"PRIx16"" "\n", cid, cqid, dw0, dw1, status);
#line 1940 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UPDATE_CQ_EVENTIDX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UPDATE_CQ_EVENTIDX) || \
    false)

static inline void trace_pci_nvme_update_cq_eventidx(uint16_t cqid, uint16_t new_eventidx)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UPDATE_CQ_EVENTIDX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 88 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_update_cq_eventidx " "cqid %"PRIu16" new_eventidx %"PRIu16"" "\n", cqid, new_eventidx);
#line 1955 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UPDATE_SQ_EVENTIDX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UPDATE_SQ_EVENTIDX) || \
    false)

static inline void trace_pci_nvme_update_sq_eventidx(uint16_t sqid, uint16_t new_eventidx)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UPDATE_SQ_EVENTIDX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 89 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_update_sq_eventidx " "sqid %"PRIu16" new_eventidx %"PRIu16"" "\n", sqid, new_eventidx);
#line 1970 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_READ) || \
    false)

static inline void trace_pci_nvme_mmio_read(uint64_t addr, unsigned size)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 90 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_read " "addr 0x%"PRIx64" size %d" "\n", addr, size);
#line 1985 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_WRITE) || \
    false)

static inline void trace_pci_nvme_mmio_write(uint64_t addr, uint64_t data, unsigned size)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 91 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_write " "addr 0x%"PRIx64" data 0x%"PRIx64" size %d" "\n", addr, data, size);
#line 2000 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_DOORBELL_CQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_DOORBELL_CQ) || \
    false)

static inline void trace_pci_nvme_mmio_doorbell_cq(uint16_t cqid, uint16_t new_head)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_DOORBELL_CQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 92 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_doorbell_cq " "cqid %"PRIu16" new_head %"PRIu16"" "\n", cqid, new_head);
#line 2015 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_DOORBELL_SQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_DOORBELL_SQ) || \
    false)

static inline void trace_pci_nvme_mmio_doorbell_sq(uint16_t sqid, uint16_t new_tail)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_DOORBELL_SQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 93 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_doorbell_sq " "sqid %"PRIu16" new_tail %"PRIu16"" "\n", sqid, new_tail);
#line 2030 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_INTM_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_INTM_SET) || \
    false)

static inline void trace_pci_nvme_mmio_intm_set(uint64_t data, uint64_t new_mask)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_INTM_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 94 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_intm_set " "wrote MMIO, interrupt mask set, data=0x%"PRIx64", new_mask=0x%"PRIx64"" "\n", data, new_mask);
#line 2045 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_INTM_CLR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_INTM_CLR) || \
    false)

static inline void trace_pci_nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_INTM_CLR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 95 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_intm_clr " "wrote MMIO, interrupt mask clr, data=0x%"PRIx64", new_mask=0x%"PRIx64"" "\n", data, new_mask);
#line 2060 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_CFG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_CFG) || \
    false)

static inline void trace_pci_nvme_mmio_cfg(uint64_t data)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_CFG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 96 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_cfg " "wrote MMIO, config controller config=0x%"PRIx64"" "\n", data);
#line 2075 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_AQATTR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_AQATTR) || \
    false)

static inline void trace_pci_nvme_mmio_aqattr(uint64_t data)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_AQATTR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 97 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_aqattr " "wrote MMIO, admin queue attributes=0x%"PRIx64"" "\n", data);
#line 2090 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_ASQADDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_ASQADDR) || \
    false)

static inline void trace_pci_nvme_mmio_asqaddr(uint64_t data)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_ASQADDR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 98 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_asqaddr " "wrote MMIO, admin submission queue address=0x%"PRIx64"" "\n", data);
#line 2105 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_ACQADDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_ACQADDR) || \
    false)

static inline void trace_pci_nvme_mmio_acqaddr(uint64_t data)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_ACQADDR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 99 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_acqaddr " "wrote MMIO, admin completion queue address=0x%"PRIx64"" "\n", data);
#line 2120 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_ASQADDR_HI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_ASQADDR_HI) || \
    false)

static inline void trace_pci_nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_ASQADDR_HI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 100 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_asqaddr_hi " "wrote MMIO, admin submission queue high half=0x%"PRIx64", new_address=0x%"PRIx64"" "\n", data, new_addr);
#line 2135 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_ACQADDR_HI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_ACQADDR_HI) || \
    false)

static inline void trace_pci_nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_addr)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_ACQADDR_HI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 101 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_acqaddr_hi " "wrote MMIO, admin completion queue high half=0x%"PRIx64", new_address=0x%"PRIx64"" "\n", data, new_addr);
#line 2150 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_START_SUCCESS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_START_SUCCESS) || \
    false)

static inline void trace_pci_nvme_mmio_start_success(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_START_SUCCESS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 102 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_start_success " "setting controller enable bit succeeded" "\n");
#line 2165 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_STOPPED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_STOPPED) || \
    false)

static inline void trace_pci_nvme_mmio_stopped(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_STOPPED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 103 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_stopped " "cleared controller enable bit" "\n");
#line 2180 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_SHUTDOWN_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_SHUTDOWN_SET) || \
    false)

static inline void trace_pci_nvme_mmio_shutdown_set(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_SHUTDOWN_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 104 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_shutdown_set " "shutdown bit set" "\n");
#line 2195 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_MMIO_SHUTDOWN_CLEARED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_MMIO_SHUTDOWN_CLEARED) || \
    false)

static inline void trace_pci_nvme_mmio_shutdown_cleared(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_MMIO_SHUTDOWN_CLEARED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 105 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_mmio_shutdown_cleared " "shutdown bit cleared" "\n");
#line 2210 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UPDATE_CQ_HEAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UPDATE_CQ_HEAD) || \
    false)

static inline void trace_pci_nvme_update_cq_head(uint16_t cqid, uint16_t new_head)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UPDATE_CQ_HEAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 106 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_update_cq_head " "cqid %"PRIu16" new_head %"PRIu16"" "\n", cqid, new_head);
#line 2225 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UPDATE_SQ_TAIL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UPDATE_SQ_TAIL) || \
    false)

static inline void trace_pci_nvme_update_sq_tail(uint16_t sqid, uint16_t new_tail)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UPDATE_SQ_TAIL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 107 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_update_sq_tail " "sqid %"PRIu16" new_tail %"PRIu16"" "\n", sqid, new_tail);
#line 2240 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_OPEN_ZONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_OPEN_ZONE) || \
    false)

static inline void trace_pci_nvme_open_zone(uint64_t slba, uint32_t zone_idx, int all)
{
    if (trace_event_get_state(TRACE_PCI_NVME_OPEN_ZONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 108 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_open_zone " "open zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" "\n", slba, zone_idx, all);
#line 2255 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_CLOSE_ZONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_CLOSE_ZONE) || \
    false)

static inline void trace_pci_nvme_close_zone(uint64_t slba, uint32_t zone_idx, int all)
{
    if (trace_event_get_state(TRACE_PCI_NVME_CLOSE_ZONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 109 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_close_zone " "close zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" "\n", slba, zone_idx, all);
#line 2270 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_FINISH_ZONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_FINISH_ZONE) || \
    false)

static inline void trace_pci_nvme_finish_zone(uint64_t slba, uint32_t zone_idx, int all)
{
    if (trace_event_get_state(TRACE_PCI_NVME_FINISH_ZONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 110 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_finish_zone " "finish zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" "\n", slba, zone_idx, all);
#line 2285 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_RESET_ZONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_RESET_ZONE) || \
    false)

static inline void trace_pci_nvme_reset_zone(uint64_t slba, uint32_t zone_idx, int all)
{
    if (trace_event_get_state(TRACE_PCI_NVME_RESET_ZONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 111 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_reset_zone " "reset zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" "\n", slba, zone_idx, all);
#line 2300 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ZNS_ZONE_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ZNS_ZONE_RESET) || \
    false)

static inline void trace_pci_nvme_zns_zone_reset(uint64_t zslba)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ZNS_ZONE_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 112 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_zns_zone_reset " "zslba 0x%"PRIx64"" "\n", zslba);
#line 2315 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_OFFLINE_ZONE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_OFFLINE_ZONE) || \
    false)

static inline void trace_pci_nvme_offline_zone(uint64_t slba, uint32_t zone_idx, int all)
{
    if (trace_event_get_state(TRACE_PCI_NVME_OFFLINE_ZONE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 113 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_offline_zone " "offline zone, slba=%"PRIu64", idx=%"PRIu32", all=%"PRIi32"" "\n", slba, zone_idx, all);
#line 2330 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_SET_DESCRIPTOR_EXTENSION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_SET_DESCRIPTOR_EXTENSION) || \
    false)

static inline void trace_pci_nvme_set_descriptor_extension(uint64_t slba, uint32_t zone_idx)
{
    if (trace_event_get_state(TRACE_PCI_NVME_SET_DESCRIPTOR_EXTENSION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 114 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_set_descriptor_extension " "set zone descriptor extension, slba=%"PRIu64", idx=%"PRIu32"" "\n", slba, zone_idx);
#line 2345 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ZD_EXTENSION_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ZD_EXTENSION_SET) || \
    false)

static inline void trace_pci_nvme_zd_extension_set(uint32_t zone_idx)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ZD_EXTENSION_SET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 115 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_zd_extension_set " "set descriptor extension for zone_idx=%"PRIu32"" "\n", zone_idx);
#line 2360 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_CLEAR_NS_CLOSE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_CLEAR_NS_CLOSE) || \
    false)

static inline void trace_pci_nvme_clear_ns_close(uint32_t state, uint64_t slba)
{
    if (trace_event_get_state(TRACE_PCI_NVME_CLEAR_NS_CLOSE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 116 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_clear_ns_close " "zone state=%"PRIu32", slba=%"PRIu64" transitioned to Closed state" "\n", state, slba);
#line 2375 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_CLEAR_NS_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_CLEAR_NS_RESET) || \
    false)

static inline void trace_pci_nvme_clear_ns_reset(uint32_t state, uint64_t slba)
{
    if (trace_event_get_state(TRACE_PCI_NVME_CLEAR_NS_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 117 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_clear_ns_reset " "zone state=%"PRIu32", slba=%"PRIu64" transitioned to Empty state" "\n", state, slba);
#line 2390 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ZONED_ZRWA_IMPLICIT_FLUSH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ZONED_ZRWA_IMPLICIT_FLUSH) || \
    false)

static inline void trace_pci_nvme_zoned_zrwa_implicit_flush(uint64_t zslba, uint32_t nlb)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ZONED_ZRWA_IMPLICIT_FLUSH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 118 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_zoned_zrwa_implicit_flush " "zslba 0x%"PRIx64" nlb %"PRIu32"" "\n", zslba, nlb);
#line 2405 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_PCI_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_PCI_RESET) || \
    false)

static inline void trace_pci_nvme_pci_reset(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_PCI_RESET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 119 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_pci_reset " "PCI Function Level Reset" "\n");
#line 2420 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_VIRT_MNGMT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_VIRT_MNGMT) || \
    false)

static inline void trace_pci_nvme_virt_mngmt(uint16_t cid, uint16_t act, uint16_t cntlid, const char*rt, uint16_t nr)
{
    if (trace_event_get_state(TRACE_PCI_NVME_VIRT_MNGMT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 120 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_virt_mngmt " "cid %"PRIu16", act=0x%"PRIx16", ctrlid=%"PRIu16" %s nr=%"PRIu16"" "\n", cid, act, cntlid, rt, nr);
#line 2435 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_FDP_RUH_CHANGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_FDP_RUH_CHANGE) || \
    false)

static inline void trace_pci_nvme_fdp_ruh_change(uint16_t rgid, uint16_t ruhid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_FDP_RUH_CHANGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 121 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_fdp_ruh_change " "change RU on RUH rgid=%"PRIu16", ruhid=%"PRIu16"" "\n", rgid, ruhid);
#line 2450 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_MDTS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_MDTS) || \
    false)

static inline void trace_pci_nvme_err_mdts(size_t len)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_MDTS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 124 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_mdts " "len %zu" "\n", len);
#line 2465 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_ZASL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_ZASL) || \
    false)

static inline void trace_pci_nvme_err_zasl(size_t len)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_ZASL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 125 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_zasl " "len %zu" "\n", len);
#line 2480 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_REQ_STATUS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_REQ_STATUS) || \
    false)

static inline void trace_pci_nvme_err_req_status(uint16_t cid, uint32_t nsid, uint16_t status, uint8_t opc)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_REQ_STATUS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 126 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_req_status " "cid %"PRIu16" nsid %"PRIu32" status 0x%"PRIx16" opc 0x%"PRIx8"" "\n", cid, nsid, status, opc);
#line 2495 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_ADDR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_ADDR_READ) || \
    false)

static inline void trace_pci_nvme_err_addr_read(uint64_t addr)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_ADDR_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 127 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_addr_read " "addr 0x%"PRIx64"" "\n", addr);
#line 2510 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_ADDR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_ADDR_WRITE) || \
    false)

static inline void trace_pci_nvme_err_addr_write(uint64_t addr)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_ADDR_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 128 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_addr_write " "addr 0x%"PRIx64"" "\n", addr);
#line 2525 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_CFS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_CFS) || \
    false)

static inline void trace_pci_nvme_err_cfs(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_CFS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 129 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_cfs " "controller fatal status" "\n");
#line 2540 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_AIO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_AIO) || \
    false)

static inline void trace_pci_nvme_err_aio(uint16_t cid, const char *errname, uint16_t status)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_AIO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 130 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_aio " "cid %"PRIu16" err '%s' status 0x%"PRIx16"" "\n", cid, errname, status);
#line 2555 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_COPY_INVALID_FORMAT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_COPY_INVALID_FORMAT) || \
    false)

static inline void trace_pci_nvme_err_copy_invalid_format(uint8_t format)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_COPY_INVALID_FORMAT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 131 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_copy_invalid_format " "format 0x%"PRIx8"" "\n", format);
#line 2570 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_SGLD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_SGLD) || \
    false)

static inline void trace_pci_nvme_err_invalid_sgld(uint16_t cid, uint8_t typ)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_SGLD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 132 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_sgld " "cid %"PRIu16" type 0x%"PRIx8"" "\n", cid, typ);
#line 2585 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_NUM_SGLD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_NUM_SGLD) || \
    false)

static inline void trace_pci_nvme_err_invalid_num_sgld(uint16_t cid, uint8_t typ)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_NUM_SGLD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 133 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_num_sgld " "cid %"PRIu16" type 0x%"PRIx8"" "\n", cid, typ);
#line 2600 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_SGL_EXCESS_LENGTH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_SGL_EXCESS_LENGTH) || \
    false)

static inline void trace_pci_nvme_err_invalid_sgl_excess_length(uint32_t residual)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_SGL_EXCESS_LENGTH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 134 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_sgl_excess_length " "residual %"PRIu32"" "\n", residual);
#line 2615 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_DMA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_DMA) || \
    false)

static inline void trace_pci_nvme_err_invalid_dma(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_DMA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 135 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_dma " "PRP/SGL is too small for transfer size" "\n");
#line 2630 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_PRPLIST_ENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_PRPLIST_ENT) || \
    false)

static inline void trace_pci_nvme_err_invalid_prplist_ent(uint64_t prplist)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_PRPLIST_ENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 136 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_prplist_ent " "PRP list entry is not page aligned: 0x%"PRIx64"" "\n", prplist);
#line 2645 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_PRP2_ALIGN_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_PRP2_ALIGN) || \
    false)

static inline void trace_pci_nvme_err_invalid_prp2_align(uint64_t prp2)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_PRP2_ALIGN)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 137 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_prp2_align " "PRP2 is not page aligned: 0x%"PRIx64"" "\n", prp2);
#line 2660 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_OPC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_OPC) || \
    false)

static inline void trace_pci_nvme_err_invalid_opc(uint8_t opc)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_OPC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 138 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_opc " "invalid opcode 0x%"PRIx8"" "\n", opc);
#line 2675 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_ADMIN_OPC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_ADMIN_OPC) || \
    false)

static inline void trace_pci_nvme_err_invalid_admin_opc(uint8_t opc)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_ADMIN_OPC)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 139 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_admin_opc " "invalid admin opcode 0x%"PRIx8"" "\n", opc);
#line 2690 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_LBA_RANGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_LBA_RANGE) || \
    false)

static inline void trace_pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_LBA_RANGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 140 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_lba_range " "Invalid LBA start=%"PRIu64" len=%"PRIu64" limit=%"PRIu64"" "\n", start, len, limit);
#line 2705 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_OFFSET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_OFFSET) || \
    false)

static inline void trace_pci_nvme_err_invalid_log_page_offset(uint64_t ofs, uint64_t size)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_OFFSET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 141 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_log_page_offset " "must be <= %"PRIu64", got %"PRIu64"" "\n", ofs, size);
#line 2720 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_CMB_INVALID_CBA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_CMB_INVALID_CBA) || \
    false)

static inline void trace_pci_nvme_err_cmb_invalid_cba(uint64_t cmbmsc)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_CMB_INVALID_CBA)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 142 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_cmb_invalid_cba " "cmbmsc 0x%"PRIx64"" "\n", cmbmsc);
#line 2735 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_CMB_NOT_ENABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_CMB_NOT_ENABLED) || \
    false)

static inline void trace_pci_nvme_err_cmb_not_enabled(uint64_t cmbmsc)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_CMB_NOT_ENABLED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 143 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_cmb_not_enabled " "cmbmsc 0x%"PRIx64"" "\n", cmbmsc);
#line 2750 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_UNALIGNED_ZONE_CMD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_UNALIGNED_ZONE_CMD) || \
    false)

static inline void trace_pci_nvme_err_unaligned_zone_cmd(uint8_t action, uint64_t slba, uint64_t zslba)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_UNALIGNED_ZONE_CMD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 144 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_unaligned_zone_cmd " "unaligned zone op 0x%"PRIx32", got slba=%"PRIu64", zslba=%"PRIu64"" "\n", action, slba, zslba);
#line 2765 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_ZONE_STATE_TRANSITION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_ZONE_STATE_TRANSITION) || \
    false)

static inline void trace_pci_nvme_err_invalid_zone_state_transition(uint8_t action, uint64_t slba, uint8_t attrs)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_ZONE_STATE_TRANSITION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 145 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_zone_state_transition " "action=0x%"PRIx8", slba=%"PRIu64", attrs=0x%"PRIx32"" "\n", action, slba, attrs);
#line 2780 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_WRITE_NOT_AT_WP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_WRITE_NOT_AT_WP) || \
    false)

static inline void trace_pci_nvme_err_write_not_at_wp(uint64_t slba, uint64_t zone, uint64_t wp)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_WRITE_NOT_AT_WP)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 146 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_write_not_at_wp " "writing at slba=%"PRIu64", zone=%"PRIu64", but wp=%"PRIu64"" "\n", slba, zone, wp);
#line 2795 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_APPEND_NOT_AT_START_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_APPEND_NOT_AT_START) || \
    false)

static inline void trace_pci_nvme_err_append_not_at_start(uint64_t slba, uint64_t zone)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_APPEND_NOT_AT_START)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 147 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_append_not_at_start " "appending at slba=%"PRIu64", but zone=%"PRIu64"" "\n", slba, zone);
#line 2810 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_ZONE_IS_FULL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_ZONE_IS_FULL) || \
    false)

static inline void trace_pci_nvme_err_zone_is_full(uint64_t zslba)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_ZONE_IS_FULL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 148 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_zone_is_full " "zslba 0x%"PRIx64"" "\n", zslba);
#line 2825 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_ZONE_IS_READ_ONLY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_ZONE_IS_READ_ONLY) || \
    false)

static inline void trace_pci_nvme_err_zone_is_read_only(uint64_t zslba)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_ZONE_IS_READ_ONLY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 149 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_zone_is_read_only " "zslba 0x%"PRIx64"" "\n", zslba);
#line 2840 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_ZONE_IS_OFFLINE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_ZONE_IS_OFFLINE) || \
    false)

static inline void trace_pci_nvme_err_zone_is_offline(uint64_t zslba)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_ZONE_IS_OFFLINE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 150 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_zone_is_offline " "zslba 0x%"PRIx64"" "\n", zslba);
#line 2855 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_ZONE_BOUNDARY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_ZONE_BOUNDARY) || \
    false)

static inline void trace_pci_nvme_err_zone_boundary(uint64_t slba, uint32_t nlb, uint64_t zcap)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_ZONE_BOUNDARY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 151 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_zone_boundary " "lba 0x%"PRIx64" nlb %"PRIu32" zcap 0x%"PRIx64"" "\n", slba, nlb, zcap);
#line 2870 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_ZONE_INVALID_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_ZONE_INVALID_WRITE) || \
    false)

static inline void trace_pci_nvme_err_zone_invalid_write(uint64_t slba, uint64_t wp)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_ZONE_INVALID_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 152 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_zone_invalid_write " "lba 0x%"PRIx64" wp 0x%"PRIx64"" "\n", slba, wp);
#line 2885 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_ZONE_WRITE_NOT_OK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_ZONE_WRITE_NOT_OK) || \
    false)

static inline void trace_pci_nvme_err_zone_write_not_ok(uint64_t slba, uint32_t nlb, uint16_t status)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_ZONE_WRITE_NOT_OK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 153 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_zone_write_not_ok " "slba=%"PRIu64", nlb=%"PRIu32", status=0x%"PRIx16"" "\n", slba, nlb, status);
#line 2900 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_ZONE_READ_NOT_OK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_ZONE_READ_NOT_OK) || \
    false)

static inline void trace_pci_nvme_err_zone_read_not_ok(uint64_t slba, uint32_t nlb, uint16_t status)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_ZONE_READ_NOT_OK)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 154 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_zone_read_not_ok " "slba=%"PRIu64", nlb=%"PRIu32", status=0x%"PRIx16"" "\n", slba, nlb, status);
#line 2915 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INSUFF_ACTIVE_RES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INSUFF_ACTIVE_RES) || \
    false)

static inline void trace_pci_nvme_err_insuff_active_res(uint32_t max_active)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INSUFF_ACTIVE_RES)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 155 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_insuff_active_res " "max_active=%"PRIu32" zone limit exceeded" "\n", max_active);
#line 2930 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INSUFF_OPEN_RES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INSUFF_OPEN_RES) || \
    false)

static inline void trace_pci_nvme_err_insuff_open_res(uint32_t max_open)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INSUFF_OPEN_RES)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 156 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_insuff_open_res " "max_open=%"PRIu32" zone limit exceeded" "\n", max_open);
#line 2945 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_ZD_EXTENSION_MAP_ERROR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_ZD_EXTENSION_MAP_ERROR) || \
    false)

static inline void trace_pci_nvme_err_zd_extension_map_error(uint32_t zone_idx)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_ZD_EXTENSION_MAP_ERROR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 157 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_zd_extension_map_error " "can't map descriptor extension for zone_idx=%"PRIu32"" "\n", zone_idx);
#line 2960 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_IOCSCI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_IOCSCI) || \
    false)

static inline void trace_pci_nvme_err_invalid_iocsci(uint32_t idx)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_IOCSCI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 158 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_iocsci " "unsupported command set combination index %"PRIu32"" "\n", idx);
#line 2975 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_DEL_SQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_DEL_SQ) || \
    false)

static inline void trace_pci_nvme_err_invalid_del_sq(uint16_t qid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_DEL_SQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 159 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_del_sq " "invalid submission queue deletion, sid=%"PRIu16"" "\n", qid);
#line 2990 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_CQID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_CQID) || \
    false)

static inline void trace_pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_CQID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 160 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_create_sq_cqid " "failed creating submission queue, invalid cqid=%"PRIu16"" "\n", cqid);
#line 3005 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SQID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SQID) || \
    false)

static inline void trace_pci_nvme_err_invalid_create_sq_sqid(uint16_t sqid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SQID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 161 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_create_sq_sqid " "failed creating submission queue, invalid sqid=%"PRIu16"" "\n", sqid);
#line 3020 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SIZE) || \
    false)

static inline void trace_pci_nvme_err_invalid_create_sq_size(uint16_t qsize)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 162 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_create_sq_size " "failed creating submission queue, invalid qsize=%"PRIu16"" "\n", qsize);
#line 3035 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_ADDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_ADDR) || \
    false)

static inline void trace_pci_nvme_err_invalid_create_sq_addr(uint64_t addr)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_ADDR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 163 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_create_sq_addr " "failed creating submission queue, addr=0x%"PRIx64"" "\n", addr);
#line 3050 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_QFLAGS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_QFLAGS) || \
    false)

static inline void trace_pci_nvme_err_invalid_create_sq_qflags(uint16_t qflags)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_QFLAGS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 164 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_create_sq_qflags " "failed creating submission queue, qflags=%"PRIu16"" "\n", qflags);
#line 3065 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_CQID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_CQID) || \
    false)

static inline void trace_pci_nvme_err_invalid_del_cq_cqid(uint16_t cqid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_CQID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 165 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_del_cq_cqid " "failed deleting completion queue, cqid=%"PRIu16"" "\n", cqid);
#line 3080 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_NOTEMPTY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_NOTEMPTY) || \
    false)

static inline void trace_pci_nvme_err_invalid_del_cq_notempty(uint16_t cqid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_NOTEMPTY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 166 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_del_cq_notempty " "failed deleting completion queue, it is not empty, cqid=%"PRIu16"" "\n", cqid);
#line 3095 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_CQID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_CQID) || \
    false)

static inline void trace_pci_nvme_err_invalid_create_cq_cqid(uint16_t cqid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_CQID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 167 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_create_cq_cqid " "failed creating completion queue, cqid=%"PRIu16"" "\n", cqid);
#line 3110 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_SIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_SIZE) || \
    false)

static inline void trace_pci_nvme_err_invalid_create_cq_size(uint16_t size)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_SIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 168 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_create_cq_size " "failed creating completion queue, size=%"PRIu16"" "\n", size);
#line 3125 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ADDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ADDR) || \
    false)

static inline void trace_pci_nvme_err_invalid_create_cq_addr(uint64_t addr)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ADDR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 169 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_create_cq_addr " "failed creating completion queue, addr=0x%"PRIx64"" "\n", addr);
#line 3140 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_VECTOR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_VECTOR) || \
    false)

static inline void trace_pci_nvme_err_invalid_create_cq_vector(uint16_t vector)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_VECTOR)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 170 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_create_cq_vector " "failed creating completion queue, vector=%"PRIu16"" "\n", vector);
#line 3155 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_QFLAGS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_QFLAGS) || \
    false)

static inline void trace_pci_nvme_err_invalid_create_cq_qflags(uint16_t qflags)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_QFLAGS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 171 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_create_cq_qflags " "failed creating completion queue, qflags=%"PRIu16"" "\n", qflags);
#line 3170 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ENTRY_SIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ENTRY_SIZE) || \
    false)

static inline void trace_pci_nvme_err_invalid_create_cq_entry_size(uint8_t iosqes, uint8_t iocqes)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ENTRY_SIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 172 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_create_cq_entry_size " "iosqes %"PRIu8" iocqes %"PRIu8"" "\n", iosqes, iocqes);
#line 3185 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_IDENTIFY_CNS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_IDENTIFY_CNS) || \
    false)

static inline void trace_pci_nvme_err_invalid_identify_cns(uint16_t cns)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_IDENTIFY_CNS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 173 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_identify_cns " "identify, invalid cns=0x%"PRIx16"" "\n", cns);
#line 3200 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_GETFEAT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_GETFEAT) || \
    false)

static inline void trace_pci_nvme_err_invalid_getfeat(int dw10)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_GETFEAT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 174 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_getfeat " "invalid get features, dw10=0x%"PRIx32"" "\n", dw10);
#line 3215 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_SETFEAT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_SETFEAT) || \
    false)

static inline void trace_pci_nvme_err_invalid_setfeat(uint32_t dw10)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_SETFEAT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 175 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_setfeat " "invalid set features, dw10=0x%"PRIx32"" "\n", dw10);
#line 3230 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE) || \
    false)

static inline void trace_pci_nvme_err_invalid_log_page(uint16_t cid, uint16_t lid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 176 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_log_page " "cid %"PRIu16" lid 0x%"PRIx16"" "\n", cid, lid);
#line 3245 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_CQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_CQ) || \
    false)

static inline void trace_pci_nvme_err_startfail_cq(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_CQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 177 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_cq " "nvme_start_ctrl failed because there are non-admin completion queues" "\n");
#line 3260 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_SQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_SQ) || \
    false)

static inline void trace_pci_nvme_err_startfail_sq(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_SQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 178 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_sq " "nvme_start_ctrl failed because there are non-admin submission queues" "\n");
#line 3275 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_ASQ_MISALIGNED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_ASQ_MISALIGNED) || \
    false)

static inline void trace_pci_nvme_err_startfail_asq_misaligned(uint64_t addr)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_ASQ_MISALIGNED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 179 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_asq_misaligned " "nvme_start_ctrl failed because the admin submission queue address is misaligned: 0x%"PRIx64"" "\n", addr);
#line 3290 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_ACQ_MISALIGNED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_ACQ_MISALIGNED) || \
    false)

static inline void trace_pci_nvme_err_startfail_acq_misaligned(uint64_t addr)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_ACQ_MISALIGNED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 180 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_acq_misaligned " "nvme_start_ctrl failed because the admin completion queue address is misaligned: 0x%"PRIx64"" "\n", addr);
#line 3305 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_SMALL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_SMALL) || \
    false)

static inline void trace_pci_nvme_err_startfail_page_too_small(uint8_t log2ps, uint8_t maxlog2ps)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_SMALL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 181 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_page_too_small " "nvme_start_ctrl failed because the page size is too small: log2size=%u, min=%u" "\n", log2ps, maxlog2ps);
#line 3320 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_LARGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_LARGE) || \
    false)

static inline void trace_pci_nvme_err_startfail_page_too_large(uint8_t log2ps, uint8_t maxlog2ps)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_LARGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 182 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_page_too_large " "nvme_start_ctrl failed because the page size is too large: log2size=%u, max=%u" "\n", log2ps, maxlog2ps);
#line 3335 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_SMALL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_SMALL) || \
    false)

static inline void trace_pci_nvme_err_startfail_cqent_too_small(uint8_t log2ps, uint8_t maxlog2ps)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_SMALL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 183 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_cqent_too_small " "nvme_start_ctrl failed because the completion queue entry size is too small: log2size=%u, min=%u" "\n", log2ps, maxlog2ps);
#line 3350 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_LARGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_LARGE) || \
    false)

static inline void trace_pci_nvme_err_startfail_cqent_too_large(uint8_t log2ps, uint8_t maxlog2ps)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_LARGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 184 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_cqent_too_large " "nvme_start_ctrl failed because the completion queue entry size is too large: log2size=%u, max=%u" "\n", log2ps, maxlog2ps);
#line 3365 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_SMALL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_SMALL) || \
    false)

static inline void trace_pci_nvme_err_startfail_sqent_too_small(uint8_t log2ps, uint8_t maxlog2ps)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_SMALL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 185 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_sqent_too_small " "nvme_start_ctrl failed because the submission queue entry size is too small: log2size=%u, min=%u" "\n", log2ps, maxlog2ps);
#line 3380 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_LARGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_LARGE) || \
    false)

static inline void trace_pci_nvme_err_startfail_sqent_too_large(uint8_t log2ps, uint8_t maxlog2ps)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_LARGE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 186 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_sqent_too_large " "nvme_start_ctrl failed because the submission queue entry size is too large: log2size=%u, max=%u" "\n", log2ps, maxlog2ps);
#line 3395 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_CSS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_CSS) || \
    false)

static inline void trace_pci_nvme_err_startfail_css(uint8_t css)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_CSS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 187 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_css " "nvme_start_ctrl failed because invalid command set selected:%u" "\n", css);
#line 3410 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_ASQENT_SZ_ZERO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_ASQENT_SZ_ZERO) || \
    false)

static inline void trace_pci_nvme_err_startfail_asqent_sz_zero(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_ASQENT_SZ_ZERO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 188 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_asqent_sz_zero " "nvme_start_ctrl failed because the admin submission queue size is zero" "\n");
#line 3425 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_ACQENT_SZ_ZERO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_ACQENT_SZ_ZERO) || \
    false)

static inline void trace_pci_nvme_err_startfail_acqent_sz_zero(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_ACQENT_SZ_ZERO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 189 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_acqent_sz_zero " "nvme_start_ctrl failed because the admin completion queue size is zero" "\n");
#line 3440 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_ZASL_TOO_SMALL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_ZASL_TOO_SMALL) || \
    false)

static inline void trace_pci_nvme_err_startfail_zasl_too_small(uint32_t zasl, uint32_t pagesz)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_ZASL_TOO_SMALL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 190 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_zasl_too_small " "nvme_start_ctrl failed because zone append size limit %"PRIu32" is too small, needs to be >= %"PRIu32"" "\n", zasl, pagesz);
#line 3455 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL) || \
    false)

static inline void trace_pci_nvme_err_startfail(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 191 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail " "setting controller enable bit failed" "\n");
#line 3470 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_STARTFAIL_VIRT_STATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_STARTFAIL_VIRT_STATE) || \
    false)

static inline void trace_pci_nvme_err_startfail_virt_state(uint16_t vq, uint16_t vi)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_STARTFAIL_VIRT_STATE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 192 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_startfail_virt_state " "nvme_start_ctrl failed due to ctrl state: vi=%u vq=%u" "\n", vq, vi);
#line 3485 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_INVALID_MGMT_ACTION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_INVALID_MGMT_ACTION) || \
    false)

static inline void trace_pci_nvme_err_invalid_mgmt_action(uint8_t action)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_INVALID_MGMT_ACTION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 193 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_invalid_mgmt_action " "action=0x%"PRIx8"" "\n", action);
#line 3500 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_ERR_IGNORED_MMIO_VF_OFFLINE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_ERR_IGNORED_MMIO_VF_OFFLINE) || \
    false)

static inline void trace_pci_nvme_err_ignored_mmio_vf_offline(uint64_t addr, unsigned size)
{
    if (trace_event_get_state(TRACE_PCI_NVME_ERR_IGNORED_MMIO_VF_OFFLINE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 194 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_err_ignored_mmio_vf_offline " "addr 0x%"PRIx64" size %d" "\n", addr, size);
#line 3515 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_MISALIGNED32_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_MISALIGNED32) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_misaligned32(uint64_t offset)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_MISALIGNED32)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 197 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_misaligned32 " "MMIO write not 32-bit aligned, offset=0x%"PRIx64"" "\n", offset);
#line 3530 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_TOOSMALL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_TOOSMALL) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_toosmall(uint64_t offset, unsigned size)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_TOOSMALL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 198 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_toosmall " "MMIO write smaller than 32 bits, offset=0x%"PRIx64", size=%u" "\n", offset, size);
#line 3545 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_INTMASK_WITH_MSIX_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_INTMASK_WITH_MSIX) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_intmask_with_msix(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_INTMASK_WITH_MSIX)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 199 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_intmask_with_msix " "undefined access to interrupt mask set when MSI-X is enabled" "\n");
#line 3560 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_RO_CSTS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_RO_CSTS) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_ro_csts(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_RO_CSTS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 200 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_ro_csts " "attempted to set a read only bit of controller status" "\n");
#line 3575 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_SSRESET_W1C_UNSUPPORTED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_SSRESET_W1C_UNSUPPORTED) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_ssreset_w1c_unsupported(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_SSRESET_W1C_UNSUPPORTED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 201 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_ssreset_w1c_unsupported " "attempted to W1C CSTS.NSSRO but CAP.NSSRS is zero (not supported)" "\n");
#line 3590 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_SSRESET_UNSUPPORTED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_SSRESET_UNSUPPORTED) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_ssreset_unsupported(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_SSRESET_UNSUPPORTED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 202 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_ssreset_unsupported " "attempted NVM subsystem reset but CAP.NSSRS is zero (not supported)" "\n");
#line 3605 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_CMBLOC_RESERVED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_CMBLOC_RESERVED) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_cmbloc_reserved(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_CMBLOC_RESERVED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 203 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_cmbloc_reserved " "invalid write to reserved CMBLOC when CMBSZ is zero, ignored" "\n");
#line 3620 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_CMBSZ_READONLY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_CMBSZ_READONLY) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_cmbsz_readonly(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_CMBSZ_READONLY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 204 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_cmbsz_readonly " "invalid write to read only CMBSZ, ignored" "\n");
#line 3635 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_PMRCAP_READONLY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_PMRCAP_READONLY) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_pmrcap_readonly(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_PMRCAP_READONLY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 205 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_pmrcap_readonly " "invalid write to read only PMRCAP, ignored" "\n");
#line 3650 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_PMRSTS_READONLY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_PMRSTS_READONLY) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_pmrsts_readonly(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_PMRSTS_READONLY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 206 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_pmrsts_readonly " "invalid write to read only PMRSTS, ignored" "\n");
#line 3665 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_PMREBS_READONLY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_PMREBS_READONLY) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_pmrebs_readonly(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_PMREBS_READONLY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 207 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_pmrebs_readonly " "invalid write to read only PMREBS, ignored" "\n");
#line 3680 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_PMRSWTP_READONLY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_PMRSWTP_READONLY) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_pmrswtp_readonly(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_PMRSWTP_READONLY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 208 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_pmrswtp_readonly " "invalid write to read only PMRSWTP, ignored" "\n");
#line 3695 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIOWR_INVALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIOWR_INVALID) || \
    false)

static inline void trace_pci_nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIOWR_INVALID)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 209 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiowr_invalid " "invalid MMIO write, offset=0x%"PRIx64", data=0x%"PRIx64"" "\n", offset, data);
#line 3710 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIORD_MISALIGNED32_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIORD_MISALIGNED32) || \
    false)

static inline void trace_pci_nvme_ub_mmiord_misaligned32(uint64_t offset)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIORD_MISALIGNED32)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 210 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiord_misaligned32 " "MMIO read not 32-bit aligned, offset=0x%"PRIx64"" "\n", offset);
#line 3725 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIORD_TOOSMALL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIORD_TOOSMALL) || \
    false)

static inline void trace_pci_nvme_ub_mmiord_toosmall(uint64_t offset)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIORD_TOOSMALL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 211 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiord_toosmall " "MMIO read smaller than 32-bits, offset=0x%"PRIx64"" "\n", offset);
#line 3740 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_MMIORD_INVALID_OFS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_MMIORD_INVALID_OFS) || \
    false)

static inline void trace_pci_nvme_ub_mmiord_invalid_ofs(uint64_t offset)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_MMIORD_INVALID_OFS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 212 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_mmiord_invalid_ofs " "MMIO read beyond last register, offset=0x%"PRIx64", returning 0" "\n", offset);
#line 3755 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_DB_WR_MISALIGNED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_DB_WR_MISALIGNED) || \
    false)

static inline void trace_pci_nvme_ub_db_wr_misaligned(uint64_t offset)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_DB_WR_MISALIGNED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 213 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_db_wr_misaligned " "doorbell write not 32-bit aligned, offset=0x%"PRIx64", ignoring" "\n", offset);
#line 3770 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_DB_WR_INVALID_CQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_DB_WR_INVALID_CQ) || \
    false)

static inline void trace_pci_nvme_ub_db_wr_invalid_cq(uint32_t qid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_DB_WR_INVALID_CQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 214 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_db_wr_invalid_cq " "completion queue doorbell write for nonexistent queue, cqid=%"PRIu32", ignoring" "\n", qid);
#line 3785 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_DB_WR_INVALID_CQHEAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_DB_WR_INVALID_CQHEAD) || \
    false)

static inline void trace_pci_nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_DB_WR_INVALID_CQHEAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 215 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_db_wr_invalid_cqhead " "completion queue doorbell write value beyond queue size, cqid=%"PRIu32", new_head=%"PRIu16", ignoring" "\n", qid, new_head);
#line 3800 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_DB_WR_INVALID_SQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_DB_WR_INVALID_SQ) || \
    false)

static inline void trace_pci_nvme_ub_db_wr_invalid_sq(uint32_t qid)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_DB_WR_INVALID_SQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 216 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_db_wr_invalid_sq " "submission queue doorbell write for nonexistent queue, sqid=%"PRIu32", ignoring" "\n", qid);
#line 3815 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_DB_WR_INVALID_SQTAIL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_DB_WR_INVALID_SQTAIL) || \
    false)

static inline void trace_pci_nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_DB_WR_INVALID_SQTAIL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 217 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_db_wr_invalid_sqtail " "submission queue doorbell write value beyond queue size, sqid=%"PRIu32", new_head=%"PRIu16", ignoring" "\n", qid, new_tail);
#line 3830 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_UNKNOWN_CSS_VALUE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_UNKNOWN_CSS_VALUE) || \
    false)

static inline void trace_pci_nvme_ub_unknown_css_value(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_UNKNOWN_CSS_VALUE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 218 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_unknown_css_value " "unknown value in cc.css field" "\n");
#line 3845 "trace/trace-hw_nvme.h"
        }
    }
}

#define TRACE_PCI_NVME_UB_TOO_MANY_MAPPINGS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCI_NVME_UB_TOO_MANY_MAPPINGS) || \
    false)

static inline void trace_pci_nvme_ub_too_many_mappings(void)
{
    if (trace_event_get_state(TRACE_PCI_NVME_UB_TOO_MANY_MAPPINGS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 219 "../hw/nvme/trace-events"
            qemu_log("pci_nvme_ub_too_many_mappings " "too many prp/sgl mappings" "\n");
#line 3860 "trace/trace-hw_nvme.h"
        }
    }
}
#endif /* TRACE_HW_NVME_GENERATED_TRACERS_H */
