/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_HW_TPM_GENERATED_TRACERS_H
#define TRACE_HW_TPM_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_TPM_CRB_MMIO_READ_EVENT;
extern TraceEvent _TRACE_TPM_CRB_MMIO_WRITE_EVENT;
extern TraceEvent _TRACE_TPM_TIS_RAISE_IRQ_EVENT;
extern TraceEvent _TRACE_TPM_TIS_NEW_ACTIVE_LOCALITY_EVENT;
extern TraceEvent _TRACE_TPM_TIS_ABORT_EVENT;
extern TraceEvent _TRACE_TPM_TIS_DATA_READ_EVENT;
extern TraceEvent _TRACE_TPM_TIS_MMIO_READ_EVENT;
extern TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_EVENT;
extern TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_LOCTY4_EVENT;
extern TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_RELEASE_LOCTY_EVENT;
extern TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_LOCTY_REQ_USE_EVENT;
extern TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_NEXT_LOCTY_EVENT;
extern TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_LOCTY_SEIZED_EVENT;
extern TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_INIT_ABORT_EVENT;
extern TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_LOWERING_IRQ_EVENT;
extern TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_DATA2SEND_EVENT;
extern TraceEvent _TRACE_TPM_TIS_PRE_SAVE_EVENT;
extern TraceEvent _TRACE_TPM_PPI_MEMSET_EVENT;
extern TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_EVENT;
extern TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_CRQ_RESULT_EVENT;
extern TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_CRQ_COMPLETE_RESULT_EVENT;
extern TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_TPM_COMMAND_EVENT;
extern TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_TPM_GET_RTCE_BUFFER_SIZE_EVENT;
extern TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_GET_VERSION_EVENT;
extern TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_PREPARE_TO_SUSPEND_EVENT;
extern TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_MSG_TYPE_EVENT;
extern TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_CRQ_EVENT;
extern TraceEvent _TRACE_TPM_SPAPR_POST_LOAD_EVENT;
extern TraceEvent _TRACE_TPM_SPAPR_CAUGHT_RESPONSE_EVENT;
extern TraceEvent _TRACE_TPM_TIS_I2C_RECV_EVENT;
extern TraceEvent _TRACE_TPM_TIS_I2C_SEND_EVENT;
extern TraceEvent _TRACE_TPM_TIS_I2C_EVENT_EVENT;
extern TraceEvent _TRACE_TPM_TIS_I2C_SEND_REG_EVENT;
extern uint16_t _TRACE_TPM_CRB_MMIO_READ_DSTATE;
extern uint16_t _TRACE_TPM_CRB_MMIO_WRITE_DSTATE;
extern uint16_t _TRACE_TPM_TIS_RAISE_IRQ_DSTATE;
extern uint16_t _TRACE_TPM_TIS_NEW_ACTIVE_LOCALITY_DSTATE;
extern uint16_t _TRACE_TPM_TIS_ABORT_DSTATE;
extern uint16_t _TRACE_TPM_TIS_DATA_READ_DSTATE;
extern uint16_t _TRACE_TPM_TIS_MMIO_READ_DSTATE;
extern uint16_t _TRACE_TPM_TIS_MMIO_WRITE_DSTATE;
extern uint16_t _TRACE_TPM_TIS_MMIO_WRITE_LOCTY4_DSTATE;
extern uint16_t _TRACE_TPM_TIS_MMIO_WRITE_RELEASE_LOCTY_DSTATE;
extern uint16_t _TRACE_TPM_TIS_MMIO_WRITE_LOCTY_REQ_USE_DSTATE;
extern uint16_t _TRACE_TPM_TIS_MMIO_WRITE_NEXT_LOCTY_DSTATE;
extern uint16_t _TRACE_TPM_TIS_MMIO_WRITE_LOCTY_SEIZED_DSTATE;
extern uint16_t _TRACE_TPM_TIS_MMIO_WRITE_INIT_ABORT_DSTATE;
extern uint16_t _TRACE_TPM_TIS_MMIO_WRITE_LOWERING_IRQ_DSTATE;
extern uint16_t _TRACE_TPM_TIS_MMIO_WRITE_DATA2SEND_DSTATE;
extern uint16_t _TRACE_TPM_TIS_PRE_SAVE_DSTATE;
extern uint16_t _TRACE_TPM_PPI_MEMSET_DSTATE;
extern uint16_t _TRACE_TPM_SPAPR_DO_CRQ_DSTATE;
extern uint16_t _TRACE_TPM_SPAPR_DO_CRQ_CRQ_RESULT_DSTATE;
extern uint16_t _TRACE_TPM_SPAPR_DO_CRQ_CRQ_COMPLETE_RESULT_DSTATE;
extern uint16_t _TRACE_TPM_SPAPR_DO_CRQ_TPM_COMMAND_DSTATE;
extern uint16_t _TRACE_TPM_SPAPR_DO_CRQ_TPM_GET_RTCE_BUFFER_SIZE_DSTATE;
extern uint16_t _TRACE_TPM_SPAPR_DO_CRQ_GET_VERSION_DSTATE;
extern uint16_t _TRACE_TPM_SPAPR_DO_CRQ_PREPARE_TO_SUSPEND_DSTATE;
extern uint16_t _TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_MSG_TYPE_DSTATE;
extern uint16_t _TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_CRQ_DSTATE;
extern uint16_t _TRACE_TPM_SPAPR_POST_LOAD_DSTATE;
extern uint16_t _TRACE_TPM_SPAPR_CAUGHT_RESPONSE_DSTATE;
extern uint16_t _TRACE_TPM_TIS_I2C_RECV_DSTATE;
extern uint16_t _TRACE_TPM_TIS_I2C_SEND_DSTATE;
extern uint16_t _TRACE_TPM_TIS_I2C_EVENT_DSTATE;
extern uint16_t _TRACE_TPM_TIS_I2C_SEND_REG_DSTATE;
#define TRACE_TPM_CRB_MMIO_READ_ENABLED 1
#define TRACE_TPM_CRB_MMIO_WRITE_ENABLED 1
#define TRACE_TPM_TIS_RAISE_IRQ_ENABLED 1
#define TRACE_TPM_TIS_NEW_ACTIVE_LOCALITY_ENABLED 1
#define TRACE_TPM_TIS_ABORT_ENABLED 1
#define TRACE_TPM_TIS_DATA_READ_ENABLED 1
#define TRACE_TPM_TIS_MMIO_READ_ENABLED 1
#define TRACE_TPM_TIS_MMIO_WRITE_ENABLED 1
#define TRACE_TPM_TIS_MMIO_WRITE_LOCTY4_ENABLED 1
#define TRACE_TPM_TIS_MMIO_WRITE_RELEASE_LOCTY_ENABLED 1
#define TRACE_TPM_TIS_MMIO_WRITE_LOCTY_REQ_USE_ENABLED 1
#define TRACE_TPM_TIS_MMIO_WRITE_NEXT_LOCTY_ENABLED 1
#define TRACE_TPM_TIS_MMIO_WRITE_LOCTY_SEIZED_ENABLED 1
#define TRACE_TPM_TIS_MMIO_WRITE_INIT_ABORT_ENABLED 1
#define TRACE_TPM_TIS_MMIO_WRITE_LOWERING_IRQ_ENABLED 1
#define TRACE_TPM_TIS_MMIO_WRITE_DATA2SEND_ENABLED 1
#define TRACE_TPM_TIS_PRE_SAVE_ENABLED 1
#define TRACE_TPM_PPI_MEMSET_ENABLED 1
#define TRACE_TPM_SPAPR_DO_CRQ_ENABLED 1
#define TRACE_TPM_SPAPR_DO_CRQ_CRQ_RESULT_ENABLED 1
#define TRACE_TPM_SPAPR_DO_CRQ_CRQ_COMPLETE_RESULT_ENABLED 1
#define TRACE_TPM_SPAPR_DO_CRQ_TPM_COMMAND_ENABLED 1
#define TRACE_TPM_SPAPR_DO_CRQ_TPM_GET_RTCE_BUFFER_SIZE_ENABLED 1
#define TRACE_TPM_SPAPR_DO_CRQ_GET_VERSION_ENABLED 1
#define TRACE_TPM_SPAPR_DO_CRQ_PREPARE_TO_SUSPEND_ENABLED 1
#define TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_MSG_TYPE_ENABLED 1
#define TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_CRQ_ENABLED 1
#define TRACE_TPM_SPAPR_POST_LOAD_ENABLED 1
#define TRACE_TPM_SPAPR_CAUGHT_RESPONSE_ENABLED 1
#define TRACE_TPM_TIS_I2C_RECV_ENABLED 1
#define TRACE_TPM_TIS_I2C_SEND_ENABLED 1
#define TRACE_TPM_TIS_I2C_EVENT_ENABLED 1
#define TRACE_TPM_TIS_I2C_SEND_REG_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_TPM_CRB_MMIO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_CRB_MMIO_READ) || \
    false)

static inline void trace_tpm_crb_mmio_read(uint64_t addr, unsigned size, uint32_t val)
{
    if (trace_event_get_state(TRACE_TPM_CRB_MMIO_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 4 "../hw/tpm/trace-events"
            qemu_log("tpm_crb_mmio_read " "CRB read 0x%016" PRIx64 " len:%u val: 0x%" PRIx32 "\n", addr, size, val);
#line 122 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_CRB_MMIO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_CRB_MMIO_WRITE) || \
    false)

static inline void trace_tpm_crb_mmio_write(uint64_t addr, unsigned size, uint32_t val)
{
    if (trace_event_get_state(TRACE_TPM_CRB_MMIO_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 5 "../hw/tpm/trace-events"
            qemu_log("tpm_crb_mmio_write " "CRB write 0x%016" PRIx64 " len:%u val: 0x%" PRIx32 "\n", addr, size, val);
#line 137 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_RAISE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_RAISE_IRQ) || \
    false)

static inline void trace_tpm_tis_raise_irq(uint32_t irqmask)
{
    if (trace_event_get_state(TRACE_TPM_TIS_RAISE_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 8 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_raise_irq " "Raising IRQ for flag 0x%08x" "\n", irqmask);
#line 152 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_NEW_ACTIVE_LOCALITY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_NEW_ACTIVE_LOCALITY) || \
    false)

static inline void trace_tpm_tis_new_active_locality(uint8_t locty)
{
    if (trace_event_get_state(TRACE_TPM_TIS_NEW_ACTIVE_LOCALITY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 9 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_new_active_locality " "Active locality is now %d" "\n", locty);
#line 167 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_ABORT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_ABORT) || \
    false)

static inline void trace_tpm_tis_abort(uint8_t locty)
{
    if (trace_event_get_state(TRACE_TPM_TIS_ABORT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 10 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_abort " "New active locality is %d" "\n", locty);
#line 182 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_DATA_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_DATA_READ) || \
    false)

static inline void trace_tpm_tis_data_read(uint32_t value, uint32_t off)
{
    if (trace_event_get_state(TRACE_TPM_TIS_DATA_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 11 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_data_read " "byte 0x%02x   [%d]" "\n", value, off);
#line 197 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_MMIO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_MMIO_READ) || \
    false)

static inline void trace_tpm_tis_mmio_read(unsigned size, uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_TPM_TIS_MMIO_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 12 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_mmio_read " " read.%u(0x%08x) = 0x%08x" "\n", size, addr, val);
#line 212 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_MMIO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_MMIO_WRITE) || \
    false)

static inline void trace_tpm_tis_mmio_write(unsigned size, uint32_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_TPM_TIS_MMIO_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 13 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_mmio_write " "write.%u(0x%08x) = 0x%08x" "\n", size, addr, val);
#line 227 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_MMIO_WRITE_LOCTY4_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_MMIO_WRITE_LOCTY4) || \
    false)

static inline void trace_tpm_tis_mmio_write_locty4(void)
{
    if (trace_event_get_state(TRACE_TPM_TIS_MMIO_WRITE_LOCTY4)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_mmio_write_locty4 " "Access to locality 4 only allowed from hardware" "\n");
#line 242 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_MMIO_WRITE_RELEASE_LOCTY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_MMIO_WRITE_RELEASE_LOCTY) || \
    false)

static inline void trace_tpm_tis_mmio_write_release_locty(uint8_t locty)
{
    if (trace_event_get_state(TRACE_TPM_TIS_MMIO_WRITE_RELEASE_LOCTY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_mmio_write_release_locty " "Releasing locality %d" "\n", locty);
#line 257 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_MMIO_WRITE_LOCTY_REQ_USE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_MMIO_WRITE_LOCTY_REQ_USE) || \
    false)

static inline void trace_tpm_tis_mmio_write_locty_req_use(uint8_t locty)
{
    if (trace_event_get_state(TRACE_TPM_TIS_MMIO_WRITE_LOCTY_REQ_USE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_mmio_write_locty_req_use " "Locality %d requests use" "\n", locty);
#line 272 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_MMIO_WRITE_NEXT_LOCTY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_MMIO_WRITE_NEXT_LOCTY) || \
    false)

static inline void trace_tpm_tis_mmio_write_next_locty(uint8_t locty)
{
    if (trace_event_get_state(TRACE_TPM_TIS_MMIO_WRITE_NEXT_LOCTY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 17 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_mmio_write_next_locty " "Next active locality is %d" "\n", locty);
#line 287 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_MMIO_WRITE_LOCTY_SEIZED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_MMIO_WRITE_LOCTY_SEIZED) || \
    false)

static inline void trace_tpm_tis_mmio_write_locty_seized(uint8_t locty, uint8_t active)
{
    if (trace_event_get_state(TRACE_TPM_TIS_MMIO_WRITE_LOCTY_SEIZED)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 18 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_mmio_write_locty_seized " "Locality %d seized from locality %d" "\n", locty, active);
#line 302 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_MMIO_WRITE_INIT_ABORT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_MMIO_WRITE_INIT_ABORT) || \
    false)

static inline void trace_tpm_tis_mmio_write_init_abort(void)
{
    if (trace_event_get_state(TRACE_TPM_TIS_MMIO_WRITE_INIT_ABORT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 19 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_mmio_write_init_abort " "Initiating abort" "\n");
#line 317 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_MMIO_WRITE_LOWERING_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_MMIO_WRITE_LOWERING_IRQ) || \
    false)

static inline void trace_tpm_tis_mmio_write_lowering_irq(void)
{
    if (trace_event_get_state(TRACE_TPM_TIS_MMIO_WRITE_LOWERING_IRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_mmio_write_lowering_irq " "Lowering IRQ" "\n");
#line 332 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_MMIO_WRITE_DATA2SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_MMIO_WRITE_DATA2SEND) || \
    false)

static inline void trace_tpm_tis_mmio_write_data2send(uint32_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_TPM_TIS_MMIO_WRITE_DATA2SEND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 21 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_mmio_write_data2send " "Data to send to TPM: 0x%08x (size=%d)" "\n", value, size);
#line 347 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_PRE_SAVE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_PRE_SAVE) || \
    false)

static inline void trace_tpm_tis_pre_save(uint8_t locty, uint32_t rw_offset)
{
    if (trace_event_get_state(TRACE_TPM_TIS_PRE_SAVE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 22 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_pre_save " "locty: %d, rw_offset = %u" "\n", locty, rw_offset);
#line 362 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_PPI_MEMSET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_PPI_MEMSET) || \
    false)

static inline void trace_tpm_ppi_memset(uint8_t *ptr, size_t size)
{
    if (trace_event_get_state(TRACE_TPM_PPI_MEMSET)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 25 "../hw/tpm/trace-events"
            qemu_log("tpm_ppi_memset " "memset: %p %zu" "\n", ptr, size);
#line 377 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_SPAPR_DO_CRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_SPAPR_DO_CRQ) || \
    false)

static inline void trace_tpm_spapr_do_crq(uint8_t raw1, uint8_t raw2)
{
    if (trace_event_get_state(TRACE_TPM_SPAPR_DO_CRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 28 "../hw/tpm/trace-events"
            qemu_log("tpm_spapr_do_crq " "1st 2 bytes in CRQ: 0x%02x 0x%02x" "\n", raw1, raw2);
#line 392 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_SPAPR_DO_CRQ_CRQ_RESULT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_SPAPR_DO_CRQ_CRQ_RESULT) || \
    false)

static inline void trace_tpm_spapr_do_crq_crq_result(void)
{
    if (trace_event_get_state(TRACE_TPM_SPAPR_DO_CRQ_CRQ_RESULT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 29 "../hw/tpm/trace-events"
            qemu_log("tpm_spapr_do_crq_crq_result " "SPAPR_VTPM_INIT_CRQ_RESULT" "\n");
#line 407 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_SPAPR_DO_CRQ_CRQ_COMPLETE_RESULT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_SPAPR_DO_CRQ_CRQ_COMPLETE_RESULT) || \
    false)

static inline void trace_tpm_spapr_do_crq_crq_complete_result(void)
{
    if (trace_event_get_state(TRACE_TPM_SPAPR_DO_CRQ_CRQ_COMPLETE_RESULT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 30 "../hw/tpm/trace-events"
            qemu_log("tpm_spapr_do_crq_crq_complete_result " "SPAPR_VTPM_INIT_CRQ_COMP_RESULT" "\n");
#line 422 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_SPAPR_DO_CRQ_TPM_COMMAND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_SPAPR_DO_CRQ_TPM_COMMAND) || \
    false)

static inline void trace_tpm_spapr_do_crq_tpm_command(void)
{
    if (trace_event_get_state(TRACE_TPM_SPAPR_DO_CRQ_TPM_COMMAND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 31 "../hw/tpm/trace-events"
            qemu_log("tpm_spapr_do_crq_tpm_command " "got TPM command payload" "\n");
#line 437 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_SPAPR_DO_CRQ_TPM_GET_RTCE_BUFFER_SIZE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_SPAPR_DO_CRQ_TPM_GET_RTCE_BUFFER_SIZE) || \
    false)

static inline void trace_tpm_spapr_do_crq_tpm_get_rtce_buffer_size(size_t buffersize)
{
    if (trace_event_get_state(TRACE_TPM_SPAPR_DO_CRQ_TPM_GET_RTCE_BUFFER_SIZE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 32 "../hw/tpm/trace-events"
            qemu_log("tpm_spapr_do_crq_tpm_get_rtce_buffer_size " "response: buffer size is %zu" "\n", buffersize);
#line 452 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_SPAPR_DO_CRQ_GET_VERSION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_SPAPR_DO_CRQ_GET_VERSION) || \
    false)

static inline void trace_tpm_spapr_do_crq_get_version(uint32_t version)
{
    if (trace_event_get_state(TRACE_TPM_SPAPR_DO_CRQ_GET_VERSION)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 33 "../hw/tpm/trace-events"
            qemu_log("tpm_spapr_do_crq_get_version " "response: version %u" "\n", version);
#line 467 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_SPAPR_DO_CRQ_PREPARE_TO_SUSPEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_SPAPR_DO_CRQ_PREPARE_TO_SUSPEND) || \
    false)

static inline void trace_tpm_spapr_do_crq_prepare_to_suspend(void)
{
    if (trace_event_get_state(TRACE_TPM_SPAPR_DO_CRQ_PREPARE_TO_SUSPEND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 34 "../hw/tpm/trace-events"
            qemu_log("tpm_spapr_do_crq_prepare_to_suspend " "response: preparing to suspend" "\n");
#line 482 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_MSG_TYPE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_MSG_TYPE) || \
    false)

static inline void trace_tpm_spapr_do_crq_unknown_msg_type(uint8_t type)
{
    if (trace_event_get_state(TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_MSG_TYPE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 35 "../hw/tpm/trace-events"
            qemu_log("tpm_spapr_do_crq_unknown_msg_type " "Unknown message type 0x%02x" "\n", type);
#line 497 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_CRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_CRQ) || \
    false)

static inline void trace_tpm_spapr_do_crq_unknown_crq(uint8_t raw1, uint8_t raw2)
{
    if (trace_event_get_state(TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_CRQ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 36 "../hw/tpm/trace-events"
            qemu_log("tpm_spapr_do_crq_unknown_crq " "unknown CRQ 0x%02x 0x%02x ..." "\n", raw1, raw2);
#line 512 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_SPAPR_POST_LOAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_SPAPR_POST_LOAD) || \
    false)

static inline void trace_tpm_spapr_post_load(void)
{
    if (trace_event_get_state(TRACE_TPM_SPAPR_POST_LOAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 37 "../hw/tpm/trace-events"
            qemu_log("tpm_spapr_post_load " "Delivering TPM response after resume" "\n");
#line 527 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_SPAPR_CAUGHT_RESPONSE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_SPAPR_CAUGHT_RESPONSE) || \
    false)

static inline void trace_tpm_spapr_caught_response(uint32_t v)
{
    if (trace_event_get_state(TRACE_TPM_SPAPR_CAUGHT_RESPONSE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 38 "../hw/tpm/trace-events"
            qemu_log("tpm_spapr_caught_response " "Caught response to deliver after resume: %u bytes" "\n", v);
#line 542 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_I2C_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_I2C_RECV) || \
    false)

static inline void trace_tpm_tis_i2c_recv(uint8_t data)
{
    if (trace_event_get_state(TRACE_TPM_TIS_I2C_RECV)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 41 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_i2c_recv " "TPM I2C read: 0x%X" "\n", data);
#line 557 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_I2C_SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_I2C_SEND) || \
    false)

static inline void trace_tpm_tis_i2c_send(uint8_t data)
{
    if (trace_event_get_state(TRACE_TPM_TIS_I2C_SEND)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 42 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_i2c_send " "TPM I2C write: 0x%X" "\n", data);
#line 572 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_I2C_EVENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_I2C_EVENT) || \
    false)

static inline void trace_tpm_tis_i2c_event(const char *event)
{
    if (trace_event_get_state(TRACE_TPM_TIS_I2C_EVENT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 43 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_i2c_event " "TPM I2C event: %s" "\n", event);
#line 587 "trace/trace-hw_tpm.h"
        }
    }
}

#define TRACE_TPM_TIS_I2C_SEND_REG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_TPM_TIS_I2C_SEND_REG) || \
    false)

static inline void trace_tpm_tis_i2c_send_reg(const char *name, int reg)
{
    if (trace_event_get_state(TRACE_TPM_TIS_I2C_SEND_REG)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 44 "../hw/tpm/trace-events"
            qemu_log("tpm_tis_i2c_send_reg " "TPM I2C write register: %s(0x%X)" "\n", name, reg);
#line 602 "trace/trace-hw_tpm.h"
        }
    }
}
#endif /* TRACE_HW_TPM_GENERATED_TRACERS_H */
