/* This file is autogenerated by tracetool, do not edit. */
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef TRACE_ACCEL_MSHV_GENERATED_TRACERS_H
#define TRACE_ACCEL_MSHV_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_MSHV_START_VCPU_THREAD_EVENT;
extern TraceEvent _TRACE_MSHV_SET_MEMORY_EVENT;
extern TraceEvent _TRACE_MSHV_MEM_IOEVENTFD_ADD_EVENT;
extern TraceEvent _TRACE_MSHV_MEM_IOEVENTFD_DEL_EVENT;
extern TraceEvent _TRACE_MSHV_HVCALL_ARGS_EVENT;
extern TraceEvent _TRACE_MSHV_HANDLE_INTERRUPT_EVENT;
extern TraceEvent _TRACE_MSHV_SET_MSI_ROUTING_EVENT;
extern TraceEvent _TRACE_MSHV_REMOVE_MSI_ROUTING_EVENT;
extern TraceEvent _TRACE_MSHV_ADD_MSI_ROUTING_EVENT;
extern TraceEvent _TRACE_MSHV_COMMIT_MSI_ROUTING_TABLE_EVENT;
extern TraceEvent _TRACE_MSHV_REGISTER_IRQFD_EVENT;
extern TraceEvent _TRACE_MSHV_IRQCHIP_UPDATE_IRQFD_NOTIFIER_GSI_EVENT;
extern TraceEvent _TRACE_MSHV_INSN_FETCH_EVENT;
extern TraceEvent _TRACE_MSHV_MEM_WRITE_EVENT;
extern TraceEvent _TRACE_MSHV_MEM_READ_EVENT;
extern TraceEvent _TRACE_MSHV_MAP_MEMORY_EVENT;
extern TraceEvent _TRACE_MSHV_UNMAP_MEMORY_EVENT;
extern TraceEvent _TRACE_MSHV_SET_PHYS_MEM_EVENT;
extern TraceEvent _TRACE_MSHV_HANDLE_MMIO_EVENT;
extern uint16_t _TRACE_MSHV_START_VCPU_THREAD_DSTATE;
extern uint16_t _TRACE_MSHV_SET_MEMORY_DSTATE;
extern uint16_t _TRACE_MSHV_MEM_IOEVENTFD_ADD_DSTATE;
extern uint16_t _TRACE_MSHV_MEM_IOEVENTFD_DEL_DSTATE;
extern uint16_t _TRACE_MSHV_HVCALL_ARGS_DSTATE;
extern uint16_t _TRACE_MSHV_HANDLE_INTERRUPT_DSTATE;
extern uint16_t _TRACE_MSHV_SET_MSI_ROUTING_DSTATE;
extern uint16_t _TRACE_MSHV_REMOVE_MSI_ROUTING_DSTATE;
extern uint16_t _TRACE_MSHV_ADD_MSI_ROUTING_DSTATE;
extern uint16_t _TRACE_MSHV_COMMIT_MSI_ROUTING_TABLE_DSTATE;
extern uint16_t _TRACE_MSHV_REGISTER_IRQFD_DSTATE;
extern uint16_t _TRACE_MSHV_IRQCHIP_UPDATE_IRQFD_NOTIFIER_GSI_DSTATE;
extern uint16_t _TRACE_MSHV_INSN_FETCH_DSTATE;
extern uint16_t _TRACE_MSHV_MEM_WRITE_DSTATE;
extern uint16_t _TRACE_MSHV_MEM_READ_DSTATE;
extern uint16_t _TRACE_MSHV_MAP_MEMORY_DSTATE;
extern uint16_t _TRACE_MSHV_UNMAP_MEMORY_DSTATE;
extern uint16_t _TRACE_MSHV_SET_PHYS_MEM_DSTATE;
extern uint16_t _TRACE_MSHV_HANDLE_MMIO_DSTATE;
#define TRACE_MSHV_START_VCPU_THREAD_ENABLED 1
#define TRACE_MSHV_SET_MEMORY_ENABLED 1
#define TRACE_MSHV_MEM_IOEVENTFD_ADD_ENABLED 1
#define TRACE_MSHV_MEM_IOEVENTFD_DEL_ENABLED 1
#define TRACE_MSHV_HVCALL_ARGS_ENABLED 1
#define TRACE_MSHV_HANDLE_INTERRUPT_ENABLED 1
#define TRACE_MSHV_SET_MSI_ROUTING_ENABLED 1
#define TRACE_MSHV_REMOVE_MSI_ROUTING_ENABLED 1
#define TRACE_MSHV_ADD_MSI_ROUTING_ENABLED 1
#define TRACE_MSHV_COMMIT_MSI_ROUTING_TABLE_ENABLED 1
#define TRACE_MSHV_REGISTER_IRQFD_ENABLED 1
#define TRACE_MSHV_IRQCHIP_UPDATE_IRQFD_NOTIFIER_GSI_ENABLED 1
#define TRACE_MSHV_INSN_FETCH_ENABLED 1
#define TRACE_MSHV_MEM_WRITE_ENABLED 1
#define TRACE_MSHV_MEM_READ_ENABLED 1
#define TRACE_MSHV_MAP_MEMORY_ENABLED 1
#define TRACE_MSHV_UNMAP_MEMORY_ENABLED 1
#define TRACE_MSHV_SET_PHYS_MEM_ENABLED 1
#define TRACE_MSHV_HANDLE_MMIO_ENABLED 1
#include "qemu/log-for-trace.h"


#define TRACE_MSHV_START_VCPU_THREAD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_START_VCPU_THREAD) || \
    false)

static inline void trace_mshv_start_vcpu_thread(const char*thread, uint32_t cpu)
{
    if (trace_event_get_state(TRACE_MSHV_START_VCPU_THREAD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 6 "../accel/mshv/trace-events"
            qemu_log("mshv_start_vcpu_thread " "thread=%s cpu_index=%d" "\n", thread, cpu);
#line 80 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_SET_MEMORY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_SET_MEMORY) || \
    false)

static inline void trace_mshv_set_memory(bool add, uint64_t gpa, uint64_t size, uint64_t user_addr, bool readonly, int ret)
{
    if (trace_event_get_state(TRACE_MSHV_SET_MEMORY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 8 "../accel/mshv/trace-events"
            qemu_log("mshv_set_memory " "add=%d gpa=0x%" PRIx64 " size=0x%" PRIx64 " user=0x%" PRIx64 " readonly=%d result=%d" "\n", add, gpa, size, user_addr, readonly, ret);
#line 95 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_MEM_IOEVENTFD_ADD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_MEM_IOEVENTFD_ADD) || \
    false)

static inline void trace_mshv_mem_ioeventfd_add(uint64_t addr, uint32_t size, uint32_t data)
{
    if (trace_event_get_state(TRACE_MSHV_MEM_IOEVENTFD_ADD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 9 "../accel/mshv/trace-events"
            qemu_log("mshv_mem_ioeventfd_add " "addr=0x%" PRIx64 " size=%d data=0x%x" "\n", addr, size, data);
#line 110 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_MEM_IOEVENTFD_DEL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_MEM_IOEVENTFD_DEL) || \
    false)

static inline void trace_mshv_mem_ioeventfd_del(uint64_t addr, uint32_t size, uint32_t data)
{
    if (trace_event_get_state(TRACE_MSHV_MEM_IOEVENTFD_DEL)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 10 "../accel/mshv/trace-events"
            qemu_log("mshv_mem_ioeventfd_del " "addr=0x%" PRIx64 " size=%d data=0x%x" "\n", addr, size, data);
#line 125 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_HVCALL_ARGS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_HVCALL_ARGS) || \
    false)

static inline void trace_mshv_hvcall_args(const char*hvcall, uint16_t code, uint16_t in_sz)
{
    if (trace_event_get_state(TRACE_MSHV_HVCALL_ARGS)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 12 "../accel/mshv/trace-events"
            qemu_log("mshv_hvcall_args " "built args for '%s' code: %d in_sz: %d" "\n", hvcall, code, in_sz);
#line 140 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_HANDLE_INTERRUPT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_HANDLE_INTERRUPT) || \
    false)

static inline void trace_mshv_handle_interrupt(uint32_t cpu, int mask)
{
    if (trace_event_get_state(TRACE_MSHV_HANDLE_INTERRUPT)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 14 "../accel/mshv/trace-events"
            qemu_log("mshv_handle_interrupt " "cpu_index=%d mask=0x%x" "\n", cpu, mask);
#line 155 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_SET_MSI_ROUTING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_SET_MSI_ROUTING) || \
    false)

static inline void trace_mshv_set_msi_routing(uint32_t gsi, uint64_t addr, uint32_t data)
{
    if (trace_event_get_state(TRACE_MSHV_SET_MSI_ROUTING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 15 "../accel/mshv/trace-events"
            qemu_log("mshv_set_msi_routing " "gsi=%d addr=0x%" PRIx64 " data=0x%x" "\n", gsi, addr, data);
#line 170 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_REMOVE_MSI_ROUTING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_REMOVE_MSI_ROUTING) || \
    false)

static inline void trace_mshv_remove_msi_routing(uint32_t gsi)
{
    if (trace_event_get_state(TRACE_MSHV_REMOVE_MSI_ROUTING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 16 "../accel/mshv/trace-events"
            qemu_log("mshv_remove_msi_routing " "gsi=%d" "\n", gsi);
#line 185 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_ADD_MSI_ROUTING_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_ADD_MSI_ROUTING) || \
    false)

static inline void trace_mshv_add_msi_routing(uint64_t addr, uint32_t data)
{
    if (trace_event_get_state(TRACE_MSHV_ADD_MSI_ROUTING)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 17 "../accel/mshv/trace-events"
            qemu_log("mshv_add_msi_routing " "addr=0x%" PRIx64 " data=0x%x" "\n", addr, data);
#line 200 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_COMMIT_MSI_ROUTING_TABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_COMMIT_MSI_ROUTING_TABLE) || \
    false)

static inline void trace_mshv_commit_msi_routing_table(int vm_fd, int len)
{
    if (trace_event_get_state(TRACE_MSHV_COMMIT_MSI_ROUTING_TABLE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 18 "../accel/mshv/trace-events"
            qemu_log("mshv_commit_msi_routing_table " "vm_fd=%d table_size=%d" "\n", vm_fd, len);
#line 215 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_REGISTER_IRQFD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_REGISTER_IRQFD) || \
    false)

static inline void trace_mshv_register_irqfd(int vm_fd, int event_fd, uint32_t gsi)
{
    if (trace_event_get_state(TRACE_MSHV_REGISTER_IRQFD)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 19 "../accel/mshv/trace-events"
            qemu_log("mshv_register_irqfd " "vm_fd=%d event_fd=%d gsi=%d" "\n", vm_fd, event_fd, gsi);
#line 230 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_IRQCHIP_UPDATE_IRQFD_NOTIFIER_GSI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_IRQCHIP_UPDATE_IRQFD_NOTIFIER_GSI) || \
    false)

static inline void trace_mshv_irqchip_update_irqfd_notifier_gsi(int event_fd, int resample_fd, int virq, bool add)
{
    if (trace_event_get_state(TRACE_MSHV_IRQCHIP_UPDATE_IRQFD_NOTIFIER_GSI)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 20 "../accel/mshv/trace-events"
            qemu_log("mshv_irqchip_update_irqfd_notifier_gsi " "event_fd=%d resample_fd=%d virq=%d add=%d" "\n", event_fd, resample_fd, virq, add);
#line 245 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_INSN_FETCH_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_INSN_FETCH) || \
    false)

static inline void trace_mshv_insn_fetch(uint64_t addr, size_t size)
{
    if (trace_event_get_state(TRACE_MSHV_INSN_FETCH)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 22 "../accel/mshv/trace-events"
            qemu_log("mshv_insn_fetch " "gpa=0x%" PRIx64 " size=%zu" "\n", addr, size);
#line 260 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_MEM_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_MEM_WRITE) || \
    false)

static inline void trace_mshv_mem_write(uint64_t addr, size_t size)
{
    if (trace_event_get_state(TRACE_MSHV_MEM_WRITE)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 23 "../accel/mshv/trace-events"
            qemu_log("mshv_mem_write " "\tgpa=0x%" PRIx64 " size=%zu" "\n", addr, size);
#line 275 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_MEM_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_MEM_READ) || \
    false)

static inline void trace_mshv_mem_read(uint64_t addr, size_t size)
{
    if (trace_event_get_state(TRACE_MSHV_MEM_READ)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 24 "../accel/mshv/trace-events"
            qemu_log("mshv_mem_read " "\tgpa=0x%" PRIx64 " size=%zu" "\n", addr, size);
#line 290 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_MAP_MEMORY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_MAP_MEMORY) || \
    false)

static inline void trace_mshv_map_memory(uint64_t userspace_addr, uint64_t gpa, uint64_t size)
{
    if (trace_event_get_state(TRACE_MSHV_MAP_MEMORY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 25 "../accel/mshv/trace-events"
            qemu_log("mshv_map_memory " "\tu_a=0x%" PRIx64 " gpa=0x%010" PRIx64 " size=0x%08" PRIx64 "\n", userspace_addr, gpa, size);
#line 305 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_UNMAP_MEMORY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_UNMAP_MEMORY) || \
    false)

static inline void trace_mshv_unmap_memory(uint64_t userspace_addr, uint64_t gpa, uint64_t size)
{
    if (trace_event_get_state(TRACE_MSHV_UNMAP_MEMORY)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 26 "../accel/mshv/trace-events"
            qemu_log("mshv_unmap_memory " "\tu_a=0x%" PRIx64 " gpa=0x%010" PRIx64 " size=0x%08" PRIx64 "\n", userspace_addr, gpa, size);
#line 320 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_SET_PHYS_MEM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_SET_PHYS_MEM) || \
    false)

static inline void trace_mshv_set_phys_mem(bool add, const char *name, uint64_t gpa)
{
    if (trace_event_get_state(TRACE_MSHV_SET_PHYS_MEM)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 27 "../accel/mshv/trace-events"
            qemu_log("mshv_set_phys_mem " "\tadd=%d name=%s gpa=0x%010" PRIx64 "\n", add, name, gpa);
#line 335 "trace/trace-accel_mshv.h"
        }
    }
}

#define TRACE_MSHV_HANDLE_MMIO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSHV_HANDLE_MMIO) || \
    false)

static inline void trace_mshv_handle_mmio(uint64_t gva, uint64_t gpa, uint64_t size, uint8_t access_type)
{
    if (trace_event_get_state(TRACE_MSHV_HANDLE_MMIO)) {
        if (qemu_loglevel_mask(LOG_TRACE)) {
#line 28 "../accel/mshv/trace-events"
            qemu_log("mshv_handle_mmio " "\tgva=0x%" PRIx64 " gpa=0x%010" PRIx64 " size=0x%" PRIx64 " access_type=%d" "\n", gva, gpa, size, access_type);
#line 350 "trace/trace-accel_mshv.h"
        }
    }
}
#endif /* TRACE_ACCEL_MSHV_GENERATED_TRACERS_H */
