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core/stdarch/crates/core_arch/src/x86_64/
avx512f.rs

1use crate::{
2    core_arch::{simd::*, x86::*, x86_64::*},
3    mem::transmute,
4};
5
6#[cfg(test)]
7use stdarch_test::assert_instr;
8
9/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
10///
11/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_i64&expand=1792)
12#[inline]
13#[target_feature(enable = "avx512f")]
14#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
15#[cfg_attr(test, assert_instr(vcvtsd2si))]
16pub fn _mm_cvtsd_i64(a: __m128d) -> i64 {
17    _mm_cvtsd_si64(a)
18}
19
20/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.
21///
22/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_i64&expand=1894)
23#[inline]
24#[target_feature(enable = "avx512f")]
25#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
26#[cfg_attr(test, assert_instr(vcvtss2si))]
27pub fn _mm_cvtss_i64(a: __m128) -> i64 {
28    _mm_cvtss_si64(a)
29}
30
31/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
32///
33/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_u64&expand=1902)
34#[inline]
35#[target_feature(enable = "avx512f")]
36#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
37#[cfg_attr(test, assert_instr(vcvtss2usi))]
38pub fn _mm_cvtss_u64(a: __m128) -> u64 {
39    unsafe { vcvtss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
40}
41
42/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.
43///
44/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_u64&expand=1800)
45#[inline]
46#[target_feature(enable = "avx512f")]
47#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
48#[cfg_attr(test, assert_instr(vcvtsd2usi))]
49pub fn _mm_cvtsd_u64(a: __m128d) -> u64 {
50    unsafe { vcvtsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
51}
52
53/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
54///
55/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvti64_ss&expand=1643)
56#[inline]
57#[target_feature(enable = "avx512f")]
58#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
59#[cfg_attr(test, assert_instr(vcvtsi2ss))]
60#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
61pub const fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 {
62    unsafe {
63        let b = b as f32;
64        simd_insert!(a, 0, b)
65    }
66}
67
68/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
69///
70/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvti64_sd&expand=1644)
71#[inline]
72#[target_feature(enable = "avx512f")]
73#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
74#[cfg_attr(test, assert_instr(vcvtsi2sd))]
75#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
76pub const fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d {
77    unsafe {
78        let b = b as f64;
79        simd_insert!(a, 0, b)
80    }
81}
82
83/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
84///
85/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_ss&expand=2035)
86#[inline]
87#[target_feature(enable = "avx512f")]
88#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
89#[cfg_attr(test, assert_instr(vcvtusi2ss))]
90#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
91pub const fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 {
92    unsafe {
93        let b = b as f32;
94        simd_insert!(a, 0, b)
95    }
96}
97
98/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
99///
100/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_sd&expand=2034)
101#[inline]
102#[target_feature(enable = "avx512f")]
103#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
104#[cfg_attr(test, assert_instr(vcvtusi2sd))]
105#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
106pub const fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d {
107    unsafe {
108        let b = b as f64;
109        simd_insert!(a, 0, b)
110    }
111}
112
113/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
114///
115/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_i64&expand=2016)
116#[inline]
117#[target_feature(enable = "avx512f")]
118#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
119#[cfg_attr(test, assert_instr(vcvttsd2si))]
120pub fn _mm_cvttsd_i64(a: __m128d) -> i64 {
121    unsafe { vcvttsd2si64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
122}
123
124/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
125///
126/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_u64&expand=2021)
127#[inline]
128#[target_feature(enable = "avx512f")]
129#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
130#[cfg_attr(test, assert_instr(vcvttsd2usi))]
131pub fn _mm_cvttsd_u64(a: __m128d) -> u64 {
132    unsafe { vcvttsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) }
133}
134
135/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.
136///
137/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=#text=_mm_cvttss_i64&expand=2023)
138#[inline]
139#[target_feature(enable = "avx512f")]
140#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
141#[cfg_attr(test, assert_instr(vcvttss2si))]
142pub fn _mm_cvttss_i64(a: __m128) -> i64 {
143    unsafe { vcvttss2si64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
144}
145
146/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.
147///
148/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttss_u64&expand=2027)
149#[inline]
150#[target_feature(enable = "avx512f")]
151#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
152#[cfg_attr(test, assert_instr(vcvttss2usi))]
153pub fn _mm_cvttss_u64(a: __m128) -> u64 {
154    unsafe { vcvttss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) }
155}
156
157/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
158/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
159/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
160/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
161/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
162/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
163/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
164///
165/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_sd&expand=1313)
166#[inline]
167#[target_feature(enable = "avx512f")]
168#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
169#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
170#[rustc_legacy_const_generics(2)]
171pub fn _mm_cvt_roundi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
172    unsafe {
173        static_assert_rounding!(ROUNDING);
174        let a = a.as_f64x2();
175        let r = vcvtsi2sd64(a, b, ROUNDING);
176        transmute(r)
177    }
178}
179
180/// Convert the signed 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.
181/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
182/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
183/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
184/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
185/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
186/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
187///
188/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_sd&expand=1367)
189#[inline]
190#[target_feature(enable = "avx512f")]
191#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
192#[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))]
193#[rustc_legacy_const_generics(2)]
194pub fn _mm_cvt_roundsi64_sd<const ROUNDING: i32>(a: __m128d, b: i64) -> __m128d {
195    unsafe {
196        static_assert_rounding!(ROUNDING);
197        let a = a.as_f64x2();
198        let r = vcvtsi2sd64(a, b, ROUNDING);
199        transmute(r)
200    }
201}
202
203/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
204/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
205/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
206/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
207/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
208/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
209/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
210///
211/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_ss&expand=1314)
212#[inline]
213#[target_feature(enable = "avx512f")]
214#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
215#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
216#[rustc_legacy_const_generics(2)]
217pub fn _mm_cvt_roundi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
218    unsafe {
219        static_assert_rounding!(ROUNDING);
220        let a = a.as_f32x4();
221        let r = vcvtsi2ss64(a, b, ROUNDING);
222        transmute(r)
223    }
224}
225
226/// Convert the unsigned 64-bit integer b to a double-precision (64-bit) floating-point element, store the result in the lower element of dst, and copy the upper element from a to the upper element of dst.\
227/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
228/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
229/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
230/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
231/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
232/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
233///
234/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_sd&expand=1379)
235#[inline]
236#[target_feature(enable = "avx512f")]
237#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
238#[cfg_attr(test, assert_instr(vcvtusi2sd, ROUNDING = 8))]
239#[rustc_legacy_const_generics(2)]
240pub fn _mm_cvt_roundu64_sd<const ROUNDING: i32>(a: __m128d, b: u64) -> __m128d {
241    unsafe {
242        static_assert_rounding!(ROUNDING);
243        let a = a.as_f64x2();
244        let r = vcvtusi2sd64(a, b, ROUNDING);
245        transmute(r)
246    }
247}
248
249/// Convert the signed 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.
250/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
251/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
252/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
253/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
254/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
255/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
256///
257/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_ss&expand=1368)
258#[inline]
259#[target_feature(enable = "avx512f")]
260#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
261#[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))]
262#[rustc_legacy_const_generics(2)]
263pub fn _mm_cvt_roundsi64_ss<const ROUNDING: i32>(a: __m128, b: i64) -> __m128 {
264    unsafe {
265        static_assert_rounding!(ROUNDING);
266        let a = a.as_f32x4();
267        let r = vcvtsi2ss64(a, b, ROUNDING);
268        transmute(r)
269    }
270}
271
272/// Convert the unsigned 64-bit integer b to a single-precision (32-bit) floating-point element, store the result in the lower element of dst, and copy the upper 3 packed elements from a to the upper elements of dst.\
273/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
274/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
275/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
276/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
277/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
278/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
279///
280/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_ss&expand=1380)
281#[inline]
282#[target_feature(enable = "avx512f")]
283#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
284#[cfg_attr(test, assert_instr(vcvtusi2ss, ROUNDING = 8))]
285#[rustc_legacy_const_generics(2)]
286pub fn _mm_cvt_roundu64_ss<const ROUNDING: i32>(a: __m128, b: u64) -> __m128 {
287    unsafe {
288        static_assert_rounding!(ROUNDING);
289        let a = a.as_f32x4();
290        let r = vcvtusi2ss64(a, b, ROUNDING);
291        transmute(r)
292    }
293}
294
295/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
296/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
297/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
298/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
299/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
300/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
301/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
302///
303/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_si64&expand=1360)
304#[inline]
305#[target_feature(enable = "avx512f")]
306#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
307#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
308#[rustc_legacy_const_generics(1)]
309pub fn _mm_cvt_roundsd_si64<const ROUNDING: i32>(a: __m128d) -> i64 {
310    unsafe {
311        static_assert_rounding!(ROUNDING);
312        let a = a.as_f64x2();
313        vcvtsd2si64(a, ROUNDING)
314    }
315}
316
317/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
318/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
319/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
320/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
321/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
322/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
323/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
324///
325/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_i64&expand=1358)
326#[inline]
327#[target_feature(enable = "avx512f")]
328#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
329#[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))]
330#[rustc_legacy_const_generics(1)]
331pub fn _mm_cvt_roundsd_i64<const ROUNDING: i32>(a: __m128d) -> i64 {
332    unsafe {
333        static_assert_rounding!(ROUNDING);
334        let a = a.as_f64x2();
335        vcvtsd2si64(a, ROUNDING)
336    }
337}
338
339/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
340/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
341/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
342/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
343/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
344/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
345/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
346///
347/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_u64&expand=1365)
348#[inline]
349#[target_feature(enable = "avx512f")]
350#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
351#[cfg_attr(test, assert_instr(vcvtsd2usi, ROUNDING = 8))]
352#[rustc_legacy_const_generics(1)]
353pub fn _mm_cvt_roundsd_u64<const ROUNDING: i32>(a: __m128d) -> u64 {
354    unsafe {
355        static_assert_rounding!(ROUNDING);
356        let a = a.as_f64x2();
357        vcvtsd2usi64(a, ROUNDING)
358    }
359}
360
361/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
362/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
363/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
364/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
365/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
366/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
367/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
368///
369/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_si64&expand=1375)
370#[inline]
371#[target_feature(enable = "avx512f")]
372#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
373#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
374#[rustc_legacy_const_generics(1)]
375pub fn _mm_cvt_roundss_si64<const ROUNDING: i32>(a: __m128) -> i64 {
376    unsafe {
377        static_assert_rounding!(ROUNDING);
378        let a = a.as_f32x4();
379        vcvtss2si64(a, ROUNDING)
380    }
381}
382
383/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer, and store the result in dst.\
384/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
385/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
386/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
387/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
388/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
389/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
390///
391/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_i64&expand=1370)
392#[inline]
393#[target_feature(enable = "avx512f")]
394#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
395#[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))]
396#[rustc_legacy_const_generics(1)]
397pub fn _mm_cvt_roundss_i64<const ROUNDING: i32>(a: __m128) -> i64 {
398    unsafe {
399        static_assert_rounding!(ROUNDING);
400        let a = a.as_f32x4();
401        vcvtss2si64(a, ROUNDING)
402    }
403}
404
405/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer, and store the result in dst.\
406/// Rounding is done according to the rounding\[3:0\] parameter, which can be one of:\
407/// * [`_MM_FROUND_TO_NEAREST_INT`] | [`_MM_FROUND_NO_EXC`] : round to nearest and suppress exceptions
408/// * [`_MM_FROUND_TO_NEG_INF`] | [`_MM_FROUND_NO_EXC`] : round down and suppress exceptions
409/// * [`_MM_FROUND_TO_POS_INF`] | [`_MM_FROUND_NO_EXC`] : round up and suppress exceptions
410/// * [`_MM_FROUND_TO_ZERO`] | [`_MM_FROUND_NO_EXC`] : truncate and suppress exceptions
411/// * [`_MM_FROUND_CUR_DIRECTION`] : use `MXCSR.RC` - see [`_MM_SET_ROUNDING_MODE`]
412///
413/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_u64&expand=1377)
414#[inline]
415#[target_feature(enable = "avx512f")]
416#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
417#[cfg_attr(test, assert_instr(vcvtss2usi, ROUNDING = 8))]
418#[rustc_legacy_const_generics(1)]
419pub fn _mm_cvt_roundss_u64<const ROUNDING: i32>(a: __m128) -> u64 {
420    unsafe {
421        static_assert_rounding!(ROUNDING);
422        let a = a.as_f32x4();
423        vcvtss2usi64(a, ROUNDING)
424    }
425}
426
427/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
428/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
429///
430/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_si64&expand=1931)
431#[inline]
432#[target_feature(enable = "avx512f")]
433#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
434#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
435#[rustc_legacy_const_generics(1)]
436pub fn _mm_cvtt_roundsd_si64<const SAE: i32>(a: __m128d) -> i64 {
437    unsafe {
438        static_assert_sae!(SAE);
439        let a = a.as_f64x2();
440        vcvttsd2si64(a, SAE)
441    }
442}
443
444/// Convert the lower double-precision (64-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
445/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
446///
447/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_i64&expand=1929)
448#[inline]
449#[target_feature(enable = "avx512f")]
450#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
451#[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))]
452#[rustc_legacy_const_generics(1)]
453pub fn _mm_cvtt_roundsd_i64<const SAE: i32>(a: __m128d) -> i64 {
454    unsafe {
455        static_assert_sae!(SAE);
456        let a = a.as_f64x2();
457        vcvttsd2si64(a, SAE)
458    }
459}
460
461/// Convert the lower double-precision (64-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
462/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
463///
464/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_u64&expand=1933)
465#[inline]
466#[target_feature(enable = "avx512f")]
467#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
468#[cfg_attr(test, assert_instr(vcvttsd2usi, SAE = 8))]
469#[rustc_legacy_const_generics(1)]
470pub fn _mm_cvtt_roundsd_u64<const SAE: i32>(a: __m128d) -> u64 {
471    unsafe {
472        static_assert_sae!(SAE);
473        let a = a.as_f64x2();
474        vcvttsd2usi64(a, SAE)
475    }
476}
477
478/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
479/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
480///
481/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_i64&expand=1935)
482#[inline]
483#[target_feature(enable = "avx512f")]
484#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
485#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
486#[rustc_legacy_const_generics(1)]
487pub fn _mm_cvtt_roundss_i64<const SAE: i32>(a: __m128) -> i64 {
488    unsafe {
489        static_assert_sae!(SAE);
490        let a = a.as_f32x4();
491        vcvttss2si64(a, SAE)
492    }
493}
494
495/// Convert the lower single-precision (32-bit) floating-point element in a to a 64-bit integer with truncation, and store the result in dst.\
496/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
497///
498/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_si64&expand=1937)
499#[inline]
500#[target_feature(enable = "avx512f")]
501#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
502#[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))]
503#[rustc_legacy_const_generics(1)]
504pub fn _mm_cvtt_roundss_si64<const SAE: i32>(a: __m128) -> i64 {
505    unsafe {
506        static_assert_sae!(SAE);
507        let a = a.as_f32x4();
508        vcvttss2si64(a, SAE)
509    }
510}
511
512/// Convert the lower single-precision (32-bit) floating-point element in a to an unsigned 64-bit integer with truncation, and store the result in dst.\
513/// Exceptions can be suppressed by passing _MM_FROUND_NO_EXC in the sae parameter.
514///
515/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_u64&expand=1939)
516#[inline]
517#[target_feature(enable = "avx512f")]
518#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
519#[cfg_attr(test, assert_instr(vcvttss2usi, SAE = 8))]
520#[rustc_legacy_const_generics(1)]
521pub fn _mm_cvtt_roundss_u64<const SAE: i32>(a: __m128) -> u64 {
522    unsafe {
523        static_assert_sae!(SAE);
524        let a = a.as_f32x4();
525        vcvttss2usi64(a, SAE)
526    }
527}
528
529#[allow(improper_ctypes)]
530unsafe extern "C" {
531    #[link_name = "llvm.x86.avx512.vcvtss2si64"]
532    fn vcvtss2si64(a: f32x4, rounding: i32) -> i64;
533    #[link_name = "llvm.x86.avx512.vcvtss2usi64"]
534    fn vcvtss2usi64(a: f32x4, rounding: i32) -> u64;
535    #[link_name = "llvm.x86.avx512.vcvtsd2si64"]
536    fn vcvtsd2si64(a: f64x2, rounding: i32) -> i64;
537    #[link_name = "llvm.x86.avx512.vcvtsd2usi64"]
538    fn vcvtsd2usi64(a: f64x2, rounding: i32) -> u64;
539
540    #[link_name = "llvm.x86.avx512.cvtsi2ss64"]
541    fn vcvtsi2ss64(a: f32x4, b: i64, rounding: i32) -> f32x4;
542    #[link_name = "llvm.x86.avx512.cvtsi2sd64"]
543    fn vcvtsi2sd64(a: f64x2, b: i64, rounding: i32) -> f64x2;
544    #[link_name = "llvm.x86.avx512.cvtusi642ss"]
545    fn vcvtusi2ss64(a: f32x4, b: u64, rounding: i32) -> f32x4;
546    #[link_name = "llvm.x86.avx512.cvtusi642sd"]
547    fn vcvtusi2sd64(a: f64x2, b: u64, rounding: i32) -> f64x2;
548
549    #[link_name = "llvm.x86.avx512.cvttss2si64"]
550    fn vcvttss2si64(a: f32x4, rounding: i32) -> i64;
551    #[link_name = "llvm.x86.avx512.cvttss2usi64"]
552    fn vcvttss2usi64(a: f32x4, rounding: i32) -> u64;
553    #[link_name = "llvm.x86.avx512.cvttsd2si64"]
554    fn vcvttsd2si64(a: f64x2, rounding: i32) -> i64;
555    #[link_name = "llvm.x86.avx512.cvttsd2usi64"]
556    fn vcvttsd2usi64(a: f64x2, rounding: i32) -> u64;
557}
558
559#[cfg(test)]
560mod tests {
561    use crate::core_arch::assert_eq_const as assert_eq;
562
563    use stdarch_test::simd_test;
564
565    use crate::core_arch::x86::*;
566    use crate::core_arch::x86_64::*;
567    use crate::hint::black_box;
568
569    #[simd_test(enable = "avx512f")]
570    const fn test_mm512_abs_epi64() {
571        let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
572        let r = _mm512_abs_epi64(a);
573        let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MAX.wrapping_add(1), 100, 100, 32);
574        assert_eq_m512i(r, e);
575    }
576
577    #[simd_test(enable = "avx512f")]
578    const fn test_mm512_mask_abs_epi64() {
579        let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
580        let r = _mm512_mask_abs_epi64(a, 0, a);
581        assert_eq_m512i(r, a);
582        let r = _mm512_mask_abs_epi64(a, 0b11111111, a);
583        let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
584        assert_eq_m512i(r, e);
585    }
586
587    #[simd_test(enable = "avx512f")]
588    const fn test_mm512_maskz_abs_epi64() {
589        let a = _mm512_set_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
590        let r = _mm512_maskz_abs_epi64(0, a);
591        assert_eq_m512i(r, _mm512_setzero_si512());
592        let r = _mm512_maskz_abs_epi64(0b11111111, a);
593        let e = _mm512_set_epi64(0, 1, 1, i64::MAX, i64::MIN, 100, 100, 32);
594        assert_eq_m512i(r, e);
595    }
596
597    #[simd_test(enable = "avx512f,avx512vl")]
598    const fn test_mm256_abs_epi64() {
599        let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
600        let r = _mm256_abs_epi64(a);
601        let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
602        assert_eq_m256i(r, e);
603    }
604
605    #[simd_test(enable = "avx512f,avx512vl")]
606    const fn test_mm256_mask_abs_epi64() {
607        let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
608        let r = _mm256_mask_abs_epi64(a, 0, a);
609        assert_eq_m256i(r, a);
610        let r = _mm256_mask_abs_epi64(a, 0b00001111, a);
611        let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
612        assert_eq_m256i(r, e);
613    }
614
615    #[simd_test(enable = "avx512f,avx512vl")]
616    const fn test_mm256_maskz_abs_epi64() {
617        let a = _mm256_set_epi64x(i64::MAX, i64::MIN, 100, -100);
618        let r = _mm256_maskz_abs_epi64(0, a);
619        assert_eq_m256i(r, _mm256_setzero_si256());
620        let r = _mm256_maskz_abs_epi64(0b00001111, a);
621        let e = _mm256_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1), 100, 100);
622        assert_eq_m256i(r, e);
623    }
624
625    #[simd_test(enable = "avx512f,avx512vl")]
626    const fn test_mm_abs_epi64() {
627        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
628        let r = _mm_abs_epi64(a);
629        let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
630        assert_eq_m128i(r, e);
631        let a = _mm_set_epi64x(100, -100);
632        let r = _mm_abs_epi64(a);
633        let e = _mm_set_epi64x(100, 100);
634        assert_eq_m128i(r, e);
635    }
636
637    #[simd_test(enable = "avx512f,avx512vl")]
638    const fn test_mm_mask_abs_epi64() {
639        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
640        let r = _mm_mask_abs_epi64(a, 0, a);
641        assert_eq_m128i(r, a);
642        let r = _mm_mask_abs_epi64(a, 0b00000011, a);
643        let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
644        assert_eq_m128i(r, e);
645        let a = _mm_set_epi64x(100, -100);
646        let r = _mm_mask_abs_epi64(a, 0b00000011, a);
647        let e = _mm_set_epi64x(100, 100);
648        assert_eq_m128i(r, e);
649    }
650
651    #[simd_test(enable = "avx512f,avx512vl")]
652    const fn test_mm_maskz_abs_epi64() {
653        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
654        let r = _mm_maskz_abs_epi64(0, a);
655        assert_eq_m128i(r, _mm_setzero_si128());
656        let r = _mm_maskz_abs_epi64(0b00000011, a);
657        let e = _mm_set_epi64x(i64::MAX, i64::MAX.wrapping_add(1));
658        assert_eq_m128i(r, e);
659        let a = _mm_set_epi64x(100, -100);
660        let r = _mm_maskz_abs_epi64(0b00000011, a);
661        let e = _mm_set_epi64x(100, 100);
662        assert_eq_m128i(r, e);
663    }
664
665    #[simd_test(enable = "avx512f")]
666    const fn test_mm512_abs_pd() {
667        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
668        let r = _mm512_abs_pd(a);
669        let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MAX, 100., 100., 32.);
670        assert_eq_m512d(r, e);
671    }
672
673    #[simd_test(enable = "avx512f")]
674    const fn test_mm512_mask_abs_pd() {
675        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
676        let r = _mm512_mask_abs_pd(a, 0, a);
677        assert_eq_m512d(r, a);
678        let r = _mm512_mask_abs_pd(a, 0b00001111, a);
679        let e = _mm512_setr_pd(0., 1., 1., f64::MAX, f64::MIN, 100., -100., -32.);
680        assert_eq_m512d(r, e);
681    }
682
683    #[simd_test(enable = "avx512f")]
684    const fn test_mm512_mask_mov_epi64() {
685        let src = _mm512_set1_epi64(1);
686        let a = _mm512_set1_epi64(2);
687        let r = _mm512_mask_mov_epi64(src, 0, a);
688        assert_eq_m512i(r, src);
689        let r = _mm512_mask_mov_epi64(src, 0b11111111, a);
690        assert_eq_m512i(r, a);
691    }
692
693    #[simd_test(enable = "avx512f")]
694    const fn test_mm512_maskz_mov_epi64() {
695        let a = _mm512_set1_epi64(2);
696        let r = _mm512_maskz_mov_epi64(0, a);
697        assert_eq_m512i(r, _mm512_setzero_si512());
698        let r = _mm512_maskz_mov_epi64(0b11111111, a);
699        assert_eq_m512i(r, a);
700    }
701
702    #[simd_test(enable = "avx512f,avx512vl")]
703    const fn test_mm256_mask_mov_epi64() {
704        let src = _mm256_set1_epi64x(1);
705        let a = _mm256_set1_epi64x(2);
706        let r = _mm256_mask_mov_epi64(src, 0, a);
707        assert_eq_m256i(r, src);
708        let r = _mm256_mask_mov_epi64(src, 0b00001111, a);
709        assert_eq_m256i(r, a);
710    }
711
712    #[simd_test(enable = "avx512f,avx512vl")]
713    const fn test_mm256_maskz_mov_epi64() {
714        let a = _mm256_set1_epi64x(2);
715        let r = _mm256_maskz_mov_epi64(0, a);
716        assert_eq_m256i(r, _mm256_setzero_si256());
717        let r = _mm256_maskz_mov_epi64(0b00001111, a);
718        assert_eq_m256i(r, a);
719    }
720
721    #[simd_test(enable = "avx512f,avx512vl")]
722    const fn test_mm_mask_mov_epi64() {
723        let src = _mm_set1_epi64x(1);
724        let a = _mm_set1_epi64x(2);
725        let r = _mm_mask_mov_epi64(src, 0, a);
726        assert_eq_m128i(r, src);
727        let r = _mm_mask_mov_epi64(src, 0b00000011, a);
728        assert_eq_m128i(r, a);
729    }
730
731    #[simd_test(enable = "avx512f,avx512vl")]
732    const fn test_mm_maskz_mov_epi64() {
733        let a = _mm_set1_epi64x(2);
734        let r = _mm_maskz_mov_epi64(0, a);
735        assert_eq_m128i(r, _mm_setzero_si128());
736        let r = _mm_maskz_mov_epi64(0b00000011, a);
737        assert_eq_m128i(r, a);
738    }
739
740    #[simd_test(enable = "avx512f")]
741    const fn test_mm512_mask_mov_pd() {
742        let src = _mm512_set1_pd(1.);
743        let a = _mm512_set1_pd(2.);
744        let r = _mm512_mask_mov_pd(src, 0, a);
745        assert_eq_m512d(r, src);
746        let r = _mm512_mask_mov_pd(src, 0b11111111, a);
747        assert_eq_m512d(r, a);
748    }
749
750    #[simd_test(enable = "avx512f")]
751    const fn test_mm512_maskz_mov_pd() {
752        let a = _mm512_set1_pd(2.);
753        let r = _mm512_maskz_mov_pd(0, a);
754        assert_eq_m512d(r, _mm512_setzero_pd());
755        let r = _mm512_maskz_mov_pd(0b11111111, a);
756        assert_eq_m512d(r, a);
757    }
758
759    #[simd_test(enable = "avx512f,avx512vl")]
760    const fn test_mm256_mask_mov_pd() {
761        let src = _mm256_set1_pd(1.);
762        let a = _mm256_set1_pd(2.);
763        let r = _mm256_mask_mov_pd(src, 0, a);
764        assert_eq_m256d(r, src);
765        let r = _mm256_mask_mov_pd(src, 0b00001111, a);
766        assert_eq_m256d(r, a);
767    }
768
769    #[simd_test(enable = "avx512f,avx512vl")]
770    const fn test_mm256_maskz_mov_pd() {
771        let a = _mm256_set1_pd(2.);
772        let r = _mm256_maskz_mov_pd(0, a);
773        assert_eq_m256d(r, _mm256_setzero_pd());
774        let r = _mm256_maskz_mov_pd(0b00001111, a);
775        assert_eq_m256d(r, a);
776    }
777
778    #[simd_test(enable = "avx512f,avx512vl")]
779    const fn test_mm_mask_mov_pd() {
780        let src = _mm_set1_pd(1.);
781        let a = _mm_set1_pd(2.);
782        let r = _mm_mask_mov_pd(src, 0, a);
783        assert_eq_m128d(r, src);
784        let r = _mm_mask_mov_pd(src, 0b00000011, a);
785        assert_eq_m128d(r, a);
786    }
787
788    #[simd_test(enable = "avx512f,avx512vl")]
789    const fn test_mm_maskz_mov_pd() {
790        let a = _mm_set1_pd(2.);
791        let r = _mm_maskz_mov_pd(0, a);
792        assert_eq_m128d(r, _mm_setzero_pd());
793        let r = _mm_maskz_mov_pd(0b00000011, a);
794        assert_eq_m128d(r, a);
795    }
796
797    #[simd_test(enable = "avx512f")]
798    const fn test_mm512_add_epi64() {
799        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
800        let b = _mm512_set1_epi64(1);
801        let r = _mm512_add_epi64(a, b);
802        let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN + 1, 101, -99, -31);
803        assert_eq_m512i(r, e);
804    }
805
806    #[simd_test(enable = "avx512f")]
807    const fn test_mm512_mask_add_epi64() {
808        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
809        let b = _mm512_set1_epi64(1);
810        let r = _mm512_mask_add_epi64(a, 0, a, b);
811        assert_eq_m512i(r, a);
812        let r = _mm512_mask_add_epi64(a, 0b00001111, a, b);
813        let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, i64::MIN, 100, -100, -32);
814        assert_eq_m512i(r, e);
815    }
816
817    #[simd_test(enable = "avx512f")]
818    const fn test_mm512_maskz_add_epi64() {
819        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
820        let b = _mm512_set1_epi64(1);
821        let r = _mm512_maskz_add_epi64(0, a, b);
822        assert_eq_m512i(r, _mm512_setzero_si512());
823        let r = _mm512_maskz_add_epi64(0b00001111, a, b);
824        let e = _mm512_setr_epi64(1, 2, 0, i64::MIN, 0, 0, 0, 0);
825        assert_eq_m512i(r, e);
826    }
827
828    #[simd_test(enable = "avx512f,avx512vl")]
829    const fn test_mm256_mask_add_epi64() {
830        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
831        let b = _mm256_set1_epi64x(1);
832        let r = _mm256_mask_add_epi64(a, 0, a, b);
833        assert_eq_m256i(r, a);
834        let r = _mm256_mask_add_epi64(a, 0b00001111, a, b);
835        let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
836        assert_eq_m256i(r, e);
837    }
838
839    #[simd_test(enable = "avx512f,avx512vl")]
840    const fn test_mm256_maskz_add_epi64() {
841        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
842        let b = _mm256_set1_epi64x(1);
843        let r = _mm256_maskz_add_epi64(0, a, b);
844        assert_eq_m256i(r, _mm256_setzero_si256());
845        let r = _mm256_maskz_add_epi64(0b00001111, a, b);
846        let e = _mm256_set_epi64x(2, 0, i64::MIN, i64::MIN + 1);
847        assert_eq_m256i(r, e);
848    }
849
850    #[simd_test(enable = "avx512f,avx512vl")]
851    const fn test_mm_mask_add_epi64() {
852        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
853        let b = _mm_set1_epi64x(1);
854        let r = _mm_mask_add_epi64(a, 0, a, b);
855        assert_eq_m128i(r, a);
856        let r = _mm_mask_add_epi64(a, 0b00000011, a, b);
857        let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
858        assert_eq_m128i(r, e);
859    }
860
861    #[simd_test(enable = "avx512f,avx512vl")]
862    const fn test_mm_maskz_add_epi64() {
863        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
864        let b = _mm_set1_epi64x(1);
865        let r = _mm_maskz_add_epi64(0, a, b);
866        assert_eq_m128i(r, _mm_setzero_si128());
867        let r = _mm_maskz_add_epi64(0b00000011, a, b);
868        let e = _mm_set_epi64x(i64::MIN, i64::MIN + 1);
869        assert_eq_m128i(r, e);
870    }
871
872    #[simd_test(enable = "avx512f")]
873    const fn test_mm512_add_pd() {
874        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
875        let b = _mm512_set1_pd(1.);
876        let r = _mm512_add_pd(a, b);
877        let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN + 1., 101., -99., -31.);
878        assert_eq_m512d(r, e);
879    }
880
881    #[simd_test(enable = "avx512f")]
882    const fn test_mm512_mask_add_pd() {
883        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
884        let b = _mm512_set1_pd(1.);
885        let r = _mm512_mask_add_pd(a, 0, a, b);
886        assert_eq_m512d(r, a);
887        let r = _mm512_mask_add_pd(a, 0b00001111, a, b);
888        let e = _mm512_setr_pd(1., 2., 0., f64::MAX, f64::MIN, 100., -100., -32.);
889        assert_eq_m512d(r, e);
890    }
891
892    #[simd_test(enable = "avx512f")]
893    const fn test_mm512_maskz_add_pd() {
894        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
895        let b = _mm512_set1_pd(1.);
896        let r = _mm512_maskz_add_pd(0, a, b);
897        assert_eq_m512d(r, _mm512_setzero_pd());
898        let r = _mm512_maskz_add_pd(0b00001111, a, b);
899        let e = _mm512_setr_pd(1., 2., 0., f64::MAX, 0., 0., 0., 0.);
900        assert_eq_m512d(r, e);
901    }
902
903    #[simd_test(enable = "avx512f,avx512vl")]
904    const fn test_mm256_mask_add_pd() {
905        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
906        let b = _mm256_set1_pd(1.);
907        let r = _mm256_mask_add_pd(a, 0, a, b);
908        assert_eq_m256d(r, a);
909        let r = _mm256_mask_add_pd(a, 0b00001111, a, b);
910        let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
911        assert_eq_m256d(r, e);
912    }
913
914    #[simd_test(enable = "avx512f,avx512vl")]
915    const fn test_mm256_maskz_add_pd() {
916        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
917        let b = _mm256_set1_pd(1.);
918        let r = _mm256_maskz_add_pd(0, a, b);
919        assert_eq_m256d(r, _mm256_setzero_pd());
920        let r = _mm256_maskz_add_pd(0b00001111, a, b);
921        let e = _mm256_set_pd(2., 0., f64::MAX, f64::MIN + 1.);
922        assert_eq_m256d(r, e);
923    }
924
925    #[simd_test(enable = "avx512f,avx512vl")]
926    const fn test_mm_mask_add_pd() {
927        let a = _mm_set_pd(f64::MAX, f64::MIN);
928        let b = _mm_set1_pd(1.);
929        let r = _mm_mask_add_pd(a, 0, a, b);
930        assert_eq_m128d(r, a);
931        let r = _mm_mask_add_pd(a, 0b00000011, a, b);
932        let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
933        assert_eq_m128d(r, e);
934    }
935
936    #[simd_test(enable = "avx512f,avx512vl")]
937    const fn test_mm_maskz_add_pd() {
938        let a = _mm_set_pd(f64::MAX, f64::MIN);
939        let b = _mm_set1_pd(1.);
940        let r = _mm_maskz_add_pd(0, a, b);
941        assert_eq_m128d(r, _mm_setzero_pd());
942        let r = _mm_maskz_add_pd(0b00000011, a, b);
943        let e = _mm_set_pd(f64::MAX, f64::MIN + 1.);
944        assert_eq_m128d(r, e);
945    }
946
947    #[simd_test(enable = "avx512f")]
948    const fn test_mm512_sub_epi64() {
949        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
950        let b = _mm512_set1_epi64(1);
951        let r = _mm512_sub_epi64(a, b);
952        let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MAX, 99, -101, -33);
953        assert_eq_m512i(r, e);
954    }
955
956    #[simd_test(enable = "avx512f")]
957    const fn test_mm512_mask_sub_epi64() {
958        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
959        let b = _mm512_set1_epi64(1);
960        let r = _mm512_mask_sub_epi64(a, 0, a, b);
961        assert_eq_m512i(r, a);
962        let r = _mm512_mask_sub_epi64(a, 0b00001111, a, b);
963        let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, i64::MIN, 100, -100, -32);
964        assert_eq_m512i(r, e);
965    }
966
967    #[simd_test(enable = "avx512f")]
968    const fn test_mm512_maskz_sub_epi64() {
969        let a = _mm512_setr_epi64(0, 1, -1, i64::MAX, i64::MIN, 100, -100, -32);
970        let b = _mm512_set1_epi64(1);
971        let r = _mm512_maskz_sub_epi64(0, a, b);
972        assert_eq_m512i(r, _mm512_setzero_si512());
973        let r = _mm512_maskz_sub_epi64(0b00001111, a, b);
974        let e = _mm512_setr_epi64(-1, 0, -2, i64::MAX - 1, 0, 0, 0, 0);
975        assert_eq_m512i(r, e);
976    }
977
978    #[simd_test(enable = "avx512f,avx512vl")]
979    const fn test_mm256_mask_sub_epi64() {
980        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
981        let b = _mm256_set1_epi64x(1);
982        let r = _mm256_mask_sub_epi64(a, 0, a, b);
983        assert_eq_m256i(r, a);
984        let r = _mm256_mask_sub_epi64(a, 0b00001111, a, b);
985        let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
986        assert_eq_m256i(r, e);
987    }
988
989    #[simd_test(enable = "avx512f,avx512vl")]
990    const fn test_mm256_maskz_sub_epi64() {
991        let a = _mm256_set_epi64x(1, -1, i64::MAX, i64::MIN);
992        let b = _mm256_set1_epi64x(1);
993        let r = _mm256_maskz_sub_epi64(0, a, b);
994        assert_eq_m256i(r, _mm256_setzero_si256());
995        let r = _mm256_maskz_sub_epi64(0b00001111, a, b);
996        let e = _mm256_set_epi64x(0, -2, i64::MAX - 1, i64::MAX);
997        assert_eq_m256i(r, e);
998    }
999
1000    #[simd_test(enable = "avx512f,avx512vl")]
1001    const fn test_mm_mask_sub_epi64() {
1002        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
1003        let b = _mm_set1_epi64x(1);
1004        let r = _mm_mask_sub_epi64(a, 0, a, b);
1005        assert_eq_m128i(r, a);
1006        let r = _mm_mask_sub_epi64(a, 0b00000011, a, b);
1007        let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
1008        assert_eq_m128i(r, e);
1009    }
1010
1011    #[simd_test(enable = "avx512f,avx512vl")]
1012    const fn test_mm_maskz_sub_epi64() {
1013        let a = _mm_set_epi64x(i64::MAX, i64::MIN);
1014        let b = _mm_set1_epi64x(1);
1015        let r = _mm_maskz_sub_epi64(0, a, b);
1016        assert_eq_m128i(r, _mm_setzero_si128());
1017        let r = _mm_maskz_sub_epi64(0b00000011, a, b);
1018        let e = _mm_set_epi64x(i64::MAX - 1, i64::MAX);
1019        assert_eq_m128i(r, e);
1020    }
1021
1022    #[simd_test(enable = "avx512f")]
1023    const fn test_mm512_sub_pd() {
1024        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1025        let b = _mm512_set1_pd(1.);
1026        let r = _mm512_sub_pd(a, b);
1027        let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 99., -101., -33.);
1028        assert_eq_m512d(r, e);
1029    }
1030
1031    #[simd_test(enable = "avx512f")]
1032    const fn test_mm512_mask_sub_pd() {
1033        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1034        let b = _mm512_set1_pd(1.);
1035        let r = _mm512_mask_sub_pd(a, 0, a, b);
1036        assert_eq_m512d(r, a);
1037        let r = _mm512_mask_sub_pd(a, 0b00001111, a, b);
1038        let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., f64::MIN, 100., -100., -32.);
1039        assert_eq_m512d(r, e);
1040    }
1041
1042    #[simd_test(enable = "avx512f")]
1043    const fn test_mm512_maskz_sub_pd() {
1044        let a = _mm512_setr_pd(0., 1., -1., f64::MAX, f64::MIN, 100., -100., -32.);
1045        let b = _mm512_set1_pd(1.);
1046        let r = _mm512_maskz_sub_pd(0, a, b);
1047        assert_eq_m512d(r, _mm512_setzero_pd());
1048        let r = _mm512_maskz_sub_pd(0b00001111, a, b);
1049        let e = _mm512_setr_pd(-1., 0., -2., f64::MAX - 1., 0., 0., 0., 0.);
1050        assert_eq_m512d(r, e);
1051    }
1052
1053    #[simd_test(enable = "avx512f,avx512vl")]
1054    const fn test_mm256_mask_sub_pd() {
1055        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1056        let b = _mm256_set1_pd(1.);
1057        let r = _mm256_mask_sub_pd(a, 0, a, b);
1058        assert_eq_m256d(r, a);
1059        let r = _mm256_mask_sub_pd(a, 0b00001111, a, b);
1060        let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1061        assert_eq_m256d(r, e);
1062    }
1063
1064    #[simd_test(enable = "avx512f,avx512vl")]
1065    const fn test_mm256_maskz_sub_pd() {
1066        let a = _mm256_set_pd(1., -1., f64::MAX, f64::MIN);
1067        let b = _mm256_set1_pd(1.);
1068        let r = _mm256_maskz_sub_pd(0, a, b);
1069        assert_eq_m256d(r, _mm256_setzero_pd());
1070        let r = _mm256_maskz_sub_pd(0b00001111, a, b);
1071        let e = _mm256_set_pd(0., -2., f64::MAX - 1., f64::MIN);
1072        assert_eq_m256d(r, e);
1073    }
1074
1075    #[simd_test(enable = "avx512f,avx512vl")]
1076    const fn test_mm_mask_sub_pd() {
1077        let a = _mm_set_pd(f64::MAX, f64::MIN);
1078        let b = _mm_set1_pd(1.);
1079        let r = _mm_mask_sub_pd(a, 0, a, b);
1080        assert_eq_m128d(r, a);
1081        let r = _mm_mask_sub_pd(a, 0b00000011, a, b);
1082        let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1083        assert_eq_m128d(r, e);
1084    }
1085
1086    #[simd_test(enable = "avx512f,avx512vl")]
1087    const fn test_mm_maskz_sub_pd() {
1088        let a = _mm_set_pd(f64::MAX, f64::MIN);
1089        let b = _mm_set1_pd(1.);
1090        let r = _mm_maskz_sub_pd(0, a, b);
1091        assert_eq_m128d(r, _mm_setzero_pd());
1092        let r = _mm_maskz_sub_pd(0b00000011, a, b);
1093        let e = _mm_set_pd(f64::MAX - 1., f64::MIN);
1094        assert_eq_m128d(r, e);
1095    }
1096
1097    #[simd_test(enable = "avx512f")]
1098    const fn test_mm512_mul_epi32() {
1099        let a = _mm512_set1_epi32(1);
1100        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1101        let r = _mm512_mul_epi32(a, b);
1102        let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1103        assert_eq_m512i(r, e);
1104    }
1105
1106    #[simd_test(enable = "avx512f")]
1107    const fn test_mm512_mask_mul_epi32() {
1108        let a = _mm512_set1_epi32(1);
1109        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1110        let r = _mm512_mask_mul_epi32(a, 0, a, b);
1111        assert_eq_m512i(r, a);
1112        let r = _mm512_mask_mul_epi32(a, 0b00001111, a, b);
1113        #[rustfmt::skip]
1114        let e = _mm512_set_epi64(
1115            1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1116            7, 5, 3, 1,
1117        );
1118        assert_eq_m512i(r, e);
1119    }
1120
1121    #[simd_test(enable = "avx512f")]
1122    const fn test_mm512_maskz_mul_epi32() {
1123        let a = _mm512_set1_epi32(1);
1124        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1125        let r = _mm512_maskz_mul_epi32(0, a, b);
1126        assert_eq_m512i(r, _mm512_setzero_si512());
1127        let r = _mm512_maskz_mul_epi32(0b00001111, a, b);
1128        let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1129        assert_eq_m512i(r, e);
1130    }
1131
1132    #[simd_test(enable = "avx512f,avx512vl")]
1133    const fn test_mm256_mask_mul_epi32() {
1134        let a = _mm256_set1_epi32(1);
1135        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1136        let r = _mm256_mask_mul_epi32(a, 0, a, b);
1137        assert_eq_m256i(r, a);
1138        let r = _mm256_mask_mul_epi32(a, 0b00001111, a, b);
1139        let e = _mm256_set_epi64x(2, 4, 6, 8);
1140        assert_eq_m256i(r, e);
1141    }
1142
1143    #[simd_test(enable = "avx512f,avx512vl")]
1144    const fn test_mm256_maskz_mul_epi32() {
1145        let a = _mm256_set1_epi32(1);
1146        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1147        let r = _mm256_maskz_mul_epi32(0, a, b);
1148        assert_eq_m256i(r, _mm256_setzero_si256());
1149        let r = _mm256_maskz_mul_epi32(0b00001111, a, b);
1150        let e = _mm256_set_epi64x(2, 4, 6, 8);
1151        assert_eq_m256i(r, e);
1152    }
1153
1154    #[simd_test(enable = "avx512f,avx512vl")]
1155    const fn test_mm_mask_mul_epi32() {
1156        let a = _mm_set1_epi32(1);
1157        let b = _mm_set_epi32(1, 2, 3, 4);
1158        let r = _mm_mask_mul_epi32(a, 0, a, b);
1159        assert_eq_m128i(r, a);
1160        let r = _mm_mask_mul_epi32(a, 0b00000011, a, b);
1161        let e = _mm_set_epi64x(2, 4);
1162        assert_eq_m128i(r, e);
1163    }
1164
1165    #[simd_test(enable = "avx512f,avx512vl")]
1166    const fn test_mm_maskz_mul_epi32() {
1167        let a = _mm_set1_epi32(1);
1168        let b = _mm_set_epi32(1, 2, 3, 4);
1169        let r = _mm_maskz_mul_epi32(0, a, b);
1170        assert_eq_m128i(r, _mm_setzero_si128());
1171        let r = _mm_maskz_mul_epi32(0b00000011, a, b);
1172        let e = _mm_set_epi64x(2, 4);
1173        assert_eq_m128i(r, e);
1174    }
1175
1176    #[simd_test(enable = "avx512f")]
1177    const fn test_mm512_mul_epu32() {
1178        let a = _mm512_set1_epi32(1);
1179        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1180        let r = _mm512_mul_epu32(a, b);
1181        let e = _mm512_set_epi64(15, 13, 11, 9, 7, 5, 3, 1);
1182        assert_eq_m512i(r, e);
1183    }
1184
1185    #[simd_test(enable = "avx512f")]
1186    const fn test_mm512_mask_mul_epu32() {
1187        let a = _mm512_set1_epi32(1);
1188        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1189        let r = _mm512_mask_mul_epu32(a, 0, a, b);
1190        assert_eq_m512i(r, a);
1191        let r = _mm512_mask_mul_epu32(a, 0b00001111, a, b);
1192        #[rustfmt::skip]
1193        let e = _mm512_set_epi64(
1194            1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32, 1 | 1 << 32,
1195            7, 5, 3, 1,
1196        );
1197        assert_eq_m512i(r, e);
1198    }
1199
1200    #[simd_test(enable = "avx512f")]
1201    const fn test_mm512_maskz_mul_epu32() {
1202        let a = _mm512_set1_epi32(1);
1203        let b = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
1204        let r = _mm512_maskz_mul_epu32(0, a, b);
1205        assert_eq_m512i(r, _mm512_setzero_si512());
1206        let r = _mm512_maskz_mul_epu32(0b00001111, a, b);
1207        let e = _mm512_set_epi64(0, 0, 0, 0, 7, 5, 3, 1);
1208        assert_eq_m512i(r, e);
1209    }
1210
1211    #[simd_test(enable = "avx512f,avx512vl")]
1212    const fn test_mm256_mask_mul_epu32() {
1213        let a = _mm256_set1_epi32(1);
1214        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1215        let r = _mm256_mask_mul_epu32(a, 0, a, b);
1216        assert_eq_m256i(r, a);
1217        let r = _mm256_mask_mul_epu32(a, 0b00001111, a, b);
1218        let e = _mm256_set_epi64x(2, 4, 6, 8);
1219        assert_eq_m256i(r, e);
1220    }
1221
1222    #[simd_test(enable = "avx512f,avx512vl")]
1223    const fn test_mm256_maskz_mul_epu32() {
1224        let a = _mm256_set1_epi32(1);
1225        let b = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
1226        let r = _mm256_maskz_mul_epu32(0, a, b);
1227        assert_eq_m256i(r, _mm256_setzero_si256());
1228        let r = _mm256_maskz_mul_epu32(0b00001111, a, b);
1229        let e = _mm256_set_epi64x(2, 4, 6, 8);
1230        assert_eq_m256i(r, e);
1231    }
1232
1233    #[simd_test(enable = "avx512f,avx512vl")]
1234    const fn test_mm_mask_mul_epu32() {
1235        let a = _mm_set1_epi32(1);
1236        let b = _mm_set_epi32(1, 2, 3, 4);
1237        let r = _mm_mask_mul_epu32(a, 0, a, b);
1238        assert_eq_m128i(r, a);
1239        let r = _mm_mask_mul_epu32(a, 0b00000011, a, b);
1240        let e = _mm_set_epi64x(2, 4);
1241        assert_eq_m128i(r, e);
1242    }
1243
1244    #[simd_test(enable = "avx512f,avx512vl")]
1245    const fn test_mm_maskz_mul_epu32() {
1246        let a = _mm_set1_epi32(1);
1247        let b = _mm_set_epi32(1, 2, 3, 4);
1248        let r = _mm_maskz_mul_epu32(0, a, b);
1249        assert_eq_m128i(r, _mm_setzero_si128());
1250        let r = _mm_maskz_mul_epu32(0b00000011, a, b);
1251        let e = _mm_set_epi64x(2, 4);
1252        assert_eq_m128i(r, e);
1253    }
1254
1255    #[simd_test(enable = "avx512f")]
1256    const fn test_mm512_mullox_epi64() {
1257        let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1258        let b = _mm512_set1_epi64(2);
1259        let r = _mm512_mullox_epi64(a, b);
1260        let e = _mm512_setr_epi64(0, 2, -2, 0, -2, 200, -200, -64);
1261        assert_eq_m512i(r, e);
1262    }
1263
1264    #[simd_test(enable = "avx512f")]
1265    const fn test_mm512_mask_mullox_epi64() {
1266        let a = _mm512_setr_epi64(0, 1, i64::MAX, i64::MIN, i64::MAX, 100, -100, -32);
1267        let b = _mm512_set1_epi64(2);
1268        let r = _mm512_mask_mullox_epi64(a, 0, a, b);
1269        assert_eq_m512i(r, a);
1270        let r = _mm512_mask_mullox_epi64(a, 0b00001111, a, b);
1271        let e = _mm512_setr_epi64(0, 2, -2, 0, i64::MAX, 100, -100, -32);
1272        assert_eq_m512i(r, e);
1273    }
1274
1275    #[simd_test(enable = "avx512f")]
1276    const fn test_mm512_mul_pd() {
1277        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1278        let b = _mm512_set1_pd(2.);
1279        let r = _mm512_mul_pd(a, b);
1280        #[rustfmt::skip]
1281        let e = _mm512_setr_pd(
1282            0., 2., f64::INFINITY, f64::NEG_INFINITY,
1283            f64::INFINITY, f64::NEG_INFINITY, -200., -64.,
1284        );
1285        assert_eq_m512d(r, e);
1286    }
1287
1288    #[simd_test(enable = "avx512f")]
1289    const fn test_mm512_mask_mul_pd() {
1290        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1291        let b = _mm512_set1_pd(2.);
1292        let r = _mm512_mask_mul_pd(a, 0, a, b);
1293        assert_eq_m512d(r, a);
1294        let r = _mm512_mask_mul_pd(a, 0b00001111, a, b);
1295        #[rustfmt::skip]
1296        let e = _mm512_setr_pd(
1297            0., 2., f64::INFINITY, f64::NEG_INFINITY,
1298            f64::MAX, f64::MIN, -100., -32.,
1299        );
1300        assert_eq_m512d(r, e);
1301    }
1302
1303    #[simd_test(enable = "avx512f")]
1304    const fn test_mm512_maskz_mul_pd() {
1305        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1306        let b = _mm512_set1_pd(2.);
1307        let r = _mm512_maskz_mul_pd(0, a, b);
1308        assert_eq_m512d(r, _mm512_setzero_pd());
1309        let r = _mm512_maskz_mul_pd(0b00001111, a, b);
1310        let e = _mm512_setr_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1311        assert_eq_m512d(r, e);
1312    }
1313
1314    #[simd_test(enable = "avx512f,avx512vl")]
1315    const fn test_mm256_mask_mul_pd() {
1316        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1317        let b = _mm256_set1_pd(2.);
1318        let r = _mm256_mask_mul_pd(a, 0, a, b);
1319        assert_eq_m256d(r, a);
1320        let r = _mm256_mask_mul_pd(a, 0b00001111, a, b);
1321        let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1322        assert_eq_m256d(r, e);
1323    }
1324
1325    #[simd_test(enable = "avx512f,avx512vl")]
1326    const fn test_mm256_maskz_mul_pd() {
1327        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1328        let b = _mm256_set1_pd(2.);
1329        let r = _mm256_maskz_mul_pd(0, a, b);
1330        assert_eq_m256d(r, _mm256_setzero_pd());
1331        let r = _mm256_maskz_mul_pd(0b00001111, a, b);
1332        let e = _mm256_set_pd(0., 2., f64::INFINITY, f64::NEG_INFINITY);
1333        assert_eq_m256d(r, e);
1334    }
1335
1336    #[simd_test(enable = "avx512f,avx512vl")]
1337    const fn test_mm_mask_mul_pd() {
1338        let a = _mm_set_pd(f64::MAX, f64::MIN);
1339        let b = _mm_set1_pd(2.);
1340        let r = _mm_mask_mul_pd(a, 0, a, b);
1341        assert_eq_m128d(r, a);
1342        let r = _mm_mask_mul_pd(a, 0b00000011, a, b);
1343        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1344        assert_eq_m128d(r, e);
1345    }
1346
1347    #[simd_test(enable = "avx512f,avx512vl")]
1348    const fn test_mm_maskz_mul_pd() {
1349        let a = _mm_set_pd(f64::MAX, f64::MIN);
1350        let b = _mm_set1_pd(2.);
1351        let r = _mm_maskz_mul_pd(0, a, b);
1352        assert_eq_m128d(r, _mm_setzero_pd());
1353        let r = _mm_maskz_mul_pd(0b00000011, a, b);
1354        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1355        assert_eq_m128d(r, e);
1356    }
1357
1358    #[simd_test(enable = "avx512f")]
1359    const fn test_mm512_div_pd() {
1360        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1361        let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1362        let r = _mm512_div_pd(a, b);
1363        #[rustfmt::skip]
1364        let e = _mm512_setr_pd(
1365            0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1366            f64::INFINITY, f64::NEG_INFINITY, -50., -16.,
1367        );
1368        assert_eq_m512d(r, e);
1369    }
1370
1371    #[simd_test(enable = "avx512f")]
1372    const fn test_mm512_mask_div_pd() {
1373        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1374        let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1375        let r = _mm512_mask_div_pd(a, 0, a, b);
1376        assert_eq_m512d(r, a);
1377        let r = _mm512_mask_div_pd(a, 0b00001111, a, b);
1378        #[rustfmt::skip]
1379        let e = _mm512_setr_pd(
1380            0., 0.5, f64::INFINITY, f64::NEG_INFINITY,
1381            f64::MAX, f64::MIN, -100., -32.,
1382        );
1383        assert_eq_m512d(r, e);
1384    }
1385
1386    #[simd_test(enable = "avx512f")]
1387    const fn test_mm512_maskz_div_pd() {
1388        let a = _mm512_setr_pd(0., 1., f64::MAX, f64::MIN, f64::MAX, f64::MIN, -100., -32.);
1389        let b = _mm512_setr_pd(2., 2., 0., 0., 0., 0., 2., 2.);
1390        let r = _mm512_maskz_div_pd(0, a, b);
1391        assert_eq_m512d(r, _mm512_setzero_pd());
1392        let r = _mm512_maskz_div_pd(0b00001111, a, b);
1393        let e = _mm512_setr_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY, 0., 0., 0., 0.);
1394        assert_eq_m512d(r, e);
1395    }
1396
1397    #[simd_test(enable = "avx512f,avx512vl")]
1398    const fn test_mm256_mask_div_pd() {
1399        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1400        let b = _mm256_set_pd(2., 2., 0., 0.);
1401        let r = _mm256_mask_div_pd(a, 0, a, b);
1402        assert_eq_m256d(r, a);
1403        let r = _mm256_mask_div_pd(a, 0b00001111, a, b);
1404        let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1405        assert_eq_m256d(r, e);
1406    }
1407
1408    #[simd_test(enable = "avx512f,avx512vl")]
1409    const fn test_mm256_maskz_div_pd() {
1410        let a = _mm256_set_pd(0., 1., f64::MAX, f64::MIN);
1411        let b = _mm256_set_pd(2., 2., 0., 0.);
1412        let r = _mm256_maskz_div_pd(0, a, b);
1413        assert_eq_m256d(r, _mm256_setzero_pd());
1414        let r = _mm256_maskz_div_pd(0b00001111, a, b);
1415        let e = _mm256_set_pd(0., 0.5, f64::INFINITY, f64::NEG_INFINITY);
1416        assert_eq_m256d(r, e);
1417    }
1418
1419    #[simd_test(enable = "avx512f,avx512vl")]
1420    const fn test_mm_mask_div_pd() {
1421        let a = _mm_set_pd(f64::MAX, f64::MIN);
1422        let b = _mm_set_pd(0., 0.);
1423        let r = _mm_mask_div_pd(a, 0, a, b);
1424        assert_eq_m128d(r, a);
1425        let r = _mm_mask_div_pd(a, 0b00000011, a, b);
1426        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1427        assert_eq_m128d(r, e);
1428    }
1429
1430    #[simd_test(enable = "avx512f,avx512vl")]
1431    const fn test_mm_maskz_div_pd() {
1432        let a = _mm_set_pd(f64::MAX, f64::MIN);
1433        let b = _mm_set_pd(0., 0.);
1434        let r = _mm_maskz_div_pd(0, a, b);
1435        assert_eq_m128d(r, _mm_setzero_pd());
1436        let r = _mm_maskz_div_pd(0b00000011, a, b);
1437        let e = _mm_set_pd(f64::INFINITY, f64::NEG_INFINITY);
1438        assert_eq_m128d(r, e);
1439    }
1440
1441    #[simd_test(enable = "avx512f")]
1442    const fn test_mm512_max_epi64() {
1443        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1444        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1445        let r = _mm512_max_epi64(a, b);
1446        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1447        assert_eq_m512i(r, e);
1448    }
1449
1450    #[simd_test(enable = "avx512f")]
1451    const fn test_mm512_mask_max_epi64() {
1452        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1453        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1454        let r = _mm512_mask_max_epi64(a, 0, a, b);
1455        assert_eq_m512i(r, a);
1456        let r = _mm512_mask_max_epi64(a, 0b00001111, a, b);
1457        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1458        assert_eq_m512i(r, e);
1459    }
1460
1461    #[simd_test(enable = "avx512f")]
1462    const fn test_mm512_maskz_max_epi64() {
1463        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1464        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1465        let r = _mm512_maskz_max_epi64(0, a, b);
1466        assert_eq_m512i(r, _mm512_setzero_si512());
1467        let r = _mm512_maskz_max_epi64(0b00001111, a, b);
1468        let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1469        assert_eq_m512i(r, e);
1470    }
1471
1472    #[simd_test(enable = "avx512f,avx512vl")]
1473    const fn test_mm256_max_epi64() {
1474        let a = _mm256_set_epi64x(0, 1, 2, 3);
1475        let b = _mm256_set_epi64x(3, 2, 1, 0);
1476        let r = _mm256_max_epi64(a, b);
1477        let e = _mm256_set_epi64x(3, 2, 2, 3);
1478        assert_eq_m256i(r, e);
1479    }
1480
1481    #[simd_test(enable = "avx512f,avx512vl")]
1482    const fn test_mm256_mask_max_epi64() {
1483        let a = _mm256_set_epi64x(0, 1, 2, 3);
1484        let b = _mm256_set_epi64x(3, 2, 1, 0);
1485        let r = _mm256_mask_max_epi64(a, 0, a, b);
1486        assert_eq_m256i(r, a);
1487        let r = _mm256_mask_max_epi64(a, 0b00001111, a, b);
1488        let e = _mm256_set_epi64x(3, 2, 2, 3);
1489        assert_eq_m256i(r, e);
1490    }
1491
1492    #[simd_test(enable = "avx512f,avx512vl")]
1493    const fn test_mm256_maskz_max_epi64() {
1494        let a = _mm256_set_epi64x(0, 1, 2, 3);
1495        let b = _mm256_set_epi64x(3, 2, 1, 0);
1496        let r = _mm256_maskz_max_epi64(0, a, b);
1497        assert_eq_m256i(r, _mm256_setzero_si256());
1498        let r = _mm256_maskz_max_epi64(0b00001111, a, b);
1499        let e = _mm256_set_epi64x(3, 2, 2, 3);
1500        assert_eq_m256i(r, e);
1501    }
1502
1503    #[simd_test(enable = "avx512f,avx512vl")]
1504    const fn test_mm_max_epi64() {
1505        let a = _mm_set_epi64x(2, 3);
1506        let b = _mm_set_epi64x(3, 2);
1507        let r = _mm_max_epi64(a, b);
1508        let e = _mm_set_epi64x(3, 3);
1509        assert_eq_m128i(r, e);
1510    }
1511
1512    #[simd_test(enable = "avx512f,avx512vl")]
1513    const fn test_mm_mask_max_epi64() {
1514        let a = _mm_set_epi64x(2, 3);
1515        let b = _mm_set_epi64x(3, 2);
1516        let r = _mm_mask_max_epi64(a, 0, a, b);
1517        assert_eq_m128i(r, a);
1518        let r = _mm_mask_max_epi64(a, 0b00000011, a, b);
1519        let e = _mm_set_epi64x(3, 3);
1520        assert_eq_m128i(r, e);
1521    }
1522
1523    #[simd_test(enable = "avx512f,avx512vl")]
1524    const fn test_mm_maskz_max_epi64() {
1525        let a = _mm_set_epi64x(2, 3);
1526        let b = _mm_set_epi64x(3, 2);
1527        let r = _mm_maskz_max_epi64(0, a, b);
1528        assert_eq_m128i(r, _mm_setzero_si128());
1529        let r = _mm_maskz_max_epi64(0b00000011, a, b);
1530        let e = _mm_set_epi64x(3, 3);
1531        assert_eq_m128i(r, e);
1532    }
1533
1534    #[simd_test(enable = "avx512f")]
1535    fn test_mm512_max_pd() {
1536        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1537        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1538        let r = _mm512_max_pd(a, b);
1539        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1540        assert_eq_m512d(r, e);
1541    }
1542
1543    #[simd_test(enable = "avx512f")]
1544    fn test_mm512_mask_max_pd() {
1545        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1546        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1547        let r = _mm512_mask_max_pd(a, 0, a, b);
1548        assert_eq_m512d(r, a);
1549        let r = _mm512_mask_max_pd(a, 0b00001111, a, b);
1550        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
1551        assert_eq_m512d(r, e);
1552    }
1553
1554    #[simd_test(enable = "avx512f")]
1555    fn test_mm512_maskz_max_pd() {
1556        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1557        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1558        let r = _mm512_maskz_max_pd(0, a, b);
1559        assert_eq_m512d(r, _mm512_setzero_pd());
1560        let r = _mm512_maskz_max_pd(0b00001111, a, b);
1561        let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
1562        assert_eq_m512d(r, e);
1563    }
1564
1565    #[simd_test(enable = "avx512f,avx512vl")]
1566    fn test_mm256_mask_max_pd() {
1567        let a = _mm256_set_pd(0., 1., 2., 3.);
1568        let b = _mm256_set_pd(3., 2., 1., 0.);
1569        let r = _mm256_mask_max_pd(a, 0, a, b);
1570        assert_eq_m256d(r, a);
1571        let r = _mm256_mask_max_pd(a, 0b00001111, a, b);
1572        let e = _mm256_set_pd(3., 2., 2., 3.);
1573        assert_eq_m256d(r, e);
1574    }
1575
1576    #[simd_test(enable = "avx512f,avx512vl")]
1577    fn test_mm256_maskz_max_pd() {
1578        let a = _mm256_set_pd(0., 1., 2., 3.);
1579        let b = _mm256_set_pd(3., 2., 1., 0.);
1580        let r = _mm256_maskz_max_pd(0, a, b);
1581        assert_eq_m256d(r, _mm256_setzero_pd());
1582        let r = _mm256_maskz_max_pd(0b00001111, a, b);
1583        let e = _mm256_set_pd(3., 2., 2., 3.);
1584        assert_eq_m256d(r, e);
1585    }
1586
1587    #[simd_test(enable = "avx512f,avx512vl")]
1588    fn test_mm_mask_max_pd() {
1589        let a = _mm_set_pd(2., 3.);
1590        let b = _mm_set_pd(3., 2.);
1591        let r = _mm_mask_max_pd(a, 0, a, b);
1592        assert_eq_m128d(r, a);
1593        let r = _mm_mask_max_pd(a, 0b00000011, a, b);
1594        let e = _mm_set_pd(3., 3.);
1595        assert_eq_m128d(r, e);
1596    }
1597
1598    #[simd_test(enable = "avx512f,avx512vl")]
1599    fn test_mm_maskz_max_pd() {
1600        let a = _mm_set_pd(2., 3.);
1601        let b = _mm_set_pd(3., 2.);
1602        let r = _mm_maskz_max_pd(0, a, b);
1603        assert_eq_m128d(r, _mm_setzero_pd());
1604        let r = _mm_maskz_max_pd(0b00000011, a, b);
1605        let e = _mm_set_pd(3., 3.);
1606        assert_eq_m128d(r, e);
1607    }
1608
1609    #[simd_test(enable = "avx512f")]
1610    const fn test_mm512_max_epu64() {
1611        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1612        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1613        let r = _mm512_max_epu64(a, b);
1614        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1615        assert_eq_m512i(r, e);
1616    }
1617
1618    #[simd_test(enable = "avx512f")]
1619    const fn test_mm512_mask_max_epu64() {
1620        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1621        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1622        let r = _mm512_mask_max_epu64(a, 0, a, b);
1623        assert_eq_m512i(r, a);
1624        let r = _mm512_mask_max_epu64(a, 0b00001111, a, b);
1625        let e = _mm512_setr_epi64(7, 6, 5, 4, 4, 5, 6, 7);
1626        assert_eq_m512i(r, e);
1627    }
1628
1629    #[simd_test(enable = "avx512f")]
1630    const fn test_mm512_maskz_max_epu64() {
1631        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1632        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1633        let r = _mm512_maskz_max_epu64(0, a, b);
1634        assert_eq_m512i(r, _mm512_setzero_si512());
1635        let r = _mm512_maskz_max_epu64(0b00001111, a, b);
1636        let e = _mm512_setr_epi64(7, 6, 5, 4, 0, 0, 0, 0);
1637        assert_eq_m512i(r, e);
1638    }
1639
1640    #[simd_test(enable = "avx512f,avx512vl")]
1641    const fn test_mm256_max_epu64() {
1642        let a = _mm256_set_epi64x(0, 1, 2, 3);
1643        let b = _mm256_set_epi64x(3, 2, 1, 0);
1644        let r = _mm256_max_epu64(a, b);
1645        let e = _mm256_set_epi64x(3, 2, 2, 3);
1646        assert_eq_m256i(r, e);
1647    }
1648
1649    #[simd_test(enable = "avx512f,avx512vl")]
1650    const fn test_mm256_mask_max_epu64() {
1651        let a = _mm256_set_epi64x(0, 1, 2, 3);
1652        let b = _mm256_set_epi64x(3, 2, 1, 0);
1653        let r = _mm256_mask_max_epu64(a, 0, a, b);
1654        assert_eq_m256i(r, a);
1655        let r = _mm256_mask_max_epu64(a, 0b00001111, a, b);
1656        let e = _mm256_set_epi64x(3, 2, 2, 3);
1657        assert_eq_m256i(r, e);
1658    }
1659
1660    #[simd_test(enable = "avx512f,avx512vl")]
1661    const fn test_mm256_maskz_max_epu64() {
1662        let a = _mm256_set_epi64x(0, 1, 2, 3);
1663        let b = _mm256_set_epi64x(3, 2, 1, 0);
1664        let r = _mm256_maskz_max_epu64(0, a, b);
1665        assert_eq_m256i(r, _mm256_setzero_si256());
1666        let r = _mm256_maskz_max_epu64(0b00001111, a, b);
1667        let e = _mm256_set_epi64x(3, 2, 2, 3);
1668        assert_eq_m256i(r, e);
1669    }
1670
1671    #[simd_test(enable = "avx512f,avx512vl")]
1672    const fn test_mm_max_epu64() {
1673        let a = _mm_set_epi64x(2, 3);
1674        let b = _mm_set_epi64x(3, 2);
1675        let r = _mm_max_epu64(a, b);
1676        let e = _mm_set_epi64x(3, 3);
1677        assert_eq_m128i(r, e);
1678    }
1679
1680    #[simd_test(enable = "avx512f,avx512vl")]
1681    const fn test_mm_mask_max_epu64() {
1682        let a = _mm_set_epi64x(2, 3);
1683        let b = _mm_set_epi64x(3, 2);
1684        let r = _mm_mask_max_epu64(a, 0, a, b);
1685        assert_eq_m128i(r, a);
1686        let r = _mm_mask_max_epu64(a, 0b00000011, a, b);
1687        let e = _mm_set_epi64x(3, 3);
1688        assert_eq_m128i(r, e);
1689    }
1690
1691    #[simd_test(enable = "avx512f,avx512vl")]
1692    const fn test_mm_maskz_max_epu64() {
1693        let a = _mm_set_epi64x(2, 3);
1694        let b = _mm_set_epi64x(3, 2);
1695        let r = _mm_maskz_max_epu64(0, a, b);
1696        assert_eq_m128i(r, _mm_setzero_si128());
1697        let r = _mm_maskz_max_epu64(0b00000011, a, b);
1698        let e = _mm_set_epi64x(3, 3);
1699        assert_eq_m128i(r, e);
1700    }
1701
1702    #[simd_test(enable = "avx512f")]
1703    const fn test_mm512_min_epi64() {
1704        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1705        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1706        let r = _mm512_min_epi64(a, b);
1707        let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1708        assert_eq_m512i(r, e);
1709    }
1710
1711    #[simd_test(enable = "avx512f")]
1712    const fn test_mm512_mask_min_epi64() {
1713        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1714        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1715        let r = _mm512_mask_min_epi64(a, 0, a, b);
1716        assert_eq_m512i(r, a);
1717        let r = _mm512_mask_min_epi64(a, 0b00001111, a, b);
1718        let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1719        assert_eq_m512i(r, e);
1720    }
1721
1722    #[simd_test(enable = "avx512f")]
1723    const fn test_mm512_maskz_min_epi64() {
1724        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1725        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1726        let r = _mm512_maskz_min_epi64(0, a, b);
1727        assert_eq_m512i(r, _mm512_setzero_si512());
1728        let r = _mm512_maskz_min_epi64(0b00001111, a, b);
1729        let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1730        assert_eq_m512i(r, e);
1731    }
1732
1733    #[simd_test(enable = "avx512f,avx512vl")]
1734    const fn test_mm256_min_epi64() {
1735        let a = _mm256_set_epi64x(0, 1, 2, 3);
1736        let b = _mm256_set_epi64x(3, 2, 1, 0);
1737        let r = _mm256_min_epi64(a, b);
1738        let e = _mm256_set_epi64x(0, 1, 1, 0);
1739        assert_eq_m256i(r, e);
1740    }
1741
1742    #[simd_test(enable = "avx512f,avx512vl")]
1743    const fn test_mm256_mask_min_epi64() {
1744        let a = _mm256_set_epi64x(0, 1, 2, 3);
1745        let b = _mm256_set_epi64x(3, 2, 1, 0);
1746        let r = _mm256_mask_min_epi64(a, 0, a, b);
1747        assert_eq_m256i(r, a);
1748        let r = _mm256_mask_min_epi64(a, 0b00001111, a, b);
1749        let e = _mm256_set_epi64x(0, 1, 1, 0);
1750        assert_eq_m256i(r, e);
1751    }
1752
1753    #[simd_test(enable = "avx512f,avx512vl")]
1754    const fn test_mm256_maskz_min_epi64() {
1755        let a = _mm256_set_epi64x(0, 1, 2, 3);
1756        let b = _mm256_set_epi64x(3, 2, 1, 0);
1757        let r = _mm256_maskz_min_epi64(0, a, b);
1758        assert_eq_m256i(r, _mm256_setzero_si256());
1759        let r = _mm256_maskz_min_epi64(0b00001111, a, b);
1760        let e = _mm256_set_epi64x(0, 1, 1, 0);
1761        assert_eq_m256i(r, e);
1762    }
1763
1764    #[simd_test(enable = "avx512f,avx512vl")]
1765    const fn test_mm_min_epi64() {
1766        let a = _mm_set_epi64x(0, 1);
1767        let b = _mm_set_epi64x(3, 2);
1768        let r = _mm_min_epi64(a, b);
1769        let e = _mm_set_epi64x(0, 1);
1770        assert_eq_m128i(r, e);
1771        let a = _mm_set_epi64x(2, 3);
1772        let b = _mm_set_epi64x(1, 0);
1773        let r = _mm_min_epi64(a, b);
1774        let e = _mm_set_epi64x(1, 0);
1775        assert_eq_m128i(r, e);
1776    }
1777
1778    #[simd_test(enable = "avx512f,avx512vl")]
1779    const fn test_mm_mask_min_epi64() {
1780        let a = _mm_set_epi64x(0, 1);
1781        let b = _mm_set_epi64x(3, 2);
1782        let r = _mm_mask_min_epi64(a, 0, a, b);
1783        assert_eq_m128i(r, a);
1784        let r = _mm_mask_min_epi64(a, 0b00000011, a, b);
1785        let e = _mm_set_epi64x(0, 1);
1786        assert_eq_m128i(r, e);
1787    }
1788
1789    #[simd_test(enable = "avx512f,avx512vl")]
1790    const fn test_mm_maskz_min_epi64() {
1791        let a = _mm_set_epi64x(0, 1);
1792        let b = _mm_set_epi64x(3, 2);
1793        let r = _mm_maskz_min_epi64(0, a, b);
1794        assert_eq_m128i(r, _mm_setzero_si128());
1795        let r = _mm_maskz_min_epi64(0b00000011, a, b);
1796        let e = _mm_set_epi64x(0, 1);
1797        assert_eq_m128i(r, e);
1798    }
1799
1800    #[simd_test(enable = "avx512f")]
1801    fn test_mm512_min_pd() {
1802        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1803        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1804        let r = _mm512_min_pd(a, b);
1805        let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
1806        assert_eq_m512d(r, e);
1807    }
1808
1809    #[simd_test(enable = "avx512f")]
1810    fn test_mm512_mask_min_pd() {
1811        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1812        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1813        let r = _mm512_mask_min_pd(a, 0, a, b);
1814        assert_eq_m512d(r, a);
1815        let r = _mm512_mask_min_pd(a, 0b00001111, a, b);
1816        let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1817        assert_eq_m512d(r, e);
1818    }
1819
1820    #[simd_test(enable = "avx512f")]
1821    fn test_mm512_maskz_min_pd() {
1822        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1823        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
1824        let r = _mm512_maskz_min_pd(0, a, b);
1825        assert_eq_m512d(r, _mm512_setzero_pd());
1826        let r = _mm512_maskz_min_pd(0b00001111, a, b);
1827        let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1828        assert_eq_m512d(r, e);
1829    }
1830
1831    #[simd_test(enable = "avx512f,avx512vl")]
1832    fn test_mm256_mask_min_pd() {
1833        let a = _mm256_set_pd(0., 1., 2., 3.);
1834        let b = _mm256_set_pd(3., 2., 1., 0.);
1835        let r = _mm256_mask_min_pd(a, 0, a, b);
1836        assert_eq_m256d(r, a);
1837        let r = _mm256_mask_min_pd(a, 0b00001111, a, b);
1838        let e = _mm256_set_pd(0., 1., 1., 0.);
1839        assert_eq_m256d(r, e);
1840    }
1841
1842    #[simd_test(enable = "avx512f,avx512vl")]
1843    fn test_mm256_maskz_min_pd() {
1844        let a = _mm256_set_pd(0., 1., 2., 3.);
1845        let b = _mm256_set_pd(3., 2., 1., 0.);
1846        let r = _mm256_maskz_min_pd(0, a, b);
1847        assert_eq_m256d(r, _mm256_setzero_pd());
1848        let r = _mm256_maskz_min_pd(0b00001111, a, b);
1849        let e = _mm256_set_pd(0., 1., 1., 0.);
1850        assert_eq_m256d(r, e);
1851    }
1852
1853    #[simd_test(enable = "avx512f,avx512vl")]
1854    fn test_mm_mask_min_pd() {
1855        let a = _mm_set_pd(0., 1.);
1856        let b = _mm_set_pd(1., 0.);
1857        let r = _mm_mask_min_pd(a, 0, a, b);
1858        assert_eq_m128d(r, a);
1859        let r = _mm_mask_min_pd(a, 0b00000011, a, b);
1860        let e = _mm_set_pd(0., 0.);
1861        assert_eq_m128d(r, e);
1862    }
1863
1864    #[simd_test(enable = "avx512f,avx512vl")]
1865    fn test_mm_maskz_min_pd() {
1866        let a = _mm_set_pd(0., 1.);
1867        let b = _mm_set_pd(1., 0.);
1868        let r = _mm_maskz_min_pd(0, a, b);
1869        assert_eq_m128d(r, _mm_setzero_pd());
1870        let r = _mm_maskz_min_pd(0b00000011, a, b);
1871        let e = _mm_set_pd(0., 0.);
1872        assert_eq_m128d(r, e);
1873    }
1874
1875    #[simd_test(enable = "avx512f")]
1876    const fn test_mm512_min_epu64() {
1877        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1878        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1879        let r = _mm512_min_epu64(a, b);
1880        let e = _mm512_setr_epi64(0, 1, 2, 3, 3, 2, 1, 0);
1881        assert_eq_m512i(r, e);
1882    }
1883
1884    #[simd_test(enable = "avx512f")]
1885    const fn test_mm512_mask_min_epu64() {
1886        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1887        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1888        let r = _mm512_mask_min_epu64(a, 0, a, b);
1889        assert_eq_m512i(r, a);
1890        let r = _mm512_mask_min_epu64(a, 0b00001111, a, b);
1891        let e = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1892        assert_eq_m512i(r, e);
1893    }
1894
1895    #[simd_test(enable = "avx512f")]
1896    const fn test_mm512_maskz_min_epu64() {
1897        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
1898        let b = _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0);
1899        let r = _mm512_maskz_min_epu64(0, a, b);
1900        assert_eq_m512i(r, _mm512_setzero_si512());
1901        let r = _mm512_maskz_min_epu64(0b00001111, a, b);
1902        let e = _mm512_setr_epi64(0, 1, 2, 3, 0, 0, 0, 0);
1903        assert_eq_m512i(r, e);
1904    }
1905
1906    #[simd_test(enable = "avx512f,avx512vl")]
1907    const fn test_mm256_min_epu64() {
1908        let a = _mm256_set_epi64x(0, 1, 2, 3);
1909        let b = _mm256_set_epi64x(3, 2, 1, 0);
1910        let r = _mm256_min_epu64(a, b);
1911        let e = _mm256_set_epi64x(0, 1, 1, 0);
1912        assert_eq_m256i(r, e);
1913    }
1914
1915    #[simd_test(enable = "avx512f,avx512vl")]
1916    const fn test_mm256_mask_min_epu64() {
1917        let a = _mm256_set_epi64x(0, 1, 2, 3);
1918        let b = _mm256_set_epi64x(3, 2, 1, 0);
1919        let r = _mm256_mask_min_epu64(a, 0, a, b);
1920        assert_eq_m256i(r, a);
1921        let r = _mm256_mask_min_epu64(a, 0b00001111, a, b);
1922        let e = _mm256_set_epi64x(0, 1, 1, 0);
1923        assert_eq_m256i(r, e);
1924    }
1925
1926    #[simd_test(enable = "avx512f,avx512vl")]
1927    const fn test_mm256_maskz_min_epu64() {
1928        let a = _mm256_set_epi64x(0, 1, 2, 3);
1929        let b = _mm256_set_epi64x(3, 2, 1, 0);
1930        let r = _mm256_maskz_min_epu64(0, a, b);
1931        assert_eq_m256i(r, _mm256_setzero_si256());
1932        let r = _mm256_maskz_min_epu64(0b00001111, a, b);
1933        let e = _mm256_set_epi64x(0, 1, 1, 0);
1934        assert_eq_m256i(r, e);
1935    }
1936
1937    #[simd_test(enable = "avx512f,avx512vl")]
1938    const fn test_mm_min_epu64() {
1939        let a = _mm_set_epi64x(0, 1);
1940        let b = _mm_set_epi64x(1, 0);
1941        let r = _mm_min_epu64(a, b);
1942        let e = _mm_set_epi64x(0, 0);
1943        assert_eq_m128i(r, e);
1944    }
1945
1946    #[simd_test(enable = "avx512f,avx512vl")]
1947    const fn test_mm_mask_min_epu64() {
1948        let a = _mm_set_epi64x(0, 1);
1949        let b = _mm_set_epi64x(1, 0);
1950        let r = _mm_mask_min_epu64(a, 0, a, b);
1951        assert_eq_m128i(r, a);
1952        let r = _mm_mask_min_epu64(a, 0b00000011, a, b);
1953        let e = _mm_set_epi64x(0, 0);
1954        assert_eq_m128i(r, e);
1955    }
1956
1957    #[simd_test(enable = "avx512f,avx512vl")]
1958    const fn test_mm_maskz_min_epu64() {
1959        let a = _mm_set_epi64x(0, 1);
1960        let b = _mm_set_epi64x(1, 0);
1961        let r = _mm_maskz_min_epu64(0, a, b);
1962        assert_eq_m128i(r, _mm_setzero_si128());
1963        let r = _mm_maskz_min_epu64(0b00000011, a, b);
1964        let e = _mm_set_epi64x(0, 0);
1965        assert_eq_m128i(r, e);
1966    }
1967
1968    #[simd_test(enable = "avx512f")]
1969    fn test_mm512_sqrt_pd() {
1970        let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1971        let r = _mm512_sqrt_pd(a);
1972        let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
1973        assert_eq_m512d(r, e);
1974    }
1975
1976    #[simd_test(enable = "avx512f")]
1977    fn test_mm512_mask_sqrt_pd() {
1978        let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1979        let r = _mm512_mask_sqrt_pd(a, 0, a);
1980        assert_eq_m512d(r, a);
1981        let r = _mm512_mask_sqrt_pd(a, 0b00001111, a);
1982        let e = _mm512_setr_pd(0., 1., 2., 3., 16., 25., 36., 49.);
1983        assert_eq_m512d(r, e);
1984    }
1985
1986    #[simd_test(enable = "avx512f")]
1987    fn test_mm512_maskz_sqrt_pd() {
1988        let a = _mm512_setr_pd(0., 1., 4., 9., 16., 25., 36., 49.);
1989        let r = _mm512_maskz_sqrt_pd(0, a);
1990        assert_eq_m512d(r, _mm512_setzero_pd());
1991        let r = _mm512_maskz_sqrt_pd(0b00001111, a);
1992        let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
1993        assert_eq_m512d(r, e);
1994    }
1995
1996    #[simd_test(enable = "avx512f,avx512vl")]
1997    fn test_mm256_mask_sqrt_pd() {
1998        let a = _mm256_set_pd(0., 1., 4., 9.);
1999        let r = _mm256_mask_sqrt_pd(a, 0, a);
2000        assert_eq_m256d(r, a);
2001        let r = _mm256_mask_sqrt_pd(a, 0b00001111, a);
2002        let e = _mm256_set_pd(0., 1., 2., 3.);
2003        assert_eq_m256d(r, e);
2004    }
2005
2006    #[simd_test(enable = "avx512f,avx512vl")]
2007    fn test_mm256_maskz_sqrt_pd() {
2008        let a = _mm256_set_pd(0., 1., 4., 9.);
2009        let r = _mm256_maskz_sqrt_pd(0, a);
2010        assert_eq_m256d(r, _mm256_setzero_pd());
2011        let r = _mm256_maskz_sqrt_pd(0b00001111, a);
2012        let e = _mm256_set_pd(0., 1., 2., 3.);
2013        assert_eq_m256d(r, e);
2014    }
2015
2016    #[simd_test(enable = "avx512f,avx512vl")]
2017    fn test_mm_mask_sqrt_pd() {
2018        let a = _mm_set_pd(0., 1.);
2019        let r = _mm_mask_sqrt_pd(a, 0, a);
2020        assert_eq_m128d(r, a);
2021        let r = _mm_mask_sqrt_pd(a, 0b00000011, a);
2022        let e = _mm_set_pd(0., 1.);
2023        assert_eq_m128d(r, e);
2024    }
2025
2026    #[simd_test(enable = "avx512f,avx512vl")]
2027    fn test_mm_maskz_sqrt_pd() {
2028        let a = _mm_set_pd(0., 1.);
2029        let r = _mm_maskz_sqrt_pd(0, a);
2030        assert_eq_m128d(r, _mm_setzero_pd());
2031        let r = _mm_maskz_sqrt_pd(0b00000011, a);
2032        let e = _mm_set_pd(0., 1.);
2033        assert_eq_m128d(r, e);
2034    }
2035
2036    #[simd_test(enable = "avx512f")]
2037    const fn test_mm512_fmadd_pd() {
2038        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2039        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2040        let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2041        let r = _mm512_fmadd_pd(a, b, c);
2042        let e = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
2043        assert_eq_m512d(r, e);
2044    }
2045
2046    #[simd_test(enable = "avx512f")]
2047    const fn test_mm512_mask_fmadd_pd() {
2048        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2049        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2050        let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2051        let r = _mm512_mask_fmadd_pd(a, 0, b, c);
2052        assert_eq_m512d(r, a);
2053        let r = _mm512_mask_fmadd_pd(a, 0b00001111, b, c);
2054        let e = _mm512_setr_pd(1., 2., 3., 4., 1., 1., 1., 1.);
2055        assert_eq_m512d(r, e);
2056    }
2057
2058    #[simd_test(enable = "avx512f")]
2059    const fn test_mm512_maskz_fmadd_pd() {
2060        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2061        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2062        let c = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2063        let r = _mm512_maskz_fmadd_pd(0, a, b, c);
2064        assert_eq_m512d(r, _mm512_setzero_pd());
2065        let r = _mm512_maskz_fmadd_pd(0b00001111, a, b, c);
2066        let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
2067        assert_eq_m512d(r, e);
2068    }
2069
2070    #[simd_test(enable = "avx512f")]
2071    const fn test_mm512_mask3_fmadd_pd() {
2072        let a = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
2073        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2074        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2075        let r = _mm512_mask3_fmadd_pd(a, b, c, 0);
2076        assert_eq_m512d(r, c);
2077        let r = _mm512_mask3_fmadd_pd(a, b, c, 0b00001111);
2078        let e = _mm512_setr_pd(1., 2., 3., 4., 2., 2., 2., 2.);
2079        assert_eq_m512d(r, e);
2080    }
2081
2082    #[simd_test(enable = "avx512f,avx512vl")]
2083    const fn test_mm256_mask_fmadd_pd() {
2084        let a = _mm256_set1_pd(1.);
2085        let b = _mm256_set_pd(0., 1., 2., 3.);
2086        let c = _mm256_set1_pd(1.);
2087        let r = _mm256_mask_fmadd_pd(a, 0, b, c);
2088        assert_eq_m256d(r, a);
2089        let r = _mm256_mask_fmadd_pd(a, 0b00001111, b, c);
2090        let e = _mm256_set_pd(1., 2., 3., 4.);
2091        assert_eq_m256d(r, e);
2092    }
2093
2094    #[simd_test(enable = "avx512f,avx512vl")]
2095    const fn test_mm256_maskz_fmadd_pd() {
2096        let a = _mm256_set1_pd(1.);
2097        let b = _mm256_set_pd(0., 1., 2., 3.);
2098        let c = _mm256_set1_pd(1.);
2099        let r = _mm256_maskz_fmadd_pd(0, a, b, c);
2100        assert_eq_m256d(r, _mm256_setzero_pd());
2101        let r = _mm256_maskz_fmadd_pd(0b00001111, a, b, c);
2102        let e = _mm256_set_pd(1., 2., 3., 4.);
2103        assert_eq_m256d(r, e);
2104    }
2105
2106    #[simd_test(enable = "avx512f,avx512vl")]
2107    const fn test_mm256_mask3_fmadd_pd() {
2108        let a = _mm256_set1_pd(1.);
2109        let b = _mm256_set_pd(0., 1., 2., 3.);
2110        let c = _mm256_set1_pd(1.);
2111        let r = _mm256_mask3_fmadd_pd(a, b, c, 0);
2112        assert_eq_m256d(r, c);
2113        let r = _mm256_mask3_fmadd_pd(a, b, c, 0b00001111);
2114        let e = _mm256_set_pd(1., 2., 3., 4.);
2115        assert_eq_m256d(r, e);
2116    }
2117
2118    #[simd_test(enable = "avx512f,avx512vl")]
2119    const fn test_mm_mask_fmadd_pd() {
2120        let a = _mm_set1_pd(1.);
2121        let b = _mm_set_pd(0., 1.);
2122        let c = _mm_set1_pd(1.);
2123        let r = _mm_mask_fmadd_pd(a, 0, b, c);
2124        assert_eq_m128d(r, a);
2125        let r = _mm_mask_fmadd_pd(a, 0b00000011, b, c);
2126        let e = _mm_set_pd(1., 2.);
2127        assert_eq_m128d(r, e);
2128    }
2129
2130    #[simd_test(enable = "avx512f,avx512vl")]
2131    const fn test_mm_maskz_fmadd_pd() {
2132        let a = _mm_set1_pd(1.);
2133        let b = _mm_set_pd(0., 1.);
2134        let c = _mm_set1_pd(1.);
2135        let r = _mm_maskz_fmadd_pd(0, a, b, c);
2136        assert_eq_m128d(r, _mm_setzero_pd());
2137        let r = _mm_maskz_fmadd_pd(0b00000011, a, b, c);
2138        let e = _mm_set_pd(1., 2.);
2139        assert_eq_m128d(r, e);
2140    }
2141
2142    #[simd_test(enable = "avx512f,avx512vl")]
2143    const fn test_mm_mask3_fmadd_pd() {
2144        let a = _mm_set1_pd(1.);
2145        let b = _mm_set_pd(0., 1.);
2146        let c = _mm_set1_pd(1.);
2147        let r = _mm_mask3_fmadd_pd(a, b, c, 0);
2148        assert_eq_m128d(r, c);
2149        let r = _mm_mask3_fmadd_pd(a, b, c, 0b00000011);
2150        let e = _mm_set_pd(1., 2.);
2151        assert_eq_m128d(r, e);
2152    }
2153
2154    #[simd_test(enable = "avx512f")]
2155    const fn test_mm512_fmsub_pd() {
2156        let a = _mm512_set1_pd(1.);
2157        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2158        let c = _mm512_set1_pd(1.);
2159        let r = _mm512_fmsub_pd(a, b, c);
2160        let e = _mm512_setr_pd(-1., 0., 1., 2., 3., 4., 5., 6.);
2161        assert_eq_m512d(r, e);
2162    }
2163
2164    #[simd_test(enable = "avx512f")]
2165    const fn test_mm512_mask_fmsub_pd() {
2166        let a = _mm512_set1_pd(1.);
2167        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2168        let c = _mm512_set1_pd(1.);
2169        let r = _mm512_mask_fmsub_pd(a, 0, b, c);
2170        assert_eq_m512d(r, a);
2171        let r = _mm512_mask_fmsub_pd(a, 0b00001111, b, c);
2172        let e = _mm512_setr_pd(-1., 0., 1., 2., 1., 1., 1., 1.);
2173        assert_eq_m512d(r, e);
2174    }
2175
2176    #[simd_test(enable = "avx512f")]
2177    const fn test_mm512_maskz_fmsub_pd() {
2178        let a = _mm512_set1_pd(1.);
2179        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2180        let c = _mm512_set1_pd(1.);
2181        let r = _mm512_maskz_fmsub_pd(0, a, b, c);
2182        assert_eq_m512d(r, _mm512_setzero_pd());
2183        let r = _mm512_maskz_fmsub_pd(0b00001111, a, b, c);
2184        let e = _mm512_setr_pd(-1., 0., 1., 2., 0., 0., 0., 0.);
2185        assert_eq_m512d(r, e);
2186    }
2187
2188    #[simd_test(enable = "avx512f")]
2189    const fn test_mm512_mask3_fmsub_pd() {
2190        let a = _mm512_set1_pd(1.);
2191        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2192        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2193        let r = _mm512_mask3_fmsub_pd(a, b, c, 0);
2194        assert_eq_m512d(r, c);
2195        let r = _mm512_mask3_fmsub_pd(a, b, c, 0b00001111);
2196        let e = _mm512_setr_pd(-1., 0., 1., 2., 2., 2., 2., 2.);
2197        assert_eq_m512d(r, e);
2198    }
2199
2200    #[simd_test(enable = "avx512f,avx512vl")]
2201    const fn test_mm256_mask_fmsub_pd() {
2202        let a = _mm256_set1_pd(1.);
2203        let b = _mm256_set_pd(0., 1., 2., 3.);
2204        let c = _mm256_set1_pd(1.);
2205        let r = _mm256_mask_fmsub_pd(a, 0, b, c);
2206        assert_eq_m256d(r, a);
2207        let r = _mm256_mask_fmsub_pd(a, 0b00001111, b, c);
2208        let e = _mm256_set_pd(-1., 0., 1., 2.);
2209        assert_eq_m256d(r, e);
2210    }
2211
2212    #[simd_test(enable = "avx512f,avx512vl")]
2213    const fn test_mm256_maskz_fmsub_pd() {
2214        let a = _mm256_set1_pd(1.);
2215        let b = _mm256_set_pd(0., 1., 2., 3.);
2216        let c = _mm256_set1_pd(1.);
2217        let r = _mm256_maskz_fmsub_pd(0, a, b, c);
2218        assert_eq_m256d(r, _mm256_setzero_pd());
2219        let r = _mm256_maskz_fmsub_pd(0b00001111, a, b, c);
2220        let e = _mm256_set_pd(-1., 0., 1., 2.);
2221        assert_eq_m256d(r, e);
2222    }
2223
2224    #[simd_test(enable = "avx512f,avx512vl")]
2225    const fn test_mm256_mask3_fmsub_pd() {
2226        let a = _mm256_set1_pd(1.);
2227        let b = _mm256_set_pd(0., 1., 2., 3.);
2228        let c = _mm256_set1_pd(1.);
2229        let r = _mm256_mask3_fmsub_pd(a, b, c, 0);
2230        assert_eq_m256d(r, c);
2231        let r = _mm256_mask3_fmsub_pd(a, b, c, 0b00001111);
2232        let e = _mm256_set_pd(-1., 0., 1., 2.);
2233        assert_eq_m256d(r, e);
2234    }
2235
2236    #[simd_test(enable = "avx512f,avx512vl")]
2237    const fn test_mm_mask_fmsub_pd() {
2238        let a = _mm_set1_pd(1.);
2239        let b = _mm_set_pd(0., 1.);
2240        let c = _mm_set1_pd(1.);
2241        let r = _mm_mask_fmsub_pd(a, 0, b, c);
2242        assert_eq_m128d(r, a);
2243        let r = _mm_mask_fmsub_pd(a, 0b00000011, b, c);
2244        let e = _mm_set_pd(-1., 0.);
2245        assert_eq_m128d(r, e);
2246    }
2247
2248    #[simd_test(enable = "avx512f,avx512vl")]
2249    const fn test_mm_maskz_fmsub_pd() {
2250        let a = _mm_set1_pd(1.);
2251        let b = _mm_set_pd(0., 1.);
2252        let c = _mm_set1_pd(1.);
2253        let r = _mm_maskz_fmsub_pd(0, a, b, c);
2254        assert_eq_m128d(r, _mm_setzero_pd());
2255        let r = _mm_maskz_fmsub_pd(0b00000011, a, b, c);
2256        let e = _mm_set_pd(-1., 0.);
2257        assert_eq_m128d(r, e);
2258    }
2259
2260    #[simd_test(enable = "avx512f,avx512vl")]
2261    const fn test_mm_mask3_fmsub_pd() {
2262        let a = _mm_set1_pd(1.);
2263        let b = _mm_set_pd(0., 1.);
2264        let c = _mm_set1_pd(1.);
2265        let r = _mm_mask3_fmsub_pd(a, b, c, 0);
2266        assert_eq_m128d(r, c);
2267        let r = _mm_mask3_fmsub_pd(a, b, c, 0b00000011);
2268        let e = _mm_set_pd(-1., 0.);
2269        assert_eq_m128d(r, e);
2270    }
2271
2272    #[simd_test(enable = "avx512f")]
2273    const fn test_mm512_fmaddsub_pd() {
2274        let a = _mm512_set1_pd(1.);
2275        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2276        let c = _mm512_set1_pd(1.);
2277        let r = _mm512_fmaddsub_pd(a, b, c);
2278        let e = _mm512_setr_pd(-1., 2., 1., 4., 3., 6., 5., 8.);
2279        assert_eq_m512d(r, e);
2280    }
2281
2282    #[simd_test(enable = "avx512f")]
2283    const fn test_mm512_mask_fmaddsub_pd() {
2284        let a = _mm512_set1_pd(1.);
2285        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2286        let c = _mm512_set1_pd(1.);
2287        let r = _mm512_mask_fmaddsub_pd(a, 0, b, c);
2288        assert_eq_m512d(r, a);
2289        let r = _mm512_mask_fmaddsub_pd(a, 0b00001111, b, c);
2290        let e = _mm512_setr_pd(-1., 2., 1., 4., 1., 1., 1., 1.);
2291        assert_eq_m512d(r, e);
2292    }
2293
2294    #[simd_test(enable = "avx512f")]
2295    const fn test_mm512_maskz_fmaddsub_pd() {
2296        let a = _mm512_set1_pd(1.);
2297        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2298        let c = _mm512_set1_pd(1.);
2299        let r = _mm512_maskz_fmaddsub_pd(0, a, b, c);
2300        assert_eq_m512d(r, _mm512_setzero_pd());
2301        let r = _mm512_maskz_fmaddsub_pd(0b00001111, a, b, c);
2302        let e = _mm512_setr_pd(-1., 2., 1., 4., 0., 0., 0., 0.);
2303        assert_eq_m512d(r, e);
2304    }
2305
2306    #[simd_test(enable = "avx512f")]
2307    const fn test_mm512_mask3_fmaddsub_pd() {
2308        let a = _mm512_set1_pd(1.);
2309        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2310        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2311        let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0);
2312        assert_eq_m512d(r, c);
2313        let r = _mm512_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2314        let e = _mm512_setr_pd(-1., 2., 1., 4., 2., 2., 2., 2.);
2315        assert_eq_m512d(r, e);
2316    }
2317
2318    #[simd_test(enable = "avx512f,avx512vl")]
2319    const fn test_mm256_mask_fmaddsub_pd() {
2320        let a = _mm256_set1_pd(1.);
2321        let b = _mm256_set_pd(0., 1., 2., 3.);
2322        let c = _mm256_set1_pd(1.);
2323        let r = _mm256_mask_fmaddsub_pd(a, 0, b, c);
2324        assert_eq_m256d(r, a);
2325        let r = _mm256_mask_fmaddsub_pd(a, 0b00001111, b, c);
2326        let e = _mm256_set_pd(1., 0., 3., 2.);
2327        assert_eq_m256d(r, e);
2328    }
2329
2330    #[simd_test(enable = "avx512f,avx512vl")]
2331    const fn test_mm256_maskz_fmaddsub_pd() {
2332        let a = _mm256_set1_pd(1.);
2333        let b = _mm256_set_pd(0., 1., 2., 3.);
2334        let c = _mm256_set1_pd(1.);
2335        let r = _mm256_maskz_fmaddsub_pd(0, a, b, c);
2336        assert_eq_m256d(r, _mm256_setzero_pd());
2337        let r = _mm256_maskz_fmaddsub_pd(0b00001111, a, b, c);
2338        let e = _mm256_set_pd(1., 0., 3., 2.);
2339        assert_eq_m256d(r, e);
2340    }
2341
2342    #[simd_test(enable = "avx512f,avx512vl")]
2343    const fn test_mm256_mask3_fmaddsub_pd() {
2344        let a = _mm256_set1_pd(1.);
2345        let b = _mm256_set_pd(0., 1., 2., 3.);
2346        let c = _mm256_set1_pd(1.);
2347        let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0);
2348        assert_eq_m256d(r, c);
2349        let r = _mm256_mask3_fmaddsub_pd(a, b, c, 0b00001111);
2350        let e = _mm256_set_pd(1., 0., 3., 2.);
2351        assert_eq_m256d(r, e);
2352    }
2353
2354    #[simd_test(enable = "avx512f,avx512vl")]
2355    const fn test_mm_mask_fmaddsub_pd() {
2356        let a = _mm_set1_pd(1.);
2357        let b = _mm_set_pd(0., 1.);
2358        let c = _mm_set1_pd(1.);
2359        let r = _mm_mask_fmaddsub_pd(a, 0, b, c);
2360        assert_eq_m128d(r, a);
2361        let r = _mm_mask_fmaddsub_pd(a, 0b00000011, b, c);
2362        let e = _mm_set_pd(1., 0.);
2363        assert_eq_m128d(r, e);
2364    }
2365
2366    #[simd_test(enable = "avx512f,avx512vl")]
2367    const fn test_mm_maskz_fmaddsub_pd() {
2368        let a = _mm_set1_pd(1.);
2369        let b = _mm_set_pd(0., 1.);
2370        let c = _mm_set1_pd(1.);
2371        let r = _mm_maskz_fmaddsub_pd(0, a, b, c);
2372        assert_eq_m128d(r, _mm_setzero_pd());
2373        let r = _mm_maskz_fmaddsub_pd(0b00000011, a, b, c);
2374        let e = _mm_set_pd(1., 0.);
2375        assert_eq_m128d(r, e);
2376    }
2377
2378    #[simd_test(enable = "avx512f,avx512vl")]
2379    const fn test_mm_mask3_fmaddsub_pd() {
2380        let a = _mm_set1_pd(1.);
2381        let b = _mm_set_pd(0., 1.);
2382        let c = _mm_set1_pd(1.);
2383        let r = _mm_mask3_fmaddsub_pd(a, b, c, 0);
2384        assert_eq_m128d(r, c);
2385        let r = _mm_mask3_fmaddsub_pd(a, b, c, 0b00000011);
2386        let e = _mm_set_pd(1., 0.);
2387        assert_eq_m128d(r, e);
2388    }
2389
2390    #[simd_test(enable = "avx512f")]
2391    const fn test_mm512_fmsubadd_pd() {
2392        let a = _mm512_set1_pd(1.);
2393        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2394        let c = _mm512_set1_pd(1.);
2395        let r = _mm512_fmsubadd_pd(a, b, c);
2396        let e = _mm512_setr_pd(1., 0., 3., 2., 5., 4., 7., 6.);
2397        assert_eq_m512d(r, e);
2398    }
2399
2400    #[simd_test(enable = "avx512f")]
2401    const fn test_mm512_mask_fmsubadd_pd() {
2402        let a = _mm512_set1_pd(1.);
2403        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2404        let c = _mm512_set1_pd(1.);
2405        let r = _mm512_mask_fmsubadd_pd(a, 0, b, c);
2406        assert_eq_m512d(r, a);
2407        let r = _mm512_mask_fmsubadd_pd(a, 0b00001111, b, c);
2408        let e = _mm512_setr_pd(1., 0., 3., 2., 1., 1., 1., 1.);
2409        assert_eq_m512d(r, e);
2410    }
2411
2412    #[simd_test(enable = "avx512f")]
2413    const fn test_mm512_maskz_fmsubadd_pd() {
2414        let a = _mm512_set1_pd(1.);
2415        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2416        let c = _mm512_set1_pd(1.);
2417        let r = _mm512_maskz_fmsubadd_pd(0, a, b, c);
2418        assert_eq_m512d(r, _mm512_setzero_pd());
2419        let r = _mm512_maskz_fmsubadd_pd(0b00001111, a, b, c);
2420        let e = _mm512_setr_pd(1., 0., 3., 2., 0., 0., 0., 0.);
2421        assert_eq_m512d(r, e);
2422    }
2423
2424    #[simd_test(enable = "avx512f")]
2425    const fn test_mm512_mask3_fmsubadd_pd() {
2426        let a = _mm512_set1_pd(1.);
2427        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2428        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2429        let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0);
2430        assert_eq_m512d(r, c);
2431        let r = _mm512_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2432        let e = _mm512_setr_pd(1., 0., 3., 2., 2., 2., 2., 2.);
2433        assert_eq_m512d(r, e);
2434    }
2435
2436    #[simd_test(enable = "avx512f,avx512vl")]
2437    const fn test_mm256_mask_fmsubadd_pd() {
2438        let a = _mm256_set1_pd(1.);
2439        let b = _mm256_set_pd(0., 1., 2., 3.);
2440        let c = _mm256_set1_pd(1.);
2441        let r = _mm256_mask_fmsubadd_pd(a, 0, b, c);
2442        assert_eq_m256d(r, a);
2443        let r = _mm256_mask_fmsubadd_pd(a, 0b00001111, b, c);
2444        let e = _mm256_set_pd(-1., 2., 1., 4.);
2445        assert_eq_m256d(r, e);
2446    }
2447
2448    #[simd_test(enable = "avx512f,avx512vl")]
2449    const fn test_mm256_maskz_fmsubadd_pd() {
2450        let a = _mm256_set1_pd(1.);
2451        let b = _mm256_set_pd(0., 1., 2., 3.);
2452        let c = _mm256_set1_pd(1.);
2453        let r = _mm256_maskz_fmsubadd_pd(0, a, b, c);
2454        assert_eq_m256d(r, _mm256_setzero_pd());
2455        let r = _mm256_maskz_fmsubadd_pd(0b00001111, a, b, c);
2456        let e = _mm256_set_pd(-1., 2., 1., 4.);
2457        assert_eq_m256d(r, e);
2458    }
2459
2460    #[simd_test(enable = "avx512f,avx512vl")]
2461    const fn test_mm256_mask3_fmsubadd_pd() {
2462        let a = _mm256_set1_pd(1.);
2463        let b = _mm256_set_pd(0., 1., 2., 3.);
2464        let c = _mm256_set1_pd(1.);
2465        let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0);
2466        assert_eq_m256d(r, c);
2467        let r = _mm256_mask3_fmsubadd_pd(a, b, c, 0b00001111);
2468        let e = _mm256_set_pd(-1., 2., 1., 4.);
2469        assert_eq_m256d(r, e);
2470    }
2471
2472    #[simd_test(enable = "avx512f,avx512vl")]
2473    const fn test_mm_mask_fmsubadd_pd() {
2474        let a = _mm_set1_pd(1.);
2475        let b = _mm_set_pd(0., 1.);
2476        let c = _mm_set1_pd(1.);
2477        let r = _mm_mask_fmsubadd_pd(a, 0, b, c);
2478        assert_eq_m128d(r, a);
2479        let r = _mm_mask_fmsubadd_pd(a, 0b00000011, b, c);
2480        let e = _mm_set_pd(-1., 2.);
2481        assert_eq_m128d(r, e);
2482    }
2483
2484    #[simd_test(enable = "avx512f,avx512vl")]
2485    const fn test_mm_maskz_fmsubadd_pd() {
2486        let a = _mm_set1_pd(1.);
2487        let b = _mm_set_pd(0., 1.);
2488        let c = _mm_set1_pd(1.);
2489        let r = _mm_maskz_fmsubadd_pd(0, a, b, c);
2490        assert_eq_m128d(r, _mm_setzero_pd());
2491        let r = _mm_maskz_fmsubadd_pd(0b00000011, a, b, c);
2492        let e = _mm_set_pd(-1., 2.);
2493        assert_eq_m128d(r, e);
2494    }
2495
2496    #[simd_test(enable = "avx512f,avx512vl")]
2497    const fn test_mm_mask3_fmsubadd_pd() {
2498        let a = _mm_set1_pd(1.);
2499        let b = _mm_set_pd(0., 1.);
2500        let c = _mm_set1_pd(1.);
2501        let r = _mm_mask3_fmsubadd_pd(a, b, c, 0);
2502        assert_eq_m128d(r, c);
2503        let r = _mm_mask3_fmsubadd_pd(a, b, c, 0b00000011);
2504        let e = _mm_set_pd(-1., 2.);
2505        assert_eq_m128d(r, e);
2506    }
2507
2508    #[simd_test(enable = "avx512f")]
2509    const fn test_mm512_fnmadd_pd() {
2510        let a = _mm512_set1_pd(1.);
2511        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2512        let c = _mm512_set1_pd(1.);
2513        let r = _mm512_fnmadd_pd(a, b, c);
2514        let e = _mm512_setr_pd(1., 0., -1., -2., -3., -4., -5., -6.);
2515        assert_eq_m512d(r, e);
2516    }
2517
2518    #[simd_test(enable = "avx512f")]
2519    const fn test_mm512_mask_fnmadd_pd() {
2520        let a = _mm512_set1_pd(1.);
2521        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2522        let c = _mm512_set1_pd(1.);
2523        let r = _mm512_mask_fnmadd_pd(a, 0, b, c);
2524        assert_eq_m512d(r, a);
2525        let r = _mm512_mask_fnmadd_pd(a, 0b00001111, b, c);
2526        let e = _mm512_setr_pd(1., 0., -1., -2., 1., 1., 1., 1.);
2527        assert_eq_m512d(r, e);
2528    }
2529
2530    #[simd_test(enable = "avx512f")]
2531    const fn test_mm512_maskz_fnmadd_pd() {
2532        let a = _mm512_set1_pd(1.);
2533        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2534        let c = _mm512_set1_pd(1.);
2535        let r = _mm512_maskz_fnmadd_pd(0, a, b, c);
2536        assert_eq_m512d(r, _mm512_setzero_pd());
2537        let r = _mm512_maskz_fnmadd_pd(0b00001111, a, b, c);
2538        let e = _mm512_setr_pd(1., 0., -1., -2., 0., 0., 0., 0.);
2539        assert_eq_m512d(r, e);
2540    }
2541
2542    #[simd_test(enable = "avx512f")]
2543    const fn test_mm512_mask3_fnmadd_pd() {
2544        let a = _mm512_set1_pd(1.);
2545        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2546        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2547        let r = _mm512_mask3_fnmadd_pd(a, b, c, 0);
2548        assert_eq_m512d(r, c);
2549        let r = _mm512_mask3_fnmadd_pd(a, b, c, 0b00001111);
2550        let e = _mm512_setr_pd(1., 0., -1., -2., 2., 2., 2., 2.);
2551        assert_eq_m512d(r, e);
2552    }
2553
2554    #[simd_test(enable = "avx512f,avx512vl")]
2555    const fn test_mm256_mask_fnmadd_pd() {
2556        let a = _mm256_set1_pd(1.);
2557        let b = _mm256_set_pd(0., 1., 2., 3.);
2558        let c = _mm256_set1_pd(1.);
2559        let r = _mm256_mask_fnmadd_pd(a, 0, b, c);
2560        assert_eq_m256d(r, a);
2561        let r = _mm256_mask_fnmadd_pd(a, 0b00001111, b, c);
2562        let e = _mm256_set_pd(1., 0., -1., -2.);
2563        assert_eq_m256d(r, e);
2564    }
2565
2566    #[simd_test(enable = "avx512f,avx512vl")]
2567    const fn test_mm256_maskz_fnmadd_pd() {
2568        let a = _mm256_set1_pd(1.);
2569        let b = _mm256_set_pd(0., 1., 2., 3.);
2570        let c = _mm256_set1_pd(1.);
2571        let r = _mm256_maskz_fnmadd_pd(0, a, b, c);
2572        assert_eq_m256d(r, _mm256_setzero_pd());
2573        let r = _mm256_maskz_fnmadd_pd(0b00001111, a, b, c);
2574        let e = _mm256_set_pd(1., 0., -1., -2.);
2575        assert_eq_m256d(r, e);
2576    }
2577
2578    #[simd_test(enable = "avx512f,avx512vl")]
2579    const fn test_mm256_mask3_fnmadd_pd() {
2580        let a = _mm256_set1_pd(1.);
2581        let b = _mm256_set_pd(0., 1., 2., 3.);
2582        let c = _mm256_set1_pd(1.);
2583        let r = _mm256_mask3_fnmadd_pd(a, b, c, 0);
2584        assert_eq_m256d(r, c);
2585        let r = _mm256_mask3_fnmadd_pd(a, b, c, 0b00001111);
2586        let e = _mm256_set_pd(1., 0., -1., -2.);
2587        assert_eq_m256d(r, e);
2588    }
2589
2590    #[simd_test(enable = "avx512f,avx512vl")]
2591    const fn test_mm_mask_fnmadd_pd() {
2592        let a = _mm_set1_pd(1.);
2593        let b = _mm_set_pd(0., 1.);
2594        let c = _mm_set1_pd(1.);
2595        let r = _mm_mask_fnmadd_pd(a, 0, b, c);
2596        assert_eq_m128d(r, a);
2597        let r = _mm_mask_fnmadd_pd(a, 0b00000011, b, c);
2598        let e = _mm_set_pd(1., 0.);
2599        assert_eq_m128d(r, e);
2600    }
2601
2602    #[simd_test(enable = "avx512f,avx512vl")]
2603    const fn test_mm_maskz_fnmadd_pd() {
2604        let a = _mm_set1_pd(1.);
2605        let b = _mm_set_pd(0., 1.);
2606        let c = _mm_set1_pd(1.);
2607        let r = _mm_maskz_fnmadd_pd(0, a, b, c);
2608        assert_eq_m128d(r, _mm_setzero_pd());
2609        let r = _mm_maskz_fnmadd_pd(0b00000011, a, b, c);
2610        let e = _mm_set_pd(1., 0.);
2611        assert_eq_m128d(r, e);
2612    }
2613
2614    #[simd_test(enable = "avx512f,avx512vl")]
2615    const fn test_mm_mask3_fnmadd_pd() {
2616        let a = _mm_set1_pd(1.);
2617        let b = _mm_set_pd(0., 1.);
2618        let c = _mm_set1_pd(1.);
2619        let r = _mm_mask3_fnmadd_pd(a, b, c, 0);
2620        assert_eq_m128d(r, c);
2621        let r = _mm_mask3_fnmadd_pd(a, b, c, 0b00000011);
2622        let e = _mm_set_pd(1., 0.);
2623        assert_eq_m128d(r, e);
2624    }
2625
2626    #[simd_test(enable = "avx512f")]
2627    const fn test_mm512_fnmsub_pd() {
2628        let a = _mm512_set1_pd(1.);
2629        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2630        let c = _mm512_set1_pd(1.);
2631        let r = _mm512_fnmsub_pd(a, b, c);
2632        let e = _mm512_setr_pd(-1., -2., -3., -4., -5., -6., -7., -8.);
2633        assert_eq_m512d(r, e);
2634    }
2635
2636    #[simd_test(enable = "avx512f")]
2637    const fn test_mm512_mask_fnmsub_pd() {
2638        let a = _mm512_set1_pd(1.);
2639        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2640        let c = _mm512_set1_pd(1.);
2641        let r = _mm512_mask_fnmsub_pd(a, 0, b, c);
2642        assert_eq_m512d(r, a);
2643        let r = _mm512_mask_fnmsub_pd(a, 0b00001111, b, c);
2644        let e = _mm512_setr_pd(-1., -2., -3., -4., 1., 1., 1., 1.);
2645        assert_eq_m512d(r, e);
2646    }
2647
2648    #[simd_test(enable = "avx512f")]
2649    const fn test_mm512_maskz_fnmsub_pd() {
2650        let a = _mm512_set1_pd(1.);
2651        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2652        let c = _mm512_set1_pd(1.);
2653        let r = _mm512_maskz_fnmsub_pd(0, a, b, c);
2654        assert_eq_m512d(r, _mm512_setzero_pd());
2655        let r = _mm512_maskz_fnmsub_pd(0b00001111, a, b, c);
2656        let e = _mm512_setr_pd(-1., -2., -3., -4., 0., 0., 0., 0.);
2657        assert_eq_m512d(r, e);
2658    }
2659
2660    #[simd_test(enable = "avx512f")]
2661    const fn test_mm512_mask3_fnmsub_pd() {
2662        let a = _mm512_set1_pd(1.);
2663        let b = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
2664        let c = _mm512_setr_pd(1., 1., 1., 1., 2., 2., 2., 2.);
2665        let r = _mm512_mask3_fnmsub_pd(a, b, c, 0);
2666        assert_eq_m512d(r, c);
2667        let r = _mm512_mask3_fnmsub_pd(a, b, c, 0b00001111);
2668        let e = _mm512_setr_pd(-1., -2., -3., -4., 2., 2., 2., 2.);
2669        assert_eq_m512d(r, e);
2670    }
2671
2672    #[simd_test(enable = "avx512f,avx512vl")]
2673    const fn test_mm256_mask_fnmsub_pd() {
2674        let a = _mm256_set1_pd(1.);
2675        let b = _mm256_set_pd(0., 1., 2., 3.);
2676        let c = _mm256_set1_pd(1.);
2677        let r = _mm256_mask_fnmsub_pd(a, 0, b, c);
2678        assert_eq_m256d(r, a);
2679        let r = _mm256_mask_fnmsub_pd(a, 0b00001111, b, c);
2680        let e = _mm256_set_pd(-1., -2., -3., -4.);
2681        assert_eq_m256d(r, e);
2682    }
2683
2684    #[simd_test(enable = "avx512f,avx512vl")]
2685    const fn test_mm256_maskz_fnmsub_pd() {
2686        let a = _mm256_set1_pd(1.);
2687        let b = _mm256_set_pd(0., 1., 2., 3.);
2688        let c = _mm256_set1_pd(1.);
2689        let r = _mm256_maskz_fnmsub_pd(0, a, b, c);
2690        assert_eq_m256d(r, _mm256_setzero_pd());
2691        let r = _mm256_maskz_fnmsub_pd(0b00001111, a, b, c);
2692        let e = _mm256_set_pd(-1., -2., -3., -4.);
2693        assert_eq_m256d(r, e);
2694    }
2695
2696    #[simd_test(enable = "avx512f,avx512vl")]
2697    const fn test_mm256_mask3_fnmsub_pd() {
2698        let a = _mm256_set1_pd(1.);
2699        let b = _mm256_set_pd(0., 1., 2., 3.);
2700        let c = _mm256_set1_pd(1.);
2701        let r = _mm256_mask3_fnmsub_pd(a, b, c, 0);
2702        assert_eq_m256d(r, c);
2703        let r = _mm256_mask3_fnmsub_pd(a, b, c, 0b00001111);
2704        let e = _mm256_set_pd(-1., -2., -3., -4.);
2705        assert_eq_m256d(r, e);
2706    }
2707
2708    #[simd_test(enable = "avx512f,avx512vl")]
2709    const fn test_mm_mask_fnmsub_pd() {
2710        let a = _mm_set1_pd(1.);
2711        let b = _mm_set_pd(0., 1.);
2712        let c = _mm_set1_pd(1.);
2713        let r = _mm_mask_fnmsub_pd(a, 0, b, c);
2714        assert_eq_m128d(r, a);
2715        let r = _mm_mask_fnmsub_pd(a, 0b00000011, b, c);
2716        let e = _mm_set_pd(-1., -2.);
2717        assert_eq_m128d(r, e);
2718    }
2719
2720    #[simd_test(enable = "avx512f,avx512vl")]
2721    const fn test_mm_maskz_fnmsub_pd() {
2722        let a = _mm_set1_pd(1.);
2723        let b = _mm_set_pd(0., 1.);
2724        let c = _mm_set1_pd(1.);
2725        let r = _mm_maskz_fnmsub_pd(0, a, b, c);
2726        assert_eq_m128d(r, _mm_setzero_pd());
2727        let r = _mm_maskz_fnmsub_pd(0b00000011, a, b, c);
2728        let e = _mm_set_pd(-1., -2.);
2729        assert_eq_m128d(r, e);
2730    }
2731
2732    #[simd_test(enable = "avx512f,avx512vl")]
2733    const fn test_mm_mask3_fnmsub_pd() {
2734        let a = _mm_set1_pd(1.);
2735        let b = _mm_set_pd(0., 1.);
2736        let c = _mm_set1_pd(1.);
2737        let r = _mm_mask3_fnmsub_pd(a, b, c, 0);
2738        assert_eq_m128d(r, c);
2739        let r = _mm_mask3_fnmsub_pd(a, b, c, 0b00000011);
2740        let e = _mm_set_pd(-1., -2.);
2741        assert_eq_m128d(r, e);
2742    }
2743
2744    #[simd_test(enable = "avx512f")]
2745    fn test_mm512_rcp14_pd() {
2746        let a = _mm512_set1_pd(3.);
2747        let r = _mm512_rcp14_pd(a);
2748        let e = _mm512_set1_pd(0.3333320617675781);
2749        assert_eq_m512d(r, e);
2750    }
2751
2752    #[simd_test(enable = "avx512f")]
2753    fn test_mm512_mask_rcp14_pd() {
2754        let a = _mm512_set1_pd(3.);
2755        let r = _mm512_mask_rcp14_pd(a, 0, a);
2756        assert_eq_m512d(r, a);
2757        let r = _mm512_mask_rcp14_pd(a, 0b11110000, a);
2758        #[rustfmt::skip]
2759        let e = _mm512_setr_pd(
2760            3., 3., 3., 3.,
2761            0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2762        );
2763        assert_eq_m512d(r, e);
2764    }
2765
2766    #[simd_test(enable = "avx512f")]
2767    fn test_mm512_maskz_rcp14_pd() {
2768        let a = _mm512_set1_pd(3.);
2769        let r = _mm512_maskz_rcp14_pd(0, a);
2770        assert_eq_m512d(r, _mm512_setzero_pd());
2771        let r = _mm512_maskz_rcp14_pd(0b11110000, a);
2772        #[rustfmt::skip]
2773        let e = _mm512_setr_pd(
2774            0., 0., 0., 0.,
2775            0.3333320617675781, 0.3333320617675781, 0.3333320617675781, 0.3333320617675781,
2776        );
2777        assert_eq_m512d(r, e);
2778    }
2779
2780    #[simd_test(enable = "avx512f,avx512vl")]
2781    fn test_mm256_rcp14_pd() {
2782        let a = _mm256_set1_pd(3.);
2783        let r = _mm256_rcp14_pd(a);
2784        let e = _mm256_set1_pd(0.3333320617675781);
2785        assert_eq_m256d(r, e);
2786    }
2787
2788    #[simd_test(enable = "avx512f,avx512vl")]
2789    fn test_mm256_mask_rcp14_pd() {
2790        let a = _mm256_set1_pd(3.);
2791        let r = _mm256_mask_rcp14_pd(a, 0, a);
2792        assert_eq_m256d(r, a);
2793        let r = _mm256_mask_rcp14_pd(a, 0b00001111, a);
2794        let e = _mm256_set1_pd(0.3333320617675781);
2795        assert_eq_m256d(r, e);
2796    }
2797
2798    #[simd_test(enable = "avx512f,avx512vl")]
2799    fn test_mm256_maskz_rcp14_pd() {
2800        let a = _mm256_set1_pd(3.);
2801        let r = _mm256_maskz_rcp14_pd(0, a);
2802        assert_eq_m256d(r, _mm256_setzero_pd());
2803        let r = _mm256_maskz_rcp14_pd(0b00001111, a);
2804        let e = _mm256_set1_pd(0.3333320617675781);
2805        assert_eq_m256d(r, e);
2806    }
2807
2808    #[simd_test(enable = "avx512f,avx512vl")]
2809    fn test_mm_rcp14_pd() {
2810        let a = _mm_set1_pd(3.);
2811        let r = _mm_rcp14_pd(a);
2812        let e = _mm_set1_pd(0.3333320617675781);
2813        assert_eq_m128d(r, e);
2814    }
2815
2816    #[simd_test(enable = "avx512f,avx512vl")]
2817    fn test_mm_mask_rcp14_pd() {
2818        let a = _mm_set1_pd(3.);
2819        let r = _mm_mask_rcp14_pd(a, 0, a);
2820        assert_eq_m128d(r, a);
2821        let r = _mm_mask_rcp14_pd(a, 0b00000011, a);
2822        let e = _mm_set1_pd(0.3333320617675781);
2823        assert_eq_m128d(r, e);
2824    }
2825
2826    #[simd_test(enable = "avx512f,avx512vl")]
2827    fn test_mm_maskz_rcp14_pd() {
2828        let a = _mm_set1_pd(3.);
2829        let r = _mm_maskz_rcp14_pd(0, a);
2830        assert_eq_m128d(r, _mm_setzero_pd());
2831        let r = _mm_maskz_rcp14_pd(0b00000011, a);
2832        let e = _mm_set1_pd(0.3333320617675781);
2833        assert_eq_m128d(r, e);
2834    }
2835
2836    #[simd_test(enable = "avx512f")]
2837    fn test_mm512_rsqrt14_pd() {
2838        let a = _mm512_set1_pd(3.);
2839        let r = _mm512_rsqrt14_pd(a);
2840        let e = _mm512_set1_pd(0.5773391723632813);
2841        assert_eq_m512d(r, e);
2842    }
2843
2844    #[simd_test(enable = "avx512f")]
2845    fn test_mm512_mask_rsqrt14_pd() {
2846        let a = _mm512_set1_pd(3.);
2847        let r = _mm512_mask_rsqrt14_pd(a, 0, a);
2848        assert_eq_m512d(r, a);
2849        let r = _mm512_mask_rsqrt14_pd(a, 0b11110000, a);
2850        #[rustfmt::skip]
2851        let e = _mm512_setr_pd(
2852            3., 3., 3., 3.,
2853            0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2854        );
2855        assert_eq_m512d(r, e);
2856    }
2857
2858    #[simd_test(enable = "avx512f")]
2859    fn test_mm512_maskz_rsqrt14_pd() {
2860        let a = _mm512_set1_pd(3.);
2861        let r = _mm512_maskz_rsqrt14_pd(0, a);
2862        assert_eq_m512d(r, _mm512_setzero_pd());
2863        let r = _mm512_maskz_rsqrt14_pd(0b11110000, a);
2864        #[rustfmt::skip]
2865        let e = _mm512_setr_pd(
2866            0., 0., 0., 0.,
2867            0.5773391723632813, 0.5773391723632813, 0.5773391723632813, 0.5773391723632813,
2868        );
2869        assert_eq_m512d(r, e);
2870    }
2871
2872    #[simd_test(enable = "avx512f,avx512vl")]
2873    fn test_mm256_rsqrt14_pd() {
2874        let a = _mm256_set1_pd(3.);
2875        let r = _mm256_rsqrt14_pd(a);
2876        let e = _mm256_set1_pd(0.5773391723632813);
2877        assert_eq_m256d(r, e);
2878    }
2879
2880    #[simd_test(enable = "avx512f,avx512vl")]
2881    fn test_mm256_mask_rsqrt14_pd() {
2882        let a = _mm256_set1_pd(3.);
2883        let r = _mm256_mask_rsqrt14_pd(a, 0, a);
2884        assert_eq_m256d(r, a);
2885        let r = _mm256_mask_rsqrt14_pd(a, 0b00001111, a);
2886        let e = _mm256_set1_pd(0.5773391723632813);
2887        assert_eq_m256d(r, e);
2888    }
2889
2890    #[simd_test(enable = "avx512f,avx512vl")]
2891    fn test_mm256_maskz_rsqrt14_pd() {
2892        let a = _mm256_set1_pd(3.);
2893        let r = _mm256_maskz_rsqrt14_pd(0, a);
2894        assert_eq_m256d(r, _mm256_setzero_pd());
2895        let r = _mm256_maskz_rsqrt14_pd(0b00001111, a);
2896        let e = _mm256_set1_pd(0.5773391723632813);
2897        assert_eq_m256d(r, e);
2898    }
2899
2900    #[simd_test(enable = "avx512f,avx512vl")]
2901    fn test_mm_rsqrt14_pd() {
2902        let a = _mm_set1_pd(3.);
2903        let r = _mm_rsqrt14_pd(a);
2904        let e = _mm_set1_pd(0.5773391723632813);
2905        assert_eq_m128d(r, e);
2906    }
2907
2908    #[simd_test(enable = "avx512f,avx512vl")]
2909    fn test_mm_mask_rsqrt14_pd() {
2910        let a = _mm_set1_pd(3.);
2911        let r = _mm_mask_rsqrt14_pd(a, 0, a);
2912        assert_eq_m128d(r, a);
2913        let r = _mm_mask_rsqrt14_pd(a, 0b00000011, a);
2914        let e = _mm_set1_pd(0.5773391723632813);
2915        assert_eq_m128d(r, e);
2916    }
2917
2918    #[simd_test(enable = "avx512f,avx512vl")]
2919    fn test_mm_maskz_rsqrt14_pd() {
2920        let a = _mm_set1_pd(3.);
2921        let r = _mm_maskz_rsqrt14_pd(0, a);
2922        assert_eq_m128d(r, _mm_setzero_pd());
2923        let r = _mm_maskz_rsqrt14_pd(0b00000011, a);
2924        let e = _mm_set1_pd(0.5773391723632813);
2925        assert_eq_m128d(r, e);
2926    }
2927
2928    #[simd_test(enable = "avx512f")]
2929    fn test_mm512_getexp_pd() {
2930        let a = _mm512_set1_pd(3.);
2931        let r = _mm512_getexp_pd(a);
2932        let e = _mm512_set1_pd(1.);
2933        assert_eq_m512d(r, e);
2934    }
2935
2936    #[simd_test(enable = "avx512f")]
2937    fn test_mm512_mask_getexp_pd() {
2938        let a = _mm512_set1_pd(3.);
2939        let r = _mm512_mask_getexp_pd(a, 0, a);
2940        assert_eq_m512d(r, a);
2941        let r = _mm512_mask_getexp_pd(a, 0b11110000, a);
2942        let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
2943        assert_eq_m512d(r, e);
2944    }
2945
2946    #[simd_test(enable = "avx512f")]
2947    fn test_mm512_maskz_getexp_pd() {
2948        let a = _mm512_set1_pd(3.);
2949        let r = _mm512_maskz_getexp_pd(0, a);
2950        assert_eq_m512d(r, _mm512_setzero_pd());
2951        let r = _mm512_maskz_getexp_pd(0b11110000, a);
2952        let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
2953        assert_eq_m512d(r, e);
2954    }
2955
2956    #[simd_test(enable = "avx512f,avx512vl")]
2957    fn test_mm256_getexp_pd() {
2958        let a = _mm256_set1_pd(3.);
2959        let r = _mm256_getexp_pd(a);
2960        let e = _mm256_set1_pd(1.);
2961        assert_eq_m256d(r, e);
2962    }
2963
2964    #[simd_test(enable = "avx512f,avx512vl")]
2965    fn test_mm256_mask_getexp_pd() {
2966        let a = _mm256_set1_pd(3.);
2967        let r = _mm256_mask_getexp_pd(a, 0, a);
2968        assert_eq_m256d(r, a);
2969        let r = _mm256_mask_getexp_pd(a, 0b00001111, a);
2970        let e = _mm256_set1_pd(1.);
2971        assert_eq_m256d(r, e);
2972    }
2973
2974    #[simd_test(enable = "avx512f,avx512vl")]
2975    fn test_mm256_maskz_getexp_pd() {
2976        let a = _mm256_set1_pd(3.);
2977        let r = _mm256_maskz_getexp_pd(0, a);
2978        assert_eq_m256d(r, _mm256_setzero_pd());
2979        let r = _mm256_maskz_getexp_pd(0b00001111, a);
2980        let e = _mm256_set1_pd(1.);
2981        assert_eq_m256d(r, e);
2982    }
2983
2984    #[simd_test(enable = "avx512f,avx512vl")]
2985    fn test_mm_getexp_pd() {
2986        let a = _mm_set1_pd(3.);
2987        let r = _mm_getexp_pd(a);
2988        let e = _mm_set1_pd(1.);
2989        assert_eq_m128d(r, e);
2990    }
2991
2992    #[simd_test(enable = "avx512f,avx512vl")]
2993    fn test_mm_mask_getexp_pd() {
2994        let a = _mm_set1_pd(3.);
2995        let r = _mm_mask_getexp_pd(a, 0, a);
2996        assert_eq_m128d(r, a);
2997        let r = _mm_mask_getexp_pd(a, 0b00000011, a);
2998        let e = _mm_set1_pd(1.);
2999        assert_eq_m128d(r, e);
3000    }
3001
3002    #[simd_test(enable = "avx512f,avx512vl")]
3003    fn test_mm_maskz_getexp_pd() {
3004        let a = _mm_set1_pd(3.);
3005        let r = _mm_maskz_getexp_pd(0, a);
3006        assert_eq_m128d(r, _mm_setzero_pd());
3007        let r = _mm_maskz_getexp_pd(0b00000011, a);
3008        let e = _mm_set1_pd(1.);
3009        assert_eq_m128d(r, e);
3010    }
3011
3012    #[simd_test(enable = "avx512f")]
3013    fn test_mm512_roundscale_pd() {
3014        let a = _mm512_set1_pd(1.1);
3015        let r = _mm512_roundscale_pd::<0b00_00_00_00>(a);
3016        let e = _mm512_set1_pd(1.0);
3017        assert_eq_m512d(r, e);
3018    }
3019
3020    #[simd_test(enable = "avx512f")]
3021    fn test_mm512_mask_roundscale_pd() {
3022        let a = _mm512_set1_pd(1.1);
3023        let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3024        let e = _mm512_set1_pd(1.1);
3025        assert_eq_m512d(r, e);
3026        let r = _mm512_mask_roundscale_pd::<0b00_00_00_00>(a, 0b11111111, a);
3027        let e = _mm512_set1_pd(1.0);
3028        assert_eq_m512d(r, e);
3029    }
3030
3031    #[simd_test(enable = "avx512f")]
3032    fn test_mm512_maskz_roundscale_pd() {
3033        let a = _mm512_set1_pd(1.1);
3034        let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3035        assert_eq_m512d(r, _mm512_setzero_pd());
3036        let r = _mm512_maskz_roundscale_pd::<0b00_00_00_00>(0b11111111, a);
3037        let e = _mm512_set1_pd(1.0);
3038        assert_eq_m512d(r, e);
3039    }
3040
3041    #[simd_test(enable = "avx512f,avx512vl")]
3042    fn test_mm256_roundscale_pd() {
3043        let a = _mm256_set1_pd(1.1);
3044        let r = _mm256_roundscale_pd::<0b00_00_00_00>(a);
3045        let e = _mm256_set1_pd(1.0);
3046        assert_eq_m256d(r, e);
3047    }
3048
3049    #[simd_test(enable = "avx512f,avx512vl")]
3050    fn test_mm256_mask_roundscale_pd() {
3051        let a = _mm256_set1_pd(1.1);
3052        let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3053        assert_eq_m256d(r, a);
3054        let r = _mm256_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00001111, a);
3055        let e = _mm256_set1_pd(1.0);
3056        assert_eq_m256d(r, e);
3057    }
3058
3059    #[simd_test(enable = "avx512f,avx512vl")]
3060    fn test_mm256_maskz_roundscale_pd() {
3061        let a = _mm256_set1_pd(1.1);
3062        let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3063        assert_eq_m256d(r, _mm256_setzero_pd());
3064        let r = _mm256_maskz_roundscale_pd::<0b00_00_00_00>(0b00001111, a);
3065        let e = _mm256_set1_pd(1.0);
3066        assert_eq_m256d(r, e);
3067    }
3068
3069    #[simd_test(enable = "avx512f,avx512vl")]
3070    fn test_mm_roundscale_pd() {
3071        let a = _mm_set1_pd(1.1);
3072        let r = _mm_roundscale_pd::<0b00_00_00_00>(a);
3073        let e = _mm_set1_pd(1.0);
3074        assert_eq_m128d(r, e);
3075    }
3076
3077    #[simd_test(enable = "avx512f,avx512vl")]
3078    fn test_mm_mask_roundscale_pd() {
3079        let a = _mm_set1_pd(1.1);
3080        let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0, a);
3081        let e = _mm_set1_pd(1.1);
3082        assert_eq_m128d(r, e);
3083        let r = _mm_mask_roundscale_pd::<0b00_00_00_00>(a, 0b00000011, a);
3084        let e = _mm_set1_pd(1.0);
3085        assert_eq_m128d(r, e);
3086    }
3087
3088    #[simd_test(enable = "avx512f,avx512vl")]
3089    fn test_mm_maskz_roundscale_pd() {
3090        let a = _mm_set1_pd(1.1);
3091        let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0, a);
3092        assert_eq_m128d(r, _mm_setzero_pd());
3093        let r = _mm_maskz_roundscale_pd::<0b00_00_00_00>(0b00000011, a);
3094        let e = _mm_set1_pd(1.0);
3095        assert_eq_m128d(r, e);
3096    }
3097
3098    #[simd_test(enable = "avx512f")]
3099    fn test_mm512_scalef_pd() {
3100        let a = _mm512_set1_pd(1.);
3101        let b = _mm512_set1_pd(3.);
3102        let r = _mm512_scalef_pd(a, b);
3103        let e = _mm512_set1_pd(8.);
3104        assert_eq_m512d(r, e);
3105    }
3106
3107    #[simd_test(enable = "avx512f")]
3108    fn test_mm512_mask_scalef_pd() {
3109        let a = _mm512_set1_pd(1.);
3110        let b = _mm512_set1_pd(3.);
3111        let r = _mm512_mask_scalef_pd(a, 0, a, b);
3112        assert_eq_m512d(r, a);
3113        let r = _mm512_mask_scalef_pd(a, 0b11110000, a, b);
3114        let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
3115        assert_eq_m512d(r, e);
3116    }
3117
3118    #[simd_test(enable = "avx512f")]
3119    fn test_mm512_maskz_scalef_pd() {
3120        let a = _mm512_set1_pd(1.);
3121        let b = _mm512_set1_pd(3.);
3122        let r = _mm512_maskz_scalef_pd(0, a, b);
3123        assert_eq_m512d(r, _mm512_setzero_pd());
3124        let r = _mm512_maskz_scalef_pd(0b11110000, a, b);
3125        let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
3126        assert_eq_m512d(r, e);
3127    }
3128
3129    #[simd_test(enable = "avx512f,avx512vl")]
3130    fn test_mm256_scalef_pd() {
3131        let a = _mm256_set1_pd(1.);
3132        let b = _mm256_set1_pd(3.);
3133        let r = _mm256_scalef_pd(a, b);
3134        let e = _mm256_set1_pd(8.);
3135        assert_eq_m256d(r, e);
3136    }
3137
3138    #[simd_test(enable = "avx512f,avx512vl")]
3139    fn test_mm256_mask_scalef_pd() {
3140        let a = _mm256_set1_pd(1.);
3141        let b = _mm256_set1_pd(3.);
3142        let r = _mm256_mask_scalef_pd(a, 0, a, b);
3143        assert_eq_m256d(r, a);
3144        let r = _mm256_mask_scalef_pd(a, 0b00001111, a, b);
3145        let e = _mm256_set1_pd(8.);
3146        assert_eq_m256d(r, e);
3147    }
3148
3149    #[simd_test(enable = "avx512f,avx512vl")]
3150    fn test_mm256_maskz_scalef_pd() {
3151        let a = _mm256_set1_pd(1.);
3152        let b = _mm256_set1_pd(3.);
3153        let r = _mm256_maskz_scalef_pd(0, a, b);
3154        assert_eq_m256d(r, _mm256_setzero_pd());
3155        let r = _mm256_maskz_scalef_pd(0b00001111, a, b);
3156        let e = _mm256_set1_pd(8.);
3157        assert_eq_m256d(r, e);
3158    }
3159
3160    #[simd_test(enable = "avx512f,avx512vl")]
3161    fn test_mm_scalef_pd() {
3162        let a = _mm_set1_pd(1.);
3163        let b = _mm_set1_pd(3.);
3164        let r = _mm_scalef_pd(a, b);
3165        let e = _mm_set1_pd(8.);
3166        assert_eq_m128d(r, e);
3167    }
3168
3169    #[simd_test(enable = "avx512f,avx512vl")]
3170    fn test_mm_mask_scalef_pd() {
3171        let a = _mm_set1_pd(1.);
3172        let b = _mm_set1_pd(3.);
3173        let r = _mm_mask_scalef_pd(a, 0, a, b);
3174        assert_eq_m128d(r, a);
3175        let r = _mm_mask_scalef_pd(a, 0b00000011, a, b);
3176        let e = _mm_set1_pd(8.);
3177        assert_eq_m128d(r, e);
3178    }
3179
3180    #[simd_test(enable = "avx512f,avx512vl")]
3181    fn test_mm_maskz_scalef_pd() {
3182        let a = _mm_set1_pd(1.);
3183        let b = _mm_set1_pd(3.);
3184        let r = _mm_maskz_scalef_pd(0, a, b);
3185        assert_eq_m128d(r, _mm_setzero_pd());
3186        let r = _mm_maskz_scalef_pd(0b00000011, a, b);
3187        let e = _mm_set1_pd(8.);
3188        assert_eq_m128d(r, e);
3189    }
3190
3191    #[simd_test(enable = "avx512f")]
3192    fn test_mm512_fixupimm_pd() {
3193        let a = _mm512_set1_pd(f64::NAN);
3194        let b = _mm512_set1_pd(f64::MAX);
3195        let c = _mm512_set1_epi64(i32::MAX as i64);
3196        let r = _mm512_fixupimm_pd::<5>(a, b, c);
3197        let e = _mm512_set1_pd(0.0);
3198        assert_eq_m512d(r, e);
3199    }
3200
3201    #[simd_test(enable = "avx512f")]
3202    fn test_mm512_mask_fixupimm_pd() {
3203        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3204        let b = _mm512_set1_pd(f64::MAX);
3205        let c = _mm512_set1_epi64(i32::MAX as i64);
3206        let r = _mm512_mask_fixupimm_pd::<5>(a, 0b11110000, b, c);
3207        let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
3208        assert_eq_m512d(r, e);
3209    }
3210
3211    #[simd_test(enable = "avx512f")]
3212    fn test_mm512_maskz_fixupimm_pd() {
3213        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
3214        let b = _mm512_set1_pd(f64::MAX);
3215        let c = _mm512_set1_epi64(i32::MAX as i64);
3216        let r = _mm512_maskz_fixupimm_pd::<5>(0b11110000, a, b, c);
3217        let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
3218        assert_eq_m512d(r, e);
3219    }
3220
3221    #[simd_test(enable = "avx512f,avx512vl")]
3222    fn test_mm256_fixupimm_pd() {
3223        let a = _mm256_set1_pd(f64::NAN);
3224        let b = _mm256_set1_pd(f64::MAX);
3225        let c = _mm256_set1_epi64x(i32::MAX as i64);
3226        let r = _mm256_fixupimm_pd::<5>(a, b, c);
3227        let e = _mm256_set1_pd(0.0);
3228        assert_eq_m256d(r, e);
3229    }
3230
3231    #[simd_test(enable = "avx512f,avx512vl")]
3232    fn test_mm256_mask_fixupimm_pd() {
3233        let a = _mm256_set1_pd(f64::NAN);
3234        let b = _mm256_set1_pd(f64::MAX);
3235        let c = _mm256_set1_epi64x(i32::MAX as i64);
3236        let r = _mm256_mask_fixupimm_pd::<5>(a, 0b00001111, b, c);
3237        let e = _mm256_set1_pd(0.0);
3238        assert_eq_m256d(r, e);
3239    }
3240
3241    #[simd_test(enable = "avx512f,avx512vl")]
3242    fn test_mm256_maskz_fixupimm_pd() {
3243        let a = _mm256_set1_pd(f64::NAN);
3244        let b = _mm256_set1_pd(f64::MAX);
3245        let c = _mm256_set1_epi64x(i32::MAX as i64);
3246        let r = _mm256_maskz_fixupimm_pd::<5>(0b00001111, a, b, c);
3247        let e = _mm256_set1_pd(0.0);
3248        assert_eq_m256d(r, e);
3249    }
3250
3251    #[simd_test(enable = "avx512f,avx512vl")]
3252    fn test_mm_fixupimm_pd() {
3253        let a = _mm_set1_pd(f64::NAN);
3254        let b = _mm_set1_pd(f64::MAX);
3255        let c = _mm_set1_epi64x(i32::MAX as i64);
3256        let r = _mm_fixupimm_pd::<5>(a, b, c);
3257        let e = _mm_set1_pd(0.0);
3258        assert_eq_m128d(r, e);
3259    }
3260
3261    #[simd_test(enable = "avx512f,avx512vl")]
3262    fn test_mm_mask_fixupimm_pd() {
3263        let a = _mm_set1_pd(f64::NAN);
3264        let b = _mm_set1_pd(f64::MAX);
3265        let c = _mm_set1_epi64x(i32::MAX as i64);
3266        let r = _mm_mask_fixupimm_pd::<5>(a, 0b00000011, b, c);
3267        let e = _mm_set1_pd(0.0);
3268        assert_eq_m128d(r, e);
3269    }
3270
3271    #[simd_test(enable = "avx512f,avx512vl")]
3272    fn test_mm_maskz_fixupimm_pd() {
3273        let a = _mm_set1_pd(f64::NAN);
3274        let b = _mm_set1_pd(f64::MAX);
3275        let c = _mm_set1_epi64x(i32::MAX as i64);
3276        let r = _mm_maskz_fixupimm_pd::<5>(0b00000011, a, b, c);
3277        let e = _mm_set1_pd(0.0);
3278        assert_eq_m128d(r, e);
3279    }
3280
3281    #[simd_test(enable = "avx512f")]
3282    fn test_mm512_ternarylogic_epi64() {
3283        let a = _mm512_set1_epi64(1 << 2);
3284        let b = _mm512_set1_epi64(1 << 1);
3285        let c = _mm512_set1_epi64(1 << 0);
3286        let r = _mm512_ternarylogic_epi64::<8>(a, b, c);
3287        let e = _mm512_set1_epi64(0);
3288        assert_eq_m512i(r, e);
3289    }
3290
3291    #[simd_test(enable = "avx512f")]
3292    fn test_mm512_mask_ternarylogic_epi64() {
3293        let src = _mm512_set1_epi64(1 << 2);
3294        let a = _mm512_set1_epi64(1 << 1);
3295        let b = _mm512_set1_epi64(1 << 0);
3296        let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3297        assert_eq_m512i(r, src);
3298        let r = _mm512_mask_ternarylogic_epi64::<8>(src, 0b11111111, a, b);
3299        let e = _mm512_set1_epi64(0);
3300        assert_eq_m512i(r, e);
3301    }
3302
3303    #[simd_test(enable = "avx512f")]
3304    fn test_mm512_maskz_ternarylogic_epi64() {
3305        let a = _mm512_set1_epi64(1 << 2);
3306        let b = _mm512_set1_epi64(1 << 1);
3307        let c = _mm512_set1_epi64(1 << 0);
3308        let r = _mm512_maskz_ternarylogic_epi64::<8>(0, a, b, c);
3309        assert_eq_m512i(r, _mm512_setzero_si512());
3310        let r = _mm512_maskz_ternarylogic_epi64::<8>(0b11111111, a, b, c);
3311        let e = _mm512_set1_epi64(0);
3312        assert_eq_m512i(r, e);
3313    }
3314
3315    #[simd_test(enable = "avx512f,avx512vl")]
3316    fn test_mm256_ternarylogic_epi64() {
3317        let a = _mm256_set1_epi64x(1 << 2);
3318        let b = _mm256_set1_epi64x(1 << 1);
3319        let c = _mm256_set1_epi64x(1 << 0);
3320        let r = _mm256_ternarylogic_epi64::<8>(a, b, c);
3321        let e = _mm256_set1_epi64x(0);
3322        assert_eq_m256i(r, e);
3323    }
3324
3325    #[simd_test(enable = "avx512f,avx512vl")]
3326    fn test_mm256_mask_ternarylogic_epi64() {
3327        let src = _mm256_set1_epi64x(1 << 2);
3328        let a = _mm256_set1_epi64x(1 << 1);
3329        let b = _mm256_set1_epi64x(1 << 0);
3330        let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3331        assert_eq_m256i(r, src);
3332        let r = _mm256_mask_ternarylogic_epi64::<8>(src, 0b00001111, a, b);
3333        let e = _mm256_set1_epi64x(0);
3334        assert_eq_m256i(r, e);
3335    }
3336
3337    #[simd_test(enable = "avx512f,avx512vl")]
3338    fn test_mm256_maskz_ternarylogic_epi64() {
3339        let a = _mm256_set1_epi64x(1 << 2);
3340        let b = _mm256_set1_epi64x(1 << 1);
3341        let c = _mm256_set1_epi64x(1 << 0);
3342        let r = _mm256_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3343        assert_eq_m256i(r, _mm256_setzero_si256());
3344        let r = _mm256_maskz_ternarylogic_epi64::<8>(0b00001111, a, b, c);
3345        let e = _mm256_set1_epi64x(0);
3346        assert_eq_m256i(r, e);
3347    }
3348
3349    #[simd_test(enable = "avx512f,avx512vl")]
3350    fn test_mm_ternarylogic_epi64() {
3351        let a = _mm_set1_epi64x(1 << 2);
3352        let b = _mm_set1_epi64x(1 << 1);
3353        let c = _mm_set1_epi64x(1 << 0);
3354        let r = _mm_ternarylogic_epi64::<8>(a, b, c);
3355        let e = _mm_set1_epi64x(0);
3356        assert_eq_m128i(r, e);
3357    }
3358
3359    #[simd_test(enable = "avx512f,avx512vl")]
3360    fn test_mm_mask_ternarylogic_epi64() {
3361        let src = _mm_set1_epi64x(1 << 2);
3362        let a = _mm_set1_epi64x(1 << 1);
3363        let b = _mm_set1_epi64x(1 << 0);
3364        let r = _mm_mask_ternarylogic_epi64::<8>(src, 0, a, b);
3365        assert_eq_m128i(r, src);
3366        let r = _mm_mask_ternarylogic_epi64::<8>(src, 0b00000011, a, b);
3367        let e = _mm_set1_epi64x(0);
3368        assert_eq_m128i(r, e);
3369    }
3370
3371    #[simd_test(enable = "avx512f,avx512vl")]
3372    fn test_mm_maskz_ternarylogic_epi64() {
3373        let a = _mm_set1_epi64x(1 << 2);
3374        let b = _mm_set1_epi64x(1 << 1);
3375        let c = _mm_set1_epi64x(1 << 0);
3376        let r = _mm_maskz_ternarylogic_epi64::<9>(0, a, b, c);
3377        assert_eq_m128i(r, _mm_setzero_si128());
3378        let r = _mm_maskz_ternarylogic_epi64::<8>(0b00000011, a, b, c);
3379        let e = _mm_set1_epi64x(0);
3380        assert_eq_m128i(r, e);
3381    }
3382
3383    #[simd_test(enable = "avx512f")]
3384    fn test_mm512_getmant_pd() {
3385        let a = _mm512_set1_pd(10.);
3386        let r = _mm512_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3387        let e = _mm512_set1_pd(1.25);
3388        assert_eq_m512d(r, e);
3389    }
3390
3391    #[simd_test(enable = "avx512f")]
3392    fn test_mm512_mask_getmant_pd() {
3393        let a = _mm512_set1_pd(10.);
3394        let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3395        assert_eq_m512d(r, a);
3396        let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11110000, a);
3397        let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
3398        assert_eq_m512d(r, e);
3399    }
3400
3401    #[simd_test(enable = "avx512f")]
3402    fn test_mm512_maskz_getmant_pd() {
3403        let a = _mm512_set1_pd(10.);
3404        let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3405        assert_eq_m512d(r, _mm512_setzero_pd());
3406        let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11110000, a);
3407        let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
3408        assert_eq_m512d(r, e);
3409    }
3410
3411    #[simd_test(enable = "avx512f,avx512vl")]
3412    fn test_mm256_getmant_pd() {
3413        let a = _mm256_set1_pd(10.);
3414        let r = _mm256_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3415        let e = _mm256_set1_pd(1.25);
3416        assert_eq_m256d(r, e);
3417    }
3418
3419    #[simd_test(enable = "avx512f,avx512vl")]
3420    fn test_mm256_mask_getmant_pd() {
3421        let a = _mm256_set1_pd(10.);
3422        let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3423        assert_eq_m256d(r, a);
3424        let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00001111, a);
3425        let e = _mm256_set1_pd(1.25);
3426        assert_eq_m256d(r, e);
3427    }
3428
3429    #[simd_test(enable = "avx512f,avx512vl")]
3430    fn test_mm256_maskz_getmant_pd() {
3431        let a = _mm256_set1_pd(10.);
3432        let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3433        assert_eq_m256d(r, _mm256_setzero_pd());
3434        let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00001111, a);
3435        let e = _mm256_set1_pd(1.25);
3436        assert_eq_m256d(r, e);
3437    }
3438
3439    #[simd_test(enable = "avx512f,avx512vl")]
3440    fn test_mm_getmant_pd() {
3441        let a = _mm_set1_pd(10.);
3442        let r = _mm_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a);
3443        let e = _mm_set1_pd(1.25);
3444        assert_eq_m128d(r, e);
3445    }
3446
3447    #[simd_test(enable = "avx512f,avx512vl")]
3448    fn test_mm_mask_getmant_pd() {
3449        let a = _mm_set1_pd(10.);
3450        let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a);
3451        assert_eq_m128d(r, a);
3452        let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00000011, a);
3453        let e = _mm_set1_pd(1.25);
3454        assert_eq_m128d(r, e);
3455    }
3456
3457    #[simd_test(enable = "avx512f,avx512vl")]
3458    fn test_mm_maskz_getmant_pd() {
3459        let a = _mm_set1_pd(10.);
3460        let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a);
3461        assert_eq_m128d(r, _mm_setzero_pd());
3462        let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00000011, a);
3463        let e = _mm_set1_pd(1.25);
3464        assert_eq_m128d(r, e);
3465    }
3466
3467    #[simd_test(enable = "avx512f")]
3468    fn test_mm512_cvtps_pd() {
3469        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3470        let r = _mm512_cvtps_pd(a);
3471        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3472        assert_eq_m512d(r, e);
3473    }
3474
3475    #[simd_test(enable = "avx512f")]
3476    fn test_mm512_mask_cvtps_pd() {
3477        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3478        let src = _mm512_set1_pd(0.);
3479        let r = _mm512_mask_cvtps_pd(src, 0, a);
3480        assert_eq_m512d(r, src);
3481        let r = _mm512_mask_cvtps_pd(src, 0b00001111, a);
3482        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3483        assert_eq_m512d(r, e);
3484    }
3485
3486    #[simd_test(enable = "avx512f")]
3487    fn test_mm512_maskz_cvtps_pd() {
3488        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3489        let r = _mm512_maskz_cvtps_pd(0, a);
3490        assert_eq_m512d(r, _mm512_setzero_pd());
3491        let r = _mm512_maskz_cvtps_pd(0b00001111, a);
3492        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3493        assert_eq_m512d(r, e);
3494    }
3495
3496    #[simd_test(enable = "avx512f")]
3497    fn test_mm512_cvtpslo_pd() {
3498        let v2 = _mm512_setr_ps(
3499            0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3500        );
3501        let r = _mm512_cvtpslo_pd(v2);
3502        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3503        assert_eq_m512d(r, e);
3504    }
3505
3506    #[simd_test(enable = "avx512f")]
3507    fn test_mm512_mask_cvtpslo_pd() {
3508        let v2 = _mm512_setr_ps(
3509            0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 100., 100., 100., 100., 100., 100., 100., 100.,
3510        );
3511        let src = _mm512_set1_pd(0.);
3512        let r = _mm512_mask_cvtpslo_pd(src, 0, v2);
3513        assert_eq_m512d(r, src);
3514        let r = _mm512_mask_cvtpslo_pd(src, 0b00001111, v2);
3515        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3516        assert_eq_m512d(r, e);
3517    }
3518
3519    #[simd_test(enable = "avx512f")]
3520    fn test_mm512_cvtpd_ps() {
3521        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3522        let r = _mm512_cvtpd_ps(a);
3523        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3524        assert_eq_m256(r, e);
3525    }
3526
3527    #[simd_test(enable = "avx512f")]
3528    fn test_mm512_mask_cvtpd_ps() {
3529        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3530        let src = _mm256_set1_ps(0.);
3531        let r = _mm512_mask_cvtpd_ps(src, 0, a);
3532        assert_eq_m256(r, src);
3533        let r = _mm512_mask_cvtpd_ps(src, 0b00001111, a);
3534        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3535        assert_eq_m256(r, e);
3536    }
3537
3538    #[simd_test(enable = "avx512f")]
3539    fn test_mm512_maskz_cvtpd_ps() {
3540        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3541        let r = _mm512_maskz_cvtpd_ps(0, a);
3542        assert_eq_m256(r, _mm256_setzero_ps());
3543        let r = _mm512_maskz_cvtpd_ps(0b00001111, a);
3544        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
3545        assert_eq_m256(r, e);
3546    }
3547
3548    #[simd_test(enable = "avx512f,avx512vl")]
3549    fn test_mm256_mask_cvtpd_ps() {
3550        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3551        let src = _mm_set1_ps(0.);
3552        let r = _mm256_mask_cvtpd_ps(src, 0, a);
3553        assert_eq_m128(r, src);
3554        let r = _mm256_mask_cvtpd_ps(src, 0b00001111, a);
3555        let e = _mm_set_ps(4., -5.5, 6., -7.5);
3556        assert_eq_m128(r, e);
3557    }
3558
3559    #[simd_test(enable = "avx512f,avx512vl")]
3560    fn test_mm256_maskz_cvtpd_ps() {
3561        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3562        let r = _mm256_maskz_cvtpd_ps(0, a);
3563        assert_eq_m128(r, _mm_setzero_ps());
3564        let r = _mm256_maskz_cvtpd_ps(0b00001111, a);
3565        let e = _mm_set_ps(4., -5.5, 6., -7.5);
3566        assert_eq_m128(r, e);
3567    }
3568
3569    #[simd_test(enable = "avx512f,avx512vl")]
3570    fn test_mm_mask_cvtpd_ps() {
3571        let a = _mm_set_pd(6., -7.5);
3572        let src = _mm_set1_ps(0.);
3573        let r = _mm_mask_cvtpd_ps(src, 0, a);
3574        assert_eq_m128(r, src);
3575        let r = _mm_mask_cvtpd_ps(src, 0b00000011, a);
3576        let e = _mm_set_ps(0., 0., 6., -7.5);
3577        assert_eq_m128(r, e);
3578    }
3579
3580    #[simd_test(enable = "avx512f,avx512vl")]
3581    fn test_mm_maskz_cvtpd_ps() {
3582        let a = _mm_set_pd(6., -7.5);
3583        let r = _mm_maskz_cvtpd_ps(0, a);
3584        assert_eq_m128(r, _mm_setzero_ps());
3585        let r = _mm_maskz_cvtpd_ps(0b00000011, a);
3586        let e = _mm_set_ps(0., 0., 6., -7.5);
3587        assert_eq_m128(r, e);
3588    }
3589
3590    #[simd_test(enable = "avx512f")]
3591    fn test_mm512_cvtpd_epi32() {
3592        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3593        let r = _mm512_cvtpd_epi32(a);
3594        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3595        assert_eq_m256i(r, e);
3596    }
3597
3598    #[simd_test(enable = "avx512f")]
3599    fn test_mm512_mask_cvtpd_epi32() {
3600        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3601        let src = _mm256_set1_epi32(0);
3602        let r = _mm512_mask_cvtpd_epi32(src, 0, a);
3603        assert_eq_m256i(r, src);
3604        let r = _mm512_mask_cvtpd_epi32(src, 0b11111111, a);
3605        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3606        assert_eq_m256i(r, e);
3607    }
3608
3609    #[simd_test(enable = "avx512f")]
3610    fn test_mm512_maskz_cvtpd_epi32() {
3611        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3612        let r = _mm512_maskz_cvtpd_epi32(0, a);
3613        assert_eq_m256i(r, _mm256_setzero_si256());
3614        let r = _mm512_maskz_cvtpd_epi32(0b11111111, a);
3615        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
3616        assert_eq_m256i(r, e);
3617    }
3618
3619    #[simd_test(enable = "avx512f,avx512vl")]
3620    fn test_mm256_mask_cvtpd_epi32() {
3621        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3622        let src = _mm_set1_epi32(0);
3623        let r = _mm256_mask_cvtpd_epi32(src, 0, a);
3624        assert_eq_m128i(r, src);
3625        let r = _mm256_mask_cvtpd_epi32(src, 0b00001111, a);
3626        let e = _mm_set_epi32(4, -6, 6, -8);
3627        assert_eq_m128i(r, e);
3628    }
3629
3630    #[simd_test(enable = "avx512f,avx512vl")]
3631    fn test_mm256_maskz_cvtpd_epi32() {
3632        let a = _mm256_set_pd(4., -5.5, 6., -7.5);
3633        let r = _mm256_maskz_cvtpd_epi32(0, a);
3634        assert_eq_m128i(r, _mm_setzero_si128());
3635        let r = _mm256_maskz_cvtpd_epi32(0b00001111, a);
3636        let e = _mm_set_epi32(4, -6, 6, -8);
3637        assert_eq_m128i(r, e);
3638    }
3639
3640    #[simd_test(enable = "avx512f,avx512vl")]
3641    fn test_mm_mask_cvtpd_epi32() {
3642        let a = _mm_set_pd(6., -7.5);
3643        let src = _mm_set1_epi32(0);
3644        let r = _mm_mask_cvtpd_epi32(src, 0, a);
3645        assert_eq_m128i(r, src);
3646        let r = _mm_mask_cvtpd_epi32(src, 0b00000011, a);
3647        let e = _mm_set_epi32(0, 0, 6, -8);
3648        assert_eq_m128i(r, e);
3649    }
3650
3651    #[simd_test(enable = "avx512f,avx512vl")]
3652    fn test_mm_maskz_cvtpd_epi32() {
3653        let a = _mm_set_pd(6., -7.5);
3654        let r = _mm_maskz_cvtpd_epi32(0, a);
3655        assert_eq_m128i(r, _mm_setzero_si128());
3656        let r = _mm_maskz_cvtpd_epi32(0b00000011, a);
3657        let e = _mm_set_epi32(0, 0, 6, -8);
3658        assert_eq_m128i(r, e);
3659    }
3660
3661    #[simd_test(enable = "avx512f")]
3662    fn test_mm512_cvtpd_epu32() {
3663        let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3664        let r = _mm512_cvtpd_epu32(a);
3665        let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3666        assert_eq_m256i(r, e);
3667    }
3668
3669    #[simd_test(enable = "avx512f")]
3670    fn test_mm512_mask_cvtpd_epu32() {
3671        let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3672        let src = _mm256_set1_epi32(0);
3673        let r = _mm512_mask_cvtpd_epu32(src, 0, a);
3674        assert_eq_m256i(r, src);
3675        let r = _mm512_mask_cvtpd_epu32(src, 0b11111111, a);
3676        let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3677        assert_eq_m256i(r, e);
3678    }
3679
3680    #[simd_test(enable = "avx512f")]
3681    fn test_mm512_maskz_cvtpd_epu32() {
3682        let a = _mm512_setr_pd(0., 1.5, 2., 3.5, 4., 5.5, 6., 7.5);
3683        let r = _mm512_maskz_cvtpd_epu32(0, a);
3684        assert_eq_m256i(r, _mm256_setzero_si256());
3685        let r = _mm512_maskz_cvtpd_epu32(0b11111111, a);
3686        let e = _mm256_setr_epi32(0, 2, 2, 4, 4, 6, 6, 8);
3687        assert_eq_m256i(r, e);
3688    }
3689
3690    #[simd_test(enable = "avx512f,avx512vl")]
3691    fn test_mm256_cvtpd_epu32() {
3692        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3693        let r = _mm256_cvtpd_epu32(a);
3694        let e = _mm_set_epi32(4, 6, 6, 8);
3695        assert_eq_m128i(r, e);
3696    }
3697
3698    #[simd_test(enable = "avx512f,avx512vl")]
3699    fn test_mm256_mask_cvtpd_epu32() {
3700        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3701        let src = _mm_set1_epi32(0);
3702        let r = _mm256_mask_cvtpd_epu32(src, 0, a);
3703        assert_eq_m128i(r, src);
3704        let r = _mm256_mask_cvtpd_epu32(src, 0b00001111, a);
3705        let e = _mm_set_epi32(4, 6, 6, 8);
3706        assert_eq_m128i(r, e);
3707    }
3708
3709    #[simd_test(enable = "avx512f,avx512vl")]
3710    fn test_mm256_maskz_cvtpd_epu32() {
3711        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
3712        let r = _mm256_maskz_cvtpd_epu32(0, a);
3713        assert_eq_m128i(r, _mm_setzero_si128());
3714        let r = _mm256_maskz_cvtpd_epu32(0b00001111, a);
3715        let e = _mm_set_epi32(4, 6, 6, 8);
3716        assert_eq_m128i(r, e);
3717    }
3718
3719    #[simd_test(enable = "avx512f,avx512vl")]
3720    fn test_mm_cvtpd_epu32() {
3721        let a = _mm_set_pd(6., 7.5);
3722        let r = _mm_cvtpd_epu32(a);
3723        let e = _mm_set_epi32(0, 0, 6, 8);
3724        assert_eq_m128i(r, e);
3725    }
3726
3727    #[simd_test(enable = "avx512f,avx512vl")]
3728    fn test_mm_mask_cvtpd_epu32() {
3729        let a = _mm_set_pd(6., 7.5);
3730        let src = _mm_set1_epi32(0);
3731        let r = _mm_mask_cvtpd_epu32(src, 0, a);
3732        assert_eq_m128i(r, src);
3733        let r = _mm_mask_cvtpd_epu32(src, 0b00000011, a);
3734        let e = _mm_set_epi32(0, 0, 6, 8);
3735        assert_eq_m128i(r, e);
3736    }
3737
3738    #[simd_test(enable = "avx512f,avx512vl")]
3739    fn test_mm_maskz_cvtpd_epu32() {
3740        let a = _mm_set_pd(6., 7.5);
3741        let r = _mm_maskz_cvtpd_epu32(0, a);
3742        assert_eq_m128i(r, _mm_setzero_si128());
3743        let r = _mm_maskz_cvtpd_epu32(0b00000011, a);
3744        let e = _mm_set_epi32(0, 0, 6, 8);
3745        assert_eq_m128i(r, e);
3746    }
3747
3748    #[simd_test(enable = "avx512f")]
3749    fn test_mm512_cvtpd_pslo() {
3750        let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3751        let r = _mm512_cvtpd_pslo(v2);
3752        let e = _mm512_setr_ps(
3753            0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5, 0., 0., 0., 0., 0., 0., 0., 0.,
3754        );
3755        assert_eq_m512(r, e);
3756    }
3757
3758    #[simd_test(enable = "avx512f")]
3759    fn test_mm512_mask_cvtpd_pslo() {
3760        let v2 = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
3761        let src = _mm512_set1_ps(0.);
3762        let r = _mm512_mask_cvtpd_pslo(src, 0, v2);
3763        assert_eq_m512(r, src);
3764        let r = _mm512_mask_cvtpd_pslo(src, 0b00001111, v2);
3765        let e = _mm512_setr_ps(
3766            0., -1.5, 2., -3.5, 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,
3767        );
3768        assert_eq_m512(r, e);
3769    }
3770
3771    #[simd_test(enable = "avx512f")]
3772    const fn test_mm512_cvtepi8_epi64() {
3773        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3774        let r = _mm512_cvtepi8_epi64(a);
3775        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3776        assert_eq_m512i(r, e);
3777    }
3778
3779    #[simd_test(enable = "avx512f")]
3780    const fn test_mm512_mask_cvtepi8_epi64() {
3781        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3782        let src = _mm512_set1_epi64(-1);
3783        let r = _mm512_mask_cvtepi8_epi64(src, 0, a);
3784        assert_eq_m512i(r, src);
3785        let r = _mm512_mask_cvtepi8_epi64(src, 0b00001111, a);
3786        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3787        assert_eq_m512i(r, e);
3788    }
3789
3790    #[simd_test(enable = "avx512f")]
3791    const fn test_mm512_maskz_cvtepi8_epi64() {
3792        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3793        let r = _mm512_maskz_cvtepi8_epi64(0, a);
3794        assert_eq_m512i(r, _mm512_setzero_si512());
3795        let r = _mm512_maskz_cvtepi8_epi64(0b00001111, a);
3796        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3797        assert_eq_m512i(r, e);
3798    }
3799
3800    #[simd_test(enable = "avx512f,avx512vl")]
3801    const fn test_mm256_mask_cvtepi8_epi64() {
3802        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3803        let src = _mm256_set1_epi64x(-1);
3804        let r = _mm256_mask_cvtepi8_epi64(src, 0, a);
3805        assert_eq_m256i(r, src);
3806        let r = _mm256_mask_cvtepi8_epi64(src, 0b00001111, a);
3807        let e = _mm256_set_epi64x(12, 13, 14, 15);
3808        assert_eq_m256i(r, e);
3809    }
3810
3811    #[simd_test(enable = "avx512f,avx512vl")]
3812    const fn test_mm256_maskz_cvtepi8_epi64() {
3813        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3814        let r = _mm256_maskz_cvtepi8_epi64(0, a);
3815        assert_eq_m256i(r, _mm256_setzero_si256());
3816        let r = _mm256_maskz_cvtepi8_epi64(0b00001111, a);
3817        let e = _mm256_set_epi64x(12, 13, 14, 15);
3818        assert_eq_m256i(r, e);
3819    }
3820
3821    #[simd_test(enable = "avx512f,avx512vl")]
3822    const fn test_mm_mask_cvtepi8_epi64() {
3823        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3824        let src = _mm_set1_epi64x(-1);
3825        let r = _mm_mask_cvtepi8_epi64(src, 0, a);
3826        assert_eq_m128i(r, src);
3827        let r = _mm_mask_cvtepi8_epi64(src, 0b00000011, a);
3828        let e = _mm_set_epi64x(14, 15);
3829        assert_eq_m128i(r, e);
3830    }
3831
3832    #[simd_test(enable = "avx512f,avx512vl")]
3833    const fn test_mm_maskz_cvtepi8_epi64() {
3834        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3835        let r = _mm_maskz_cvtepi8_epi64(0, a);
3836        assert_eq_m128i(r, _mm_setzero_si128());
3837        let r = _mm_maskz_cvtepi8_epi64(0b00000011, a);
3838        let e = _mm_set_epi64x(14, 15);
3839        assert_eq_m128i(r, e);
3840    }
3841
3842    #[simd_test(enable = "avx512f")]
3843    const fn test_mm512_cvtepu8_epi64() {
3844        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3845        let r = _mm512_cvtepu8_epi64(a);
3846        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3847        assert_eq_m512i(r, e);
3848    }
3849
3850    #[simd_test(enable = "avx512f")]
3851    const fn test_mm512_mask_cvtepu8_epi64() {
3852        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3853        let src = _mm512_set1_epi64(-1);
3854        let r = _mm512_mask_cvtepu8_epi64(src, 0, a);
3855        assert_eq_m512i(r, src);
3856        let r = _mm512_mask_cvtepu8_epi64(src, 0b00001111, a);
3857        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3858        assert_eq_m512i(r, e);
3859    }
3860
3861    #[simd_test(enable = "avx512f")]
3862    const fn test_mm512_maskz_cvtepu8_epi64() {
3863        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3864        let r = _mm512_maskz_cvtepu8_epi64(0, a);
3865        assert_eq_m512i(r, _mm512_setzero_si512());
3866        let r = _mm512_maskz_cvtepu8_epi64(0b00001111, a);
3867        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3868        assert_eq_m512i(r, e);
3869    }
3870
3871    #[simd_test(enable = "avx512f,avx512vl")]
3872    const fn test_mm256_mask_cvtepu8_epi64() {
3873        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3874        let src = _mm256_set1_epi64x(-1);
3875        let r = _mm256_mask_cvtepu8_epi64(src, 0, a);
3876        assert_eq_m256i(r, src);
3877        let r = _mm256_mask_cvtepu8_epi64(src, 0b00001111, a);
3878        let e = _mm256_set_epi64x(12, 13, 14, 15);
3879        assert_eq_m256i(r, e);
3880    }
3881
3882    #[simd_test(enable = "avx512f,avx512vl")]
3883    const fn test_mm256_maskz_cvtepu8_epi64() {
3884        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3885        let r = _mm256_maskz_cvtepu8_epi64(0, a);
3886        assert_eq_m256i(r, _mm256_setzero_si256());
3887        let r = _mm256_maskz_cvtepu8_epi64(0b00001111, a);
3888        let e = _mm256_set_epi64x(12, 13, 14, 15);
3889        assert_eq_m256i(r, e);
3890    }
3891
3892    #[simd_test(enable = "avx512f,avx512vl")]
3893    const fn test_mm_mask_cvtepu8_epi64() {
3894        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3895        let src = _mm_set1_epi64x(-1);
3896        let r = _mm_mask_cvtepu8_epi64(src, 0, a);
3897        assert_eq_m128i(r, src);
3898        let r = _mm_mask_cvtepu8_epi64(src, 0b00000011, a);
3899        let e = _mm_set_epi64x(14, 15);
3900        assert_eq_m128i(r, e);
3901    }
3902
3903    #[simd_test(enable = "avx512f,avx512vl")]
3904    const fn test_mm_maskz_cvtepu8_epi64() {
3905        let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
3906        let r = _mm_maskz_cvtepu8_epi64(0, a);
3907        assert_eq_m128i(r, _mm_setzero_si128());
3908        let r = _mm_maskz_cvtepu8_epi64(0b00000011, a);
3909        let e = _mm_set_epi64x(14, 15);
3910        assert_eq_m128i(r, e);
3911    }
3912
3913    #[simd_test(enable = "avx512f")]
3914    const fn test_mm512_cvtepi16_epi64() {
3915        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3916        let r = _mm512_cvtepi16_epi64(a);
3917        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3918        assert_eq_m512i(r, e);
3919    }
3920
3921    #[simd_test(enable = "avx512f")]
3922    const fn test_mm512_mask_cvtepi16_epi64() {
3923        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3924        let src = _mm512_set1_epi64(-1);
3925        let r = _mm512_mask_cvtepi16_epi64(src, 0, a);
3926        assert_eq_m512i(r, src);
3927        let r = _mm512_mask_cvtepi16_epi64(src, 0b00001111, a);
3928        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
3929        assert_eq_m512i(r, e);
3930    }
3931
3932    #[simd_test(enable = "avx512f")]
3933    const fn test_mm512_maskz_cvtepi16_epi64() {
3934        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3935        let r = _mm512_maskz_cvtepi16_epi64(0, a);
3936        assert_eq_m512i(r, _mm512_setzero_si512());
3937        let r = _mm512_maskz_cvtepi16_epi64(0b00001111, a);
3938        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
3939        assert_eq_m512i(r, e);
3940    }
3941
3942    #[simd_test(enable = "avx512f,avx512vl")]
3943    const fn test_mm256_mask_cvtepi16_epi64() {
3944        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3945        let src = _mm256_set1_epi64x(-1);
3946        let r = _mm256_mask_cvtepi16_epi64(src, 0, a);
3947        assert_eq_m256i(r, src);
3948        let r = _mm256_mask_cvtepi16_epi64(src, 0b00001111, a);
3949        let e = _mm256_set_epi64x(12, 13, 14, 15);
3950        assert_eq_m256i(r, e);
3951    }
3952
3953    #[simd_test(enable = "avx512f,avx512vl")]
3954    const fn test_mm256_maskz_cvtepi16_epi64() {
3955        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3956        let r = _mm256_maskz_cvtepi16_epi64(0, a);
3957        assert_eq_m256i(r, _mm256_setzero_si256());
3958        let r = _mm256_maskz_cvtepi16_epi64(0b00001111, a);
3959        let e = _mm256_set_epi64x(12, 13, 14, 15);
3960        assert_eq_m256i(r, e);
3961    }
3962
3963    #[simd_test(enable = "avx512f,avx512vl")]
3964    const fn test_mm_mask_cvtepi16_epi64() {
3965        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3966        let src = _mm_set1_epi64x(-1);
3967        let r = _mm_mask_cvtepi16_epi64(src, 0, a);
3968        assert_eq_m128i(r, src);
3969        let r = _mm_mask_cvtepi16_epi64(src, 0b00000011, a);
3970        let e = _mm_set_epi64x(14, 15);
3971        assert_eq_m128i(r, e);
3972    }
3973
3974    #[simd_test(enable = "avx512f,avx512vl")]
3975    const fn test_mm_maskz_cvtepi16_epi64() {
3976        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3977        let r = _mm_maskz_cvtepi16_epi64(0, a);
3978        assert_eq_m128i(r, _mm_setzero_si128());
3979        let r = _mm_maskz_cvtepi16_epi64(0b00000011, a);
3980        let e = _mm_set_epi64x(14, 15);
3981        assert_eq_m128i(r, e);
3982    }
3983
3984    #[simd_test(enable = "avx512f")]
3985    const fn test_mm512_cvtepu16_epi64() {
3986        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3987        let r = _mm512_cvtepu16_epi64(a);
3988        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
3989        assert_eq_m512i(r, e);
3990    }
3991
3992    #[simd_test(enable = "avx512f")]
3993    const fn test_mm512_mask_cvtepu16_epi64() {
3994        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
3995        let src = _mm512_set1_epi64(-1);
3996        let r = _mm512_mask_cvtepu16_epi64(src, 0, a);
3997        assert_eq_m512i(r, src);
3998        let r = _mm512_mask_cvtepu16_epi64(src, 0b00001111, a);
3999        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4000        assert_eq_m512i(r, e);
4001    }
4002
4003    #[simd_test(enable = "avx512f")]
4004    const fn test_mm512_maskz_cvtepu16_epi64() {
4005        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4006        let r = _mm512_maskz_cvtepu16_epi64(0, a);
4007        assert_eq_m512i(r, _mm512_setzero_si512());
4008        let r = _mm512_maskz_cvtepu16_epi64(0b00001111, a);
4009        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4010        assert_eq_m512i(r, e);
4011    }
4012
4013    #[simd_test(enable = "avx512f,avx512vl")]
4014    const fn test_mm256_mask_cvtepu16_epi64() {
4015        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4016        let src = _mm256_set1_epi64x(-1);
4017        let r = _mm256_mask_cvtepu16_epi64(src, 0, a);
4018        assert_eq_m256i(r, src);
4019        let r = _mm256_mask_cvtepu16_epi64(src, 0b00001111, a);
4020        let e = _mm256_set_epi64x(12, 13, 14, 15);
4021        assert_eq_m256i(r, e);
4022    }
4023
4024    #[simd_test(enable = "avx512f,avx512vl")]
4025    const fn test_mm256_maskz_cvtepu16_epi64() {
4026        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4027        let r = _mm256_maskz_cvtepu16_epi64(0, a);
4028        assert_eq_m256i(r, _mm256_setzero_si256());
4029        let r = _mm256_maskz_cvtepu16_epi64(0b00001111, a);
4030        let e = _mm256_set_epi64x(12, 13, 14, 15);
4031        assert_eq_m256i(r, e);
4032    }
4033
4034    #[simd_test(enable = "avx512f,avx512vl")]
4035    const fn test_mm_mask_cvtepu16_epi64() {
4036        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4037        let src = _mm_set1_epi64x(-1);
4038        let r = _mm_mask_cvtepu16_epi64(src, 0, a);
4039        assert_eq_m128i(r, src);
4040        let r = _mm_mask_cvtepu16_epi64(src, 0b00000011, a);
4041        let e = _mm_set_epi64x(14, 15);
4042        assert_eq_m128i(r, e);
4043    }
4044
4045    #[simd_test(enable = "avx512f,avx512vl")]
4046    const fn test_mm_maskz_cvtepu16_epi64() {
4047        let a = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4048        let r = _mm_maskz_cvtepu16_epi64(0, a);
4049        assert_eq_m128i(r, _mm_setzero_si128());
4050        let r = _mm_maskz_cvtepu16_epi64(0b00000011, a);
4051        let e = _mm_set_epi64x(14, 15);
4052        assert_eq_m128i(r, e);
4053    }
4054
4055    #[simd_test(enable = "avx512f")]
4056    const fn test_mm512_cvtepi32_epi64() {
4057        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4058        let r = _mm512_cvtepi32_epi64(a);
4059        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4060        assert_eq_m512i(r, e);
4061    }
4062
4063    #[simd_test(enable = "avx512f")]
4064    const fn test_mm512_mask_cvtepi32_epi64() {
4065        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4066        let src = _mm512_set1_epi64(-1);
4067        let r = _mm512_mask_cvtepi32_epi64(src, 0, a);
4068        assert_eq_m512i(r, src);
4069        let r = _mm512_mask_cvtepi32_epi64(src, 0b00001111, a);
4070        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4071        assert_eq_m512i(r, e);
4072    }
4073
4074    #[simd_test(enable = "avx512f")]
4075    const fn test_mm512_maskz_cvtepi32_epi64() {
4076        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4077        let r = _mm512_maskz_cvtepi32_epi64(0, a);
4078        assert_eq_m512i(r, _mm512_setzero_si512());
4079        let r = _mm512_maskz_cvtepi32_epi64(0b00001111, a);
4080        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4081        assert_eq_m512i(r, e);
4082    }
4083
4084    #[simd_test(enable = "avx512f,avx512vl")]
4085    const fn test_mm256_mask_cvtepi32_epi64() {
4086        let a = _mm_set_epi32(8, 9, 10, 11);
4087        let src = _mm256_set1_epi64x(-1);
4088        let r = _mm256_mask_cvtepi32_epi64(src, 0, a);
4089        assert_eq_m256i(r, src);
4090        let r = _mm256_mask_cvtepi32_epi64(src, 0b00001111, a);
4091        let e = _mm256_set_epi64x(8, 9, 10, 11);
4092        assert_eq_m256i(r, e);
4093    }
4094
4095    #[simd_test(enable = "avx512f,avx512vl")]
4096    const fn test_mm256_maskz_cvtepi32_epi64() {
4097        let a = _mm_set_epi32(8, 9, 10, 11);
4098        let r = _mm256_maskz_cvtepi32_epi64(0, a);
4099        assert_eq_m256i(r, _mm256_setzero_si256());
4100        let r = _mm256_maskz_cvtepi32_epi64(0b00001111, a);
4101        let e = _mm256_set_epi64x(8, 9, 10, 11);
4102        assert_eq_m256i(r, e);
4103    }
4104
4105    #[simd_test(enable = "avx512f,avx512vl")]
4106    const fn test_mm_mask_cvtepi32_epi64() {
4107        let a = _mm_set_epi32(8, 9, 10, 11);
4108        let src = _mm_set1_epi64x(0);
4109        let r = _mm_mask_cvtepi32_epi64(src, 0, a);
4110        assert_eq_m128i(r, src);
4111        let r = _mm_mask_cvtepi32_epi64(src, 0b00000011, a);
4112        let e = _mm_set_epi64x(10, 11);
4113        assert_eq_m128i(r, e);
4114    }
4115
4116    #[simd_test(enable = "avx512f,avx512vl")]
4117    const fn test_mm_maskz_cvtepi32_epi64() {
4118        let a = _mm_set_epi32(8, 9, 10, 11);
4119        let r = _mm_maskz_cvtepi32_epi64(0, a);
4120        assert_eq_m128i(r, _mm_setzero_si128());
4121        let r = _mm_maskz_cvtepi32_epi64(0b00000011, a);
4122        let e = _mm_set_epi64x(10, 11);
4123        assert_eq_m128i(r, e);
4124    }
4125
4126    #[simd_test(enable = "avx512f")]
4127    const fn test_mm512_cvtepu32_epi64() {
4128        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4129        let r = _mm512_cvtepu32_epi64(a);
4130        let e = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4131        assert_eq_m512i(r, e);
4132    }
4133
4134    #[simd_test(enable = "avx512f")]
4135    const fn test_mm512_mask_cvtepu32_epi64() {
4136        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4137        let src = _mm512_set1_epi64(-1);
4138        let r = _mm512_mask_cvtepu32_epi64(src, 0, a);
4139        assert_eq_m512i(r, src);
4140        let r = _mm512_mask_cvtepu32_epi64(src, 0b00001111, a);
4141        let e = _mm512_set_epi64(-1, -1, -1, -1, 12, 13, 14, 15);
4142        assert_eq_m512i(r, e);
4143    }
4144
4145    #[simd_test(enable = "avx512f")]
4146    const fn test_mm512_maskz_cvtepu32_epi64() {
4147        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4148        let r = _mm512_maskz_cvtepu32_epi64(0, a);
4149        assert_eq_m512i(r, _mm512_setzero_si512());
4150        let r = _mm512_maskz_cvtepu32_epi64(0b00001111, a);
4151        let e = _mm512_set_epi64(0, 0, 0, 0, 12, 13, 14, 15);
4152        assert_eq_m512i(r, e);
4153    }
4154
4155    #[simd_test(enable = "avx512f,avx512vl")]
4156    const fn test_mm256_mask_cvtepu32_epi64() {
4157        let a = _mm_set_epi32(12, 13, 14, 15);
4158        let src = _mm256_set1_epi64x(-1);
4159        let r = _mm256_mask_cvtepu32_epi64(src, 0, a);
4160        assert_eq_m256i(r, src);
4161        let r = _mm256_mask_cvtepu32_epi64(src, 0b00001111, a);
4162        let e = _mm256_set_epi64x(12, 13, 14, 15);
4163        assert_eq_m256i(r, e);
4164    }
4165
4166    #[simd_test(enable = "avx512f,avx512vl")]
4167    const fn test_mm256_maskz_cvtepu32_epi64() {
4168        let a = _mm_set_epi32(12, 13, 14, 15);
4169        let r = _mm256_maskz_cvtepu32_epi64(0, a);
4170        assert_eq_m256i(r, _mm256_setzero_si256());
4171        let r = _mm256_maskz_cvtepu32_epi64(0b00001111, a);
4172        let e = _mm256_set_epi64x(12, 13, 14, 15);
4173        assert_eq_m256i(r, e);
4174    }
4175
4176    #[simd_test(enable = "avx512f,avx512vl")]
4177    const fn test_mm_mask_cvtepu32_epi64() {
4178        let a = _mm_set_epi32(12, 13, 14, 15);
4179        let src = _mm_set1_epi64x(-1);
4180        let r = _mm_mask_cvtepu32_epi64(src, 0, a);
4181        assert_eq_m128i(r, src);
4182        let r = _mm_mask_cvtepu32_epi64(src, 0b00000011, a);
4183        let e = _mm_set_epi64x(14, 15);
4184        assert_eq_m128i(r, e);
4185    }
4186
4187    #[simd_test(enable = "avx512f,avx512vl")]
4188    const fn test_mm_maskz_cvtepu32_epi64() {
4189        let a = _mm_set_epi32(12, 13, 14, 15);
4190        let r = _mm_maskz_cvtepu32_epi64(0, a);
4191        assert_eq_m128i(r, _mm_setzero_si128());
4192        let r = _mm_maskz_cvtepu32_epi64(0b00000011, a);
4193        let e = _mm_set_epi64x(14, 15);
4194        assert_eq_m128i(r, e);
4195    }
4196
4197    #[simd_test(enable = "avx512f")]
4198    const fn test_mm512_cvtepi32_pd() {
4199        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4200        let r = _mm512_cvtepi32_pd(a);
4201        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4202        assert_eq_m512d(r, e);
4203    }
4204
4205    #[simd_test(enable = "avx512f")]
4206    const fn test_mm512_mask_cvtepi32_pd() {
4207        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4208        let src = _mm512_set1_pd(-1.);
4209        let r = _mm512_mask_cvtepi32_pd(src, 0, a);
4210        assert_eq_m512d(r, src);
4211        let r = _mm512_mask_cvtepi32_pd(src, 0b00001111, a);
4212        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4213        assert_eq_m512d(r, e);
4214    }
4215
4216    #[simd_test(enable = "avx512f")]
4217    const fn test_mm512_maskz_cvtepi32_pd() {
4218        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4219        let r = _mm512_maskz_cvtepi32_pd(0, a);
4220        assert_eq_m512d(r, _mm512_setzero_pd());
4221        let r = _mm512_maskz_cvtepi32_pd(0b00001111, a);
4222        let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4223        assert_eq_m512d(r, e);
4224    }
4225
4226    #[simd_test(enable = "avx512f,avx512vl")]
4227    const fn test_mm256_mask_cvtepi32_pd() {
4228        let a = _mm_set_epi32(12, 13, 14, 15);
4229        let src = _mm256_set1_pd(-1.);
4230        let r = _mm256_mask_cvtepi32_pd(src, 0, a);
4231        assert_eq_m256d(r, src);
4232        let r = _mm256_mask_cvtepi32_pd(src, 0b00001111, a);
4233        let e = _mm256_set_pd(12., 13., 14., 15.);
4234        assert_eq_m256d(r, e);
4235    }
4236
4237    #[simd_test(enable = "avx512f,avx512vl")]
4238    const fn test_mm256_maskz_cvtepi32_pd() {
4239        let a = _mm_set_epi32(12, 13, 14, 15);
4240        let r = _mm256_maskz_cvtepi32_pd(0, a);
4241        assert_eq_m256d(r, _mm256_setzero_pd());
4242        let r = _mm256_maskz_cvtepi32_pd(0b00001111, a);
4243        let e = _mm256_set_pd(12., 13., 14., 15.);
4244        assert_eq_m256d(r, e);
4245    }
4246
4247    #[simd_test(enable = "avx512f,avx512vl")]
4248    const fn test_mm_mask_cvtepi32_pd() {
4249        let a = _mm_set_epi32(12, 13, 14, 15);
4250        let src = _mm_set1_pd(-1.);
4251        let r = _mm_mask_cvtepi32_pd(src, 0, a);
4252        assert_eq_m128d(r, src);
4253        let r = _mm_mask_cvtepi32_pd(src, 0b00000011, a);
4254        let e = _mm_set_pd(14., 15.);
4255        assert_eq_m128d(r, e);
4256    }
4257
4258    #[simd_test(enable = "avx512f,avx512vl")]
4259    const fn test_mm_maskz_cvtepi32_pd() {
4260        let a = _mm_set_epi32(12, 13, 14, 15);
4261        let r = _mm_maskz_cvtepi32_pd(0, a);
4262        assert_eq_m128d(r, _mm_setzero_pd());
4263        let r = _mm_maskz_cvtepi32_pd(0b00000011, a);
4264        let e = _mm_set_pd(14., 15.);
4265        assert_eq_m128d(r, e);
4266    }
4267
4268    #[simd_test(enable = "avx512f")]
4269    const fn test_mm512_cvtepu32_pd() {
4270        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4271        let r = _mm512_cvtepu32_pd(a);
4272        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4273        assert_eq_m512d(r, e);
4274    }
4275
4276    #[simd_test(enable = "avx512f")]
4277    const fn test_mm512_mask_cvtepu32_pd() {
4278        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4279        let src = _mm512_set1_pd(-1.);
4280        let r = _mm512_mask_cvtepu32_pd(src, 0, a);
4281        assert_eq_m512d(r, src);
4282        let r = _mm512_mask_cvtepu32_pd(src, 0b00001111, a);
4283        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4284        assert_eq_m512d(r, e);
4285    }
4286
4287    #[simd_test(enable = "avx512f")]
4288    const fn test_mm512_maskz_cvtepu32_pd() {
4289        let a = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4290        let r = _mm512_maskz_cvtepu32_pd(0, a);
4291        assert_eq_m512d(r, _mm512_setzero_pd());
4292        let r = _mm512_maskz_cvtepu32_pd(0b00001111, a);
4293        let e = _mm512_set_pd(0., 0., 0., 0., 12., 13., 14., 15.);
4294        assert_eq_m512d(r, e);
4295    }
4296
4297    #[simd_test(enable = "avx512f,avx512vl")]
4298    const fn test_mm256_cvtepu32_pd() {
4299        let a = _mm_set_epi32(12, 13, 14, 15);
4300        let r = _mm256_cvtepu32_pd(a);
4301        let e = _mm256_set_pd(12., 13., 14., 15.);
4302        assert_eq_m256d(r, e);
4303    }
4304
4305    #[simd_test(enable = "avx512f,avx512vl")]
4306    const fn test_mm256_mask_cvtepu32_pd() {
4307        let a = _mm_set_epi32(12, 13, 14, 15);
4308        let src = _mm256_set1_pd(-1.);
4309        let r = _mm256_mask_cvtepu32_pd(src, 0, a);
4310        assert_eq_m256d(r, src);
4311        let r = _mm256_mask_cvtepu32_pd(src, 0b00001111, a);
4312        let e = _mm256_set_pd(12., 13., 14., 15.);
4313        assert_eq_m256d(r, e);
4314    }
4315
4316    #[simd_test(enable = "avx512f,avx512vl")]
4317    const fn test_mm256_maskz_cvtepu32_pd() {
4318        let a = _mm_set_epi32(12, 13, 14, 15);
4319        let r = _mm256_maskz_cvtepu32_pd(0, a);
4320        assert_eq_m256d(r, _mm256_setzero_pd());
4321        let r = _mm256_maskz_cvtepu32_pd(0b00001111, a);
4322        let e = _mm256_set_pd(12., 13., 14., 15.);
4323        assert_eq_m256d(r, e);
4324    }
4325
4326    #[simd_test(enable = "avx512f,avx512vl")]
4327    const fn test_mm_cvtepu32_pd() {
4328        let a = _mm_set_epi32(12, 13, 14, 15);
4329        let r = _mm_cvtepu32_pd(a);
4330        let e = _mm_set_pd(14., 15.);
4331        assert_eq_m128d(r, e);
4332    }
4333
4334    #[simd_test(enable = "avx512f,avx512vl")]
4335    const fn test_mm_mask_cvtepu32_pd() {
4336        let a = _mm_set_epi32(12, 13, 14, 15);
4337        let src = _mm_set1_pd(-1.);
4338        let r = _mm_mask_cvtepu32_pd(src, 0, a);
4339        assert_eq_m128d(r, src);
4340        let r = _mm_mask_cvtepu32_pd(src, 0b00000011, a);
4341        let e = _mm_set_pd(14., 15.);
4342        assert_eq_m128d(r, e);
4343    }
4344
4345    #[simd_test(enable = "avx512f,avx512vl")]
4346    const fn test_mm_maskz_cvtepu32_pd() {
4347        let a = _mm_set_epi32(12, 13, 14, 15);
4348        let r = _mm_maskz_cvtepu32_pd(0, a);
4349        assert_eq_m128d(r, _mm_setzero_pd());
4350        let r = _mm_maskz_cvtepu32_pd(0b00000011, a);
4351        let e = _mm_set_pd(14., 15.);
4352        assert_eq_m128d(r, e);
4353    }
4354
4355    #[simd_test(enable = "avx512f")]
4356    const fn test_mm512_cvtepi32lo_pd() {
4357        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4358        let r = _mm512_cvtepi32lo_pd(a);
4359        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4360        assert_eq_m512d(r, e);
4361    }
4362
4363    #[simd_test(enable = "avx512f")]
4364    const fn test_mm512_mask_cvtepi32lo_pd() {
4365        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4366        let src = _mm512_set1_pd(-1.);
4367        let r = _mm512_mask_cvtepi32lo_pd(src, 0, a);
4368        assert_eq_m512d(r, src);
4369        let r = _mm512_mask_cvtepi32lo_pd(src, 0b00001111, a);
4370        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4371        assert_eq_m512d(r, e);
4372    }
4373
4374    #[simd_test(enable = "avx512f")]
4375    const fn test_mm512_cvtepu32lo_pd() {
4376        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4377        let r = _mm512_cvtepu32lo_pd(a);
4378        let e = _mm512_set_pd(8., 9., 10., 11., 12., 13., 14., 15.);
4379        assert_eq_m512d(r, e);
4380    }
4381
4382    #[simd_test(enable = "avx512f")]
4383    const fn test_mm512_mask_cvtepu32lo_pd() {
4384        let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
4385        let src = _mm512_set1_pd(-1.);
4386        let r = _mm512_mask_cvtepu32lo_pd(src, 0, a);
4387        assert_eq_m512d(r, src);
4388        let r = _mm512_mask_cvtepu32lo_pd(src, 0b00001111, a);
4389        let e = _mm512_set_pd(-1., -1., -1., -1., 12., 13., 14., 15.);
4390        assert_eq_m512d(r, e);
4391    }
4392
4393    #[simd_test(enable = "avx512f")]
4394    const fn test_mm512_cvtepi64_epi32() {
4395        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4396        let r = _mm512_cvtepi64_epi32(a);
4397        let e = _mm256_set_epi32(8, 9, 10, 11, 12, 13, 14, 15);
4398        assert_eq_m256i(r, e);
4399    }
4400
4401    #[simd_test(enable = "avx512f")]
4402    const fn test_mm512_mask_cvtepi64_epi32() {
4403        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4404        let src = _mm256_set1_epi32(-1);
4405        let r = _mm512_mask_cvtepi64_epi32(src, 0, a);
4406        assert_eq_m256i(r, src);
4407        let r = _mm512_mask_cvtepi64_epi32(src, 0b00001111, a);
4408        let e = _mm256_set_epi32(-1, -1, -1, -1, 12, 13, 14, 15);
4409        assert_eq_m256i(r, e);
4410    }
4411
4412    #[simd_test(enable = "avx512f")]
4413    const fn test_mm512_maskz_cvtepi64_epi32() {
4414        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4415        let r = _mm512_maskz_cvtepi64_epi32(0, a);
4416        assert_eq_m256i(r, _mm256_setzero_si256());
4417        let r = _mm512_maskz_cvtepi64_epi32(0b00001111, a);
4418        let e = _mm256_set_epi32(0, 0, 0, 0, 12, 13, 14, 15);
4419        assert_eq_m256i(r, e);
4420    }
4421
4422    #[simd_test(enable = "avx512f,avx512vl")]
4423    const fn test_mm256_cvtepi64_epi32() {
4424        let a = _mm256_set_epi64x(1, 2, 3, 4);
4425        let r = _mm256_cvtepi64_epi32(a);
4426        let e = _mm_set_epi32(1, 2, 3, 4);
4427        assert_eq_m128i(r, e);
4428    }
4429
4430    #[simd_test(enable = "avx512f,avx512vl")]
4431    const fn test_mm256_mask_cvtepi64_epi32() {
4432        let a = _mm256_set_epi64x(1, 2, 3, 4);
4433        let src = _mm_set1_epi32(0);
4434        let r = _mm256_mask_cvtepi64_epi32(src, 0, a);
4435        assert_eq_m128i(r, src);
4436        let r = _mm256_mask_cvtepi64_epi32(src, 0b00001111, a);
4437        let e = _mm_set_epi32(1, 2, 3, 4);
4438        assert_eq_m128i(r, e);
4439    }
4440
4441    #[simd_test(enable = "avx512f,avx512vl")]
4442    const fn test_mm256_maskz_cvtepi64_epi32() {
4443        let a = _mm256_set_epi64x(1, 2, 3, 4);
4444        let r = _mm256_maskz_cvtepi64_epi32(0, a);
4445        assert_eq_m128i(r, _mm_setzero_si128());
4446        let r = _mm256_maskz_cvtepi64_epi32(0b00001111, a);
4447        let e = _mm_set_epi32(1, 2, 3, 4);
4448        assert_eq_m128i(r, e);
4449    }
4450
4451    #[simd_test(enable = "avx512f,avx512vl")]
4452    fn test_mm_cvtepi64_epi32() {
4453        let a = _mm_set_epi64x(3, 4);
4454        let r = _mm_cvtepi64_epi32(a);
4455        let e = _mm_set_epi32(0, 0, 3, 4);
4456        assert_eq_m128i(r, e);
4457    }
4458
4459    #[simd_test(enable = "avx512f,avx512vl")]
4460    fn test_mm_mask_cvtepi64_epi32() {
4461        let a = _mm_set_epi64x(3, 4);
4462        let src = _mm_set1_epi32(0);
4463        let r = _mm_mask_cvtepi64_epi32(src, 0, a);
4464        assert_eq_m128i(r, src);
4465        let r = _mm_mask_cvtepi64_epi32(src, 0b00000011, a);
4466        let e = _mm_set_epi32(0, 0, 3, 4);
4467        assert_eq_m128i(r, e);
4468    }
4469
4470    #[simd_test(enable = "avx512f,avx512vl")]
4471    fn test_mm_maskz_cvtepi64_epi32() {
4472        let a = _mm_set_epi64x(3, 4);
4473        let r = _mm_maskz_cvtepi64_epi32(0, a);
4474        assert_eq_m128i(r, _mm_setzero_si128());
4475        let r = _mm_maskz_cvtepi64_epi32(0b00000011, a);
4476        let e = _mm_set_epi32(0, 0, 3, 4);
4477        assert_eq_m128i(r, e);
4478    }
4479
4480    #[simd_test(enable = "avx512f")]
4481    const fn test_mm512_cvtepi64_epi16() {
4482        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4483        let r = _mm512_cvtepi64_epi16(a);
4484        let e = _mm_set_epi16(8, 9, 10, 11, 12, 13, 14, 15);
4485        assert_eq_m128i(r, e);
4486    }
4487
4488    #[simd_test(enable = "avx512f")]
4489    const fn test_mm512_mask_cvtepi64_epi16() {
4490        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4491        let src = _mm_set1_epi16(-1);
4492        let r = _mm512_mask_cvtepi64_epi16(src, 0, a);
4493        assert_eq_m128i(r, src);
4494        let r = _mm512_mask_cvtepi64_epi16(src, 0b00001111, a);
4495        let e = _mm_set_epi16(-1, -1, -1, -1, 12, 13, 14, 15);
4496        assert_eq_m128i(r, e);
4497    }
4498
4499    #[simd_test(enable = "avx512f")]
4500    const fn test_mm512_maskz_cvtepi64_epi16() {
4501        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4502        let r = _mm512_maskz_cvtepi64_epi16(0, a);
4503        assert_eq_m128i(r, _mm_setzero_si128());
4504        let r = _mm512_maskz_cvtepi64_epi16(0b00001111, a);
4505        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4506        assert_eq_m128i(r, e);
4507    }
4508
4509    #[simd_test(enable = "avx512f,avx512vl")]
4510    fn test_mm256_cvtepi64_epi16() {
4511        let a = _mm256_set_epi64x(12, 13, 14, 15);
4512        let r = _mm256_cvtepi64_epi16(a);
4513        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4514        assert_eq_m128i(r, e);
4515    }
4516
4517    #[simd_test(enable = "avx512f,avx512vl")]
4518    fn test_mm256_mask_cvtepi64_epi16() {
4519        let a = _mm256_set_epi64x(12, 13, 14, 15);
4520        let src = _mm_set1_epi16(0);
4521        let r = _mm256_mask_cvtepi64_epi16(src, 0, a);
4522        assert_eq_m128i(r, src);
4523        let r = _mm256_mask_cvtepi64_epi16(src, 0b11111111, a);
4524        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4525        assert_eq_m128i(r, e);
4526    }
4527
4528    #[simd_test(enable = "avx512f,avx512vl")]
4529    fn test_mm256_maskz_cvtepi64_epi16() {
4530        let a = _mm256_set_epi64x(12, 13, 14, 15);
4531        let r = _mm256_maskz_cvtepi64_epi16(0, a);
4532        assert_eq_m128i(r, _mm_setzero_si128());
4533        let r = _mm256_maskz_cvtepi64_epi16(0b11111111, a);
4534        let e = _mm_set_epi16(0, 0, 0, 0, 12, 13, 14, 15);
4535        assert_eq_m128i(r, e);
4536    }
4537
4538    #[simd_test(enable = "avx512f,avx512vl")]
4539    fn test_mm_cvtepi64_epi16() {
4540        let a = _mm_set_epi64x(14, 15);
4541        let r = _mm_cvtepi64_epi16(a);
4542        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4543        assert_eq_m128i(r, e);
4544    }
4545
4546    #[simd_test(enable = "avx512f,avx512vl")]
4547    fn test_mm_mask_cvtepi64_epi16() {
4548        let a = _mm_set_epi64x(14, 15);
4549        let src = _mm_set1_epi16(0);
4550        let r = _mm_mask_cvtepi64_epi16(src, 0, a);
4551        assert_eq_m128i(r, src);
4552        let r = _mm_mask_cvtepi64_epi16(src, 0b11111111, a);
4553        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4554        assert_eq_m128i(r, e);
4555    }
4556
4557    #[simd_test(enable = "avx512f,avx512vl")]
4558    fn test_mm_maskz_cvtepi64_epi16() {
4559        let a = _mm_set_epi64x(14, 15);
4560        let r = _mm_maskz_cvtepi64_epi16(0, a);
4561        assert_eq_m128i(r, _mm_setzero_si128());
4562        let r = _mm_maskz_cvtepi64_epi16(0b11111111, a);
4563        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 14, 15);
4564        assert_eq_m128i(r, e);
4565    }
4566
4567    #[simd_test(enable = "avx512f")]
4568    fn test_mm512_cvtepi64_epi8() {
4569        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4570        let r = _mm512_cvtepi64_epi8(a);
4571        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
4572        assert_eq_m128i(r, e);
4573    }
4574
4575    #[simd_test(enable = "avx512f")]
4576    fn test_mm512_mask_cvtepi64_epi8() {
4577        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4578        let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4579        let r = _mm512_mask_cvtepi64_epi8(src, 0, a);
4580        assert_eq_m128i(r, src);
4581        let r = _mm512_mask_cvtepi64_epi8(src, 0b00001111, a);
4582        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 12, 13, 14, 15);
4583        assert_eq_m128i(r, e);
4584    }
4585
4586    #[simd_test(enable = "avx512f")]
4587    fn test_mm512_maskz_cvtepi64_epi8() {
4588        let a = _mm512_set_epi64(8, 9, 10, 11, 12, 13, 14, 15);
4589        let r = _mm512_maskz_cvtepi64_epi8(0, a);
4590        assert_eq_m128i(r, _mm_setzero_si128());
4591        let r = _mm512_maskz_cvtepi64_epi8(0b00001111, a);
4592        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4593        assert_eq_m128i(r, e);
4594    }
4595
4596    #[simd_test(enable = "avx512f,avx512vl")]
4597    fn test_mm256_cvtepi64_epi8() {
4598        let a = _mm256_set_epi64x(12, 13, 14, 15);
4599        let r = _mm256_cvtepi64_epi8(a);
4600        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4601        assert_eq_m128i(r, e);
4602    }
4603
4604    #[simd_test(enable = "avx512f,avx512vl")]
4605    fn test_mm256_mask_cvtepi64_epi8() {
4606        let a = _mm256_set_epi64x(12, 13, 14, 15);
4607        let src = _mm_set1_epi8(0);
4608        let r = _mm256_mask_cvtepi64_epi8(src, 0, a);
4609        assert_eq_m128i(r, src);
4610        let r = _mm256_mask_cvtepi64_epi8(src, 0b00001111, a);
4611        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4612        assert_eq_m128i(r, e);
4613    }
4614
4615    #[simd_test(enable = "avx512f,avx512vl")]
4616    fn test_mm256_maskz_cvtepi64_epi8() {
4617        let a = _mm256_set_epi64x(12, 13, 14, 15);
4618        let r = _mm256_maskz_cvtepi64_epi8(0, a);
4619        assert_eq_m128i(r, _mm_setzero_si128());
4620        let r = _mm256_maskz_cvtepi64_epi8(0b00001111, a);
4621        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 13, 14, 15);
4622        assert_eq_m128i(r, e);
4623    }
4624
4625    #[simd_test(enable = "avx512f,avx512vl")]
4626    fn test_mm_cvtepi64_epi8() {
4627        let a = _mm_set_epi64x(14, 15);
4628        let r = _mm_cvtepi64_epi8(a);
4629        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4630        assert_eq_m128i(r, e);
4631    }
4632
4633    #[simd_test(enable = "avx512f,avx512vl")]
4634    fn test_mm_mask_cvtepi64_epi8() {
4635        let a = _mm_set_epi64x(14, 15);
4636        let src = _mm_set1_epi8(0);
4637        let r = _mm_mask_cvtepi64_epi8(src, 0, a);
4638        assert_eq_m128i(r, src);
4639        let r = _mm_mask_cvtepi64_epi8(src, 0b00000011, a);
4640        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4641        assert_eq_m128i(r, e);
4642    }
4643
4644    #[simd_test(enable = "avx512f,avx512vl")]
4645    fn test_mm_maskz_cvtepi64_epi8() {
4646        let a = _mm_set_epi64x(14, 15);
4647        let r = _mm_maskz_cvtepi64_epi8(0, a);
4648        assert_eq_m128i(r, _mm_setzero_si128());
4649        let r = _mm_maskz_cvtepi64_epi8(0b00000011, a);
4650        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15);
4651        assert_eq_m128i(r, e);
4652    }
4653
4654    #[simd_test(enable = "avx512f")]
4655    fn test_mm512_cvtsepi64_epi32() {
4656        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4657        let r = _mm512_cvtsepi64_epi32(a);
4658        let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, i32::MIN, i32::MAX);
4659        assert_eq_m256i(r, e);
4660    }
4661
4662    #[simd_test(enable = "avx512f")]
4663    fn test_mm512_mask_cvtsepi64_epi32() {
4664        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4665        let src = _mm256_set1_epi32(-1);
4666        let r = _mm512_mask_cvtsepi64_epi32(src, 0, a);
4667        assert_eq_m256i(r, src);
4668        let r = _mm512_mask_cvtsepi64_epi32(src, 0b00001111, a);
4669        let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, i32::MIN, i32::MAX);
4670        assert_eq_m256i(r, e);
4671    }
4672
4673    #[simd_test(enable = "avx512f")]
4674    fn test_mm512_maskz_cvtsepi64_epi32() {
4675        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4676        let r = _mm512_maskz_cvtsepi64_epi32(0, a);
4677        assert_eq_m256i(r, _mm256_setzero_si256());
4678        let r = _mm512_maskz_cvtsepi64_epi32(0b00001111, a);
4679        let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, i32::MIN, i32::MAX);
4680        assert_eq_m256i(r, e);
4681    }
4682
4683    #[simd_test(enable = "avx512f,avx512vl")]
4684    fn test_mm256_cvtsepi64_epi32() {
4685        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4686        let r = _mm256_cvtsepi64_epi32(a);
4687        let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4688        assert_eq_m128i(r, e);
4689    }
4690
4691    #[simd_test(enable = "avx512f,avx512vl")]
4692    fn test_mm256_mask_cvtsepi64_epi32() {
4693        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4694        let src = _mm_set1_epi32(-1);
4695        let r = _mm256_mask_cvtsepi64_epi32(src, 0, a);
4696        assert_eq_m128i(r, src);
4697        let r = _mm256_mask_cvtsepi64_epi32(src, 0b00001111, a);
4698        let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4699        assert_eq_m128i(r, e);
4700    }
4701
4702    #[simd_test(enable = "avx512f,avx512vl")]
4703    fn test_mm256_maskz_cvtsepi64_epi32() {
4704        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4705        let r = _mm256_maskz_cvtsepi64_epi32(0, a);
4706        assert_eq_m128i(r, _mm_setzero_si128());
4707        let r = _mm256_maskz_cvtsepi64_epi32(0b00001111, a);
4708        let e = _mm_set_epi32(4, 5, i32::MIN, i32::MAX);
4709        assert_eq_m128i(r, e);
4710    }
4711
4712    #[simd_test(enable = "avx512f,avx512vl")]
4713    fn test_mm_cvtsepi64_epi32() {
4714        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4715        let r = _mm_cvtsepi64_epi32(a);
4716        let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4717        assert_eq_m128i(r, e);
4718    }
4719
4720    #[simd_test(enable = "avx512f,avx512vl")]
4721    fn test_mm_mask_cvtsepi64_epi32() {
4722        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4723        let src = _mm_set1_epi32(0);
4724        let r = _mm_mask_cvtsepi64_epi32(src, 0, a);
4725        assert_eq_m128i(r, src);
4726        let r = _mm_mask_cvtsepi64_epi32(src, 0b00000011, a);
4727        let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4728        assert_eq_m128i(r, e);
4729    }
4730
4731    #[simd_test(enable = "avx512f,avx512vl")]
4732    fn test_mm_maskz_cvtsepi64_epi32() {
4733        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4734        let r = _mm_maskz_cvtsepi64_epi32(0, a);
4735        assert_eq_m128i(r, _mm_setzero_si128());
4736        let r = _mm_maskz_cvtsepi64_epi32(0b00000011, a);
4737        let e = _mm_set_epi32(0, 0, i32::MIN, i32::MAX);
4738        assert_eq_m128i(r, e);
4739    }
4740
4741    #[simd_test(enable = "avx512f")]
4742    fn test_mm512_cvtsepi64_epi16() {
4743        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4744        let r = _mm512_cvtsepi64_epi16(a);
4745        let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, i16::MIN, i16::MAX);
4746        assert_eq_m128i(r, e);
4747    }
4748
4749    #[simd_test(enable = "avx512f")]
4750    fn test_mm512_mask_cvtsepi64_epi16() {
4751        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4752        let src = _mm_set1_epi16(-1);
4753        let r = _mm512_mask_cvtsepi64_epi16(src, 0, a);
4754        assert_eq_m128i(r, src);
4755        let r = _mm512_mask_cvtsepi64_epi16(src, 0b00001111, a);
4756        let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, i16::MIN, i16::MAX);
4757        assert_eq_m128i(r, e);
4758    }
4759
4760    #[simd_test(enable = "avx512f")]
4761    fn test_mm512_maskz_cvtsepi64_epi16() {
4762        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4763        let r = _mm512_maskz_cvtsepi64_epi16(0, a);
4764        assert_eq_m128i(r, _mm_setzero_si128());
4765        let r = _mm512_maskz_cvtsepi64_epi16(0b00001111, a);
4766        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4767        assert_eq_m128i(r, e);
4768    }
4769
4770    #[simd_test(enable = "avx512f,avx512vl")]
4771    fn test_mm256_cvtsepi64_epi16() {
4772        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4773        let r = _mm256_cvtsepi64_epi16(a);
4774        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4775        assert_eq_m128i(r, e);
4776    }
4777
4778    #[simd_test(enable = "avx512f,avx512vl")]
4779    fn test_mm256_mask_cvtsepi64_epi16() {
4780        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4781        let src = _mm_set1_epi16(0);
4782        let r = _mm256_mask_cvtsepi64_epi16(src, 0, a);
4783        assert_eq_m128i(r, src);
4784        let r = _mm256_mask_cvtsepi64_epi16(src, 0b00001111, a);
4785        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4786        assert_eq_m128i(r, e);
4787    }
4788
4789    #[simd_test(enable = "avx512f,avx512vl")]
4790    fn test_mm256_maskz_cvtsepi64_epi16() {
4791        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4792        let r = _mm256_maskz_cvtsepi64_epi16(0, a);
4793        assert_eq_m128i(r, _mm_setzero_si128());
4794        let r = _mm256_maskz_cvtsepi64_epi16(0b00001111, a);
4795        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, i16::MIN, i16::MAX);
4796        assert_eq_m128i(r, e);
4797    }
4798
4799    #[simd_test(enable = "avx512f,avx512vl")]
4800    fn test_mm_cvtsepi64_epi16() {
4801        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4802        let r = _mm_cvtsepi64_epi16(a);
4803        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4804        assert_eq_m128i(r, e);
4805    }
4806
4807    #[simd_test(enable = "avx512f,avx512vl")]
4808    fn test_mm_mask_cvtsepi64_epi16() {
4809        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4810        let src = _mm_set1_epi16(0);
4811        let r = _mm_mask_cvtsepi64_epi16(src, 0, a);
4812        assert_eq_m128i(r, src);
4813        let r = _mm_mask_cvtsepi64_epi16(src, 0b00000011, a);
4814        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4815        assert_eq_m128i(r, e);
4816    }
4817
4818    #[simd_test(enable = "avx512f,avx512vl")]
4819    fn test_mm_maskz_cvtsepi64_epi16() {
4820        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4821        let r = _mm_maskz_cvtsepi64_epi16(0, a);
4822        assert_eq_m128i(r, _mm_setzero_si128());
4823        let r = _mm_maskz_cvtsepi64_epi16(0b00000011, a);
4824        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MIN, i16::MAX);
4825        assert_eq_m128i(r, e);
4826    }
4827
4828    #[simd_test(enable = "avx512f")]
4829    fn test_mm512_cvtsepi64_epi8() {
4830        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4831        let r = _mm512_cvtsepi64_epi8(a);
4832        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, i8::MIN, i8::MAX);
4833        assert_eq_m128i(r, e);
4834    }
4835
4836    #[simd_test(enable = "avx512f")]
4837    fn test_mm512_mask_cvtsepi64_epi8() {
4838        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4839        let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
4840        let r = _mm512_mask_cvtsepi64_epi8(src, 0, a);
4841        assert_eq_m128i(r, src);
4842        let r = _mm512_mask_cvtsepi64_epi8(src, 0b00001111, a);
4843        #[rustfmt::skip]
4844        let e = _mm_set_epi8(
4845            0, 0, 0, 0,
4846            0, 0, 0, 0,
4847            -1, -1, -1, -1,
4848            4, 5, i8::MIN, i8::MAX,
4849        );
4850        assert_eq_m128i(r, e);
4851    }
4852
4853    #[simd_test(enable = "avx512f")]
4854    fn test_mm512_maskz_cvtsepi64_epi8() {
4855        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MAX);
4856        let r = _mm512_maskz_cvtsepi64_epi8(0, a);
4857        assert_eq_m128i(r, _mm_setzero_si128());
4858        let r = _mm512_maskz_cvtsepi64_epi8(0b00001111, a);
4859        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4860        assert_eq_m128i(r, e);
4861    }
4862
4863    #[simd_test(enable = "avx512f,avx512vl")]
4864    fn test_mm256_cvtsepi64_epi8() {
4865        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4866        let r = _mm256_cvtsepi64_epi8(a);
4867        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4868        assert_eq_m128i(r, e);
4869    }
4870
4871    #[simd_test(enable = "avx512f,avx512vl")]
4872    fn test_mm256_mask_cvtsepi64_epi8() {
4873        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4874        let src = _mm_set1_epi8(0);
4875        let r = _mm256_mask_cvtsepi64_epi8(src, 0, a);
4876        assert_eq_m128i(r, src);
4877        let r = _mm256_mask_cvtsepi64_epi8(src, 0b00001111, a);
4878        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4879        assert_eq_m128i(r, e);
4880    }
4881
4882    #[simd_test(enable = "avx512f,avx512vl")]
4883    fn test_mm256_maskz_cvtsepi64_epi8() {
4884        let a = _mm256_set_epi64x(4, 5, i64::MIN, i64::MAX);
4885        let r = _mm256_maskz_cvtsepi64_epi8(0, a);
4886        assert_eq_m128i(r, _mm_setzero_si128());
4887        let r = _mm256_maskz_cvtsepi64_epi8(0b00001111, a);
4888        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, i8::MIN, i8::MAX);
4889        assert_eq_m128i(r, e);
4890    }
4891
4892    #[simd_test(enable = "avx512f,avx512vl")]
4893    fn test_mm_cvtsepi64_epi8() {
4894        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4895        let r = _mm_cvtsepi64_epi8(a);
4896        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4897        assert_eq_m128i(r, e);
4898    }
4899
4900    #[simd_test(enable = "avx512f,avx512vl")]
4901    fn test_mm_mask_cvtsepi64_epi8() {
4902        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4903        let src = _mm_set1_epi8(0);
4904        let r = _mm_mask_cvtsepi64_epi8(src, 0, a);
4905        assert_eq_m128i(r, src);
4906        let r = _mm_mask_cvtsepi64_epi8(src, 0b00000011, a);
4907        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4908        assert_eq_m128i(r, e);
4909    }
4910
4911    #[simd_test(enable = "avx512f,avx512vl")]
4912    fn test_mm_maskz_cvtsepi64_epi8() {
4913        let a = _mm_set_epi64x(i64::MIN, i64::MAX);
4914        let r = _mm_maskz_cvtsepi64_epi8(0, a);
4915        assert_eq_m128i(r, _mm_setzero_si128());
4916        let r = _mm_maskz_cvtsepi64_epi8(0b00000011, a);
4917        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MAX);
4918        assert_eq_m128i(r, e);
4919    }
4920
4921    #[simd_test(enable = "avx512f")]
4922    fn test_mm512_cvtusepi64_epi32() {
4923        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4924        let r = _mm512_cvtusepi64_epi32(a);
4925        let e = _mm256_set_epi32(0, 1, 2, 3, 4, 5, -1, -1);
4926        assert_eq_m256i(r, e);
4927    }
4928
4929    #[simd_test(enable = "avx512f")]
4930    fn test_mm512_mask_cvtusepi64_epi32() {
4931        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4932        let src = _mm256_set1_epi32(-1);
4933        let r = _mm512_mask_cvtusepi64_epi32(src, 0, a);
4934        assert_eq_m256i(r, src);
4935        let r = _mm512_mask_cvtusepi64_epi32(src, 0b00001111, a);
4936        let e = _mm256_set_epi32(-1, -1, -1, -1, 4, 5, -1, -1);
4937        assert_eq_m256i(r, e);
4938    }
4939
4940    #[simd_test(enable = "avx512f")]
4941    fn test_mm512_maskz_cvtusepi64_epi32() {
4942        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
4943        let r = _mm512_maskz_cvtusepi64_epi32(0, a);
4944        assert_eq_m256i(r, _mm256_setzero_si256());
4945        let r = _mm512_maskz_cvtusepi64_epi32(0b00001111, a);
4946        let e = _mm256_set_epi32(0, 0, 0, 0, 4, 5, -1, -1);
4947        assert_eq_m256i(r, e);
4948    }
4949
4950    #[simd_test(enable = "avx512f,avx512vl")]
4951    fn test_mm256_cvtusepi64_epi32() {
4952        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4953        let r = _mm256_cvtusepi64_epi32(a);
4954        let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4955        assert_eq_m128i(r, e);
4956    }
4957
4958    #[simd_test(enable = "avx512f,avx512vl")]
4959    fn test_mm256_mask_cvtusepi64_epi32() {
4960        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4961        let src = _mm_set1_epi32(0);
4962        let r = _mm256_mask_cvtusepi64_epi32(src, 0, a);
4963        assert_eq_m128i(r, src);
4964        let r = _mm256_mask_cvtusepi64_epi32(src, 0b00001111, a);
4965        let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4966        assert_eq_m128i(r, e);
4967    }
4968
4969    #[simd_test(enable = "avx512f,avx512vl")]
4970    fn test_mm256_maskz_cvtusepi64_epi32() {
4971        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
4972        let r = _mm256_maskz_cvtusepi64_epi32(0, a);
4973        assert_eq_m128i(r, _mm_setzero_si128());
4974        let r = _mm256_maskz_cvtusepi64_epi32(0b00001111, a);
4975        let e = _mm_set_epi32(4, 5, 6, u32::MAX as i32);
4976        assert_eq_m128i(r, e);
4977    }
4978
4979    #[simd_test(enable = "avx512f,avx512vl")]
4980    fn test_mm_cvtusepi64_epi32() {
4981        let a = _mm_set_epi64x(6, i64::MAX);
4982        let r = _mm_cvtusepi64_epi32(a);
4983        let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4984        assert_eq_m128i(r, e);
4985    }
4986
4987    #[simd_test(enable = "avx512f,avx512vl")]
4988    fn test_mm_mask_cvtusepi64_epi32() {
4989        let a = _mm_set_epi64x(6, i64::MAX);
4990        let src = _mm_set1_epi32(0);
4991        let r = _mm_mask_cvtusepi64_epi32(src, 0, a);
4992        assert_eq_m128i(r, src);
4993        let r = _mm_mask_cvtusepi64_epi32(src, 0b00000011, a);
4994        let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
4995        assert_eq_m128i(r, e);
4996    }
4997
4998    #[simd_test(enable = "avx512f,avx512vl")]
4999    fn test_mm_maskz_cvtusepi64_epi32() {
5000        let a = _mm_set_epi64x(6, i64::MAX);
5001        let r = _mm_maskz_cvtusepi64_epi32(0, a);
5002        assert_eq_m128i(r, _mm_setzero_si128());
5003        let r = _mm_maskz_cvtusepi64_epi32(0b00000011, a);
5004        let e = _mm_set_epi32(0, 0, 6, u32::MAX as i32);
5005        assert_eq_m128i(r, e);
5006    }
5007
5008    #[simd_test(enable = "avx512f")]
5009    fn test_mm512_cvtusepi64_epi16() {
5010        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5011        let r = _mm512_cvtusepi64_epi16(a);
5012        let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, -1, -1);
5013        assert_eq_m128i(r, e);
5014    }
5015
5016    #[simd_test(enable = "avx512f")]
5017    fn test_mm512_mask_cvtusepi64_epi16() {
5018        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5019        let src = _mm_set1_epi16(-1);
5020        let r = _mm512_mask_cvtusepi64_epi16(src, 0, a);
5021        assert_eq_m128i(r, src);
5022        let r = _mm512_mask_cvtusepi64_epi16(src, 0b00001111, a);
5023        let e = _mm_set_epi16(-1, -1, -1, -1, 4, 5, -1, -1);
5024        assert_eq_m128i(r, e);
5025    }
5026
5027    #[simd_test(enable = "avx512f")]
5028    fn test_mm512_maskz_cvtusepi64_epi16() {
5029        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5030        let r = _mm512_maskz_cvtusepi64_epi16(0, a);
5031        assert_eq_m128i(r, _mm_setzero_si128());
5032        let r = _mm512_maskz_cvtusepi64_epi16(0b00001111, a);
5033        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, -1, -1);
5034        assert_eq_m128i(r, e);
5035    }
5036
5037    #[simd_test(enable = "avx512f,avx512vl")]
5038    fn test_mm256_cvtusepi64_epi16() {
5039        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5040        let r = _mm256_cvtusepi64_epi16(a);
5041        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5042        assert_eq_m128i(r, e);
5043    }
5044
5045    #[simd_test(enable = "avx512f,avx512vl")]
5046    fn test_mm256_mask_cvtusepi64_epi16() {
5047        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5048        let src = _mm_set1_epi16(0);
5049        let r = _mm256_mask_cvtusepi64_epi16(src, 0, a);
5050        assert_eq_m128i(r, src);
5051        let r = _mm256_mask_cvtusepi64_epi16(src, 0b00001111, a);
5052        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5053        assert_eq_m128i(r, e);
5054    }
5055
5056    #[simd_test(enable = "avx512f,avx512vl")]
5057    fn test_mm256_maskz_cvtusepi64_epi16() {
5058        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5059        let r = _mm256_maskz_cvtusepi64_epi16(0, a);
5060        assert_eq_m128i(r, _mm_setzero_si128());
5061        let r = _mm256_maskz_cvtusepi64_epi16(0b00001111, a);
5062        let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, u16::MAX as i16);
5063        assert_eq_m128i(r, e);
5064    }
5065
5066    #[simd_test(enable = "avx512f,avx512vl")]
5067    fn test_mm_cvtusepi64_epi16() {
5068        let a = _mm_set_epi64x(6, i64::MAX);
5069        let r = _mm_cvtusepi64_epi16(a);
5070        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5071        assert_eq_m128i(r, e);
5072    }
5073
5074    #[simd_test(enable = "avx512f,avx512vl")]
5075    fn test_mm_mask_cvtusepi64_epi16() {
5076        let a = _mm_set_epi64x(6, i64::MAX);
5077        let src = _mm_set1_epi16(0);
5078        let r = _mm_mask_cvtusepi64_epi16(src, 0, a);
5079        assert_eq_m128i(r, src);
5080        let r = _mm_mask_cvtusepi64_epi16(src, 0b00000011, a);
5081        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5082        assert_eq_m128i(r, e);
5083    }
5084
5085    #[simd_test(enable = "avx512f,avx512vl")]
5086    fn test_mm_maskz_cvtusepi64_epi16() {
5087        let a = _mm_set_epi64x(6, i64::MAX);
5088        let r = _mm_maskz_cvtusepi64_epi16(0, a);
5089        assert_eq_m128i(r, _mm_setzero_si128());
5090        let r = _mm_maskz_cvtusepi64_epi16(0b00000011, a);
5091        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 6, u16::MAX as i16);
5092        assert_eq_m128i(r, e);
5093    }
5094
5095    #[simd_test(enable = "avx512f")]
5096    fn test_mm512_cvtusepi64_epi8() {
5097        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5098        let r = _mm512_cvtusepi64_epi8(a);
5099        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, -1, -1);
5100        assert_eq_m128i(r, e);
5101    }
5102
5103    #[simd_test(enable = "avx512f")]
5104    fn test_mm512_mask_cvtusepi64_epi8() {
5105        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5106        let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
5107        let r = _mm512_mask_cvtusepi64_epi8(src, 0, a);
5108        assert_eq_m128i(r, src);
5109        let r = _mm512_mask_cvtusepi64_epi8(src, 0b00001111, a);
5110        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, 4, 5, -1, -1);
5111        assert_eq_m128i(r, e);
5112    }
5113
5114    #[simd_test(enable = "avx512f")]
5115    fn test_mm512_maskz_cvtusepi64_epi8() {
5116        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, i64::MIN, i64::MIN);
5117        let r = _mm512_maskz_cvtusepi64_epi8(0, a);
5118        assert_eq_m128i(r, _mm_setzero_si128());
5119        let r = _mm512_maskz_cvtusepi64_epi8(0b00001111, a);
5120        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, -1, -1);
5121        assert_eq_m128i(r, e);
5122    }
5123
5124    #[simd_test(enable = "avx512f,avx512vl")]
5125    fn test_mm256_cvtusepi64_epi8() {
5126        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5127        let r = _mm256_cvtusepi64_epi8(a);
5128        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5129        assert_eq_m128i(r, e);
5130    }
5131
5132    #[simd_test(enable = "avx512f,avx512vl")]
5133    fn test_mm256_mask_cvtusepi64_epi8() {
5134        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5135        let src = _mm_set1_epi8(0);
5136        let r = _mm256_mask_cvtusepi64_epi8(src, 0, a);
5137        assert_eq_m128i(r, src);
5138        let r = _mm256_mask_cvtusepi64_epi8(src, 0b00001111, a);
5139        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5140        assert_eq_m128i(r, e);
5141    }
5142
5143    #[simd_test(enable = "avx512f,avx512vl")]
5144    fn test_mm256_maskz_cvtusepi64_epi8() {
5145        let a = _mm256_set_epi64x(4, 5, 6, i64::MAX);
5146        let r = _mm256_maskz_cvtusepi64_epi8(0, a);
5147        assert_eq_m128i(r, _mm_setzero_si128());
5148        let r = _mm256_maskz_cvtusepi64_epi8(0b00001111, a);
5149        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 5, 6, u8::MAX as i8);
5150        assert_eq_m128i(r, e);
5151    }
5152
5153    #[simd_test(enable = "avx512f,avx512vl")]
5154    fn test_mm_cvtusepi64_epi8() {
5155        let a = _mm_set_epi64x(6, i64::MAX);
5156        let r = _mm_cvtusepi64_epi8(a);
5157        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5158        assert_eq_m128i(r, e);
5159    }
5160
5161    #[simd_test(enable = "avx512f,avx512vl")]
5162    fn test_mm_mask_cvtusepi64_epi8() {
5163        let a = _mm_set_epi64x(6, i64::MAX);
5164        let src = _mm_set1_epi8(0);
5165        let r = _mm_mask_cvtusepi64_epi8(src, 0, a);
5166        assert_eq_m128i(r, src);
5167        let r = _mm_mask_cvtusepi64_epi8(src, 0b00000011, a);
5168        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5169        assert_eq_m128i(r, e);
5170    }
5171
5172    #[simd_test(enable = "avx512f,avx512vl")]
5173    fn test_mm_maskz_cvtusepi64_epi8() {
5174        let a = _mm_set_epi64x(6, i64::MAX);
5175        let r = _mm_maskz_cvtusepi64_epi8(0, a);
5176        assert_eq_m128i(r, _mm_setzero_si128());
5177        let r = _mm_maskz_cvtusepi64_epi8(0b00000011, a);
5178        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, u8::MAX as i8);
5179        assert_eq_m128i(r, e);
5180    }
5181
5182    #[simd_test(enable = "avx512f")]
5183    fn test_mm512_cvtt_roundpd_epi32() {
5184        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5185        let r = _mm512_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(a);
5186        let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5187        assert_eq_m256i(r, e);
5188    }
5189
5190    #[simd_test(enable = "avx512f")]
5191    fn test_mm512_mask_cvtt_roundpd_epi32() {
5192        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5193        let src = _mm256_set1_epi32(0);
5194        let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0, a);
5195        assert_eq_m256i(r, src);
5196        let r = _mm512_mask_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5197        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5198        assert_eq_m256i(r, e);
5199    }
5200
5201    #[simd_test(enable = "avx512f")]
5202    fn test_mm512_maskz_cvtt_roundpd_epi32() {
5203        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5204        let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0, a);
5205        assert_eq_m256i(r, _mm256_setzero_si256());
5206        let r = _mm512_maskz_cvtt_roundpd_epi32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5207        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5208        assert_eq_m256i(r, e);
5209    }
5210
5211    #[simd_test(enable = "avx512f")]
5212    fn test_mm512_cvtt_roundpd_epu32() {
5213        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5214        let r = _mm512_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(a);
5215        let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5216        assert_eq_m256i(r, e);
5217    }
5218
5219    #[simd_test(enable = "avx512f")]
5220    fn test_mm512_mask_cvtt_roundpd_epu32() {
5221        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5222        let src = _mm256_set1_epi32(0);
5223        let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0, a);
5224        assert_eq_m256i(r, src);
5225        let r = _mm512_mask_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(src, 0b00001111, a);
5226        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5227        assert_eq_m256i(r, e);
5228    }
5229
5230    #[simd_test(enable = "avx512f")]
5231    fn test_mm512_maskz_cvtt_roundpd_epu32() {
5232        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5233        let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0, a);
5234        assert_eq_m256i(r, _mm256_setzero_si256());
5235        let r = _mm512_maskz_cvtt_roundpd_epu32::<_MM_FROUND_NO_EXC>(0b00001111, a);
5236        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5237        assert_eq_m256i(r, e);
5238    }
5239
5240    #[simd_test(enable = "avx512f")]
5241    fn test_mm512_cvttpd_epi32() {
5242        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5243        let r = _mm512_cvttpd_epi32(a);
5244        let e = _mm256_setr_epi32(0, -1, 2, -3, 4, -5, 6, -7);
5245        assert_eq_m256i(r, e);
5246    }
5247
5248    #[simd_test(enable = "avx512f")]
5249    fn test_mm512_mask_cvttpd_epi32() {
5250        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5251        let src = _mm256_set1_epi32(0);
5252        let r = _mm512_mask_cvttpd_epi32(src, 0, a);
5253        assert_eq_m256i(r, src);
5254        let r = _mm512_mask_cvttpd_epi32(src, 0b00001111, a);
5255        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5256        assert_eq_m256i(r, e);
5257    }
5258
5259    #[simd_test(enable = "avx512f")]
5260    fn test_mm512_maskz_cvttpd_epi32() {
5261        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5262        let r = _mm512_maskz_cvttpd_epi32(0, a);
5263        assert_eq_m256i(r, _mm256_setzero_si256());
5264        let r = _mm512_maskz_cvttpd_epi32(0b00001111, a);
5265        let e = _mm256_setr_epi32(0, -1, 2, -3, 0, 0, 0, 0);
5266        assert_eq_m256i(r, e);
5267    }
5268
5269    #[simd_test(enable = "avx512f,avx512vl")]
5270    fn test_mm256_mask_cvttpd_epi32() {
5271        let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5272        let src = _mm_set1_epi32(0);
5273        let r = _mm256_mask_cvttpd_epi32(src, 0, a);
5274        assert_eq_m128i(r, src);
5275        let r = _mm256_mask_cvttpd_epi32(src, 0b00001111, a);
5276        let e = _mm_setr_epi32(4, -5, 6, -7);
5277        assert_eq_m128i(r, e);
5278    }
5279
5280    #[simd_test(enable = "avx512f,avx512vl")]
5281    fn test_mm256_maskz_cvttpd_epi32() {
5282        let a = _mm256_setr_pd(4., -5.5, 6., -7.5);
5283        let r = _mm256_maskz_cvttpd_epi32(0, a);
5284        assert_eq_m128i(r, _mm_setzero_si128());
5285        let r = _mm256_maskz_cvttpd_epi32(0b00001111, a);
5286        let e = _mm_setr_epi32(4, -5, 6, -7);
5287        assert_eq_m128i(r, e);
5288    }
5289
5290    #[simd_test(enable = "avx512f,avx512vl")]
5291    fn test_mm_mask_cvttpd_epi32() {
5292        let a = _mm_set_pd(6., -7.5);
5293        let src = _mm_set1_epi32(0);
5294        let r = _mm_mask_cvttpd_epi32(src, 0, a);
5295        assert_eq_m128i(r, src);
5296        let r = _mm_mask_cvttpd_epi32(src, 0b00000011, a);
5297        let e = _mm_set_epi32(0, 0, 6, -7);
5298        assert_eq_m128i(r, e);
5299    }
5300
5301    #[simd_test(enable = "avx512f,avx512vl")]
5302    fn test_mm_maskz_cvttpd_epi32() {
5303        let a = _mm_set_pd(6., -7.5);
5304        let r = _mm_maskz_cvttpd_epi32(0, a);
5305        assert_eq_m128i(r, _mm_setzero_si128());
5306        let r = _mm_maskz_cvttpd_epi32(0b00000011, a);
5307        let e = _mm_set_epi32(0, 0, 6, -7);
5308        assert_eq_m128i(r, e);
5309    }
5310
5311    #[simd_test(enable = "avx512f")]
5312    fn test_mm512_cvttpd_epu32() {
5313        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5314        let r = _mm512_cvttpd_epu32(a);
5315        let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
5316        assert_eq_m256i(r, e);
5317    }
5318
5319    #[simd_test(enable = "avx512f")]
5320    fn test_mm512_mask_cvttpd_epu32() {
5321        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5322        let src = _mm256_set1_epi32(0);
5323        let r = _mm512_mask_cvttpd_epu32(src, 0, a);
5324        assert_eq_m256i(r, src);
5325        let r = _mm512_mask_cvttpd_epu32(src, 0b00001111, a);
5326        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5327        assert_eq_m256i(r, e);
5328    }
5329
5330    #[simd_test(enable = "avx512f")]
5331    fn test_mm512_maskz_cvttpd_epu32() {
5332        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
5333        let r = _mm512_maskz_cvttpd_epu32(0, a);
5334        assert_eq_m256i(r, _mm256_setzero_si256());
5335        let r = _mm512_maskz_cvttpd_epu32(0b00001111, a);
5336        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
5337        assert_eq_m256i(r, e);
5338    }
5339
5340    #[simd_test(enable = "avx512f,avx512vl")]
5341    fn test_mm256_cvttpd_epu32() {
5342        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5343        let r = _mm256_cvttpd_epu32(a);
5344        let e = _mm_set_epi32(4, 5, 6, 7);
5345        assert_eq_m128i(r, e);
5346    }
5347
5348    #[simd_test(enable = "avx512f,avx512vl")]
5349    fn test_mm256_mask_cvttpd_epu32() {
5350        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5351        let src = _mm_set1_epi32(0);
5352        let r = _mm256_mask_cvttpd_epu32(src, 0, a);
5353        assert_eq_m128i(r, src);
5354        let r = _mm256_mask_cvttpd_epu32(src, 0b00001111, a);
5355        let e = _mm_set_epi32(4, 5, 6, 7);
5356        assert_eq_m128i(r, e);
5357    }
5358
5359    #[simd_test(enable = "avx512f,avx512vl")]
5360    fn test_mm256_maskz_cvttpd_epu32() {
5361        let a = _mm256_set_pd(4., 5.5, 6., 7.5);
5362        let r = _mm256_maskz_cvttpd_epu32(0, a);
5363        assert_eq_m128i(r, _mm_setzero_si128());
5364        let r = _mm256_maskz_cvttpd_epu32(0b00001111, a);
5365        let e = _mm_set_epi32(4, 5, 6, 7);
5366        assert_eq_m128i(r, e);
5367    }
5368
5369    #[simd_test(enable = "avx512f,avx512vl")]
5370    fn test_mm_cvttpd_epu32() {
5371        let a = _mm_set_pd(6., 7.5);
5372        let r = _mm_cvttpd_epu32(a);
5373        let e = _mm_set_epi32(0, 0, 6, 7);
5374        assert_eq_m128i(r, e);
5375    }
5376
5377    #[simd_test(enable = "avx512f,avx512vl")]
5378    fn test_mm_mask_cvttpd_epu32() {
5379        let a = _mm_set_pd(6., 7.5);
5380        let src = _mm_set1_epi32(0);
5381        let r = _mm_mask_cvttpd_epu32(src, 0, a);
5382        assert_eq_m128i(r, src);
5383        let r = _mm_mask_cvttpd_epu32(src, 0b00000011, a);
5384        let e = _mm_set_epi32(0, 0, 6, 7);
5385        assert_eq_m128i(r, e);
5386    }
5387
5388    #[simd_test(enable = "avx512f,avx512vl")]
5389    fn test_mm_maskz_cvttpd_epu32() {
5390        let a = _mm_set_pd(6., 7.5);
5391        let r = _mm_maskz_cvttpd_epu32(0, a);
5392        assert_eq_m128i(r, _mm_setzero_si128());
5393        let r = _mm_maskz_cvttpd_epu32(0b00000011, a);
5394        let e = _mm_set_epi32(0, 0, 6, 7);
5395        assert_eq_m128i(r, e);
5396    }
5397
5398    #[simd_test(enable = "avx512f")]
5399    fn test_mm512_add_round_pd() {
5400        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5401        let b = _mm512_set1_pd(-1.);
5402        let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5403        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5404        assert_eq_m512d(r, e);
5405        let r = _mm512_add_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5406        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5407        assert_eq_m512d(r, e);
5408    }
5409
5410    #[simd_test(enable = "avx512f")]
5411    fn test_mm512_mask_add_round_pd() {
5412        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5413        let b = _mm512_set1_pd(-1.);
5414        let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5415            a, 0, a, b,
5416        );
5417        assert_eq_m512d(r, a);
5418        let r = _mm512_mask_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5419            a, 0b11110000, a, b,
5420        );
5421        let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5422        assert_eq_m512d(r, e);
5423    }
5424
5425    #[simd_test(enable = "avx512f")]
5426    fn test_mm512_maskz_add_round_pd() {
5427        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5428        let b = _mm512_set1_pd(-1.);
5429        let r =
5430            _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5431        assert_eq_m512d(r, _mm512_setzero_pd());
5432        let r = _mm512_maskz_add_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5433            0b11110000, a, b,
5434        );
5435        let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5436        assert_eq_m512d(r, e);
5437    }
5438
5439    #[simd_test(enable = "avx512f")]
5440    fn test_mm512_sub_round_pd() {
5441        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5442        let b = _mm512_set1_pd(1.);
5443        let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5444        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -1.0);
5445        assert_eq_m512d(r, e);
5446        let r = _mm512_sub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5447        let e = _mm512_setr_pd(7., 8.5, 9., 10.5, 11., 12.5, 13., -0.9999999999999999);
5448        assert_eq_m512d(r, e);
5449    }
5450
5451    #[simd_test(enable = "avx512f")]
5452    fn test_mm512_mask_sub_round_pd() {
5453        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5454        let b = _mm512_set1_pd(1.);
5455        let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5456            a, 0, a, b,
5457        );
5458        assert_eq_m512d(r, a);
5459        let r = _mm512_mask_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5460            a, 0b11110000, a, b,
5461        );
5462        let e = _mm512_setr_pd(8., 9.5, 10., 11.5, 11., 12.5, 13., -1.0);
5463        assert_eq_m512d(r, e);
5464    }
5465
5466    #[simd_test(enable = "avx512f")]
5467    fn test_mm512_maskz_sub_round_pd() {
5468        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.000000000000000007);
5469        let b = _mm512_set1_pd(1.);
5470        let r =
5471            _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5472        assert_eq_m512d(r, _mm512_setzero_pd());
5473        let r = _mm512_maskz_sub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5474            0b11110000, a, b,
5475        );
5476        let e = _mm512_setr_pd(0., 0., 0., 0., 11., 12.5, 13., -1.0);
5477        assert_eq_m512d(r, e);
5478    }
5479
5480    #[simd_test(enable = "avx512f")]
5481    fn test_mm512_mul_round_pd() {
5482        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5483        let b = _mm512_set1_pd(0.1);
5484        let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5485        let e = _mm512_setr_pd(
5486            0.8,
5487            0.9500000000000001,
5488            1.,
5489            1.1500000000000001,
5490            1.2000000000000002,
5491            1.35,
5492            1.4000000000000001,
5493            0.,
5494        );
5495        assert_eq_m512d(r, e);
5496        let r = _mm512_mul_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5497        let e = _mm512_setr_pd(0.8, 0.95, 1.0, 1.15, 1.2, 1.3499999999999999, 1.4, 0.0);
5498        assert_eq_m512d(r, e);
5499    }
5500
5501    #[simd_test(enable = "avx512f")]
5502    fn test_mm512_mask_mul_round_pd() {
5503        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5504        let b = _mm512_set1_pd(0.1);
5505        let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5506            a, 0, a, b,
5507        );
5508        assert_eq_m512d(r, a);
5509        let r = _mm512_mask_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5510            a, 0b11110000, a, b,
5511        );
5512        let e = _mm512_setr_pd(
5513            8.,
5514            9.5,
5515            10.,
5516            11.5,
5517            1.2000000000000002,
5518            1.35,
5519            1.4000000000000001,
5520            0.,
5521        );
5522        assert_eq_m512d(r, e);
5523    }
5524
5525    #[simd_test(enable = "avx512f")]
5526    fn test_mm512_maskz_mul_round_pd() {
5527        let a = _mm512_setr_pd(8., 9.5, 10., 11.5, 12., 13.5, 14., 0.);
5528        let b = _mm512_set1_pd(0.1);
5529        let r =
5530            _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5531        assert_eq_m512d(r, _mm512_setzero_pd());
5532        let r = _mm512_maskz_mul_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5533            0b11110000, a, b,
5534        );
5535        let e = _mm512_setr_pd(
5536            0.,
5537            0.,
5538            0.,
5539            0.,
5540            1.2000000000000002,
5541            1.35,
5542            1.4000000000000001,
5543            0.,
5544        );
5545        assert_eq_m512d(r, e);
5546    }
5547
5548    #[simd_test(enable = "avx512f")]
5549    fn test_mm512_div_round_pd() {
5550        let a = _mm512_set1_pd(1.);
5551        let b = _mm512_set1_pd(3.);
5552        let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
5553        let e = _mm512_set1_pd(0.3333333333333333);
5554        assert_eq_m512d(r, e);
5555        let r = _mm512_div_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
5556        let e = _mm512_set1_pd(0.3333333333333333);
5557        assert_eq_m512d(r, e);
5558    }
5559
5560    #[simd_test(enable = "avx512f")]
5561    fn test_mm512_mask_div_round_pd() {
5562        let a = _mm512_set1_pd(1.);
5563        let b = _mm512_set1_pd(3.);
5564        let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5565            a, 0, a, b,
5566        );
5567        assert_eq_m512d(r, a);
5568        let r = _mm512_mask_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5569            a, 0b11110000, a, b,
5570        );
5571        let e = _mm512_setr_pd(
5572            1.,
5573            1.,
5574            1.,
5575            1.,
5576            0.3333333333333333,
5577            0.3333333333333333,
5578            0.3333333333333333,
5579            0.3333333333333333,
5580        );
5581        assert_eq_m512d(r, e);
5582    }
5583
5584    #[simd_test(enable = "avx512f")]
5585    fn test_mm512_maskz_div_round_pd() {
5586        let a = _mm512_set1_pd(1.);
5587        let b = _mm512_set1_pd(3.);
5588        let r =
5589            _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a, b);
5590        assert_eq_m512d(r, _mm512_setzero_pd());
5591        let r = _mm512_maskz_div_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5592            0b11110000, a, b,
5593        );
5594        let e = _mm512_setr_pd(
5595            0.,
5596            0.,
5597            0.,
5598            0.,
5599            0.3333333333333333,
5600            0.3333333333333333,
5601            0.3333333333333333,
5602            0.3333333333333333,
5603        );
5604        assert_eq_m512d(r, e);
5605    }
5606
5607    #[simd_test(enable = "avx512f")]
5608    fn test_mm512_sqrt_round_pd() {
5609        let a = _mm512_set1_pd(3.);
5610        let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a);
5611        let e = _mm512_set1_pd(1.7320508075688772);
5612        assert_eq_m512d(r, e);
5613        let r = _mm512_sqrt_round_pd::<{ _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC }>(a);
5614        let e = _mm512_set1_pd(1.7320508075688774);
5615        assert_eq_m512d(r, e);
5616    }
5617
5618    #[simd_test(enable = "avx512f")]
5619    fn test_mm512_mask_sqrt_round_pd() {
5620        let a = _mm512_set1_pd(3.);
5621        let r =
5622            _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, 0, a);
5623        assert_eq_m512d(r, a);
5624        let r = _mm512_mask_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5625            a, 0b11110000, a,
5626        );
5627        let e = _mm512_setr_pd(
5628            3.,
5629            3.,
5630            3.,
5631            3.,
5632            1.7320508075688772,
5633            1.7320508075688772,
5634            1.7320508075688772,
5635            1.7320508075688772,
5636        );
5637        assert_eq_m512d(r, e);
5638    }
5639
5640    #[simd_test(enable = "avx512f")]
5641    fn test_mm512_maskz_sqrt_round_pd() {
5642        let a = _mm512_set1_pd(3.);
5643        let r =
5644            _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(0, a);
5645        assert_eq_m512d(r, _mm512_setzero_pd());
5646        let r = _mm512_maskz_sqrt_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5647            0b11110000, a,
5648        );
5649        let e = _mm512_setr_pd(
5650            0.,
5651            0.,
5652            0.,
5653            0.,
5654            1.7320508075688772,
5655            1.7320508075688772,
5656            1.7320508075688772,
5657            1.7320508075688772,
5658        );
5659        assert_eq_m512d(r, e);
5660    }
5661
5662    #[simd_test(enable = "avx512f")]
5663    fn test_mm512_fmadd_round_pd() {
5664        let a = _mm512_set1_pd(0.000000000000000007);
5665        let b = _mm512_set1_pd(1.);
5666        let c = _mm512_set1_pd(-1.);
5667        let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5668        let e = _mm512_set1_pd(-1.);
5669        assert_eq_m512d(r, e);
5670        let r = _mm512_fmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5671        let e = _mm512_set1_pd(-0.9999999999999999);
5672        assert_eq_m512d(r, e);
5673    }
5674
5675    #[simd_test(enable = "avx512f")]
5676    fn test_mm512_mask_fmadd_round_pd() {
5677        let a = _mm512_set1_pd(0.000000000000000007);
5678        let b = _mm512_set1_pd(1.);
5679        let c = _mm512_set1_pd(-1.);
5680        let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5681            a, 0, b, c,
5682        );
5683        assert_eq_m512d(r, a);
5684        let r = _mm512_mask_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5685            a, 0b00001111, b, c,
5686        );
5687        let e = _mm512_setr_pd(
5688            -1.,
5689            -1.,
5690            -1.,
5691            -1.,
5692            0.000000000000000007,
5693            0.000000000000000007,
5694            0.000000000000000007,
5695            0.000000000000000007,
5696        );
5697        assert_eq_m512d(r, e);
5698    }
5699
5700    #[simd_test(enable = "avx512f")]
5701    fn test_mm512_maskz_fmadd_round_pd() {
5702        let a = _mm512_set1_pd(0.000000000000000007);
5703        let b = _mm512_set1_pd(1.);
5704        let c = _mm512_set1_pd(-1.);
5705        let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5706            0, a, b, c,
5707        );
5708        assert_eq_m512d(r, _mm512_setzero_pd());
5709        let r = _mm512_maskz_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5710            0b00001111, a, b, c,
5711        );
5712        let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5713        assert_eq_m512d(r, e);
5714    }
5715
5716    #[simd_test(enable = "avx512f")]
5717    fn test_mm512_mask3_fmadd_round_pd() {
5718        let a = _mm512_set1_pd(0.000000000000000007);
5719        let b = _mm512_set1_pd(1.);
5720        let c = _mm512_set1_pd(-1.);
5721        let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5722            a, b, c, 0,
5723        );
5724        assert_eq_m512d(r, c);
5725        let r = _mm512_mask3_fmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5726            a, b, c, 0b00001111,
5727        );
5728        let e = _mm512_setr_pd(-1., -1., -1., -1., -1., -1., -1., -1.);
5729        assert_eq_m512d(r, e);
5730    }
5731
5732    #[simd_test(enable = "avx512f")]
5733    fn test_mm512_fmsub_round_pd() {
5734        let a = _mm512_set1_pd(0.000000000000000007);
5735        let b = _mm512_set1_pd(1.);
5736        let c = _mm512_set1_pd(1.);
5737        let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5738        let e = _mm512_set1_pd(-1.);
5739        assert_eq_m512d(r, e);
5740        let r = _mm512_fmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5741        let e = _mm512_set1_pd(-0.9999999999999999);
5742        assert_eq_m512d(r, e);
5743    }
5744
5745    #[simd_test(enable = "avx512f")]
5746    fn test_mm512_mask_fmsub_round_pd() {
5747        let a = _mm512_set1_pd(0.000000000000000007);
5748        let b = _mm512_set1_pd(1.);
5749        let c = _mm512_set1_pd(1.);
5750        let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5751            a, 0, b, c,
5752        );
5753        assert_eq_m512d(r, a);
5754        let r = _mm512_mask_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5755            a, 0b00001111, b, c,
5756        );
5757        let e = _mm512_setr_pd(
5758            -1.,
5759            -1.,
5760            -1.,
5761            -1.,
5762            0.000000000000000007,
5763            0.000000000000000007,
5764            0.000000000000000007,
5765            0.000000000000000007,
5766        );
5767        assert_eq_m512d(r, e);
5768    }
5769
5770    #[simd_test(enable = "avx512f")]
5771    fn test_mm512_maskz_fmsub_round_pd() {
5772        let a = _mm512_set1_pd(0.000000000000000007);
5773        let b = _mm512_set1_pd(1.);
5774        let c = _mm512_set1_pd(1.);
5775        let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5776            0, a, b, c,
5777        );
5778        assert_eq_m512d(r, _mm512_setzero_pd());
5779        let r = _mm512_maskz_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5780            0b00001111, a, b, c,
5781        );
5782        let e = _mm512_setr_pd(-1., -1., -1., -1., 0., 0., 0., 0.);
5783        assert_eq_m512d(r, e);
5784    }
5785
5786    #[simd_test(enable = "avx512f")]
5787    fn test_mm512_mask3_fmsub_round_pd() {
5788        let a = _mm512_set1_pd(0.000000000000000007);
5789        let b = _mm512_set1_pd(1.);
5790        let c = _mm512_set1_pd(1.);
5791        let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5792            a, b, c, 0,
5793        );
5794        assert_eq_m512d(r, c);
5795        let r = _mm512_mask3_fmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5796            a, b, c, 0b00001111,
5797        );
5798        let e = _mm512_setr_pd(-1., -1., -1., -1., 1., 1., 1., 1.);
5799        assert_eq_m512d(r, e);
5800    }
5801
5802    #[simd_test(enable = "avx512f")]
5803    fn test_mm512_fmaddsub_round_pd() {
5804        let a = _mm512_set1_pd(0.000000000000000007);
5805        let b = _mm512_set1_pd(1.);
5806        let c = _mm512_set1_pd(-1.);
5807        let r =
5808            _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5809        let e = _mm512_setr_pd(1., -1., 1., -1., 1., -1., 1., -1.);
5810        assert_eq_m512d(r, e);
5811        let r = _mm512_fmaddsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5812        let e = _mm512_setr_pd(
5813            1.,
5814            -0.9999999999999999,
5815            1.,
5816            -0.9999999999999999,
5817            1.,
5818            -0.9999999999999999,
5819            1.,
5820            -0.9999999999999999,
5821        );
5822        assert_eq_m512d(r, e);
5823    }
5824
5825    #[simd_test(enable = "avx512f")]
5826    fn test_mm512_mask_fmaddsub_round_pd() {
5827        let a = _mm512_set1_pd(0.000000000000000007);
5828        let b = _mm512_set1_pd(1.);
5829        let c = _mm512_set1_pd(-1.);
5830        let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5831            a, 0, b, c,
5832        );
5833        assert_eq_m512d(r, a);
5834        let r = _mm512_mask_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5835            a, 0b00001111, b, c,
5836        );
5837        let e = _mm512_setr_pd(
5838            1.,
5839            -1.,
5840            1.,
5841            -1.,
5842            0.000000000000000007,
5843            0.000000000000000007,
5844            0.000000000000000007,
5845            0.000000000000000007,
5846        );
5847        assert_eq_m512d(r, e);
5848    }
5849
5850    #[simd_test(enable = "avx512f")]
5851    fn test_mm512_maskz_fmaddsub_round_pd() {
5852        let a = _mm512_set1_pd(0.000000000000000007);
5853        let b = _mm512_set1_pd(1.);
5854        let c = _mm512_set1_pd(-1.);
5855        let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5856            0, a, b, c,
5857        );
5858        assert_eq_m512d(r, _mm512_setzero_pd());
5859        let r = _mm512_maskz_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5860            0b00001111, a, b, c,
5861        );
5862        let e = _mm512_setr_pd(1., -1., 1., -1., 0., 0., 0., 0.);
5863        assert_eq_m512d(r, e);
5864    }
5865
5866    #[simd_test(enable = "avx512f")]
5867    fn test_mm512_mask3_fmaddsub_round_pd() {
5868        let a = _mm512_set1_pd(0.000000000000000007);
5869        let b = _mm512_set1_pd(1.);
5870        let c = _mm512_set1_pd(-1.);
5871        let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5872            a, b, c, 0,
5873        );
5874        assert_eq_m512d(r, c);
5875        let r = _mm512_mask3_fmaddsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5876            a, b, c, 0b00001111,
5877        );
5878        let e = _mm512_setr_pd(1., -1., 1., -1., -1., -1., -1., -1.);
5879        assert_eq_m512d(r, e);
5880    }
5881
5882    #[simd_test(enable = "avx512f")]
5883    fn test_mm512_fmsubadd_round_pd() {
5884        let a = _mm512_set1_pd(0.000000000000000007);
5885        let b = _mm512_set1_pd(1.);
5886        let c = _mm512_set1_pd(-1.);
5887        let r =
5888            _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5889        let e = _mm512_setr_pd(-1., 1., -1., 1., -1., 1., -1., 1.);
5890        assert_eq_m512d(r, e);
5891        let r = _mm512_fmsubadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5892        let e = _mm512_setr_pd(
5893            -0.9999999999999999,
5894            1.,
5895            -0.9999999999999999,
5896            1.,
5897            -0.9999999999999999,
5898            1.,
5899            -0.9999999999999999,
5900            1.,
5901        );
5902        assert_eq_m512d(r, e);
5903    }
5904
5905    #[simd_test(enable = "avx512f")]
5906    fn test_mm512_mask_fmsubadd_round_pd() {
5907        let a = _mm512_set1_pd(0.000000000000000007);
5908        let b = _mm512_set1_pd(1.);
5909        let c = _mm512_set1_pd(-1.);
5910        let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5911            a, 0, b, c,
5912        );
5913        assert_eq_m512d(r, a);
5914        let r = _mm512_mask_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5915            a, 0b00001111, b, c,
5916        );
5917        let e = _mm512_setr_pd(
5918            -1.,
5919            1.,
5920            -1.,
5921            1.,
5922            0.000000000000000007,
5923            0.000000000000000007,
5924            0.000000000000000007,
5925            0.000000000000000007,
5926        );
5927        assert_eq_m512d(r, e);
5928    }
5929
5930    #[simd_test(enable = "avx512f")]
5931    fn test_mm512_maskz_fmsubadd_round_pd() {
5932        let a = _mm512_set1_pd(0.000000000000000007);
5933        let b = _mm512_set1_pd(1.);
5934        let c = _mm512_set1_pd(-1.);
5935        let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5936            0, a, b, c,
5937        );
5938        assert_eq_m512d(r, _mm512_setzero_pd());
5939        let r = _mm512_maskz_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5940            0b00001111, a, b, c,
5941        );
5942        let e = _mm512_setr_pd(-1., 1., -1., 1., 0., 0., 0., 0.);
5943        assert_eq_m512d(r, e);
5944    }
5945
5946    #[simd_test(enable = "avx512f")]
5947    fn test_mm512_mask3_fmsubadd_round_pd() {
5948        let a = _mm512_set1_pd(0.000000000000000007);
5949        let b = _mm512_set1_pd(1.);
5950        let c = _mm512_set1_pd(-1.);
5951        let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5952            a, b, c, 0,
5953        );
5954        assert_eq_m512d(r, c);
5955        let r = _mm512_mask3_fmsubadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5956            a, b, c, 0b00001111,
5957        );
5958        let e = _mm512_setr_pd(-1., 1., -1., 1., -1., -1., -1., -1.);
5959        assert_eq_m512d(r, e);
5960    }
5961
5962    #[simd_test(enable = "avx512f")]
5963    fn test_mm512_fnmadd_round_pd() {
5964        let a = _mm512_set1_pd(0.000000000000000007);
5965        let b = _mm512_set1_pd(1.);
5966        let c = _mm512_set1_pd(1.);
5967        let r =
5968            _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
5969        let e = _mm512_set1_pd(1.);
5970        assert_eq_m512d(r, e);
5971        let r = _mm512_fnmadd_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
5972        let e = _mm512_set1_pd(0.9999999999999999);
5973        assert_eq_m512d(r, e);
5974    }
5975
5976    #[simd_test(enable = "avx512f")]
5977    fn test_mm512_mask_fnmadd_round_pd() {
5978        let a = _mm512_set1_pd(0.000000000000000007);
5979        let b = _mm512_set1_pd(1.);
5980        let c = _mm512_set1_pd(1.);
5981        let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5982            a, 0, b, c,
5983        );
5984        assert_eq_m512d(r, a);
5985        let r = _mm512_mask_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
5986            a, 0b00001111, b, c,
5987        );
5988        let e = _mm512_setr_pd(
5989            1.,
5990            1.,
5991            1.,
5992            1.,
5993            0.000000000000000007,
5994            0.000000000000000007,
5995            0.000000000000000007,
5996            0.000000000000000007,
5997        );
5998        assert_eq_m512d(r, e);
5999    }
6000
6001    #[simd_test(enable = "avx512f")]
6002    fn test_mm512_maskz_fnmadd_round_pd() {
6003        let a = _mm512_set1_pd(0.000000000000000007);
6004        let b = _mm512_set1_pd(1.);
6005        let c = _mm512_set1_pd(1.);
6006        let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6007            0, a, b, c,
6008        );
6009        assert_eq_m512d(r, _mm512_setzero_pd());
6010        let r = _mm512_maskz_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6011            0b00001111, a, b, c,
6012        );
6013        let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
6014        assert_eq_m512d(r, e);
6015    }
6016
6017    #[simd_test(enable = "avx512f")]
6018    fn test_mm512_mask3_fnmadd_round_pd() {
6019        let a = _mm512_set1_pd(0.000000000000000007);
6020        let b = _mm512_set1_pd(1.);
6021        let c = _mm512_set1_pd(1.);
6022        let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6023            a, b, c, 0,
6024        );
6025        assert_eq_m512d(r, c);
6026        let r = _mm512_mask3_fnmadd_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6027            a, b, c, 0b00001111,
6028        );
6029        let e = _mm512_setr_pd(1., 1., 1., 1., 1., 1., 1., 1.);
6030        assert_eq_m512d(r, e);
6031    }
6032
6033    #[simd_test(enable = "avx512f")]
6034    fn test_mm512_fnmsub_round_pd() {
6035        let a = _mm512_set1_pd(0.000000000000000007);
6036        let b = _mm512_set1_pd(1.);
6037        let c = _mm512_set1_pd(-1.);
6038        let r =
6039            _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b, c);
6040        let e = _mm512_set1_pd(1.);
6041        assert_eq_m512d(r, e);
6042        let r = _mm512_fnmsub_round_pd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b, c);
6043        let e = _mm512_set1_pd(0.9999999999999999);
6044        assert_eq_m512d(r, e);
6045    }
6046
6047    #[simd_test(enable = "avx512f")]
6048    fn test_mm512_mask_fnmsub_round_pd() {
6049        let a = _mm512_set1_pd(0.000000000000000007);
6050        let b = _mm512_set1_pd(1.);
6051        let c = _mm512_set1_pd(-1.);
6052        let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6053            a, 0, b, c,
6054        );
6055        assert_eq_m512d(r, a);
6056        let r = _mm512_mask_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6057            a, 0b00001111, b, c,
6058        );
6059        let e = _mm512_setr_pd(
6060            1.,
6061            1.,
6062            1.,
6063            1.,
6064            0.000000000000000007,
6065            0.000000000000000007,
6066            0.000000000000000007,
6067            0.000000000000000007,
6068        );
6069        assert_eq_m512d(r, e);
6070    }
6071
6072    #[simd_test(enable = "avx512f")]
6073    fn test_mm512_maskz_fnmsub_round_pd() {
6074        let a = _mm512_set1_pd(0.000000000000000007);
6075        let b = _mm512_set1_pd(1.);
6076        let c = _mm512_set1_pd(-1.);
6077        let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6078            0, a, b, c,
6079        );
6080        assert_eq_m512d(r, _mm512_setzero_pd());
6081        let r = _mm512_maskz_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6082            0b00001111, a, b, c,
6083        );
6084        let e = _mm512_setr_pd(1., 1., 1., 1., 0., 0., 0., 0.);
6085        assert_eq_m512d(r, e);
6086    }
6087
6088    #[simd_test(enable = "avx512f")]
6089    fn test_mm512_mask3_fnmsub_round_pd() {
6090        let a = _mm512_set1_pd(0.000000000000000007);
6091        let b = _mm512_set1_pd(1.);
6092        let c = _mm512_set1_pd(-1.);
6093        let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6094            a, b, c, 0,
6095        );
6096        assert_eq_m512d(r, c);
6097        let r = _mm512_mask3_fnmsub_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6098            a, b, c, 0b00001111,
6099        );
6100        let e = _mm512_setr_pd(1., 1., 1., 1., -1., -1., -1., -1.);
6101        assert_eq_m512d(r, e);
6102    }
6103
6104    #[simd_test(enable = "avx512f")]
6105    fn test_mm512_max_round_pd() {
6106        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6107        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6108        let r = _mm512_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6109        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6110        assert_eq_m512d(r, e);
6111    }
6112
6113    #[simd_test(enable = "avx512f")]
6114    fn test_mm512_mask_max_round_pd() {
6115        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6116        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6117        let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6118        assert_eq_m512d(r, a);
6119        let r = _mm512_mask_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6120        let e = _mm512_setr_pd(7., 6., 5., 4., 4., 5., 6., 7.);
6121        assert_eq_m512d(r, e);
6122    }
6123
6124    #[simd_test(enable = "avx512f")]
6125    fn test_mm512_maskz_max_round_pd() {
6126        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6127        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6128        let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6129        assert_eq_m512d(r, _mm512_setzero_pd());
6130        let r = _mm512_maskz_max_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6131        let e = _mm512_setr_pd(7., 6., 5., 4., 0., 0., 0., 0.);
6132        assert_eq_m512d(r, e);
6133    }
6134
6135    #[simd_test(enable = "avx512f")]
6136    fn test_mm512_min_round_pd() {
6137        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6138        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6139        let r = _mm512_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, b);
6140        let e = _mm512_setr_pd(0., 1., 2., 3., 3., 2., 1., 0.);
6141        assert_eq_m512d(r, e);
6142    }
6143
6144    #[simd_test(enable = "avx512f")]
6145    fn test_mm512_mask_min_round_pd() {
6146        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6147        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6148        let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a, b);
6149        assert_eq_m512d(r, a);
6150        let r = _mm512_mask_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b00001111, a, b);
6151        let e = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6152        assert_eq_m512d(r, e);
6153    }
6154
6155    #[simd_test(enable = "avx512f")]
6156    fn test_mm512_maskz_min_round_pd() {
6157        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
6158        let b = _mm512_setr_pd(7., 6., 5., 4., 3., 2., 1., 0.);
6159        let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a, b);
6160        assert_eq_m512d(r, _mm512_setzero_pd());
6161        let r = _mm512_maskz_min_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a, b);
6162        let e = _mm512_setr_pd(0., 1., 2., 3., 0., 0., 0., 0.);
6163        assert_eq_m512d(r, e);
6164    }
6165
6166    #[simd_test(enable = "avx512f")]
6167    fn test_mm512_getexp_round_pd() {
6168        let a = _mm512_set1_pd(3.);
6169        let r = _mm512_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6170        let e = _mm512_set1_pd(1.);
6171        assert_eq_m512d(r, e);
6172    }
6173
6174    #[simd_test(enable = "avx512f")]
6175    fn test_mm512_mask_getexp_round_pd() {
6176        let a = _mm512_set1_pd(3.);
6177        let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0, a);
6178        assert_eq_m512d(r, a);
6179        let r = _mm512_mask_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(a, 0b11110000, a);
6180        let e = _mm512_setr_pd(3., 3., 3., 3., 1., 1., 1., 1.);
6181        assert_eq_m512d(r, e);
6182    }
6183
6184    #[simd_test(enable = "avx512f")]
6185    fn test_mm512_maskz_getexp_round_pd() {
6186        let a = _mm512_set1_pd(3.);
6187        let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6188        assert_eq_m512d(r, _mm512_setzero_pd());
6189        let r = _mm512_maskz_getexp_round_pd::<_MM_FROUND_CUR_DIRECTION>(0b11110000, a);
6190        let e = _mm512_setr_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6191        assert_eq_m512d(r, e);
6192    }
6193
6194    #[simd_test(enable = "avx512f")]
6195    fn test_mm512_roundscale_round_pd() {
6196        let a = _mm512_set1_pd(1.1);
6197        let r = _mm512_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a);
6198        let e = _mm512_set1_pd(1.0);
6199        assert_eq_m512d(r, e);
6200    }
6201
6202    #[simd_test(enable = "avx512f")]
6203    fn test_mm512_mask_roundscale_round_pd() {
6204        let a = _mm512_set1_pd(1.1);
6205        let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a);
6206        let e = _mm512_set1_pd(1.1);
6207        assert_eq_m512d(r, e);
6208        let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, a);
6209        let e = _mm512_set1_pd(1.0);
6210        assert_eq_m512d(r, e);
6211    }
6212
6213    #[simd_test(enable = "avx512f")]
6214    fn test_mm512_maskz_roundscale_round_pd() {
6215        let a = _mm512_set1_pd(1.1);
6216        let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0, a);
6217        assert_eq_m512d(r, _mm512_setzero_pd());
6218        let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111, a);
6219        let e = _mm512_set1_pd(1.0);
6220        assert_eq_m512d(r, e);
6221    }
6222
6223    #[simd_test(enable = "avx512f")]
6224    fn test_mm512_scalef_round_pd() {
6225        let a = _mm512_set1_pd(1.);
6226        let b = _mm512_set1_pd(3.);
6227        let r = _mm512_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(a, b);
6228        let e = _mm512_set1_pd(8.);
6229        assert_eq_m512d(r, e);
6230    }
6231
6232    #[simd_test(enable = "avx512f")]
6233    fn test_mm512_mask_scalef_round_pd() {
6234        let a = _mm512_set1_pd(1.);
6235        let b = _mm512_set1_pd(3.);
6236        let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6237            a, 0, a, b,
6238        );
6239        assert_eq_m512d(r, a);
6240        let r = _mm512_mask_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6241            a, 0b11110000, a, b,
6242        );
6243        let e = _mm512_set_pd(8., 8., 8., 8., 1., 1., 1., 1.);
6244        assert_eq_m512d(r, e);
6245    }
6246
6247    #[simd_test(enable = "avx512f")]
6248    fn test_mm512_maskz_scalef_round_pd() {
6249        let a = _mm512_set1_pd(1.);
6250        let b = _mm512_set1_pd(3.);
6251        let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6252            0, a, b,
6253        );
6254        assert_eq_m512d(r, _mm512_setzero_pd());
6255        let r = _mm512_maskz_scalef_round_pd::<{ _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC }>(
6256            0b11110000, a, b,
6257        );
6258        let e = _mm512_set_pd(8., 8., 8., 8., 0., 0., 0., 0.);
6259        assert_eq_m512d(r, e);
6260    }
6261
6262    #[simd_test(enable = "avx512f")]
6263    fn test_mm512_fixupimm_round_pd() {
6264        let a = _mm512_set1_pd(f64::NAN);
6265        let b = _mm512_set1_pd(f64::MAX);
6266        let c = _mm512_set1_epi64(i32::MAX as i64);
6267        let r = _mm512_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c);
6268        let e = _mm512_set1_pd(0.0);
6269        assert_eq_m512d(r, e);
6270    }
6271
6272    #[simd_test(enable = "avx512f")]
6273    fn test_mm512_mask_fixupimm_round_pd() {
6274        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6275        let b = _mm512_set1_pd(f64::MAX);
6276        let c = _mm512_set1_epi64(i32::MAX as i64);
6277        let r = _mm512_mask_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11110000, b, c);
6278        let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.);
6279        assert_eq_m512d(r, e);
6280    }
6281
6282    #[simd_test(enable = "avx512f")]
6283    fn test_mm512_maskz_fixupimm_round_pd() {
6284        let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.);
6285        let b = _mm512_set1_pd(f64::MAX);
6286        let c = _mm512_set1_epi64(i32::MAX as i64);
6287        let r = _mm512_maskz_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(0b11110000, a, b, c);
6288        let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.);
6289        assert_eq_m512d(r, e);
6290    }
6291
6292    #[simd_test(enable = "avx512f")]
6293    fn test_mm512_getmant_round_pd() {
6294        let a = _mm512_set1_pd(10.);
6295        let r = _mm512_getmant_round_pd::<
6296            _MM_MANT_NORM_1_2,
6297            _MM_MANT_SIGN_SRC,
6298            _MM_FROUND_CUR_DIRECTION,
6299        >(a);
6300        let e = _mm512_set1_pd(1.25);
6301        assert_eq_m512d(r, e);
6302    }
6303
6304    #[simd_test(enable = "avx512f")]
6305    fn test_mm512_mask_getmant_round_pd() {
6306        let a = _mm512_set1_pd(10.);
6307        let r = _mm512_mask_getmant_round_pd::<
6308            _MM_MANT_NORM_1_2,
6309            _MM_MANT_SIGN_SRC,
6310            _MM_FROUND_CUR_DIRECTION,
6311        >(a, 0, a);
6312        assert_eq_m512d(r, a);
6313        let r = _mm512_mask_getmant_round_pd::<
6314            _MM_MANT_NORM_1_2,
6315            _MM_MANT_SIGN_SRC,
6316            _MM_FROUND_CUR_DIRECTION,
6317        >(a, 0b11110000, a);
6318        let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25);
6319        assert_eq_m512d(r, e);
6320    }
6321
6322    #[simd_test(enable = "avx512f")]
6323    fn test_mm512_maskz_getmant_round_pd() {
6324        let a = _mm512_set1_pd(10.);
6325        let r = _mm512_maskz_getmant_round_pd::<
6326            _MM_MANT_NORM_1_2,
6327            _MM_MANT_SIGN_SRC,
6328            _MM_FROUND_CUR_DIRECTION,
6329        >(0, a);
6330        assert_eq_m512d(r, _mm512_setzero_pd());
6331        let r = _mm512_maskz_getmant_round_pd::<
6332            _MM_MANT_NORM_1_2,
6333            _MM_MANT_SIGN_SRC,
6334            _MM_FROUND_CUR_DIRECTION,
6335        >(0b11110000, a);
6336        let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25);
6337        assert_eq_m512d(r, e);
6338    }
6339
6340    #[simd_test(enable = "avx512f")]
6341    fn test_mm512_cvt_roundps_pd() {
6342        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6343        let r = _mm512_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(a);
6344        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6345        assert_eq_m512d(r, e);
6346    }
6347
6348    #[simd_test(enable = "avx512f")]
6349    fn test_mm512_mask_cvt_roundps_pd() {
6350        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6351        let src = _mm512_set1_pd(0.);
6352        let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6353        assert_eq_m512d(r, src);
6354        let r = _mm512_mask_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6355        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6356        assert_eq_m512d(r, e);
6357    }
6358
6359    #[simd_test(enable = "avx512f")]
6360    fn test_mm512_maskz_cvt_roundps_pd() {
6361        let a = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6362        let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0, a);
6363        assert_eq_m512d(r, _mm512_setzero_pd());
6364        let r = _mm512_maskz_cvt_roundps_pd::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6365        let e = _mm512_setr_pd(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6366        assert_eq_m512d(r, e);
6367    }
6368
6369    #[simd_test(enable = "avx512f")]
6370    fn test_mm512_cvt_roundpd_ps() {
6371        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6372        let r = _mm512_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(a);
6373        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6374        assert_eq_m256(r, e);
6375    }
6376
6377    #[simd_test(enable = "avx512f")]
6378    fn test_mm512_mask_cvt_roundpd_ps() {
6379        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6380        let src = _mm256_set1_ps(0.);
6381        let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6382        assert_eq_m256(r, src);
6383        let r = _mm512_mask_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6384        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6385        assert_eq_m256(r, e);
6386    }
6387
6388    #[simd_test(enable = "avx512f")]
6389    fn test_mm512_maskz_cvt_roundpd_ps() {
6390        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6391        let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0, a);
6392        assert_eq_m256(r, _mm256_setzero_ps());
6393        let r = _mm512_maskz_cvt_roundpd_ps::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6394        let e = _mm256_setr_ps(0., -1.5, 2., -3.5, 0., 0., 0., 0.);
6395        assert_eq_m256(r, e);
6396    }
6397
6398    #[simd_test(enable = "avx512f")]
6399    fn test_mm512_cvt_roundpd_epi32() {
6400        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6401        let r = _mm512_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(a);
6402        let e = _mm256_setr_epi32(0, -2, 2, -4, 4, -6, 6, -8);
6403        assert_eq_m256i(r, e);
6404    }
6405
6406    #[simd_test(enable = "avx512f")]
6407    fn test_mm512_mask_cvt_roundpd_epi32() {
6408        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6409        let src = _mm256_set1_epi32(0);
6410        let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6411        assert_eq_m256i(r, src);
6412        let r = _mm512_mask_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6413        let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6414        assert_eq_m256i(r, e);
6415    }
6416
6417    #[simd_test(enable = "avx512f")]
6418    fn test_mm512_maskz_cvt_roundpd_epi32() {
6419        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6420        let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6421        assert_eq_m256i(r, _mm256_setzero_si256());
6422        let r = _mm512_maskz_cvt_roundpd_epi32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6423        let e = _mm256_setr_epi32(0, -2, 2, -4, 0, 0, 0, 0);
6424        assert_eq_m256i(r, e);
6425    }
6426
6427    #[simd_test(enable = "avx512f")]
6428    fn test_mm512_cvt_roundpd_epu32() {
6429        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6430        let r = _mm512_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(a);
6431        let e = _mm256_setr_epi32(0, -1, 2, -1, 4, -1, 6, -1);
6432        assert_eq_m256i(r, e);
6433    }
6434
6435    #[simd_test(enable = "avx512f")]
6436    fn test_mm512_mask_cvt_roundpd_epu32() {
6437        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6438        let src = _mm256_set1_epi32(0);
6439        let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0, a);
6440        assert_eq_m256i(r, src);
6441        let r = _mm512_mask_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(src, 0b00001111, a);
6442        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6443        assert_eq_m256i(r, e);
6444    }
6445
6446    #[simd_test(enable = "avx512f")]
6447    fn test_mm512_maskz_cvt_roundpd_epu32() {
6448        let a = _mm512_setr_pd(0., -1.5, 2., -3.5, 4., -5.5, 6., -7.5);
6449        let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0, a);
6450        assert_eq_m256i(r, _mm256_setzero_si256());
6451        let r = _mm512_maskz_cvt_roundpd_epu32::<_MM_FROUND_CUR_DIRECTION>(0b00001111, a);
6452        let e = _mm256_setr_epi32(0, -1, 2, -1, 0, 0, 0, 0);
6453        assert_eq_m256i(r, e);
6454    }
6455
6456    #[simd_test(enable = "avx512f")]
6457    const fn test_mm512_setzero_pd() {
6458        assert_eq_m512d(_mm512_setzero_pd(), _mm512_set1_pd(0.));
6459    }
6460
6461    #[simd_test(enable = "avx512f")]
6462    const fn test_mm512_set1_epi64() {
6463        let r = _mm512_set_epi64(2, 2, 2, 2, 2, 2, 2, 2);
6464        assert_eq_m512i(r, _mm512_set1_epi64(2));
6465    }
6466
6467    #[simd_test(enable = "avx512f")]
6468    const fn test_mm512_set1_pd() {
6469        let expected = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
6470        assert_eq_m512d(expected, _mm512_set1_pd(2.));
6471    }
6472
6473    #[simd_test(enable = "avx512f")]
6474    const fn test_mm512_set4_epi64() {
6475        let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6476        assert_eq_m512i(r, _mm512_set4_epi64(4, 3, 2, 1));
6477    }
6478
6479    #[simd_test(enable = "avx512f")]
6480    const fn test_mm512_set4_pd() {
6481        let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6482        assert_eq_m512d(r, _mm512_set4_pd(4., 3., 2., 1.));
6483    }
6484
6485    #[simd_test(enable = "avx512f")]
6486    const fn test_mm512_setr4_epi64() {
6487        let r = _mm512_set_epi64(4, 3, 2, 1, 4, 3, 2, 1);
6488        assert_eq_m512i(r, _mm512_setr4_epi64(1, 2, 3, 4));
6489    }
6490
6491    #[simd_test(enable = "avx512f")]
6492    const fn test_mm512_setr4_pd() {
6493        let r = _mm512_set_pd(4., 3., 2., 1., 4., 3., 2., 1.);
6494        assert_eq_m512d(r, _mm512_setr4_pd(1., 2., 3., 4.));
6495    }
6496
6497    #[simd_test(enable = "avx512f")]
6498    fn test_mm512_cmplt_pd_mask() {
6499        #[rustfmt::skip]
6500        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6501        let b = _mm512_set1_pd(-1.);
6502        let m = _mm512_cmplt_pd_mask(a, b);
6503        assert_eq!(m, 0b00000101);
6504    }
6505
6506    #[simd_test(enable = "avx512f")]
6507    fn test_mm512_mask_cmplt_pd_mask() {
6508        #[rustfmt::skip]
6509        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6510        let b = _mm512_set1_pd(-1.);
6511        let mask = 0b01100110;
6512        let r = _mm512_mask_cmplt_pd_mask(mask, a, b);
6513        assert_eq!(r, 0b00000100);
6514    }
6515
6516    #[simd_test(enable = "avx512f")]
6517    fn test_mm512_cmpnlt_pd_mask() {
6518        #[rustfmt::skip]
6519        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6520        let b = _mm512_set1_pd(-1.);
6521        assert_eq!(_mm512_cmpnlt_pd_mask(a, b), !_mm512_cmplt_pd_mask(a, b));
6522    }
6523
6524    #[simd_test(enable = "avx512f")]
6525    fn test_mm512_mask_cmpnlt_pd_mask() {
6526        #[rustfmt::skip]
6527        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6528        let b = _mm512_set1_pd(-1.);
6529        let mask = 0b01111010;
6530        assert_eq!(_mm512_mask_cmpnlt_pd_mask(mask, a, b), 0b01111010);
6531    }
6532
6533    #[simd_test(enable = "avx512f")]
6534    fn test_mm512_cmple_pd_mask() {
6535        #[rustfmt::skip]
6536        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6537        let b = _mm512_set1_pd(-1.);
6538        assert_eq!(_mm512_cmple_pd_mask(a, b), 0b00100101);
6539    }
6540
6541    #[simd_test(enable = "avx512f")]
6542    fn test_mm512_mask_cmple_pd_mask() {
6543        #[rustfmt::skip]
6544        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6545        let b = _mm512_set1_pd(-1.);
6546        let mask = 0b01111010;
6547        assert_eq!(_mm512_mask_cmple_pd_mask(mask, a, b), 0b00100000);
6548    }
6549
6550    #[simd_test(enable = "avx512f")]
6551    fn test_mm512_cmpnle_pd_mask() {
6552        #[rustfmt::skip]
6553        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6554        let b = _mm512_set1_pd(-1.);
6555        let m = _mm512_cmpnle_pd_mask(b, a);
6556        assert_eq!(m, 0b00001101);
6557    }
6558
6559    #[simd_test(enable = "avx512f")]
6560    fn test_mm512_mask_cmpnle_pd_mask() {
6561        #[rustfmt::skip]
6562        let a = _mm512_set_pd(0., 1., -1., f64::MAX, f64::NAN, f64::MIN, 100., -100.);
6563        let b = _mm512_set1_pd(-1.);
6564        let mask = 0b01100110;
6565        let r = _mm512_mask_cmpnle_pd_mask(mask, b, a);
6566        assert_eq!(r, 0b00000100);
6567    }
6568
6569    #[simd_test(enable = "avx512f")]
6570    fn test_mm512_cmpeq_pd_mask() {
6571        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6572        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6573        let m = _mm512_cmpeq_pd_mask(b, a);
6574        assert_eq!(m, 0b11001101);
6575    }
6576
6577    #[simd_test(enable = "avx512f")]
6578    fn test_mm512_mask_cmpeq_pd_mask() {
6579        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6580        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6581        let mask = 0b01111010;
6582        let r = _mm512_mask_cmpeq_pd_mask(mask, b, a);
6583        assert_eq!(r, 0b01001000);
6584    }
6585
6586    #[simd_test(enable = "avx512f")]
6587    fn test_mm512_cmpneq_pd_mask() {
6588        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6589        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6590        let m = _mm512_cmpneq_pd_mask(b, a);
6591        assert_eq!(m, 0b00110010);
6592    }
6593
6594    #[simd_test(enable = "avx512f")]
6595    fn test_mm512_mask_cmpneq_pd_mask() {
6596        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, f64::NAN, -100.);
6597        let b = _mm512_set_pd(0., 1., 13., 42., f64::MAX, f64::MIN, f64::NAN, -100.);
6598        let mask = 0b01111010;
6599        let r = _mm512_mask_cmpneq_pd_mask(mask, b, a);
6600        assert_eq!(r, 0b00110010)
6601    }
6602
6603    #[simd_test(enable = "avx512f")]
6604    fn test_mm512_cmp_pd_mask() {
6605        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6606        let b = _mm512_set1_pd(-1.);
6607        let m = _mm512_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6608        assert_eq!(m, 0b00000101);
6609    }
6610
6611    #[simd_test(enable = "avx512f")]
6612    fn test_mm512_mask_cmp_pd_mask() {
6613        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6614        let b = _mm512_set1_pd(-1.);
6615        let mask = 0b01100110;
6616        let r = _mm512_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6617        assert_eq!(r, 0b00000100);
6618    }
6619
6620    #[simd_test(enable = "avx512f,avx512vl")]
6621    fn test_mm256_cmp_pd_mask() {
6622        let a = _mm256_set_pd(0., 1., -1., 13.);
6623        let b = _mm256_set1_pd(1.);
6624        let m = _mm256_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6625        assert_eq!(m, 0b00001010);
6626    }
6627
6628    #[simd_test(enable = "avx512f,avx512vl")]
6629    fn test_mm256_mask_cmp_pd_mask() {
6630        let a = _mm256_set_pd(0., 1., -1., 13.);
6631        let b = _mm256_set1_pd(1.);
6632        let mask = 0b11111111;
6633        let r = _mm256_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6634        assert_eq!(r, 0b00001010);
6635    }
6636
6637    #[simd_test(enable = "avx512f,avx512vl")]
6638    fn test_mm_cmp_pd_mask() {
6639        let a = _mm_set_pd(0., 1.);
6640        let b = _mm_set1_pd(1.);
6641        let m = _mm_cmp_pd_mask::<_CMP_LT_OQ>(a, b);
6642        assert_eq!(m, 0b00000010);
6643    }
6644
6645    #[simd_test(enable = "avx512f,avx512vl")]
6646    fn test_mm_mask_cmp_pd_mask() {
6647        let a = _mm_set_pd(0., 1.);
6648        let b = _mm_set1_pd(1.);
6649        let mask = 0b11111111;
6650        let r = _mm_mask_cmp_pd_mask::<_CMP_LT_OQ>(mask, a, b);
6651        assert_eq!(r, 0b00000010);
6652    }
6653
6654    #[simd_test(enable = "avx512f")]
6655    fn test_mm512_cmp_round_pd_mask() {
6656        #[rustfmt::skip]
6657        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6658        let b = _mm512_set1_pd(-1.);
6659        let m = _mm512_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(a, b);
6660        assert_eq!(m, 0b00000101);
6661    }
6662
6663    #[simd_test(enable = "avx512f")]
6664    fn test_mm512_mask_cmp_round_pd_mask() {
6665        #[rustfmt::skip]
6666        let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.);
6667        let b = _mm512_set1_pd(-1.);
6668        let mask = 0b01100110;
6669        let r = _mm512_mask_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(mask, a, b);
6670        assert_eq!(r, 0b00000100);
6671    }
6672
6673    #[simd_test(enable = "avx512f")]
6674    fn test_mm512_cmpord_pd_mask() {
6675        #[rustfmt::skip]
6676        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6677        #[rustfmt::skip]
6678        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6679        let m = _mm512_cmpord_pd_mask(a, b);
6680        assert_eq!(m, 0b00000101);
6681    }
6682
6683    #[simd_test(enable = "avx512f")]
6684    fn test_mm512_mask_cmpord_pd_mask() {
6685        #[rustfmt::skip]
6686        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6687        #[rustfmt::skip]
6688        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6689        let mask = 0b11000011;
6690        let m = _mm512_mask_cmpord_pd_mask(mask, a, b);
6691        assert_eq!(m, 0b00000001);
6692    }
6693
6694    #[simd_test(enable = "avx512f")]
6695    fn test_mm512_cmpunord_pd_mask() {
6696        #[rustfmt::skip]
6697        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6698        #[rustfmt::skip]
6699        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6700        let m = _mm512_cmpunord_pd_mask(a, b);
6701
6702        assert_eq!(m, 0b11111010);
6703    }
6704
6705    #[simd_test(enable = "avx512f")]
6706    fn test_mm512_mask_cmpunord_pd_mask() {
6707        #[rustfmt::skip]
6708        let a = _mm512_set_pd(f64::NAN, f64::MAX, f64::NAN, f64::MIN, f64::NAN, -1., f64::NAN, 0.);
6709        #[rustfmt::skip]
6710        let b = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, f64::MIN, f64::MAX, -1., 0.);
6711        let mask = 0b00001111;
6712        let m = _mm512_mask_cmpunord_pd_mask(mask, a, b);
6713        assert_eq!(m, 0b000001010);
6714    }
6715
6716    #[simd_test(enable = "avx512f")]
6717    const fn test_mm512_cmplt_epu64_mask() {
6718        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6719        let b = _mm512_set1_epi64(-1);
6720        let m = _mm512_cmplt_epu64_mask(a, b);
6721        assert_eq!(m, 0b11001111);
6722    }
6723
6724    #[simd_test(enable = "avx512f")]
6725    const fn test_mm512_mask_cmplt_epu64_mask() {
6726        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6727        let b = _mm512_set1_epi64(-1);
6728        let mask = 0b01111010;
6729        let r = _mm512_mask_cmplt_epu64_mask(mask, a, b);
6730        assert_eq!(r, 0b01001010);
6731    }
6732
6733    #[simd_test(enable = "avx512f,avx512vl")]
6734    const fn test_mm256_cmplt_epu64_mask() {
6735        let a = _mm256_set_epi64x(0, 1, 2, 100);
6736        let b = _mm256_set1_epi64x(2);
6737        let r = _mm256_cmplt_epu64_mask(a, b);
6738        assert_eq!(r, 0b00001100);
6739    }
6740
6741    #[simd_test(enable = "avx512f,avx512vl")]
6742    const fn test_mm256_mask_cmplt_epu64_mask() {
6743        let a = _mm256_set_epi64x(0, 1, 2, 100);
6744        let b = _mm256_set1_epi64x(2);
6745        let mask = 0b11111111;
6746        let r = _mm256_mask_cmplt_epu64_mask(mask, a, b);
6747        assert_eq!(r, 0b00001100);
6748    }
6749
6750    #[simd_test(enable = "avx512f,avx512vl")]
6751    const fn test_mm_cmplt_epu64_mask() {
6752        let a = _mm_set_epi64x(0, 1);
6753        let b = _mm_set1_epi64x(2);
6754        let r = _mm_cmplt_epu64_mask(a, b);
6755        assert_eq!(r, 0b00000011);
6756    }
6757
6758    #[simd_test(enable = "avx512f,avx512vl")]
6759    const fn test_mm_mask_cmplt_epu64_mask() {
6760        let a = _mm_set_epi64x(0, 1);
6761        let b = _mm_set1_epi64x(2);
6762        let mask = 0b11111111;
6763        let r = _mm_mask_cmplt_epu64_mask(mask, a, b);
6764        assert_eq!(r, 0b00000011);
6765    }
6766
6767    #[simd_test(enable = "avx512f")]
6768    const fn test_mm512_cmpgt_epu64_mask() {
6769        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6770        let b = _mm512_set1_epi64(-1);
6771        let m = _mm512_cmpgt_epu64_mask(b, a);
6772        assert_eq!(m, 0b11001111);
6773    }
6774
6775    #[simd_test(enable = "avx512f")]
6776    const fn test_mm512_mask_cmpgt_epu64_mask() {
6777        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6778        let b = _mm512_set1_epi64(-1);
6779        let mask = 0b01111010;
6780        let r = _mm512_mask_cmpgt_epu64_mask(mask, b, a);
6781        assert_eq!(r, 0b01001010);
6782    }
6783
6784    #[simd_test(enable = "avx512f,avx512vl")]
6785    const fn test_mm256_cmpgt_epu64_mask() {
6786        let a = _mm256_set_epi64x(0, 1, 2, 3);
6787        let b = _mm256_set1_epi64x(1);
6788        let r = _mm256_cmpgt_epu64_mask(a, b);
6789        assert_eq!(r, 0b00000011);
6790    }
6791
6792    #[simd_test(enable = "avx512f,avx512vl")]
6793    const fn test_mm256_mask_cmpgt_epu64_mask() {
6794        let a = _mm256_set_epi64x(0, 1, 2, 3);
6795        let b = _mm256_set1_epi64x(1);
6796        let mask = 0b11111111;
6797        let r = _mm256_mask_cmpgt_epu64_mask(mask, a, b);
6798        assert_eq!(r, 0b00000011);
6799    }
6800
6801    #[simd_test(enable = "avx512f,avx512vl")]
6802    const fn test_mm_cmpgt_epu64_mask() {
6803        let a = _mm_set_epi64x(1, 2);
6804        let b = _mm_set1_epi64x(1);
6805        let r = _mm_cmpgt_epu64_mask(a, b);
6806        assert_eq!(r, 0b00000001);
6807    }
6808
6809    #[simd_test(enable = "avx512f,avx512vl")]
6810    const fn test_mm_mask_cmpgt_epu64_mask() {
6811        let a = _mm_set_epi64x(1, 2);
6812        let b = _mm_set1_epi64x(1);
6813        let mask = 0b11111111;
6814        let r = _mm_mask_cmpgt_epu64_mask(mask, a, b);
6815        assert_eq!(r, 0b00000001);
6816    }
6817
6818    #[simd_test(enable = "avx512f")]
6819    const fn test_mm512_cmple_epu64_mask() {
6820        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6821        let b = _mm512_set1_epi64(-1);
6822        assert_eq!(
6823            _mm512_cmple_epu64_mask(a, b),
6824            !_mm512_cmpgt_epu64_mask(a, b)
6825        )
6826    }
6827
6828    #[simd_test(enable = "avx512f")]
6829    const fn test_mm512_mask_cmple_epu64_mask() {
6830        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6831        let b = _mm512_set1_epi64(-1);
6832        let mask = 0b01111010;
6833        assert_eq!(_mm512_mask_cmple_epu64_mask(mask, a, b), 0b01111010);
6834    }
6835
6836    #[simd_test(enable = "avx512f,avx512vl")]
6837    const fn test_mm256_cmple_epu64_mask() {
6838        let a = _mm256_set_epi64x(0, 1, 2, 1);
6839        let b = _mm256_set1_epi64x(1);
6840        let r = _mm256_cmple_epu64_mask(a, b);
6841        assert_eq!(r, 0b00001101)
6842    }
6843
6844    #[simd_test(enable = "avx512f,avx512vl")]
6845    const fn test_mm256_mask_cmple_epu64_mask() {
6846        let a = _mm256_set_epi64x(0, 1, 2, 1);
6847        let b = _mm256_set1_epi64x(1);
6848        let mask = 0b11111111;
6849        let r = _mm256_mask_cmple_epu64_mask(mask, a, b);
6850        assert_eq!(r, 0b00001101)
6851    }
6852
6853    #[simd_test(enable = "avx512f,avx512vl")]
6854    const fn test_mm_cmple_epu64_mask() {
6855        let a = _mm_set_epi64x(0, 1);
6856        let b = _mm_set1_epi64x(1);
6857        let r = _mm_cmple_epu64_mask(a, b);
6858        assert_eq!(r, 0b00000011)
6859    }
6860
6861    #[simd_test(enable = "avx512f,avx512vl")]
6862    const fn test_mm_mask_cmple_epu64_mask() {
6863        let a = _mm_set_epi64x(0, 1);
6864        let b = _mm_set1_epi64x(1);
6865        let mask = 0b11111111;
6866        let r = _mm_mask_cmple_epu64_mask(mask, a, b);
6867        assert_eq!(r, 0b00000011)
6868    }
6869
6870    #[simd_test(enable = "avx512f")]
6871    const fn test_mm512_cmpge_epu64_mask() {
6872        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6873        let b = _mm512_set1_epi64(-1);
6874        assert_eq!(
6875            _mm512_cmpge_epu64_mask(a, b),
6876            !_mm512_cmplt_epu64_mask(a, b)
6877        );
6878    }
6879
6880    #[simd_test(enable = "avx512f")]
6881    const fn test_mm512_mask_cmpge_epu64_mask() {
6882        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6883        let b = _mm512_set1_epi64(-1);
6884        let mask = 0b11111111;
6885        let r = _mm512_mask_cmpge_epu64_mask(mask, a, b);
6886        assert_eq!(r, 0b00110000);
6887    }
6888
6889    #[simd_test(enable = "avx512f,avx512vl")]
6890    const fn test_mm256_cmpge_epu64_mask() {
6891        let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6892        let b = _mm256_set1_epi64x(1);
6893        let r = _mm256_cmpge_epu64_mask(a, b);
6894        assert_eq!(r, 0b00000111);
6895    }
6896
6897    #[simd_test(enable = "avx512f,avx512vl")]
6898    const fn test_mm256_mask_cmpge_epu64_mask() {
6899        let a = _mm256_set_epi64x(0, 1, 2, u64::MAX as i64);
6900        let b = _mm256_set1_epi64x(1);
6901        let mask = 0b11111111;
6902        let r = _mm256_mask_cmpge_epu64_mask(mask, a, b);
6903        assert_eq!(r, 0b00000111);
6904    }
6905
6906    #[simd_test(enable = "avx512f,avx512vl")]
6907    const fn test_mm_cmpge_epu64_mask() {
6908        let a = _mm_set_epi64x(0, 1);
6909        let b = _mm_set1_epi64x(1);
6910        let r = _mm_cmpge_epu64_mask(a, b);
6911        assert_eq!(r, 0b00000001);
6912    }
6913
6914    #[simd_test(enable = "avx512f,avx512vl")]
6915    const fn test_mm_mask_cmpge_epu64_mask() {
6916        let a = _mm_set_epi64x(0, 1);
6917        let b = _mm_set1_epi64x(1);
6918        let mask = 0b11111111;
6919        let r = _mm_mask_cmpge_epu64_mask(mask, a, b);
6920        assert_eq!(r, 0b00000001);
6921    }
6922
6923    #[simd_test(enable = "avx512f")]
6924    const fn test_mm512_cmpeq_epu64_mask() {
6925        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6926        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6927        let m = _mm512_cmpeq_epu64_mask(b, a);
6928        assert_eq!(m, 0b11001111);
6929    }
6930
6931    #[simd_test(enable = "avx512f")]
6932    const fn test_mm512_mask_cmpeq_epu64_mask() {
6933        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6934        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6935        let mask = 0b01111010;
6936        let r = _mm512_mask_cmpeq_epu64_mask(mask, b, a);
6937        assert_eq!(r, 0b01001010);
6938    }
6939
6940    #[simd_test(enable = "avx512f,avx512vl")]
6941    const fn test_mm256_cmpeq_epu64_mask() {
6942        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6943        let b = _mm256_set_epi64x(0, 1, 13, 42);
6944        let m = _mm256_cmpeq_epu64_mask(b, a);
6945        assert_eq!(m, 0b00001100);
6946    }
6947
6948    #[simd_test(enable = "avx512f,avx512vl")]
6949    const fn test_mm256_mask_cmpeq_epu64_mask() {
6950        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6951        let b = _mm256_set_epi64x(0, 1, 13, 42);
6952        let mask = 0b11111111;
6953        let r = _mm256_mask_cmpeq_epu64_mask(mask, b, a);
6954        assert_eq!(r, 0b00001100);
6955    }
6956
6957    #[simd_test(enable = "avx512f,avx512vl")]
6958    const fn test_mm_cmpeq_epu64_mask() {
6959        let a = _mm_set_epi64x(0, 1);
6960        let b = _mm_set_epi64x(0, 1);
6961        let m = _mm_cmpeq_epu64_mask(b, a);
6962        assert_eq!(m, 0b00000011);
6963    }
6964
6965    #[simd_test(enable = "avx512f,avx512vl")]
6966    const fn test_mm_mask_cmpeq_epu64_mask() {
6967        let a = _mm_set_epi64x(0, 1);
6968        let b = _mm_set_epi64x(0, 1);
6969        let mask = 0b11111111;
6970        let r = _mm_mask_cmpeq_epu64_mask(mask, b, a);
6971        assert_eq!(r, 0b00000011);
6972    }
6973
6974    #[simd_test(enable = "avx512f")]
6975    const fn test_mm512_cmpneq_epu64_mask() {
6976        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
6977        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6978        let m = _mm512_cmpneq_epu64_mask(b, a);
6979        assert_eq!(m, !_mm512_cmpeq_epu64_mask(b, a));
6980    }
6981
6982    #[simd_test(enable = "avx512f")]
6983    const fn test_mm512_mask_cmpneq_epu64_mask() {
6984        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, -100, 100);
6985        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
6986        let mask = 0b01111010;
6987        let r = _mm512_mask_cmpneq_epu64_mask(mask, b, a);
6988        assert_eq!(r, 0b00110010);
6989    }
6990
6991    #[simd_test(enable = "avx512f,avx512vl")]
6992    const fn test_mm256_cmpneq_epu64_mask() {
6993        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
6994        let b = _mm256_set_epi64x(0, 1, 13, 42);
6995        let r = _mm256_cmpneq_epu64_mask(b, a);
6996        assert_eq!(r, 0b00000011);
6997    }
6998
6999    #[simd_test(enable = "avx512f,avx512vl")]
7000    const fn test_mm256_mask_cmpneq_epu64_mask() {
7001        let a = _mm256_set_epi64x(0, 1, -1, u64::MAX as i64);
7002        let b = _mm256_set_epi64x(0, 1, 13, 42);
7003        let mask = 0b11111111;
7004        let r = _mm256_mask_cmpneq_epu64_mask(mask, b, a);
7005        assert_eq!(r, 0b00000011);
7006    }
7007
7008    #[simd_test(enable = "avx512f,avx512vl")]
7009    const fn test_mm_cmpneq_epu64_mask() {
7010        let a = _mm_set_epi64x(-1, u64::MAX as i64);
7011        let b = _mm_set_epi64x(13, 42);
7012        let r = _mm_cmpneq_epu64_mask(b, a);
7013        assert_eq!(r, 0b00000011);
7014    }
7015
7016    #[simd_test(enable = "avx512f,avx512vl")]
7017    const fn test_mm_mask_cmpneq_epu64_mask() {
7018        let a = _mm_set_epi64x(-1, u64::MAX as i64);
7019        let b = _mm_set_epi64x(13, 42);
7020        let mask = 0b11111111;
7021        let r = _mm_mask_cmpneq_epu64_mask(mask, b, a);
7022        assert_eq!(r, 0b00000011);
7023    }
7024
7025    #[simd_test(enable = "avx512f")]
7026    const fn test_mm512_cmp_epu64_mask() {
7027        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7028        let b = _mm512_set1_epi64(-1);
7029        let m = _mm512_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7030        assert_eq!(m, 0b11001111);
7031    }
7032
7033    #[simd_test(enable = "avx512f")]
7034    const fn test_mm512_mask_cmp_epu64_mask() {
7035        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7036        let b = _mm512_set1_epi64(-1);
7037        let mask = 0b01111010;
7038        let r = _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7039        assert_eq!(r, 0b01001010);
7040    }
7041
7042    #[simd_test(enable = "avx512f,avx512vl")]
7043    const fn test_mm256_cmp_epu64_mask() {
7044        let a = _mm256_set_epi64x(0, 1, -1, 100);
7045        let b = _mm256_set1_epi64x(1);
7046        let m = _mm256_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7047        assert_eq!(m, 0b00001000);
7048    }
7049
7050    #[simd_test(enable = "avx512f,avx512vl")]
7051    const fn test_mm256_mask_cmp_epu64_mask() {
7052        let a = _mm256_set_epi64x(0, 1, -1, 100);
7053        let b = _mm256_set1_epi64x(1);
7054        let mask = 0b11111111;
7055        let r = _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7056        assert_eq!(r, 0b00001000);
7057    }
7058
7059    #[simd_test(enable = "avx512f,avx512vl")]
7060    const fn test_mm_cmp_epu64_mask() {
7061        let a = _mm_set_epi64x(0, 1);
7062        let b = _mm_set1_epi64x(1);
7063        let m = _mm_cmp_epu64_mask::<_MM_CMPINT_LT>(a, b);
7064        assert_eq!(m, 0b00000010);
7065    }
7066
7067    #[simd_test(enable = "avx512f,avx512vl")]
7068    const fn test_mm_mask_cmp_epu64_mask() {
7069        let a = _mm_set_epi64x(0, 1);
7070        let b = _mm_set1_epi64x(1);
7071        let mask = 0b11111111;
7072        let r = _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(mask, a, b);
7073        assert_eq!(r, 0b00000010);
7074    }
7075
7076    #[simd_test(enable = "avx512f")]
7077    const fn test_mm512_cmplt_epi64_mask() {
7078        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7079        let b = _mm512_set1_epi64(-1);
7080        let m = _mm512_cmplt_epi64_mask(a, b);
7081        assert_eq!(m, 0b00000101);
7082    }
7083
7084    #[simd_test(enable = "avx512f")]
7085    const fn test_mm512_mask_cmplt_epi64_mask() {
7086        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7087        let b = _mm512_set1_epi64(-1);
7088        let mask = 0b01100110;
7089        let r = _mm512_mask_cmplt_epi64_mask(mask, a, b);
7090        assert_eq!(r, 0b00000100);
7091    }
7092
7093    #[simd_test(enable = "avx512f,avx512vl")]
7094    const fn test_mm256_cmplt_epi64_mask() {
7095        let a = _mm256_set_epi64x(0, 1, -1, -13);
7096        let b = _mm256_set1_epi64x(-1);
7097        let r = _mm256_cmplt_epi64_mask(a, b);
7098        assert_eq!(r, 0b00000001);
7099    }
7100
7101    #[simd_test(enable = "avx512f,avx512vl")]
7102    const fn test_mm256_mask_cmplt_epi64_mask() {
7103        let a = _mm256_set_epi64x(0, 1, -1, -13);
7104        let b = _mm256_set1_epi64x(-1);
7105        let mask = 0b11111111;
7106        let r = _mm256_mask_cmplt_epi64_mask(mask, a, b);
7107        assert_eq!(r, 0b00000001);
7108    }
7109
7110    #[simd_test(enable = "avx512f,avx512vl")]
7111    const fn test_mm_cmplt_epi64_mask() {
7112        let a = _mm_set_epi64x(-1, -13);
7113        let b = _mm_set1_epi64x(-1);
7114        let r = _mm_cmplt_epi64_mask(a, b);
7115        assert_eq!(r, 0b00000001);
7116    }
7117
7118    #[simd_test(enable = "avx512f,avx512vl")]
7119    const fn test_mm_mask_cmplt_epi64_mask() {
7120        let a = _mm_set_epi64x(-1, -13);
7121        let b = _mm_set1_epi64x(-1);
7122        let mask = 0b11111111;
7123        let r = _mm_mask_cmplt_epi64_mask(mask, a, b);
7124        assert_eq!(r, 0b00000001);
7125    }
7126
7127    #[simd_test(enable = "avx512f")]
7128    const fn test_mm512_cmpgt_epi64_mask() {
7129        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7130        let b = _mm512_set1_epi64(-1);
7131        let m = _mm512_cmpgt_epi64_mask(b, a);
7132        assert_eq!(m, 0b00000101);
7133    }
7134
7135    #[simd_test(enable = "avx512f")]
7136    const fn test_mm512_mask_cmpgt_epi64_mask() {
7137        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7138        let b = _mm512_set1_epi64(-1);
7139        let mask = 0b01100110;
7140        let r = _mm512_mask_cmpgt_epi64_mask(mask, b, a);
7141        assert_eq!(r, 0b00000100);
7142    }
7143
7144    #[simd_test(enable = "avx512f,avx512vl")]
7145    const fn test_mm256_cmpgt_epi64_mask() {
7146        let a = _mm256_set_epi64x(0, 1, -1, 13);
7147        let b = _mm256_set1_epi64x(-1);
7148        let r = _mm256_cmpgt_epi64_mask(a, b);
7149        assert_eq!(r, 0b00001101);
7150    }
7151
7152    #[simd_test(enable = "avx512f,avx512vl")]
7153    const fn test_mm256_mask_cmpgt_epi64_mask() {
7154        let a = _mm256_set_epi64x(0, 1, -1, 13);
7155        let b = _mm256_set1_epi64x(-1);
7156        let mask = 0b11111111;
7157        let r = _mm256_mask_cmpgt_epi64_mask(mask, a, b);
7158        assert_eq!(r, 0b00001101);
7159    }
7160
7161    #[simd_test(enable = "avx512f,avx512vl")]
7162    const fn test_mm_cmpgt_epi64_mask() {
7163        let a = _mm_set_epi64x(0, -1);
7164        let b = _mm_set1_epi64x(-1);
7165        let r = _mm_cmpgt_epi64_mask(a, b);
7166        assert_eq!(r, 0b00000010);
7167    }
7168
7169    #[simd_test(enable = "avx512f,avx512vl")]
7170    const fn test_mm_mask_cmpgt_epi64_mask() {
7171        let a = _mm_set_epi64x(0, -1);
7172        let b = _mm_set1_epi64x(-1);
7173        let mask = 0b11111111;
7174        let r = _mm_mask_cmpgt_epi64_mask(mask, a, b);
7175        assert_eq!(r, 0b00000010);
7176    }
7177
7178    #[simd_test(enable = "avx512f")]
7179    const fn test_mm512_cmple_epi64_mask() {
7180        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7181        let b = _mm512_set1_epi64(-1);
7182        assert_eq!(
7183            _mm512_cmple_epi64_mask(a, b),
7184            !_mm512_cmpgt_epi64_mask(a, b)
7185        )
7186    }
7187
7188    #[simd_test(enable = "avx512f")]
7189    const fn test_mm512_mask_cmple_epi64_mask() {
7190        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7191        let b = _mm512_set1_epi64(-1);
7192        let mask = 0b01111010;
7193        assert_eq!(_mm512_mask_cmple_epi64_mask(mask, a, b), 0b00110000);
7194    }
7195
7196    #[simd_test(enable = "avx512f,avx512vl")]
7197    const fn test_mm256_cmple_epi64_mask() {
7198        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7199        let b = _mm256_set1_epi64x(-1);
7200        let r = _mm256_cmple_epi64_mask(a, b);
7201        assert_eq!(r, 0b00000010)
7202    }
7203
7204    #[simd_test(enable = "avx512f,avx512vl")]
7205    const fn test_mm256_mask_cmple_epi64_mask() {
7206        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7207        let b = _mm256_set1_epi64x(-1);
7208        let mask = 0b11111111;
7209        let r = _mm256_mask_cmple_epi64_mask(mask, a, b);
7210        assert_eq!(r, 0b00000010)
7211    }
7212
7213    #[simd_test(enable = "avx512f,avx512vl")]
7214    const fn test_mm_cmple_epi64_mask() {
7215        let a = _mm_set_epi64x(0, 1);
7216        let b = _mm_set1_epi64x(1);
7217        let r = _mm_cmple_epi64_mask(a, b);
7218        assert_eq!(r, 0b00000011)
7219    }
7220
7221    #[simd_test(enable = "avx512f,avx512vl")]
7222    const fn test_mm_mask_cmple_epi64_mask() {
7223        let a = _mm_set_epi64x(0, 1);
7224        let b = _mm_set1_epi64x(1);
7225        let mask = 0b11111111;
7226        let r = _mm_mask_cmple_epi64_mask(mask, a, b);
7227        assert_eq!(r, 0b00000011)
7228    }
7229
7230    #[simd_test(enable = "avx512f")]
7231    const fn test_mm512_cmpge_epi64_mask() {
7232        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7233        let b = _mm512_set1_epi64(-1);
7234        assert_eq!(
7235            _mm512_cmpge_epi64_mask(a, b),
7236            !_mm512_cmplt_epi64_mask(a, b)
7237        )
7238    }
7239
7240    #[simd_test(enable = "avx512f")]
7241    const fn test_mm512_mask_cmpge_epi64_mask() {
7242        let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100);
7243        let b = _mm512_set1_epi64(-1);
7244        let mask = 0b11111111;
7245        let r = _mm512_mask_cmpge_epi64_mask(mask, a, b);
7246        assert_eq!(r, 0b11111010);
7247    }
7248
7249    #[simd_test(enable = "avx512f,avx512vl")]
7250    const fn test_mm256_cmpge_epi64_mask() {
7251        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7252        let b = _mm256_set1_epi64x(-1);
7253        let r = _mm256_cmpge_epi64_mask(a, b);
7254        assert_eq!(r, 0b00001111);
7255    }
7256
7257    #[simd_test(enable = "avx512f,avx512vl")]
7258    const fn test_mm256_mask_cmpge_epi64_mask() {
7259        let a = _mm256_set_epi64x(0, 1, -1, i64::MAX);
7260        let b = _mm256_set1_epi64x(-1);
7261        let mask = 0b11111111;
7262        let r = _mm256_mask_cmpge_epi64_mask(mask, a, b);
7263        assert_eq!(r, 0b00001111);
7264    }
7265
7266    #[simd_test(enable = "avx512f,avx512vl")]
7267    const fn test_mm_cmpge_epi64_mask() {
7268        let a = _mm_set_epi64x(0, 1);
7269        let b = _mm_set1_epi64x(-1);
7270        let r = _mm_cmpge_epi64_mask(a, b);
7271        assert_eq!(r, 0b00000011);
7272    }
7273
7274    #[simd_test(enable = "avx512f,avx512vl")]
7275    const fn test_mm_mask_cmpge_epi64_mask() {
7276        let a = _mm_set_epi64x(0, 1);
7277        let b = _mm_set1_epi64x(-1);
7278        let mask = 0b11111111;
7279        let r = _mm_mask_cmpge_epi64_mask(mask, a, b);
7280        assert_eq!(r, 0b00000011);
7281    }
7282
7283    #[simd_test(enable = "avx512f")]
7284    const fn test_mm512_cmpeq_epi64_mask() {
7285        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7286        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7287        let m = _mm512_cmpeq_epi64_mask(b, a);
7288        assert_eq!(m, 0b11001111);
7289    }
7290
7291    #[simd_test(enable = "avx512f")]
7292    const fn test_mm512_mask_cmpeq_epi64_mask() {
7293        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7294        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7295        let mask = 0b01111010;
7296        let r = _mm512_mask_cmpeq_epi64_mask(mask, b, a);
7297        assert_eq!(r, 0b01001010);
7298    }
7299
7300    #[simd_test(enable = "avx512f,avx512vl")]
7301    const fn test_mm256_cmpeq_epi64_mask() {
7302        let a = _mm256_set_epi64x(0, 1, -1, 13);
7303        let b = _mm256_set_epi64x(0, 1, 13, 42);
7304        let m = _mm256_cmpeq_epi64_mask(b, a);
7305        assert_eq!(m, 0b00001100);
7306    }
7307
7308    #[simd_test(enable = "avx512f,avx512vl")]
7309    const fn test_mm256_mask_cmpeq_epi64_mask() {
7310        let a = _mm256_set_epi64x(0, 1, -1, 13);
7311        let b = _mm256_set_epi64x(0, 1, 13, 42);
7312        let mask = 0b11111111;
7313        let r = _mm256_mask_cmpeq_epi64_mask(mask, b, a);
7314        assert_eq!(r, 0b00001100);
7315    }
7316
7317    #[simd_test(enable = "avx512f,avx512vl")]
7318    const fn test_mm_cmpeq_epi64_mask() {
7319        let a = _mm_set_epi64x(0, 1);
7320        let b = _mm_set_epi64x(0, 1);
7321        let m = _mm_cmpeq_epi64_mask(b, a);
7322        assert_eq!(m, 0b00000011);
7323    }
7324
7325    #[simd_test(enable = "avx512f,avx512vl")]
7326    const fn test_mm_mask_cmpeq_epi64_mask() {
7327        let a = _mm_set_epi64x(0, 1);
7328        let b = _mm_set_epi64x(0, 1);
7329        let mask = 0b11111111;
7330        let r = _mm_mask_cmpeq_epi64_mask(mask, b, a);
7331        assert_eq!(r, 0b00000011);
7332    }
7333
7334    #[simd_test(enable = "avx512f")]
7335    const fn test_mm512_set_epi64() {
7336        let r = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7337        assert_eq_m512i(r, _mm512_set_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7338    }
7339
7340    #[simd_test(enable = "avx512f")]
7341    const fn test_mm512_setr_epi64() {
7342        let r = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
7343        assert_eq_m512i(r, _mm512_setr_epi64(7, 6, 5, 4, 3, 2, 1, 0))
7344    }
7345
7346    #[simd_test(enable = "avx512f")]
7347    const fn test_mm512_cmpneq_epi64_mask() {
7348        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7349        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7350        let m = _mm512_cmpneq_epi64_mask(b, a);
7351        assert_eq!(m, !_mm512_cmpeq_epi64_mask(b, a));
7352    }
7353
7354    #[simd_test(enable = "avx512f")]
7355    const fn test_mm512_mask_cmpneq_epi64_mask() {
7356        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, -100, 100);
7357        let b = _mm512_set_epi64(0, 1, 13, 42, i64::MAX, i64::MIN, 100, -100);
7358        let mask = 0b01111010;
7359        let r = _mm512_mask_cmpneq_epi64_mask(mask, b, a);
7360        assert_eq!(r, 0b00110010)
7361    }
7362
7363    #[simd_test(enable = "avx512f,avx512vl")]
7364    const fn test_mm256_cmpneq_epi64_mask() {
7365        let a = _mm256_set_epi64x(0, 1, -1, 13);
7366        let b = _mm256_set_epi64x(0, 1, 13, 42);
7367        let r = _mm256_cmpneq_epi64_mask(b, a);
7368        assert_eq!(r, 0b00000011)
7369    }
7370
7371    #[simd_test(enable = "avx512f,avx512vl")]
7372    const fn test_mm256_mask_cmpneq_epi64_mask() {
7373        let a = _mm256_set_epi64x(0, 1, -1, 13);
7374        let b = _mm256_set_epi64x(0, 1, 13, 42);
7375        let mask = 0b11111111;
7376        let r = _mm256_mask_cmpneq_epi64_mask(mask, b, a);
7377        assert_eq!(r, 0b00000011)
7378    }
7379
7380    #[simd_test(enable = "avx512f,avx512vl")]
7381    const fn test_mm_cmpneq_epi64_mask() {
7382        let a = _mm_set_epi64x(-1, 13);
7383        let b = _mm_set_epi64x(13, 42);
7384        let r = _mm_cmpneq_epi64_mask(b, a);
7385        assert_eq!(r, 0b00000011)
7386    }
7387
7388    #[simd_test(enable = "avx512f,avx512vl")]
7389    const fn test_mm_mask_cmpneq_epi64_mask() {
7390        let a = _mm_set_epi64x(-1, 13);
7391        let b = _mm_set_epi64x(13, 42);
7392        let mask = 0b11111111;
7393        let r = _mm_mask_cmpneq_epi64_mask(mask, b, a);
7394        assert_eq!(r, 0b00000011)
7395    }
7396
7397    #[simd_test(enable = "avx512f")]
7398    const fn test_mm512_cmp_epi64_mask() {
7399        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7400        let b = _mm512_set1_epi64(-1);
7401        let m = _mm512_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7402        assert_eq!(m, 0b00000101);
7403    }
7404
7405    #[simd_test(enable = "avx512f")]
7406    const fn test_mm512_mask_cmp_epi64_mask() {
7407        let a = _mm512_set_epi64(0, 1, -1, 13, i64::MAX, i64::MIN, 100, -100);
7408        let b = _mm512_set1_epi64(-1);
7409        let mask = 0b01100110;
7410        let r = _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7411        assert_eq!(r, 0b00000100);
7412    }
7413
7414    #[simd_test(enable = "avx512f,avx512vl")]
7415    const fn test_mm256_cmp_epi64_mask() {
7416        let a = _mm256_set_epi64x(0, 1, -1, 13);
7417        let b = _mm256_set1_epi64x(1);
7418        let m = _mm256_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7419        assert_eq!(m, 0b00001010);
7420    }
7421
7422    #[simd_test(enable = "avx512f,avx512vl")]
7423    const fn test_mm256_mask_cmp_epi64_mask() {
7424        let a = _mm256_set_epi64x(0, 1, -1, 13);
7425        let b = _mm256_set1_epi64x(1);
7426        let mask = 0b11111111;
7427        let r = _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7428        assert_eq!(r, 0b00001010);
7429    }
7430
7431    #[simd_test(enable = "avx512f,avx512vl")]
7432    const fn test_mm_cmp_epi64_mask() {
7433        let a = _mm_set_epi64x(0, 1);
7434        let b = _mm_set1_epi64x(1);
7435        let m = _mm_cmp_epi64_mask::<_MM_CMPINT_LT>(a, b);
7436        assert_eq!(m, 0b00000010);
7437    }
7438
7439    #[simd_test(enable = "avx512f,avx512vl")]
7440    const fn test_mm_mask_cmp_epi64_mask() {
7441        let a = _mm_set_epi64x(0, 1);
7442        let b = _mm_set1_epi64x(1);
7443        let mask = 0b11111111;
7444        let r = _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(mask, a, b);
7445        assert_eq!(r, 0b00000010);
7446    }
7447
7448    #[simd_test(enable = "avx512f")]
7449    fn test_mm512_i32gather_pd() {
7450        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7451        // A multiplier of 8 is word-addressing
7452        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7453        let r = unsafe { _mm512_i32gather_pd::<8>(index, arr.as_ptr()) };
7454        assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7455    }
7456
7457    #[simd_test(enable = "avx512f")]
7458    fn test_mm512_mask_i32gather_pd() {
7459        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7460        let src = _mm512_set1_pd(2.);
7461        let mask = 0b10101010;
7462        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7463        // A multiplier of 8 is word-addressing
7464        let r = unsafe { _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr()) };
7465        assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7466    }
7467
7468    #[simd_test(enable = "avx512f")]
7469    fn test_mm512_i64gather_pd() {
7470        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7471        // A multiplier of 8 is word-addressing
7472        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7473        let r = unsafe { _mm512_i64gather_pd::<8>(index, arr.as_ptr()) };
7474        assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
7475    }
7476
7477    #[simd_test(enable = "avx512f")]
7478    fn test_mm512_mask_i64gather_pd() {
7479        let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
7480        let src = _mm512_set1_pd(2.);
7481        let mask = 0b10101010;
7482        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7483        // A multiplier of 8 is word-addressing
7484        let r = unsafe { _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr()) };
7485        assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
7486    }
7487
7488    #[simd_test(enable = "avx512f")]
7489    fn test_mm512_i64gather_ps() {
7490        let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7491        // A multiplier of 4 is word-addressing
7492        #[rustfmt::skip]
7493        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7494        let r = unsafe { _mm512_i64gather_ps::<4>(index, arr.as_ptr()) };
7495        assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.));
7496    }
7497
7498    #[simd_test(enable = "avx512f")]
7499    fn test_mm512_mask_i64gather_ps() {
7500        let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
7501        let src = _mm256_set1_ps(2.);
7502        let mask = 0b10101010;
7503        #[rustfmt::skip]
7504        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7505        // A multiplier of 4 is word-addressing
7506        let r = unsafe { _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr()) };
7507        assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.));
7508    }
7509
7510    #[simd_test(enable = "avx512f")]
7511    fn test_mm512_i32gather_epi64() {
7512        let mut arr = [0i64; 128];
7513        for i in 0..128i64 {
7514            arr[i as usize] = i;
7515        }
7516        // A multiplier of 8 is word-addressing
7517        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7518        let r = unsafe { _mm512_i32gather_epi64::<8>(index, arr.as_ptr()) };
7519        assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7520    }
7521
7522    #[simd_test(enable = "avx512f")]
7523    fn test_mm512_mask_i32gather_epi64() {
7524        let mut arr = [0i64; 128];
7525        for i in 0..128i64 {
7526            arr[i as usize] = i;
7527        }
7528        let src = _mm512_set1_epi64(2);
7529        let mask = 0b10101010;
7530        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7531        // A multiplier of 8 is word-addressing
7532        let r = unsafe { _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr()) };
7533        assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7534    }
7535
7536    #[simd_test(enable = "avx512f")]
7537    fn test_mm512_i64gather_epi64() {
7538        let mut arr = [0i64; 128];
7539        for i in 0..128i64 {
7540            arr[i as usize] = i;
7541        }
7542        // A multiplier of 8 is word-addressing
7543        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7544        let r = unsafe { _mm512_i64gather_epi64::<8>(index, arr.as_ptr()) };
7545        assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
7546    }
7547
7548    #[simd_test(enable = "avx512f")]
7549    fn test_mm512_mask_i64gather_epi64() {
7550        let mut arr = [0i64; 128];
7551        for i in 0..128i64 {
7552            arr[i as usize] = i;
7553        }
7554        let src = _mm512_set1_epi64(2);
7555        let mask = 0b10101010;
7556        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7557        // A multiplier of 8 is word-addressing
7558        let r = unsafe { _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr()) };
7559        assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
7560    }
7561
7562    #[simd_test(enable = "avx512f")]
7563    fn test_mm512_i64gather_epi32() {
7564        let mut arr = [0i64; 128];
7565        for i in 0..128i64 {
7566            arr[i as usize] = i;
7567        }
7568        // A multiplier of 8 is word-addressing
7569        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7570        let r = unsafe { _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32) };
7571        assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112));
7572    }
7573
7574    #[simd_test(enable = "avx512f")]
7575    fn test_mm512_mask_i64gather_epi32() {
7576        let mut arr = [0i64; 128];
7577        for i in 0..128i64 {
7578            arr[i as usize] = i;
7579        }
7580        let src = _mm256_set1_epi32(2);
7581        let mask = 0b10101010;
7582        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7583        // A multiplier of 8 is word-addressing
7584        let r = unsafe {
7585            _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32)
7586        };
7587        assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112));
7588    }
7589
7590    #[simd_test(enable = "avx512f")]
7591    fn test_mm512_i32scatter_pd() {
7592        let mut arr = [0f64; 128];
7593        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7594        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7595        // A multiplier of 8 is word-addressing
7596        unsafe {
7597            _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src);
7598        }
7599        let mut expected = [0f64; 128];
7600        for i in 0..8 {
7601            expected[i * 16] = (i + 1) as f64;
7602        }
7603        assert_eq!(&arr[..], &expected[..],);
7604    }
7605
7606    #[simd_test(enable = "avx512f")]
7607    fn test_mm512_mask_i32scatter_pd() {
7608        let mut arr = [0f64; 128];
7609        let mask = 0b10101010;
7610        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7611        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7612        // A multiplier of 8 is word-addressing
7613        unsafe {
7614            _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
7615        }
7616        let mut expected = [0f64; 128];
7617        for i in 0..4 {
7618            expected[i * 32 + 16] = 2. * (i + 1) as f64;
7619        }
7620        assert_eq!(&arr[..], &expected[..],);
7621    }
7622
7623    #[simd_test(enable = "avx512f")]
7624    fn test_mm512_i64scatter_pd() {
7625        let mut arr = [0f64; 128];
7626        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7627        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7628        // A multiplier of 8 is word-addressing
7629        unsafe {
7630            _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src);
7631        }
7632        let mut expected = [0f64; 128];
7633        for i in 0..8 {
7634            expected[i * 16] = (i + 1) as f64;
7635        }
7636        assert_eq!(&arr[..], &expected[..],);
7637    }
7638
7639    #[simd_test(enable = "avx512f")]
7640    fn test_mm512_mask_i64scatter_pd() {
7641        let mut arr = [0f64; 128];
7642        let mask = 0b10101010;
7643        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7644        let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
7645        // A multiplier of 8 is word-addressing
7646        unsafe {
7647            _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
7648        }
7649        let mut expected = [0f64; 128];
7650        for i in 0..4 {
7651            expected[i * 32 + 16] = 2. * (i + 1) as f64;
7652        }
7653        assert_eq!(&arr[..], &expected[..],);
7654    }
7655
7656    #[simd_test(enable = "avx512f")]
7657    fn test_mm512_i64scatter_ps() {
7658        let mut arr = [0f32; 128];
7659        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7660        let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7661        // A multiplier of 4 is word-addressing
7662        unsafe {
7663            _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src);
7664        }
7665        let mut expected = [0f32; 128];
7666        for i in 0..8 {
7667            expected[i * 16] = (i + 1) as f32;
7668        }
7669        assert_eq!(&arr[..], &expected[..],);
7670    }
7671
7672    #[simd_test(enable = "avx512f")]
7673    fn test_mm512_mask_i64scatter_ps() {
7674        let mut arr = [0f32; 128];
7675        let mask = 0b10101010;
7676        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7677        let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
7678        // A multiplier of 4 is word-addressing
7679        unsafe {
7680            _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
7681        }
7682        let mut expected = [0f32; 128];
7683        for i in 0..4 {
7684            expected[i * 32 + 16] = 2. * (i + 1) as f32;
7685        }
7686        assert_eq!(&arr[..], &expected[..],);
7687    }
7688
7689    #[simd_test(enable = "avx512f")]
7690    fn test_mm512_i32scatter_epi64() {
7691        let mut arr = [0i64; 128];
7692        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7693        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7694        // A multiplier of 8 is word-addressing
7695        unsafe {
7696            _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
7697        }
7698        let mut expected = [0i64; 128];
7699        for i in 0..8 {
7700            expected[i * 16] = (i + 1) as i64;
7701        }
7702        assert_eq!(&arr[..], &expected[..],);
7703    }
7704
7705    #[simd_test(enable = "avx512f")]
7706    fn test_mm512_mask_i32scatter_epi64() {
7707        let mut arr = [0i64; 128];
7708        let mask = 0b10101010;
7709        let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
7710        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7711        // A multiplier of 8 is word-addressing
7712        unsafe {
7713            _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
7714        }
7715        let mut expected = [0i64; 128];
7716        for i in 0..4 {
7717            expected[i * 32 + 16] = 2 * (i + 1) as i64;
7718        }
7719        assert_eq!(&arr[..], &expected[..],);
7720    }
7721
7722    #[simd_test(enable = "avx512f")]
7723    fn test_mm512_i64scatter_epi64() {
7724        let mut arr = [0i64; 128];
7725        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7726        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7727        // A multiplier of 8 is word-addressing
7728        unsafe {
7729            _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
7730        }
7731        let mut expected = [0i64; 128];
7732        for i in 0..8 {
7733            expected[i * 16] = (i + 1) as i64;
7734        }
7735        assert_eq!(&arr[..], &expected[..],);
7736    }
7737
7738    #[simd_test(enable = "avx512f")]
7739    fn test_mm512_mask_i64scatter_epi64() {
7740        let mut arr = [0i64; 128];
7741        let mask = 0b10101010;
7742        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7743        let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
7744        // A multiplier of 8 is word-addressing
7745        unsafe {
7746            _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
7747        }
7748        let mut expected = [0i64; 128];
7749        for i in 0..4 {
7750            expected[i * 32 + 16] = 2 * (i + 1) as i64;
7751        }
7752        assert_eq!(&arr[..], &expected[..],);
7753    }
7754
7755    #[simd_test(enable = "avx512f")]
7756    fn test_mm512_i64scatter_epi32() {
7757        let mut arr = [0i32; 128];
7758        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7759        let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7760        // A multiplier of 4 is word-addressing
7761        unsafe {
7762            _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
7763        }
7764        let mut expected = [0i32; 128];
7765        for i in 0..8 {
7766            expected[i * 16] = (i + 1) as i32;
7767        }
7768        assert_eq!(&arr[..], &expected[..],);
7769    }
7770
7771    #[simd_test(enable = "avx512f")]
7772    fn test_mm512_mask_i64scatter_epi32() {
7773        let mut arr = [0i32; 128];
7774        let mask = 0b10101010;
7775        let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
7776        let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
7777        // A multiplier of 4 is word-addressing
7778        unsafe {
7779            _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
7780        }
7781        let mut expected = [0i32; 128];
7782        for i in 0..4 {
7783            expected[i * 32 + 16] = 2 * (i + 1) as i32;
7784        }
7785        assert_eq!(&arr[..], &expected[..],);
7786    }
7787
7788    #[simd_test(enable = "avx512f")]
7789    fn test_mm512_i32logather_epi64() {
7790        let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7791        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7792        let r = unsafe { _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr()) };
7793        let expected = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7794        assert_eq_m512i(expected, r);
7795    }
7796
7797    #[simd_test(enable = "avx512f")]
7798    fn test_mm512_mask_i32logather_epi64() {
7799        let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7800        let src = _mm512_setr_epi64(9, 10, 11, 12, 13, 14, 15, 16);
7801        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7802        let r = unsafe {
7803            _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr())
7804        };
7805        let expected = _mm512_setr_epi64(2, 10, 4, 12, 6, 14, 8, 16);
7806        assert_eq_m512i(expected, r);
7807    }
7808
7809    #[simd_test(enable = "avx512f")]
7810    fn test_mm512_i32logather_pd() {
7811        let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7812        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7813        let r = unsafe { _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr()) };
7814        let expected = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7815        assert_eq_m512d(expected, r);
7816    }
7817
7818    #[simd_test(enable = "avx512f")]
7819    fn test_mm512_mask_i32logather_pd() {
7820        let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7821        let src = _mm512_setr_pd(9., 10., 11., 12., 13., 14., 15., 16.);
7822        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7823        let r =
7824            unsafe { _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr()) };
7825        let expected = _mm512_setr_pd(2., 10., 4., 12., 6., 14., 8., 16.);
7826        assert_eq_m512d(expected, r);
7827    }
7828
7829    #[simd_test(enable = "avx512f")]
7830    fn test_mm512_i32loscatter_epi64() {
7831        let mut base_addr: [i64; 8] = [0; 8];
7832        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7833        let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7834        unsafe {
7835            _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
7836        }
7837        let expected = [1, 2, 3, 4, 5, 6, 7, 8];
7838        assert_eq!(expected, base_addr);
7839    }
7840
7841    #[simd_test(enable = "avx512f")]
7842    fn test_mm512_mask_i32loscatter_epi64() {
7843        let mut base_addr: [i64; 8] = [0; 8];
7844        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7845        let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
7846        unsafe {
7847            _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
7848        }
7849        let expected = [0, 2, 0, 4, 0, 6, 0, 8];
7850        assert_eq!(expected, base_addr);
7851    }
7852
7853    #[simd_test(enable = "avx512f")]
7854    fn test_mm512_i32loscatter_pd() {
7855        let mut base_addr: [f64; 8] = [0.; 8];
7856        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7857        let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7858        unsafe {
7859            _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
7860        }
7861        let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
7862        assert_eq!(expected, base_addr);
7863    }
7864
7865    #[simd_test(enable = "avx512f")]
7866    fn test_mm512_mask_i32loscatter_pd() {
7867        let mut base_addr: [f64; 8] = [0.; 8];
7868        let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
7869        let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
7870        unsafe {
7871            _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
7872        }
7873        let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
7874        assert_eq!(expected, base_addr);
7875    }
7876
7877    #[simd_test(enable = "avx512f,avx512vl")]
7878    fn test_mm_mmask_i32gather_epi32() {
7879        let base_addr: [i32; 4] = [1, 2, 3, 4];
7880        let src = _mm_setr_epi32(5, 6, 7, 8);
7881        let vindex = _mm_setr_epi32(1, 2, 3, 0);
7882        let r = unsafe { _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
7883        let expected = _mm_setr_epi32(2, 6, 4, 8);
7884        assert_eq_m128i(expected, r);
7885    }
7886
7887    #[simd_test(enable = "avx512f,avx512vl")]
7888    fn test_mm_mmask_i32gather_epi64() {
7889        let base_addr: [i64; 2] = [1, 2];
7890        let src = _mm_setr_epi64x(5, 6);
7891        let vindex = _mm_setr_epi32(1, 0, -1, -1);
7892        let r = unsafe { _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
7893        let expected = _mm_setr_epi64x(2, 6);
7894        assert_eq_m128i(expected, r);
7895    }
7896
7897    #[simd_test(enable = "avx512f,avx512vl")]
7898    fn test_mm_mmask_i32gather_pd() {
7899        let base_addr: [f64; 2] = [1., 2.];
7900        let src = _mm_setr_pd(5., 6.);
7901        let vindex = _mm_setr_epi32(1, 0, -1, -1);
7902        let r = unsafe { _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
7903        let expected = _mm_setr_pd(2., 6.);
7904        assert_eq_m128d(expected, r);
7905    }
7906
7907    #[simd_test(enable = "avx512f,avx512vl")]
7908    fn test_mm_mmask_i32gather_ps() {
7909        let base_addr: [f32; 4] = [1., 2., 3., 4.];
7910        let src = _mm_setr_ps(5., 6., 7., 8.);
7911        let vindex = _mm_setr_epi32(1, 2, 3, 0);
7912        let r = unsafe { _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
7913        let expected = _mm_setr_ps(2., 6., 4., 8.);
7914        assert_eq_m128(expected, r);
7915    }
7916
7917    #[simd_test(enable = "avx512f,avx512vl")]
7918    fn test_mm_mmask_i64gather_epi32() {
7919        let base_addr: [i32; 2] = [1, 2];
7920        let src = _mm_setr_epi32(5, 6, 7, 8);
7921        let vindex = _mm_setr_epi64x(1, 0);
7922        let r = unsafe { _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr()) };
7923        let expected = _mm_setr_epi32(2, 6, 0, 0);
7924        assert_eq_m128i(expected, r);
7925    }
7926
7927    #[simd_test(enable = "avx512f,avx512vl")]
7928    fn test_mm_mmask_i64gather_epi64() {
7929        let base_addr: [i64; 2] = [1, 2];
7930        let src = _mm_setr_epi64x(5, 6);
7931        let vindex = _mm_setr_epi64x(1, 0);
7932        let r = unsafe { _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
7933        let expected = _mm_setr_epi64x(2, 6);
7934        assert_eq_m128i(expected, r);
7935    }
7936
7937    #[simd_test(enable = "avx512f,avx512vl")]
7938    fn test_mm_mmask_i64gather_pd() {
7939        let base_addr: [f64; 2] = [1., 2.];
7940        let src = _mm_setr_pd(5., 6.);
7941        let vindex = _mm_setr_epi64x(1, 0);
7942        let r = unsafe { _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
7943        let expected = _mm_setr_pd(2., 6.);
7944        assert_eq_m128d(expected, r);
7945    }
7946
7947    #[simd_test(enable = "avx512f,avx512vl")]
7948    fn test_mm_mmask_i64gather_ps() {
7949        let base_addr: [f32; 2] = [1., 2.];
7950        let src = _mm_setr_ps(5., 6., 7., 8.);
7951        let vindex = _mm_setr_epi64x(1, 0);
7952        let r = unsafe { _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr()) };
7953        let expected = _mm_setr_ps(2., 6., 0., 0.);
7954        assert_eq_m128(expected, r);
7955    }
7956
7957    #[simd_test(enable = "avx512f,avx512vl")]
7958    fn test_mm256_mmask_i32gather_epi32() {
7959        let base_addr: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
7960        let src = _mm256_setr_epi32(9, 10, 11, 12, 13, 14, 15, 16);
7961        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7962        let r = unsafe {
7963            _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr())
7964        };
7965        let expected = _mm256_setr_epi32(2, 10, 4, 12, 6, 14, 8, 16);
7966        assert_eq_m256i(expected, r);
7967    }
7968
7969    #[simd_test(enable = "avx512f,avx512vl")]
7970    fn test_mm256_mmask_i32gather_epi64() {
7971        let base_addr: [i64; 4] = [1, 2, 3, 4];
7972        let src = _mm256_setr_epi64x(9, 10, 11, 12);
7973        let vindex = _mm_setr_epi32(1, 2, 3, 4);
7974        let r =
7975            unsafe { _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
7976        let expected = _mm256_setr_epi64x(2, 10, 4, 12);
7977        assert_eq_m256i(expected, r);
7978    }
7979
7980    #[simd_test(enable = "avx512f,avx512vl")]
7981    fn test_mm256_mmask_i32gather_pd() {
7982        let base_addr: [f64; 4] = [1., 2., 3., 4.];
7983        let src = _mm256_setr_pd(9., 10., 11., 12.);
7984        let vindex = _mm_setr_epi32(1, 2, 3, 4);
7985        let r = unsafe { _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
7986        let expected = _mm256_setr_pd(2., 10., 4., 12.);
7987        assert_eq_m256d(expected, r);
7988    }
7989
7990    #[simd_test(enable = "avx512f,avx512vl")]
7991    fn test_mm256_mmask_i32gather_ps() {
7992        let base_addr: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
7993        let src = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
7994        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
7995        let r =
7996            unsafe { _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr()) };
7997        let expected = _mm256_setr_ps(2., 10., 4., 12., 6., 14., 8., 16.);
7998        assert_eq_m256(expected, r);
7999    }
8000
8001    #[simd_test(enable = "avx512f,avx512vl")]
8002    fn test_mm256_mmask_i64gather_epi32() {
8003        let base_addr: [i32; 4] = [1, 2, 3, 4];
8004        let src = _mm_setr_epi32(9, 10, 11, 12);
8005        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8006        let r =
8007            unsafe { _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
8008        let expected = _mm_setr_epi32(2, 10, 4, 12);
8009        assert_eq_m128i(expected, r);
8010    }
8011
8012    #[simd_test(enable = "avx512f,avx512vl")]
8013    fn test_mm256_mmask_i64gather_epi64() {
8014        let base_addr: [i64; 4] = [1, 2, 3, 4];
8015        let src = _mm256_setr_epi64x(9, 10, 11, 12);
8016        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8017        let r =
8018            unsafe { _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
8019        let expected = _mm256_setr_epi64x(2, 10, 4, 12);
8020        assert_eq_m256i(expected, r);
8021    }
8022
8023    #[simd_test(enable = "avx512f,avx512vl")]
8024    fn test_mm256_mmask_i64gather_pd() {
8025        let base_addr: [f64; 4] = [1., 2., 3., 4.];
8026        let src = _mm256_setr_pd(9., 10., 11., 12.);
8027        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8028        let r = unsafe { _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
8029        let expected = _mm256_setr_pd(2., 10., 4., 12.);
8030        assert_eq_m256d(expected, r);
8031    }
8032
8033    #[simd_test(enable = "avx512f,avx512vl")]
8034    fn test_mm256_mmask_i64gather_ps() {
8035        let base_addr: [f32; 4] = [1., 2., 3., 4.];
8036        let src = _mm_setr_ps(9., 10., 11., 12.);
8037        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8038        let r = unsafe { _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
8039        let expected = _mm_setr_ps(2., 10., 4., 12.);
8040        assert_eq_m128(expected, r);
8041    }
8042
8043    #[simd_test(enable = "avx512f,avx512vl")]
8044    fn test_mm_i32scatter_epi32() {
8045        let mut base_addr: [i32; 4] = [0; 4];
8046        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8047        let src = _mm_setr_epi32(2, 3, 4, 1);
8048        unsafe {
8049            _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8050        }
8051        let expected = [1, 2, 3, 4];
8052        assert_eq!(expected, base_addr);
8053    }
8054
8055    #[simd_test(enable = "avx512f,avx512vl")]
8056    fn test_mm_mask_i32scatter_epi32() {
8057        let mut base_addr: [i32; 4] = [0; 4];
8058        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8059        let src = _mm_setr_epi32(2, 3, 4, 1);
8060        unsafe {
8061            _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8062        }
8063        let expected = [0, 2, 0, 4];
8064        assert_eq!(expected, base_addr);
8065    }
8066
8067    #[simd_test(enable = "avx512f,avx512vl")]
8068    fn test_mm_i32scatter_epi64() {
8069        let mut base_addr: [i64; 2] = [0; 2];
8070        let vindex = _mm_setr_epi32(1, 0, -1, -1);
8071        let src = _mm_setr_epi64x(2, 1);
8072        unsafe {
8073            _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8074        }
8075        let expected = [1, 2];
8076        assert_eq!(expected, base_addr);
8077    }
8078
8079    #[simd_test(enable = "avx512f,avx512vl")]
8080    fn test_mm_mask_i32scatter_epi64() {
8081        let mut base_addr: [i64; 2] = [0; 2];
8082        let vindex = _mm_setr_epi32(1, 0, -1, -1);
8083        let src = _mm_setr_epi64x(2, 1);
8084        unsafe {
8085            _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8086        }
8087        let expected = [0, 2];
8088        assert_eq!(expected, base_addr);
8089    }
8090
8091    #[simd_test(enable = "avx512f,avx512vl")]
8092    fn test_mm_i32scatter_pd() {
8093        let mut base_addr: [f64; 2] = [0.; 2];
8094        let vindex = _mm_setr_epi32(1, 0, -1, -1);
8095        let src = _mm_setr_pd(2., 1.);
8096        unsafe {
8097            _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8098        }
8099        let expected = [1., 2.];
8100        assert_eq!(expected, base_addr);
8101    }
8102
8103    #[simd_test(enable = "avx512f,avx512vl")]
8104    fn test_mm_mask_i32scatter_pd() {
8105        let mut base_addr: [f64; 2] = [0.; 2];
8106        let vindex = _mm_setr_epi32(1, 0, -1, -1);
8107        let src = _mm_setr_pd(2., 1.);
8108        unsafe {
8109            _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8110        }
8111        let expected = [0., 2.];
8112        assert_eq!(expected, base_addr);
8113    }
8114
8115    #[simd_test(enable = "avx512f,avx512vl")]
8116    fn test_mm_i32scatter_ps() {
8117        let mut base_addr: [f32; 4] = [0.; 4];
8118        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8119        let src = _mm_setr_ps(2., 3., 4., 1.);
8120        unsafe {
8121            _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8122        }
8123        let expected = [1., 2., 3., 4.];
8124        assert_eq!(expected, base_addr);
8125    }
8126
8127    #[simd_test(enable = "avx512f,avx512vl")]
8128    fn test_mm_mask_i32scatter_ps() {
8129        let mut base_addr: [f32; 4] = [0.; 4];
8130        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8131        let src = _mm_setr_ps(2., 3., 4., 1.);
8132        unsafe {
8133            _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8134        }
8135        let expected = [0., 2., 0., 4.];
8136        assert_eq!(expected, base_addr);
8137    }
8138
8139    #[simd_test(enable = "avx512f,avx512vl")]
8140    fn test_mm_i64scatter_epi32() {
8141        let mut base_addr: [i32; 2] = [0; 2];
8142        let vindex = _mm_setr_epi64x(1, 0);
8143        let src = _mm_setr_epi32(2, 1, -1, -1);
8144        unsafe {
8145            _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8146        }
8147        let expected = [1, 2];
8148        assert_eq!(expected, base_addr);
8149    }
8150
8151    #[simd_test(enable = "avx512f,avx512vl")]
8152    fn test_mm_mask_i64scatter_epi32() {
8153        let mut base_addr: [i32; 2] = [0; 2];
8154        let vindex = _mm_setr_epi64x(1, 0);
8155        let src = _mm_setr_epi32(2, 1, -1, -1);
8156        unsafe {
8157            _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8158        }
8159        let expected = [0, 2];
8160        assert_eq!(expected, base_addr);
8161    }
8162
8163    #[simd_test(enable = "avx512f,avx512vl")]
8164    fn test_mm_i64scatter_epi64() {
8165        let mut base_addr: [i64; 2] = [0; 2];
8166        let vindex = _mm_setr_epi64x(1, 0);
8167        let src = _mm_setr_epi64x(2, 1);
8168        unsafe {
8169            _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8170        }
8171        let expected = [1, 2];
8172        assert_eq!(expected, base_addr);
8173    }
8174
8175    #[simd_test(enable = "avx512f,avx512vl")]
8176    fn test_mm_mask_i64scatter_epi64() {
8177        let mut base_addr: [i64; 2] = [0; 2];
8178        let vindex = _mm_setr_epi64x(1, 0);
8179        let src = _mm_setr_epi64x(2, 1);
8180        unsafe {
8181            _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8182        }
8183        let expected = [0, 2];
8184        assert_eq!(expected, base_addr);
8185    }
8186
8187    #[simd_test(enable = "avx512f,avx512vl")]
8188    fn test_mm_i64scatter_pd() {
8189        let mut base_addr: [f64; 2] = [0.; 2];
8190        let vindex = _mm_setr_epi64x(1, 0);
8191        let src = _mm_setr_pd(2., 1.);
8192        unsafe {
8193            _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8194        }
8195        let expected = [1., 2.];
8196        assert_eq!(expected, base_addr);
8197    }
8198
8199    #[simd_test(enable = "avx512f,avx512vl")]
8200    fn test_mm_mask_i64scatter_pd() {
8201        let mut base_addr: [f64; 2] = [0.; 2];
8202        let vindex = _mm_setr_epi64x(1, 0);
8203        let src = _mm_setr_pd(2., 1.);
8204        unsafe {
8205            _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8206        }
8207        let expected = [0., 2.];
8208        assert_eq!(expected, base_addr);
8209    }
8210
8211    #[simd_test(enable = "avx512f,avx512vl")]
8212    fn test_mm_i64scatter_ps() {
8213        let mut base_addr: [f32; 2] = [0.; 2];
8214        let vindex = _mm_setr_epi64x(1, 0);
8215        let src = _mm_setr_ps(2., 1., -1., -1.);
8216        unsafe {
8217            _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8218        }
8219        let expected = [1., 2.];
8220        assert_eq!(expected, base_addr);
8221    }
8222
8223    #[simd_test(enable = "avx512f,avx512vl")]
8224    fn test_mm_mask_i64scatter_ps() {
8225        let mut base_addr: [f32; 2] = [0.; 2];
8226        let vindex = _mm_setr_epi64x(1, 0);
8227        let src = _mm_setr_ps(2., 1., -1., -1.);
8228        unsafe {
8229            _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
8230        }
8231        let expected = [0., 2.];
8232        assert_eq!(expected, base_addr);
8233    }
8234
8235    #[simd_test(enable = "avx512f,avx512vl")]
8236    fn test_mm256_i32scatter_epi32() {
8237        let mut base_addr: [i32; 8] = [0; 8];
8238        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8239        let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8240        unsafe {
8241            _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8242        }
8243        let expected = [1, 2, 3, 4, 5, 6, 7, 8];
8244        assert_eq!(expected, base_addr);
8245    }
8246
8247    #[simd_test(enable = "avx512f,avx512vl")]
8248    fn test_mm256_mask_i32scatter_epi32() {
8249        let mut base_addr: [i32; 8] = [0; 8];
8250        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8251        let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
8252        unsafe {
8253            _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
8254        }
8255        let expected = [0, 2, 0, 4, 0, 6, 0, 8];
8256        assert_eq!(expected, base_addr);
8257    }
8258
8259    #[simd_test(enable = "avx512f,avx512vl")]
8260    fn test_mm256_i32scatter_epi64() {
8261        let mut base_addr: [i64; 4] = [0; 4];
8262        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8263        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8264        unsafe {
8265            _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8266        }
8267        let expected = [1, 2, 3, 4];
8268        assert_eq!(expected, base_addr);
8269    }
8270
8271    #[simd_test(enable = "avx512f,avx512vl")]
8272    fn test_mm256_mask_i32scatter_epi64() {
8273        let mut base_addr: [i64; 4] = [0; 4];
8274        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8275        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8276        unsafe {
8277            _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8278        }
8279        let expected = [0, 2, 0, 4];
8280        assert_eq!(expected, base_addr);
8281    }
8282
8283    #[simd_test(enable = "avx512f,avx512vl")]
8284    fn test_mm256_i32scatter_pd() {
8285        let mut base_addr: [f64; 4] = [0.; 4];
8286        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8287        let src = _mm256_setr_pd(2., 3., 4., 1.);
8288        unsafe {
8289            _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8290        }
8291        let expected = [1., 2., 3., 4.];
8292        assert_eq!(expected, base_addr);
8293    }
8294
8295    #[simd_test(enable = "avx512f,avx512vl")]
8296    fn test_mm256_mask_i32scatter_pd() {
8297        let mut base_addr: [f64; 4] = [0.; 4];
8298        let vindex = _mm_setr_epi32(1, 2, 3, 0);
8299        let src = _mm256_setr_pd(2., 3., 4., 1.);
8300        unsafe {
8301            _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8302        }
8303        let expected = [0., 2., 0., 4.];
8304        assert_eq!(expected, base_addr);
8305    }
8306
8307    #[simd_test(enable = "avx512f,avx512vl")]
8308    fn test_mm256_i32scatter_ps() {
8309        let mut base_addr: [f32; 8] = [0.; 8];
8310        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8311        let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8312        unsafe {
8313            _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8314        }
8315        let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
8316        assert_eq!(expected, base_addr);
8317    }
8318
8319    #[simd_test(enable = "avx512f,avx512vl")]
8320    fn test_mm256_mask_i32scatter_ps() {
8321        let mut base_addr: [f32; 8] = [0.; 8];
8322        let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
8323        let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
8324        unsafe {
8325            _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
8326        }
8327        let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
8328        assert_eq!(expected, base_addr);
8329    }
8330
8331    #[simd_test(enable = "avx512f,avx512vl")]
8332    fn test_mm256_i64scatter_epi32() {
8333        let mut base_addr: [i32; 4] = [0; 4];
8334        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8335        let src = _mm_setr_epi32(2, 3, 4, 1);
8336        unsafe {
8337            _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
8338        }
8339        let expected = [1, 2, 3, 4];
8340        assert_eq!(expected, base_addr);
8341    }
8342
8343    #[simd_test(enable = "avx512f,avx512vl")]
8344    fn test_mm256_mask_i64scatter_epi32() {
8345        let mut base_addr: [i32; 4] = [0; 4];
8346        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8347        let src = _mm_setr_epi32(2, 3, 4, 1);
8348        unsafe {
8349            _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8350        }
8351        let expected = [0, 2, 0, 4];
8352        assert_eq!(expected, base_addr);
8353    }
8354
8355    #[simd_test(enable = "avx512f,avx512vl")]
8356    fn test_mm256_i64scatter_epi64() {
8357        let mut base_addr: [i64; 4] = [0; 4];
8358        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8359        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8360        unsafe {
8361            _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
8362        }
8363        let expected = [1, 2, 3, 4];
8364        assert_eq!(expected, base_addr);
8365    }
8366
8367    #[simd_test(enable = "avx512f,avx512vl")]
8368    fn test_mm256_mask_i64scatter_epi64() {
8369        let mut base_addr: [i64; 4] = [0; 4];
8370        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8371        let src = _mm256_setr_epi64x(2, 3, 4, 1);
8372        unsafe {
8373            _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8374        }
8375        let expected = [0, 2, 0, 4];
8376        assert_eq!(expected, base_addr);
8377    }
8378
8379    #[simd_test(enable = "avx512f,avx512vl")]
8380    fn test_mm256_i64scatter_pd() {
8381        let mut base_addr: [f64; 4] = [0.; 4];
8382        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8383        let src = _mm256_setr_pd(2., 3., 4., 1.);
8384        unsafe {
8385            _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
8386        }
8387        let expected = [1., 2., 3., 4.];
8388        assert_eq!(expected, base_addr);
8389    }
8390
8391    #[simd_test(enable = "avx512f,avx512vl")]
8392    fn test_mm256_mask_i64scatter_pd() {
8393        let mut base_addr: [f64; 4] = [0.; 4];
8394        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8395        let src = _mm256_setr_pd(2., 3., 4., 1.);
8396        unsafe {
8397            _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8398        }
8399        let expected = [0., 2., 0., 4.];
8400        assert_eq!(expected, base_addr);
8401    }
8402
8403    #[simd_test(enable = "avx512f,avx512vl")]
8404    fn test_mm256_i64scatter_ps() {
8405        let mut base_addr: [f32; 4] = [0.; 4];
8406        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8407        let src = _mm_setr_ps(2., 3., 4., 1.);
8408        unsafe {
8409            _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
8410        }
8411        let expected = [1., 2., 3., 4.];
8412        assert_eq!(expected, base_addr);
8413    }
8414
8415    #[simd_test(enable = "avx512f,avx512vl")]
8416    fn test_mm256_mask_i64scatter_ps() {
8417        let mut base_addr: [f32; 4] = [0.; 4];
8418        let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
8419        let src = _mm_setr_ps(2., 3., 4., 1.);
8420        unsafe {
8421            _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
8422        }
8423        let expected = [0., 2., 0., 4.];
8424        assert_eq!(expected, base_addr);
8425    }
8426
8427    #[simd_test(enable = "avx512f")]
8428    const fn test_mm512_rol_epi64() {
8429        #[rustfmt::skip]
8430        let a = _mm512_set_epi64(
8431            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8432            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8433        );
8434        let r = _mm512_rol_epi64::<1>(a);
8435        #[rustfmt::skip]
8436        let e = _mm512_set_epi64(
8437            1 << 0, 1 << 33, 1 << 33, 1 << 33,
8438            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8439        );
8440        assert_eq_m512i(r, e);
8441    }
8442
8443    #[simd_test(enable = "avx512f")]
8444    const fn test_mm512_mask_rol_epi64() {
8445        #[rustfmt::skip]
8446        let a = _mm512_set_epi64(
8447            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8448            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8449        );
8450        let r = _mm512_mask_rol_epi64::<1>(a, 0, a);
8451        assert_eq_m512i(r, a);
8452        let r = _mm512_mask_rol_epi64::<1>(a, 0b11111111, a);
8453        #[rustfmt::skip]
8454        let e = _mm512_set_epi64(
8455            1 << 0,  1 << 33, 1 << 33, 1 << 33,
8456            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8457        );
8458        assert_eq_m512i(r, e);
8459    }
8460
8461    #[simd_test(enable = "avx512f")]
8462    const fn test_mm512_maskz_rol_epi64() {
8463        #[rustfmt::skip]
8464        let a = _mm512_set_epi64(
8465            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8466            1 << 32, 1 << 32, 1 << 32, 1 << 63,
8467        );
8468        let r = _mm512_maskz_rol_epi64::<1>(0, a);
8469        assert_eq_m512i(r, _mm512_setzero_si512());
8470        let r = _mm512_maskz_rol_epi64::<1>(0b00001111, a);
8471        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 1 << 0);
8472        assert_eq_m512i(r, e);
8473    }
8474
8475    #[simd_test(enable = "avx512f,avx512vl")]
8476    const fn test_mm256_rol_epi64() {
8477        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8478        let r = _mm256_rol_epi64::<1>(a);
8479        let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8480        assert_eq_m256i(r, e);
8481    }
8482
8483    #[simd_test(enable = "avx512f,avx512vl")]
8484    const fn test_mm256_mask_rol_epi64() {
8485        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8486        let r = _mm256_mask_rol_epi64::<1>(a, 0, a);
8487        assert_eq_m256i(r, a);
8488        let r = _mm256_mask_rol_epi64::<1>(a, 0b00001111, a);
8489        let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8490        assert_eq_m256i(r, e);
8491    }
8492
8493    #[simd_test(enable = "avx512f,avx512vl")]
8494    const fn test_mm256_maskz_rol_epi64() {
8495        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8496        let r = _mm256_maskz_rol_epi64::<1>(0, a);
8497        assert_eq_m256i(r, _mm256_setzero_si256());
8498        let r = _mm256_maskz_rol_epi64::<1>(0b00001111, a);
8499        let e = _mm256_set_epi64x(1 << 0, 1 << 33, 1 << 33, 1 << 33);
8500        assert_eq_m256i(r, e);
8501    }
8502
8503    #[simd_test(enable = "avx512f,avx512vl")]
8504    const fn test_mm_rol_epi64() {
8505        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8506        let r = _mm_rol_epi64::<1>(a);
8507        let e = _mm_set_epi64x(1 << 0, 1 << 33);
8508        assert_eq_m128i(r, e);
8509    }
8510
8511    #[simd_test(enable = "avx512f,avx512vl")]
8512    const fn test_mm_mask_rol_epi64() {
8513        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8514        let r = _mm_mask_rol_epi64::<1>(a, 0, a);
8515        assert_eq_m128i(r, a);
8516        let r = _mm_mask_rol_epi64::<1>(a, 0b00000011, a);
8517        let e = _mm_set_epi64x(1 << 0, 1 << 33);
8518        assert_eq_m128i(r, e);
8519    }
8520
8521    #[simd_test(enable = "avx512f,avx512vl")]
8522    const fn test_mm_maskz_rol_epi64() {
8523        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8524        let r = _mm_maskz_rol_epi64::<1>(0, a);
8525        assert_eq_m128i(r, _mm_setzero_si128());
8526        let r = _mm_maskz_rol_epi64::<1>(0b00000011, a);
8527        let e = _mm_set_epi64x(1 << 0, 1 << 33);
8528        assert_eq_m128i(r, e);
8529    }
8530
8531    #[simd_test(enable = "avx512f")]
8532    const fn test_mm512_ror_epi64() {
8533        #[rustfmt::skip]
8534        let a = _mm512_set_epi64(
8535            1 << 0,  1 << 32, 1 << 32, 1 << 32,
8536            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8537        );
8538        let r = _mm512_ror_epi64::<1>(a);
8539        #[rustfmt::skip]
8540        let e = _mm512_set_epi64(
8541            1 << 63, 1 << 31, 1 << 31, 1 << 31,
8542            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8543        );
8544        assert_eq_m512i(r, e);
8545    }
8546
8547    #[simd_test(enable = "avx512f")]
8548    const fn test_mm512_mask_ror_epi64() {
8549        #[rustfmt::skip]
8550        let a = _mm512_set_epi64(
8551            1 << 0,  1 << 32, 1 << 32, 1 << 32,
8552            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8553        );
8554        let r = _mm512_mask_ror_epi64::<1>(a, 0, a);
8555        assert_eq_m512i(r, a);
8556        let r = _mm512_mask_ror_epi64::<1>(a, 0b11111111, a);
8557        #[rustfmt::skip]
8558        let e = _mm512_set_epi64(
8559            1 << 63, 1 << 31, 1 << 31, 1 << 31,
8560            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8561        );
8562        assert_eq_m512i(r, e);
8563    }
8564
8565    #[simd_test(enable = "avx512f")]
8566    const fn test_mm512_maskz_ror_epi64() {
8567        #[rustfmt::skip]
8568        let a = _mm512_set_epi64(
8569            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8570            1 << 32, 1 << 32, 1 << 32, 1 << 0,
8571        );
8572        let r = _mm512_maskz_ror_epi64::<1>(0, a);
8573        assert_eq_m512i(r, _mm512_setzero_si512());
8574        let r = _mm512_maskz_ror_epi64::<1>(0b00001111, a);
8575        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 1 << 63);
8576        assert_eq_m512i(r, e);
8577    }
8578
8579    #[simd_test(enable = "avx512f,avx512vl")]
8580    const fn test_mm256_ror_epi64() {
8581        let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8582        let r = _mm256_ror_epi64::<1>(a);
8583        let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8584        assert_eq_m256i(r, e);
8585    }
8586
8587    #[simd_test(enable = "avx512f,avx512vl")]
8588    const fn test_mm256_mask_ror_epi64() {
8589        let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8590        let r = _mm256_mask_ror_epi64::<1>(a, 0, a);
8591        assert_eq_m256i(r, a);
8592        let r = _mm256_mask_ror_epi64::<1>(a, 0b00001111, a);
8593        let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8594        assert_eq_m256i(r, e);
8595    }
8596
8597    #[simd_test(enable = "avx512f,avx512vl")]
8598    const fn test_mm256_maskz_ror_epi64() {
8599        let a = _mm256_set_epi64x(1 << 0, 1 << 32, 1 << 32, 1 << 32);
8600        let r = _mm256_maskz_ror_epi64::<1>(0, a);
8601        assert_eq_m256i(r, _mm256_setzero_si256());
8602        let r = _mm256_maskz_ror_epi64::<1>(0b00001111, a);
8603        let e = _mm256_set_epi64x(1 << 63, 1 << 31, 1 << 31, 1 << 31);
8604        assert_eq_m256i(r, e);
8605    }
8606
8607    #[simd_test(enable = "avx512f,avx512vl")]
8608    const fn test_mm_ror_epi64() {
8609        let a = _mm_set_epi64x(1 << 0, 1 << 32);
8610        let r = _mm_ror_epi64::<1>(a);
8611        let e = _mm_set_epi64x(1 << 63, 1 << 31);
8612        assert_eq_m128i(r, e);
8613    }
8614
8615    #[simd_test(enable = "avx512f,avx512vl")]
8616    const fn test_mm_mask_ror_epi64() {
8617        let a = _mm_set_epi64x(1 << 0, 1 << 32);
8618        let r = _mm_mask_ror_epi64::<1>(a, 0, a);
8619        assert_eq_m128i(r, a);
8620        let r = _mm_mask_ror_epi64::<1>(a, 0b00000011, a);
8621        let e = _mm_set_epi64x(1 << 63, 1 << 31);
8622        assert_eq_m128i(r, e);
8623    }
8624
8625    #[simd_test(enable = "avx512f,avx512vl")]
8626    const fn test_mm_maskz_ror_epi64() {
8627        let a = _mm_set_epi64x(1 << 0, 1 << 32);
8628        let r = _mm_maskz_ror_epi64::<1>(0, a);
8629        assert_eq_m128i(r, _mm_setzero_si128());
8630        let r = _mm_maskz_ror_epi64::<1>(0b00000011, a);
8631        let e = _mm_set_epi64x(1 << 63, 1 << 31);
8632        assert_eq_m128i(r, e);
8633    }
8634
8635    #[simd_test(enable = "avx512f")]
8636    const fn test_mm512_slli_epi64() {
8637        #[rustfmt::skip]
8638        let a = _mm512_set_epi64(
8639            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8640            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8641        );
8642        let r = _mm512_slli_epi64::<1>(a);
8643        #[rustfmt::skip]
8644        let e = _mm512_set_epi64(
8645            0, 1 << 33, 1 << 33, 1 << 33,
8646            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8647        );
8648        assert_eq_m512i(r, e);
8649    }
8650
8651    #[simd_test(enable = "avx512f")]
8652    const fn test_mm512_mask_slli_epi64() {
8653        #[rustfmt::skip]
8654        let a = _mm512_set_epi64(
8655            1 << 63, 1 << 32, 1 << 32, 1 << 32,
8656            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8657        );
8658        let r = _mm512_mask_slli_epi64::<1>(a, 0, a);
8659        assert_eq_m512i(r, a);
8660        let r = _mm512_mask_slli_epi64::<1>(a, 0b11111111, a);
8661        #[rustfmt::skip]
8662        let e = _mm512_set_epi64(
8663            0, 1 << 33, 1 << 33, 1 << 33,
8664            1 << 33, 1 << 33, 1 << 33, 1 << 33,
8665        );
8666        assert_eq_m512i(r, e);
8667    }
8668
8669    #[simd_test(enable = "avx512f")]
8670    const fn test_mm512_maskz_slli_epi64() {
8671        #[rustfmt::skip]
8672        let a = _mm512_set_epi64(
8673            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8674            1 << 32, 1 << 32, 1 << 32, 1 << 63,
8675        );
8676        let r = _mm512_maskz_slli_epi64::<1>(0, a);
8677        assert_eq_m512i(r, _mm512_setzero_si512());
8678        let r = _mm512_maskz_slli_epi64::<1>(0b00001111, a);
8679        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
8680        assert_eq_m512i(r, e);
8681    }
8682
8683    #[simd_test(enable = "avx512f,avx512vl")]
8684    const fn test_mm256_mask_slli_epi64() {
8685        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8686        let r = _mm256_mask_slli_epi64::<1>(a, 0, a);
8687        assert_eq_m256i(r, a);
8688        let r = _mm256_mask_slli_epi64::<1>(a, 0b00001111, a);
8689        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8690        assert_eq_m256i(r, e);
8691    }
8692
8693    #[simd_test(enable = "avx512f,avx512vl")]
8694    const fn test_mm256_maskz_slli_epi64() {
8695        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
8696        let r = _mm256_maskz_slli_epi64::<1>(0, a);
8697        assert_eq_m256i(r, _mm256_setzero_si256());
8698        let r = _mm256_maskz_slli_epi64::<1>(0b00001111, a);
8699        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
8700        assert_eq_m256i(r, e);
8701    }
8702
8703    #[simd_test(enable = "avx512f,avx512vl")]
8704    const fn test_mm_mask_slli_epi64() {
8705        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8706        let r = _mm_mask_slli_epi64::<1>(a, 0, a);
8707        assert_eq_m128i(r, a);
8708        let r = _mm_mask_slli_epi64::<1>(a, 0b00000011, a);
8709        let e = _mm_set_epi64x(0, 1 << 33);
8710        assert_eq_m128i(r, e);
8711    }
8712
8713    #[simd_test(enable = "avx512f,avx512vl")]
8714    const fn test_mm_maskz_slli_epi64() {
8715        let a = _mm_set_epi64x(1 << 63, 1 << 32);
8716        let r = _mm_maskz_slli_epi64::<1>(0, a);
8717        assert_eq_m128i(r, _mm_setzero_si128());
8718        let r = _mm_maskz_slli_epi64::<1>(0b00000011, a);
8719        let e = _mm_set_epi64x(0, 1 << 33);
8720        assert_eq_m128i(r, e);
8721    }
8722
8723    #[simd_test(enable = "avx512f")]
8724    const fn test_mm512_srli_epi64() {
8725        #[rustfmt::skip]
8726        let a = _mm512_set_epi64(
8727            1 << 0, 1 << 32, 1 << 32, 1 << 32,
8728            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8729        );
8730        let r = _mm512_srli_epi64::<1>(a);
8731        #[rustfmt::skip]
8732        let e = _mm512_set_epi64(
8733            0, 1 << 31, 1 << 31, 1 << 31,
8734            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8735        );
8736        assert_eq_m512i(r, e);
8737    }
8738
8739    #[simd_test(enable = "avx512f")]
8740    const fn test_mm512_mask_srli_epi64() {
8741        #[rustfmt::skip]
8742        let a = _mm512_set_epi64(
8743            1 << 0, 1 << 32, 1 << 32, 1 << 32,
8744            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8745        );
8746        let r = _mm512_mask_srli_epi64::<1>(a, 0, a);
8747        assert_eq_m512i(r, a);
8748        let r = _mm512_mask_srli_epi64::<1>(a, 0b11111111, a);
8749        #[rustfmt::skip]
8750        let e = _mm512_set_epi64(
8751            0, 1 << 31, 1 << 31, 1 << 31,
8752            1 << 31, 1 << 31, 1 << 31, 1 << 31,
8753        );
8754        assert_eq_m512i(r, e);
8755    }
8756
8757    #[simd_test(enable = "avx512f")]
8758    const fn test_mm512_maskz_srli_epi64() {
8759        #[rustfmt::skip]
8760        let a = _mm512_set_epi64(
8761            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8762            1 << 32, 1 << 32, 1 << 32, 1 << 0,
8763        );
8764        let r = _mm512_maskz_srli_epi64::<1>(0, a);
8765        assert_eq_m512i(r, _mm512_setzero_si512());
8766        let r = _mm512_maskz_srli_epi64::<1>(0b00001111, a);
8767        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
8768        assert_eq_m512i(r, e);
8769    }
8770
8771    #[simd_test(enable = "avx512f,avx512vl")]
8772    const fn test_mm256_mask_srli_epi64() {
8773        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8774        let r = _mm256_mask_srli_epi64::<1>(a, 0, a);
8775        assert_eq_m256i(r, a);
8776        let r = _mm256_mask_srli_epi64::<1>(a, 0b00001111, a);
8777        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8778        assert_eq_m256i(r, e);
8779    }
8780
8781    #[simd_test(enable = "avx512f,avx512vl")]
8782    const fn test_mm256_maskz_srli_epi64() {
8783        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
8784        let r = _mm256_maskz_srli_epi64::<1>(0, a);
8785        assert_eq_m256i(r, _mm256_setzero_si256());
8786        let r = _mm256_maskz_srli_epi64::<1>(0b00001111, a);
8787        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
8788        assert_eq_m256i(r, e);
8789    }
8790
8791    #[simd_test(enable = "avx512f,avx512vl")]
8792    const fn test_mm_mask_srli_epi64() {
8793        let a = _mm_set_epi64x(1 << 5, 0);
8794        let r = _mm_mask_srli_epi64::<1>(a, 0, a);
8795        assert_eq_m128i(r, a);
8796        let r = _mm_mask_srli_epi64::<1>(a, 0b00000011, a);
8797        let e = _mm_set_epi64x(1 << 4, 0);
8798        assert_eq_m128i(r, e);
8799    }
8800
8801    #[simd_test(enable = "avx512f,avx512vl")]
8802    const fn test_mm_maskz_srli_epi64() {
8803        let a = _mm_set_epi64x(1 << 5, 0);
8804        let r = _mm_maskz_srli_epi64::<1>(0, a);
8805        assert_eq_m128i(r, _mm_setzero_si128());
8806        let r = _mm_maskz_srli_epi64::<1>(0b00000011, a);
8807        let e = _mm_set_epi64x(1 << 4, 0);
8808        assert_eq_m128i(r, e);
8809    }
8810
8811    #[simd_test(enable = "avx512f")]
8812    const fn test_mm512_rolv_epi64() {
8813        #[rustfmt::skip]
8814        let a = _mm512_set_epi64(
8815            1 << 32, 1 << 63, 1 << 32, 1 << 32,
8816            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8817        );
8818        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8819        let r = _mm512_rolv_epi64(a, b);
8820        #[rustfmt::skip]
8821        let e = _mm512_set_epi64(
8822            1 << 32, 1 << 0,  1 << 34, 1 << 35,
8823            1 << 36, 1 << 37, 1 << 38, 1 << 39,
8824        );
8825        assert_eq_m512i(r, e);
8826    }
8827
8828    #[simd_test(enable = "avx512f")]
8829    const fn test_mm512_mask_rolv_epi64() {
8830        #[rustfmt::skip]
8831        let a = _mm512_set_epi64(
8832            1 << 32, 1 << 63, 1 << 32, 1 << 32,
8833            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8834        );
8835        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8836        let r = _mm512_mask_rolv_epi64(a, 0, a, b);
8837        assert_eq_m512i(r, a);
8838        let r = _mm512_mask_rolv_epi64(a, 0b11111111, a, b);
8839        #[rustfmt::skip]
8840        let e = _mm512_set_epi64(
8841            1 << 32, 1 << 0,  1 << 34, 1 << 35,
8842            1 << 36, 1 << 37, 1 << 38, 1 << 39,
8843        );
8844        assert_eq_m512i(r, e);
8845    }
8846
8847    #[simd_test(enable = "avx512f")]
8848    const fn test_mm512_maskz_rolv_epi64() {
8849        #[rustfmt::skip]
8850        let a = _mm512_set_epi64(
8851            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8852            1 << 32, 1 << 32, 1 << 32, 1 << 62,
8853        );
8854        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8855        let r = _mm512_maskz_rolv_epi64(0, a, b);
8856        assert_eq_m512i(r, _mm512_setzero_si512());
8857        let r = _mm512_maskz_rolv_epi64(0b00001111, a, b);
8858        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 1 << 0);
8859        assert_eq_m512i(r, e);
8860    }
8861
8862    #[simd_test(enable = "avx512f,avx512vl")]
8863    const fn test_mm256_rolv_epi64() {
8864        let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8865        let b = _mm256_set_epi64x(0, 1, 2, 3);
8866        let r = _mm256_rolv_epi64(a, b);
8867        let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8868        assert_eq_m256i(r, e);
8869    }
8870
8871    #[simd_test(enable = "avx512f,avx512vl")]
8872    const fn test_mm256_mask_rolv_epi64() {
8873        let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8874        let b = _mm256_set_epi64x(0, 1, 2, 3);
8875        let r = _mm256_mask_rolv_epi64(a, 0, a, b);
8876        assert_eq_m256i(r, a);
8877        let r = _mm256_mask_rolv_epi64(a, 0b00001111, a, b);
8878        let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8879        assert_eq_m256i(r, e);
8880    }
8881
8882    #[simd_test(enable = "avx512f,avx512vl")]
8883    const fn test_mm256_maskz_rolv_epi64() {
8884        let a = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 32, 1 << 32);
8885        let b = _mm256_set_epi64x(0, 1, 2, 3);
8886        let r = _mm256_maskz_rolv_epi64(0, a, b);
8887        assert_eq_m256i(r, _mm256_setzero_si256());
8888        let r = _mm256_maskz_rolv_epi64(0b00001111, a, b);
8889        let e = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 34, 1 << 35);
8890        assert_eq_m256i(r, e);
8891    }
8892
8893    #[simd_test(enable = "avx512f,avx512vl")]
8894    const fn test_mm_rolv_epi64() {
8895        let a = _mm_set_epi64x(1 << 32, 1 << 63);
8896        let b = _mm_set_epi64x(0, 1);
8897        let r = _mm_rolv_epi64(a, b);
8898        let e = _mm_set_epi64x(1 << 32, 1 << 0);
8899        assert_eq_m128i(r, e);
8900    }
8901
8902    #[simd_test(enable = "avx512f,avx512vl")]
8903    const fn test_mm_mask_rolv_epi64() {
8904        let a = _mm_set_epi64x(1 << 32, 1 << 63);
8905        let b = _mm_set_epi64x(0, 1);
8906        let r = _mm_mask_rolv_epi64(a, 0, a, b);
8907        assert_eq_m128i(r, a);
8908        let r = _mm_mask_rolv_epi64(a, 0b00000011, a, b);
8909        let e = _mm_set_epi64x(1 << 32, 1 << 0);
8910        assert_eq_m128i(r, e);
8911    }
8912
8913    #[simd_test(enable = "avx512f,avx512vl")]
8914    const fn test_mm_maskz_rolv_epi64() {
8915        let a = _mm_set_epi64x(1 << 32, 1 << 63);
8916        let b = _mm_set_epi64x(0, 1);
8917        let r = _mm_maskz_rolv_epi64(0, a, b);
8918        assert_eq_m128i(r, _mm_setzero_si128());
8919        let r = _mm_maskz_rolv_epi64(0b00000011, a, b);
8920        let e = _mm_set_epi64x(1 << 32, 1 << 0);
8921        assert_eq_m128i(r, e);
8922    }
8923
8924    #[simd_test(enable = "avx512f")]
8925    const fn test_mm512_rorv_epi64() {
8926        #[rustfmt::skip]
8927        let a = _mm512_set_epi64(
8928            1 << 32, 1 << 0, 1 << 32, 1 << 32,
8929            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8930        );
8931        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8932        let r = _mm512_rorv_epi64(a, b);
8933        #[rustfmt::skip]
8934        let e = _mm512_set_epi64(
8935            1 << 32, 1 << 63, 1 << 30, 1 << 29,
8936            1 << 28, 1 << 27, 1 << 26, 1 << 25,
8937        );
8938        assert_eq_m512i(r, e);
8939    }
8940
8941    #[simd_test(enable = "avx512f")]
8942    const fn test_mm512_mask_rorv_epi64() {
8943        #[rustfmt::skip]
8944        let a = _mm512_set_epi64(
8945            1 << 32, 1 << 0, 1 << 32, 1 << 32,
8946            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8947        );
8948        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
8949        let r = _mm512_mask_rorv_epi64(a, 0, a, b);
8950        assert_eq_m512i(r, a);
8951        let r = _mm512_mask_rorv_epi64(a, 0b11111111, a, b);
8952        #[rustfmt::skip]
8953        let e = _mm512_set_epi64(
8954            1 << 32, 1 << 63, 1 << 30, 1 << 29,
8955            1 << 28, 1 << 27, 1 << 26, 1 << 25,
8956        );
8957        assert_eq_m512i(r, e);
8958    }
8959
8960    #[simd_test(enable = "avx512f")]
8961    const fn test_mm512_maskz_rorv_epi64() {
8962        #[rustfmt::skip]
8963        let a = _mm512_set_epi64(
8964            1 << 32, 1 << 32, 1 << 32, 1 << 32,
8965            1 << 32, 1 << 32, 1 << 32, 1 << 0,
8966        );
8967        let b = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 2);
8968        let r = _mm512_maskz_rorv_epi64(0, a, b);
8969        assert_eq_m512i(r, _mm512_setzero_si512());
8970        let r = _mm512_maskz_rorv_epi64(0b00001111, a, b);
8971        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 1 << 62);
8972        assert_eq_m512i(r, e);
8973    }
8974
8975    #[simd_test(enable = "avx512f,avx512vl")]
8976    const fn test_mm256_rorv_epi64() {
8977        let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8978        let b = _mm256_set_epi64x(0, 1, 2, 3);
8979        let r = _mm256_rorv_epi64(a, b);
8980        let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8981        assert_eq_m256i(r, e);
8982    }
8983
8984    #[simd_test(enable = "avx512f,avx512vl")]
8985    const fn test_mm256_mask_rorv_epi64() {
8986        let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8987        let b = _mm256_set_epi64x(0, 1, 2, 3);
8988        let r = _mm256_mask_rorv_epi64(a, 0, a, b);
8989        assert_eq_m256i(r, a);
8990        let r = _mm256_mask_rorv_epi64(a, 0b00001111, a, b);
8991        let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
8992        assert_eq_m256i(r, e);
8993    }
8994
8995    #[simd_test(enable = "avx512f,avx512vl")]
8996    const fn test_mm256_maskz_rorv_epi64() {
8997        let a = _mm256_set_epi64x(1 << 32, 1 << 0, 1 << 32, 1 << 32);
8998        let b = _mm256_set_epi64x(0, 1, 2, 3);
8999        let r = _mm256_maskz_rorv_epi64(0, a, b);
9000        assert_eq_m256i(r, _mm256_setzero_si256());
9001        let r = _mm256_maskz_rorv_epi64(0b00001111, a, b);
9002        let e = _mm256_set_epi64x(1 << 32, 1 << 63, 1 << 30, 1 << 29);
9003        assert_eq_m256i(r, e);
9004    }
9005
9006    #[simd_test(enable = "avx512f,avx512vl")]
9007    const fn test_mm_rorv_epi64() {
9008        let a = _mm_set_epi64x(1 << 32, 1 << 0);
9009        let b = _mm_set_epi64x(0, 1);
9010        let r = _mm_rorv_epi64(a, b);
9011        let e = _mm_set_epi64x(1 << 32, 1 << 63);
9012        assert_eq_m128i(r, e);
9013    }
9014
9015    #[simd_test(enable = "avx512f,avx512vl")]
9016    const fn test_mm_mask_rorv_epi64() {
9017        let a = _mm_set_epi64x(1 << 32, 1 << 0);
9018        let b = _mm_set_epi64x(0, 1);
9019        let r = _mm_mask_rorv_epi64(a, 0, a, b);
9020        assert_eq_m128i(r, a);
9021        let r = _mm_mask_rorv_epi64(a, 0b00000011, a, b);
9022        let e = _mm_set_epi64x(1 << 32, 1 << 63);
9023        assert_eq_m128i(r, e);
9024    }
9025
9026    #[simd_test(enable = "avx512f,avx512vl")]
9027    const fn test_mm_maskz_rorv_epi64() {
9028        let a = _mm_set_epi64x(1 << 32, 1 << 0);
9029        let b = _mm_set_epi64x(0, 1);
9030        let r = _mm_maskz_rorv_epi64(0, a, b);
9031        assert_eq_m128i(r, _mm_setzero_si128());
9032        let r = _mm_maskz_rorv_epi64(0b00000011, a, b);
9033        let e = _mm_set_epi64x(1 << 32, 1 << 63);
9034        assert_eq_m128i(r, e);
9035    }
9036
9037    #[simd_test(enable = "avx512f")]
9038    const fn test_mm512_sllv_epi64() {
9039        #[rustfmt::skip]
9040        let a = _mm512_set_epi64(
9041            1 << 32, 1 << 63, 1 << 32, 1 << 32,
9042            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9043        );
9044        let count = _mm512_set_epi64(0, 2, 2, 3, 4, 5, 6, 7);
9045        let r = _mm512_sllv_epi64(a, count);
9046        #[rustfmt::skip]
9047        let e = _mm512_set_epi64(
9048            1 << 32, 0, 1 << 34, 1 << 35,
9049            1 << 36, 1 << 37, 1 << 38, 1 << 39,
9050        );
9051        assert_eq_m512i(r, e);
9052    }
9053
9054    #[simd_test(enable = "avx512f")]
9055    const fn test_mm512_mask_sllv_epi64() {
9056        #[rustfmt::skip]
9057        let a = _mm512_set_epi64(
9058            1 << 32, 1 << 32, 1 << 63, 1 << 32,
9059            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9060        );
9061        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9062        let r = _mm512_mask_sllv_epi64(a, 0, a, count);
9063        assert_eq_m512i(r, a);
9064        let r = _mm512_mask_sllv_epi64(a, 0b11111111, a, count);
9065        #[rustfmt::skip]
9066        let e = _mm512_set_epi64(
9067            1 << 32, 1 << 33, 0, 1 << 35,
9068            1 << 36, 1 << 37, 1 << 38, 1 << 39,
9069        );
9070        assert_eq_m512i(r, e);
9071    }
9072
9073    #[simd_test(enable = "avx512f")]
9074    const fn test_mm512_maskz_sllv_epi64() {
9075        #[rustfmt::skip]
9076        let a = _mm512_set_epi64(
9077            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9078            1 << 32, 1 << 32, 1 << 32, 1 << 63,
9079        );
9080        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 1);
9081        let r = _mm512_maskz_sllv_epi64(0, a, count);
9082        assert_eq_m512i(r, _mm512_setzero_si512());
9083        let r = _mm512_maskz_sllv_epi64(0b00001111, a, count);
9084        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 36, 1 << 37, 1 << 38, 0);
9085        assert_eq_m512i(r, e);
9086    }
9087
9088    #[simd_test(enable = "avx512f,avx512vl")]
9089    const fn test_mm256_mask_sllv_epi64() {
9090        let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
9091        let count = _mm256_set_epi64x(0, 1, 2, 3);
9092        let r = _mm256_mask_sllv_epi64(a, 0, a, count);
9093        assert_eq_m256i(r, a);
9094        let r = _mm256_mask_sllv_epi64(a, 0b00001111, a, count);
9095        let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
9096        assert_eq_m256i(r, e);
9097    }
9098
9099    #[simd_test(enable = "avx512f,avx512vl")]
9100    const fn test_mm256_maskz_sllv_epi64() {
9101        let a = _mm256_set_epi64x(1 << 32, 1 << 32, 1 << 63, 1 << 32);
9102        let count = _mm256_set_epi64x(0, 1, 2, 3);
9103        let r = _mm256_maskz_sllv_epi64(0, a, count);
9104        assert_eq_m256i(r, _mm256_setzero_si256());
9105        let r = _mm256_maskz_sllv_epi64(0b00001111, a, count);
9106        let e = _mm256_set_epi64x(1 << 32, 1 << 33, 0, 1 << 35);
9107        assert_eq_m256i(r, e);
9108    }
9109
9110    #[simd_test(enable = "avx512f,avx512vl")]
9111    const fn test_mm_mask_sllv_epi64() {
9112        let a = _mm_set_epi64x(1 << 63, 1 << 32);
9113        let count = _mm_set_epi64x(2, 3);
9114        let r = _mm_mask_sllv_epi64(a, 0, a, count);
9115        assert_eq_m128i(r, a);
9116        let r = _mm_mask_sllv_epi64(a, 0b00000011, a, count);
9117        let e = _mm_set_epi64x(0, 1 << 35);
9118        assert_eq_m128i(r, e);
9119    }
9120
9121    #[simd_test(enable = "avx512f,avx512vl")]
9122    const fn test_mm_maskz_sllv_epi64() {
9123        let a = _mm_set_epi64x(1 << 63, 1 << 32);
9124        let count = _mm_set_epi64x(2, 3);
9125        let r = _mm_maskz_sllv_epi64(0, a, count);
9126        assert_eq_m128i(r, _mm_setzero_si128());
9127        let r = _mm_maskz_sllv_epi64(0b00000011, a, count);
9128        let e = _mm_set_epi64x(0, 1 << 35);
9129        assert_eq_m128i(r, e);
9130    }
9131
9132    #[simd_test(enable = "avx512f")]
9133    const fn test_mm512_srlv_epi64() {
9134        #[rustfmt::skip]
9135        let a = _mm512_set_epi64(
9136            1 << 32, 1 << 0, 1 << 32, 1 << 32,
9137            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9138        );
9139        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9140        let r = _mm512_srlv_epi64(a, count);
9141        #[rustfmt::skip]
9142        let e = _mm512_set_epi64(
9143            1 << 32, 0, 1 << 30, 1 << 29,
9144            1 << 28, 1 << 27, 1 << 26, 1 << 25,
9145        );
9146        assert_eq_m512i(r, e);
9147    }
9148
9149    #[simd_test(enable = "avx512f")]
9150    const fn test_mm512_mask_srlv_epi64() {
9151        #[rustfmt::skip]
9152        let a = _mm512_set_epi64(
9153            1 << 32, 1 << 0, 1 << 32, 1 << 32,
9154            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9155        );
9156        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9157        let r = _mm512_mask_srlv_epi64(a, 0, a, count);
9158        assert_eq_m512i(r, a);
9159        let r = _mm512_mask_srlv_epi64(a, 0b11111111, a, count);
9160        #[rustfmt::skip]
9161        let e = _mm512_set_epi64(
9162            1 << 32, 0, 1 << 30, 1 << 29,
9163            1 << 28, 1 << 27, 1 << 26, 1 << 25,
9164        );
9165        assert_eq_m512i(r, e);
9166    }
9167
9168    #[simd_test(enable = "avx512f")]
9169    const fn test_mm512_maskz_srlv_epi64() {
9170        #[rustfmt::skip]
9171        let a = _mm512_set_epi64(
9172            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9173            1 << 32, 1 << 32, 1 << 32, 1 << 0,
9174        );
9175        let count = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9176        let r = _mm512_maskz_srlv_epi64(0, a, count);
9177        assert_eq_m512i(r, _mm512_setzero_si512());
9178        let r = _mm512_maskz_srlv_epi64(0b00001111, a, count);
9179        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 28, 1 << 27, 1 << 26, 0);
9180        assert_eq_m512i(r, e);
9181    }
9182
9183    #[simd_test(enable = "avx512f,avx512vl")]
9184    const fn test_mm256_mask_srlv_epi64() {
9185        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9186        let count = _mm256_set1_epi64x(1);
9187        let r = _mm256_mask_srlv_epi64(a, 0, a, count);
9188        assert_eq_m256i(r, a);
9189        let r = _mm256_mask_srlv_epi64(a, 0b00001111, a, count);
9190        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9191        assert_eq_m256i(r, e);
9192    }
9193
9194    #[simd_test(enable = "avx512f,avx512vl")]
9195    const fn test_mm256_maskz_srlv_epi64() {
9196        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9197        let count = _mm256_set1_epi64x(1);
9198        let r = _mm256_maskz_srlv_epi64(0, a, count);
9199        assert_eq_m256i(r, _mm256_setzero_si256());
9200        let r = _mm256_maskz_srlv_epi64(0b00001111, a, count);
9201        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9202        assert_eq_m256i(r, e);
9203    }
9204
9205    #[simd_test(enable = "avx512f,avx512vl")]
9206    const fn test_mm_mask_srlv_epi64() {
9207        let a = _mm_set_epi64x(1 << 5, 0);
9208        let count = _mm_set1_epi64x(1);
9209        let r = _mm_mask_srlv_epi64(a, 0, a, count);
9210        assert_eq_m128i(r, a);
9211        let r = _mm_mask_srlv_epi64(a, 0b00000011, a, count);
9212        let e = _mm_set_epi64x(1 << 4, 0);
9213        assert_eq_m128i(r, e);
9214    }
9215
9216    #[simd_test(enable = "avx512f,avx512vl")]
9217    const fn test_mm_maskz_srlv_epi64() {
9218        let a = _mm_set_epi64x(1 << 5, 0);
9219        let count = _mm_set1_epi64x(1);
9220        let r = _mm_maskz_srlv_epi64(0, a, count);
9221        assert_eq_m128i(r, _mm_setzero_si128());
9222        let r = _mm_maskz_srlv_epi64(0b00000011, a, count);
9223        let e = _mm_set_epi64x(1 << 4, 0);
9224        assert_eq_m128i(r, e);
9225    }
9226
9227    #[simd_test(enable = "avx512f")]
9228    fn test_mm512_sll_epi64() {
9229        #[rustfmt::skip]
9230        let a = _mm512_set_epi64(
9231            1 << 63, 1 << 32, 1 << 32, 1 << 32,
9232            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9233        );
9234        let count = _mm_set_epi64x(0, 1);
9235        let r = _mm512_sll_epi64(a, count);
9236        #[rustfmt::skip]
9237        let e = _mm512_set_epi64(
9238            0, 1 << 33, 1 << 33, 1 << 33,
9239            1 << 33, 1 << 33, 1 << 33, 1 << 33,
9240        );
9241        assert_eq_m512i(r, e);
9242        let count = _mm_set_epi64x(1, 0);
9243        let r = _mm512_sll_epi64(a, count);
9244        assert_eq_m512i(r, a);
9245    }
9246
9247    #[simd_test(enable = "avx512f")]
9248    fn test_mm512_mask_sll_epi64() {
9249        #[rustfmt::skip]
9250        let a = _mm512_set_epi64(
9251            1 << 63, 1 << 32, 1 << 32, 1 << 32,
9252            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9253        );
9254        let count = _mm_set_epi64x(0, 1);
9255        let r = _mm512_mask_sll_epi64(a, 0, a, count);
9256        assert_eq_m512i(r, a);
9257        let r = _mm512_mask_sll_epi64(a, 0b11111111, a, count);
9258        #[rustfmt::skip]
9259        let e = _mm512_set_epi64(
9260            0, 1 << 33, 1 << 33, 1 << 33,
9261            1 << 33, 1 << 33, 1 << 33, 1 << 33,
9262        );
9263        assert_eq_m512i(r, e);
9264    }
9265
9266    #[simd_test(enable = "avx512f")]
9267    fn test_mm512_maskz_sll_epi64() {
9268        #[rustfmt::skip]
9269        let a = _mm512_set_epi64(
9270            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9271            1 << 32, 1 << 32, 1 << 32, 1 << 63,
9272        );
9273        let count = _mm_set_epi64x(0, 1);
9274        let r = _mm512_maskz_sll_epi64(0, a, count);
9275        assert_eq_m512i(r, _mm512_setzero_si512());
9276        let r = _mm512_maskz_sll_epi64(0b00001111, a, count);
9277        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 33, 1 << 33, 1 << 33, 0);
9278        assert_eq_m512i(r, e);
9279    }
9280
9281    #[simd_test(enable = "avx512f,avx512vl")]
9282    fn test_mm256_mask_sll_epi64() {
9283        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9284        let count = _mm_set_epi64x(0, 1);
9285        let r = _mm256_mask_sll_epi64(a, 0, a, count);
9286        assert_eq_m256i(r, a);
9287        let r = _mm256_mask_sll_epi64(a, 0b00001111, a, count);
9288        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9289        assert_eq_m256i(r, e);
9290    }
9291
9292    #[simd_test(enable = "avx512f,avx512vl")]
9293    fn test_mm256_maskz_sll_epi64() {
9294        let a = _mm256_set_epi64x(1 << 63, 1 << 32, 1 << 32, 1 << 32);
9295        let count = _mm_set_epi64x(0, 1);
9296        let r = _mm256_maskz_sll_epi64(0, a, count);
9297        assert_eq_m256i(r, _mm256_setzero_si256());
9298        let r = _mm256_maskz_sll_epi64(0b00001111, a, count);
9299        let e = _mm256_set_epi64x(0, 1 << 33, 1 << 33, 1 << 33);
9300        assert_eq_m256i(r, e);
9301    }
9302
9303    #[simd_test(enable = "avx512f,avx512vl")]
9304    fn test_mm_mask_sll_epi64() {
9305        let a = _mm_set_epi64x(1 << 63, 1 << 32);
9306        let count = _mm_set_epi64x(0, 1);
9307        let r = _mm_mask_sll_epi64(a, 0, a, count);
9308        assert_eq_m128i(r, a);
9309        let r = _mm_mask_sll_epi64(a, 0b00000011, a, count);
9310        let e = _mm_set_epi64x(0, 1 << 33);
9311        assert_eq_m128i(r, e);
9312    }
9313
9314    #[simd_test(enable = "avx512f,avx512vl")]
9315    fn test_mm_maskz_sll_epi64() {
9316        let a = _mm_set_epi64x(1 << 63, 1 << 32);
9317        let count = _mm_set_epi64x(0, 1);
9318        let r = _mm_maskz_sll_epi64(0, a, count);
9319        assert_eq_m128i(r, _mm_setzero_si128());
9320        let r = _mm_maskz_sll_epi64(0b00000011, a, count);
9321        let e = _mm_set_epi64x(0, 1 << 33);
9322        assert_eq_m128i(r, e);
9323    }
9324
9325    #[simd_test(enable = "avx512f")]
9326    fn test_mm512_srl_epi64() {
9327        #[rustfmt::skip]
9328        let a = _mm512_set_epi64(
9329            1 << 0, 1 << 32, 1 << 32, 1 << 32,
9330            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9331        );
9332        let count = _mm_set_epi64x(0, 1);
9333        let r = _mm512_srl_epi64(a, count);
9334        #[rustfmt::skip]
9335        let e = _mm512_set_epi64(
9336            0, 1 << 31, 1 << 31, 1 << 31,
9337            1 << 31, 1 << 31, 1 << 31, 1 << 31,
9338        );
9339        assert_eq_m512i(r, e);
9340    }
9341
9342    #[simd_test(enable = "avx512f")]
9343    fn test_mm512_mask_srl_epi64() {
9344        #[rustfmt::skip]
9345        let a = _mm512_set_epi64(
9346            1 << 0, 1 << 32, 1 << 32, 1 << 32,
9347            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9348        );
9349        let count = _mm_set_epi64x(0, 1);
9350        let r = _mm512_mask_srl_epi64(a, 0, a, count);
9351        assert_eq_m512i(r, a);
9352        let r = _mm512_mask_srl_epi64(a, 0b11111111, a, count);
9353        #[rustfmt::skip]
9354        let e = _mm512_set_epi64(
9355            0, 1 << 31, 1 << 31, 1 << 31,
9356            1 << 31, 1 << 31, 1 << 31, 1 << 31,
9357        );
9358        assert_eq_m512i(r, e);
9359    }
9360
9361    #[simd_test(enable = "avx512f")]
9362    fn test_mm512_maskz_srl_epi64() {
9363        #[rustfmt::skip]
9364        let a = _mm512_set_epi64(
9365            1 << 32, 1 << 32, 1 << 32, 1 << 32,
9366            1 << 32, 1 << 32, 1 << 32, 1 << 0,
9367        );
9368        let count = _mm_set_epi64x(0, 1);
9369        let r = _mm512_maskz_srl_epi64(0, a, count);
9370        assert_eq_m512i(r, _mm512_setzero_si512());
9371        let r = _mm512_maskz_srl_epi64(0b00001111, a, count);
9372        let e = _mm512_set_epi64(0, 0, 0, 0, 1 << 31, 1 << 31, 1 << 31, 0);
9373        assert_eq_m512i(r, e);
9374    }
9375
9376    #[simd_test(enable = "avx512f,avx512vl")]
9377    fn test_mm256_mask_srl_epi64() {
9378        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9379        let count = _mm_set_epi64x(0, 1);
9380        let r = _mm256_mask_srl_epi64(a, 0, a, count);
9381        assert_eq_m256i(r, a);
9382        let r = _mm256_mask_srl_epi64(a, 0b00001111, a, count);
9383        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9384        assert_eq_m256i(r, e);
9385    }
9386
9387    #[simd_test(enable = "avx512f,avx512vl")]
9388    fn test_mm256_maskz_srl_epi64() {
9389        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9390        let count = _mm_set_epi64x(0, 1);
9391        let r = _mm256_maskz_srl_epi64(0, a, count);
9392        assert_eq_m256i(r, _mm256_setzero_si256());
9393        let r = _mm256_maskz_srl_epi64(0b00001111, a, count);
9394        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9395        assert_eq_m256i(r, e);
9396    }
9397
9398    #[simd_test(enable = "avx512f,avx512vl")]
9399    fn test_mm_mask_srl_epi64() {
9400        let a = _mm_set_epi64x(1 << 5, 0);
9401        let count = _mm_set_epi64x(0, 1);
9402        let r = _mm_mask_srl_epi64(a, 0, a, count);
9403        assert_eq_m128i(r, a);
9404        let r = _mm_mask_srl_epi64(a, 0b00000011, a, count);
9405        let e = _mm_set_epi64x(1 << 4, 0);
9406        assert_eq_m128i(r, e);
9407    }
9408
9409    #[simd_test(enable = "avx512f,avx512vl")]
9410    fn test_mm_maskz_srl_epi64() {
9411        let a = _mm_set_epi64x(1 << 5, 0);
9412        let count = _mm_set_epi64x(0, 1);
9413        let r = _mm_maskz_srl_epi64(0, a, count);
9414        assert_eq_m128i(r, _mm_setzero_si128());
9415        let r = _mm_maskz_srl_epi64(0b00000011, a, count);
9416        let e = _mm_set_epi64x(1 << 4, 0);
9417        assert_eq_m128i(r, e);
9418    }
9419
9420    #[simd_test(enable = "avx512f")]
9421    fn test_mm512_sra_epi64() {
9422        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9423        let count = _mm_set_epi64x(0, 2);
9424        let r = _mm512_sra_epi64(a, count);
9425        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9426        assert_eq_m512i(r, e);
9427    }
9428
9429    #[simd_test(enable = "avx512f")]
9430    fn test_mm512_mask_sra_epi64() {
9431        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9432        let count = _mm_set_epi64x(0, 2);
9433        let r = _mm512_mask_sra_epi64(a, 0, a, count);
9434        assert_eq_m512i(r, a);
9435        let r = _mm512_mask_sra_epi64(a, 0b11111111, a, count);
9436        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -4);
9437        assert_eq_m512i(r, e);
9438    }
9439
9440    #[simd_test(enable = "avx512f")]
9441    fn test_mm512_maskz_sra_epi64() {
9442        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9443        let count = _mm_set_epi64x(0, 2);
9444        let r = _mm512_maskz_sra_epi64(0, a, count);
9445        assert_eq_m512i(r, _mm512_setzero_si512());
9446        let r = _mm512_maskz_sra_epi64(0b00001111, a, count);
9447        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -4);
9448        assert_eq_m512i(r, e);
9449    }
9450
9451    #[simd_test(enable = "avx512f,avx512vl")]
9452    fn test_mm256_sra_epi64() {
9453        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9454        let count = _mm_set_epi64x(0, 1);
9455        let r = _mm256_sra_epi64(a, count);
9456        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9457        assert_eq_m256i(r, e);
9458    }
9459
9460    #[simd_test(enable = "avx512f,avx512vl")]
9461    fn test_mm256_mask_sra_epi64() {
9462        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9463        let count = _mm_set_epi64x(0, 1);
9464        let r = _mm256_mask_sra_epi64(a, 0, a, count);
9465        assert_eq_m256i(r, a);
9466        let r = _mm256_mask_sra_epi64(a, 0b00001111, a, count);
9467        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9468        assert_eq_m256i(r, e);
9469    }
9470
9471    #[simd_test(enable = "avx512f,avx512vl")]
9472    fn test_mm256_maskz_sra_epi64() {
9473        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9474        let count = _mm_set_epi64x(0, 1);
9475        let r = _mm256_maskz_sra_epi64(0, a, count);
9476        assert_eq_m256i(r, _mm256_setzero_si256());
9477        let r = _mm256_maskz_sra_epi64(0b00001111, a, count);
9478        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9479        assert_eq_m256i(r, e);
9480    }
9481
9482    #[simd_test(enable = "avx512f,avx512vl")]
9483    fn test_mm_sra_epi64() {
9484        let a = _mm_set_epi64x(1 << 5, 0);
9485        let count = _mm_set_epi64x(0, 1);
9486        let r = _mm_sra_epi64(a, count);
9487        let e = _mm_set_epi64x(1 << 4, 0);
9488        assert_eq_m128i(r, e);
9489    }
9490
9491    #[simd_test(enable = "avx512f,avx512vl")]
9492    fn test_mm_mask_sra_epi64() {
9493        let a = _mm_set_epi64x(1 << 5, 0);
9494        let count = _mm_set_epi64x(0, 1);
9495        let r = _mm_mask_sra_epi64(a, 0, a, count);
9496        assert_eq_m128i(r, a);
9497        let r = _mm_mask_sra_epi64(a, 0b00000011, a, count);
9498        let e = _mm_set_epi64x(1 << 4, 0);
9499        assert_eq_m128i(r, e);
9500    }
9501
9502    #[simd_test(enable = "avx512f,avx512vl")]
9503    fn test_mm_maskz_sra_epi64() {
9504        let a = _mm_set_epi64x(1 << 5, 0);
9505        let count = _mm_set_epi64x(0, 1);
9506        let r = _mm_maskz_sra_epi64(0, a, count);
9507        assert_eq_m128i(r, _mm_setzero_si128());
9508        let r = _mm_maskz_sra_epi64(0b00000011, a, count);
9509        let e = _mm_set_epi64x(1 << 4, 0);
9510        assert_eq_m128i(r, e);
9511    }
9512
9513    #[simd_test(enable = "avx512f")]
9514    const fn test_mm512_srav_epi64() {
9515        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9516        let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9517        let r = _mm512_srav_epi64(a, count);
9518        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9519        assert_eq_m512i(r, e);
9520    }
9521
9522    #[simd_test(enable = "avx512f")]
9523    const fn test_mm512_mask_srav_epi64() {
9524        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9525        let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9526        let r = _mm512_mask_srav_epi64(a, 0, a, count);
9527        assert_eq_m512i(r, a);
9528        let r = _mm512_mask_srav_epi64(a, 0b11111111, a, count);
9529        let e = _mm512_set_epi64(0, -2, 0, 0, 0, 0, 3, -8);
9530        assert_eq_m512i(r, e);
9531    }
9532
9533    #[simd_test(enable = "avx512f")]
9534    const fn test_mm512_maskz_srav_epi64() {
9535        let a = _mm512_set_epi64(1, -8, 0, 0, 0, 0, 15, -16);
9536        let count = _mm512_set_epi64(2, 2, 0, 0, 0, 0, 2, 1);
9537        let r = _mm512_maskz_srav_epi64(0, a, count);
9538        assert_eq_m512i(r, _mm512_setzero_si512());
9539        let r = _mm512_maskz_srav_epi64(0b00001111, a, count);
9540        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 3, -8);
9541        assert_eq_m512i(r, e);
9542    }
9543
9544    #[simd_test(enable = "avx512f,avx512vl")]
9545    const fn test_mm256_srav_epi64() {
9546        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9547        let count = _mm256_set1_epi64x(1);
9548        let r = _mm256_srav_epi64(a, count);
9549        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9550        assert_eq_m256i(r, e);
9551    }
9552
9553    #[simd_test(enable = "avx512f,avx512vl")]
9554    const fn test_mm256_mask_srav_epi64() {
9555        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9556        let count = _mm256_set1_epi64x(1);
9557        let r = _mm256_mask_srav_epi64(a, 0, a, count);
9558        assert_eq_m256i(r, a);
9559        let r = _mm256_mask_srav_epi64(a, 0b00001111, a, count);
9560        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9561        assert_eq_m256i(r, e);
9562    }
9563
9564    #[simd_test(enable = "avx512f,avx512vl")]
9565    const fn test_mm256_maskz_srav_epi64() {
9566        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9567        let count = _mm256_set1_epi64x(1);
9568        let r = _mm256_maskz_srav_epi64(0, a, count);
9569        assert_eq_m256i(r, _mm256_setzero_si256());
9570        let r = _mm256_maskz_srav_epi64(0b00001111, a, count);
9571        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9572        assert_eq_m256i(r, e);
9573    }
9574
9575    #[simd_test(enable = "avx512f,avx512vl")]
9576    const fn test_mm_srav_epi64() {
9577        let a = _mm_set_epi64x(1 << 5, 0);
9578        let count = _mm_set1_epi64x(1);
9579        let r = _mm_srav_epi64(a, count);
9580        let e = _mm_set_epi64x(1 << 4, 0);
9581        assert_eq_m128i(r, e);
9582    }
9583
9584    #[simd_test(enable = "avx512f,avx512vl")]
9585    const fn test_mm_mask_srav_epi64() {
9586        let a = _mm_set_epi64x(1 << 5, 0);
9587        let count = _mm_set1_epi64x(1);
9588        let r = _mm_mask_srav_epi64(a, 0, a, count);
9589        assert_eq_m128i(r, a);
9590        let r = _mm_mask_srav_epi64(a, 0b00000011, a, count);
9591        let e = _mm_set_epi64x(1 << 4, 0);
9592        assert_eq_m128i(r, e);
9593    }
9594
9595    #[simd_test(enable = "avx512f,avx512vl")]
9596    const fn test_mm_maskz_srav_epi64() {
9597        let a = _mm_set_epi64x(1 << 5, 0);
9598        let count = _mm_set1_epi64x(1);
9599        let r = _mm_maskz_srav_epi64(0, a, count);
9600        assert_eq_m128i(r, _mm_setzero_si128());
9601        let r = _mm_maskz_srav_epi64(0b00000011, a, count);
9602        let e = _mm_set_epi64x(1 << 4, 0);
9603        assert_eq_m128i(r, e);
9604    }
9605
9606    #[simd_test(enable = "avx512f")]
9607    const fn test_mm512_srai_epi64() {
9608        let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9609        let r = _mm512_srai_epi64::<2>(a);
9610        let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9611        assert_eq_m512i(r, e);
9612    }
9613
9614    #[simd_test(enable = "avx512f")]
9615    const fn test_mm512_mask_srai_epi64() {
9616        let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9617        let r = _mm512_mask_srai_epi64::<2>(a, 0, a);
9618        assert_eq_m512i(r, a);
9619        let r = _mm512_mask_srai_epi64::<2>(a, 0b11111111, a);
9620        let e = _mm512_set_epi64(0, -1, 3, 0, 0, 0, 0, -4);
9621        assert_eq_m512i(r, e);
9622    }
9623
9624    #[simd_test(enable = "avx512f")]
9625    const fn test_mm512_maskz_srai_epi64() {
9626        let a = _mm512_set_epi64(1, -4, 15, 0, 0, 0, 0, -16);
9627        let r = _mm512_maskz_srai_epi64::<2>(0, a);
9628        assert_eq_m512i(r, _mm512_setzero_si512());
9629        let r = _mm512_maskz_srai_epi64::<2>(0b00001111, a);
9630        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, -4);
9631        assert_eq_m512i(r, e);
9632    }
9633
9634    #[simd_test(enable = "avx512f,avx512vl")]
9635    const fn test_mm256_srai_epi64() {
9636        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9637        let r = _mm256_srai_epi64::<1>(a);
9638        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9639        assert_eq_m256i(r, e);
9640    }
9641
9642    #[simd_test(enable = "avx512f,avx512vl")]
9643    const fn test_mm256_mask_srai_epi64() {
9644        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9645        let r = _mm256_mask_srai_epi64::<1>(a, 0, a);
9646        assert_eq_m256i(r, a);
9647        let r = _mm256_mask_srai_epi64::<1>(a, 0b00001111, a);
9648        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9649        assert_eq_m256i(r, e);
9650    }
9651
9652    #[simd_test(enable = "avx512f,avx512vl")]
9653    const fn test_mm256_maskz_srai_epi64() {
9654        let a = _mm256_set_epi64x(1 << 5, 0, 0, 0);
9655        let r = _mm256_maskz_srai_epi64::<1>(0, a);
9656        assert_eq_m256i(r, _mm256_setzero_si256());
9657        let r = _mm256_maskz_srai_epi64::<1>(0b00001111, a);
9658        let e = _mm256_set_epi64x(1 << 4, 0, 0, 0);
9659        assert_eq_m256i(r, e);
9660    }
9661
9662    #[simd_test(enable = "avx512f,avx512vl")]
9663    const fn test_mm_srai_epi64() {
9664        let a = _mm_set_epi64x(1 << 5, 0);
9665        let r = _mm_srai_epi64::<1>(a);
9666        let e = _mm_set_epi64x(1 << 4, 0);
9667        assert_eq_m128i(r, e);
9668    }
9669
9670    #[simd_test(enable = "avx512f,avx512vl")]
9671    const fn test_mm_mask_srai_epi64() {
9672        let a = _mm_set_epi64x(1 << 5, 0);
9673        let r = _mm_mask_srai_epi64::<1>(a, 0, a);
9674        assert_eq_m128i(r, a);
9675        let r = _mm_mask_srai_epi64::<1>(a, 0b00000011, a);
9676        let e = _mm_set_epi64x(1 << 4, 0);
9677        assert_eq_m128i(r, e);
9678    }
9679
9680    #[simd_test(enable = "avx512f,avx512vl")]
9681    const fn test_mm_maskz_srai_epi64() {
9682        let a = _mm_set_epi64x(1 << 5, 0);
9683        let r = _mm_maskz_srai_epi64::<1>(0, a);
9684        assert_eq_m128i(r, _mm_setzero_si128());
9685        let r = _mm_maskz_srai_epi64::<1>(0b00000011, a);
9686        let e = _mm_set_epi64x(1 << 4, 0);
9687        assert_eq_m128i(r, e);
9688    }
9689
9690    #[simd_test(enable = "avx512f")]
9691    const fn test_mm512_permute_pd() {
9692        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9693        let r = _mm512_permute_pd::<0b11_11_11_11>(a);
9694        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9695        assert_eq_m512d(r, e);
9696    }
9697
9698    #[simd_test(enable = "avx512f")]
9699    const fn test_mm512_mask_permute_pd() {
9700        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9701        let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0, a);
9702        assert_eq_m512d(r, a);
9703        let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0b11111111, a);
9704        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9705        assert_eq_m512d(r, e);
9706    }
9707
9708    #[simd_test(enable = "avx512f")]
9709    const fn test_mm512_maskz_permute_pd() {
9710        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9711        let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0, a);
9712        assert_eq_m512d(r, _mm512_setzero_pd());
9713        let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0b11111111, a);
9714        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9715        assert_eq_m512d(r, e);
9716    }
9717
9718    #[simd_test(enable = "avx512f,avx512vl")]
9719    const fn test_mm256_mask_permute_pd() {
9720        let a = _mm256_set_pd(3., 2., 1., 0.);
9721        let r = _mm256_mask_permute_pd::<0b11_11>(a, 0, a);
9722        assert_eq_m256d(r, a);
9723        let r = _mm256_mask_permute_pd::<0b11_11>(a, 0b00001111, a);
9724        let e = _mm256_set_pd(3., 3., 1., 1.);
9725        assert_eq_m256d(r, e);
9726    }
9727
9728    #[simd_test(enable = "avx512f,avx512vl")]
9729    const fn test_mm256_maskz_permute_pd() {
9730        let a = _mm256_set_pd(3., 2., 1., 0.);
9731        let r = _mm256_maskz_permute_pd::<0b11_11>(0, a);
9732        assert_eq_m256d(r, _mm256_setzero_pd());
9733        let r = _mm256_maskz_permute_pd::<0b11_11>(0b00001111, a);
9734        let e = _mm256_set_pd(3., 3., 1., 1.);
9735        assert_eq_m256d(r, e);
9736    }
9737
9738    #[simd_test(enable = "avx512f,avx512vl")]
9739    const fn test_mm_mask_permute_pd() {
9740        let a = _mm_set_pd(1., 0.);
9741        let r = _mm_mask_permute_pd::<0b11>(a, 0, a);
9742        assert_eq_m128d(r, a);
9743        let r = _mm_mask_permute_pd::<0b11>(a, 0b00000011, a);
9744        let e = _mm_set_pd(1., 1.);
9745        assert_eq_m128d(r, e);
9746    }
9747
9748    #[simd_test(enable = "avx512f,avx512vl")]
9749    const fn test_mm_maskz_permute_pd() {
9750        let a = _mm_set_pd(1., 0.);
9751        let r = _mm_maskz_permute_pd::<0b11>(0, a);
9752        assert_eq_m128d(r, _mm_setzero_pd());
9753        let r = _mm_maskz_permute_pd::<0b11>(0b00000011, a);
9754        let e = _mm_set_pd(1., 1.);
9755        assert_eq_m128d(r, e);
9756    }
9757
9758    #[simd_test(enable = "avx512f")]
9759    const fn test_mm512_permutex_epi64() {
9760        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9761        let r = _mm512_permutex_epi64::<0b11_11_11_11>(a);
9762        let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9763        assert_eq_m512i(r, e);
9764    }
9765
9766    #[simd_test(enable = "avx512f")]
9767    const fn test_mm512_mask_permutex_epi64() {
9768        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9769        let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9770        assert_eq_m512i(r, a);
9771        let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0b11111111, a);
9772        let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9773        assert_eq_m512i(r, e);
9774    }
9775
9776    #[simd_test(enable = "avx512f")]
9777    const fn test_mm512_maskz_permutex_epi64() {
9778        let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9779        let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9780        assert_eq_m512i(r, _mm512_setzero_si512());
9781        let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0b11111111, a);
9782        let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7);
9783        assert_eq_m512i(r, e);
9784    }
9785
9786    #[simd_test(enable = "avx512f,avx512vl")]
9787    const fn test_mm256_permutex_epi64() {
9788        let a = _mm256_set_epi64x(3, 2, 1, 0);
9789        let r = _mm256_permutex_epi64::<0b11_11_11_11>(a);
9790        let e = _mm256_set_epi64x(3, 3, 3, 3);
9791        assert_eq_m256i(r, e);
9792    }
9793
9794    #[simd_test(enable = "avx512f,avx512vl")]
9795    const fn test_mm256_mask_permutex_epi64() {
9796        let a = _mm256_set_epi64x(3, 2, 1, 0);
9797        let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a);
9798        assert_eq_m256i(r, a);
9799        let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0b00001111, a);
9800        let e = _mm256_set_epi64x(3, 3, 3, 3);
9801        assert_eq_m256i(r, e);
9802    }
9803
9804    #[simd_test(enable = "avx512f,avx512vl")]
9805    const fn test_mm256_maskz_permutex_epi64() {
9806        let a = _mm256_set_epi64x(3, 2, 1, 0);
9807        let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a);
9808        assert_eq_m256i(r, _mm256_setzero_si256());
9809        let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0b00001111, a);
9810        let e = _mm256_set_epi64x(3, 3, 3, 3);
9811        assert_eq_m256i(r, e);
9812    }
9813
9814    #[simd_test(enable = "avx512f")]
9815    const fn test_mm512_permutex_pd() {
9816        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9817        let r = _mm512_permutex_pd::<0b11_11_11_11>(a);
9818        let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9819        assert_eq_m512d(r, e);
9820    }
9821
9822    #[simd_test(enable = "avx512f")]
9823    const fn test_mm512_mask_permutex_pd() {
9824        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9825        let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9826        assert_eq_m512d(r, a);
9827        let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0b11111111, a);
9828        let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9829        assert_eq_m512d(r, e);
9830    }
9831
9832    #[simd_test(enable = "avx512f")]
9833    const fn test_mm512_maskz_permutex_pd() {
9834        let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9835        let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9836        assert_eq_m512d(r, _mm512_setzero_pd());
9837        let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0b11111111, a);
9838        let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.);
9839        assert_eq_m512d(r, e);
9840    }
9841
9842    #[simd_test(enable = "avx512f,avx512vl")]
9843    const fn test_mm256_permutex_pd() {
9844        let a = _mm256_set_pd(0., 1., 2., 3.);
9845        let r = _mm256_permutex_pd::<0b11_11_11_11>(a);
9846        let e = _mm256_set_pd(0., 0., 0., 0.);
9847        assert_eq_m256d(r, e);
9848    }
9849
9850    #[simd_test(enable = "avx512f,avx512vl")]
9851    const fn test_mm256_mask_permutex_pd() {
9852        let a = _mm256_set_pd(0., 1., 2., 3.);
9853        let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0, a);
9854        assert_eq_m256d(r, a);
9855        let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0b00001111, a);
9856        let e = _mm256_set_pd(0., 0., 0., 0.);
9857        assert_eq_m256d(r, e);
9858    }
9859
9860    #[simd_test(enable = "avx512f,avx512vl")]
9861    const fn test_mm256_maskz_permutex_pd() {
9862        let a = _mm256_set_pd(0., 1., 2., 3.);
9863        let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0, a);
9864        assert_eq_m256d(r, _mm256_setzero_pd());
9865        let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0b00001111, a);
9866        let e = _mm256_set_pd(0., 0., 0., 0.);
9867        assert_eq_m256d(r, e);
9868    }
9869
9870    #[simd_test(enable = "avx512f")]
9871    fn test_mm512_permutevar_pd() {
9872        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9873        let b = _mm512_set1_epi64(0b1);
9874        let r = _mm512_permutevar_pd(a, b);
9875        let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9876        assert_eq_m512d(r, e);
9877    }
9878
9879    #[simd_test(enable = "avx512f")]
9880    fn test_mm512_mask_permutevar_pd() {
9881        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9882        let b = _mm512_set1_epi64(0b1);
9883        let r = _mm512_mask_permutevar_pd(a, 0, a, b);
9884        assert_eq_m512d(r, a);
9885        let r = _mm512_mask_permutevar_pd(a, 0b11111111, a, b);
9886        let e = _mm512_set_pd(1., 1., 3., 3., 5., 5., 7., 7.);
9887        assert_eq_m512d(r, e);
9888    }
9889
9890    #[simd_test(enable = "avx512f")]
9891    fn test_mm512_maskz_permutevar_pd() {
9892        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
9893        let b = _mm512_set1_epi64(0b1);
9894        let r = _mm512_maskz_permutevar_pd(0, a, b);
9895        assert_eq_m512d(r, _mm512_setzero_pd());
9896        let r = _mm512_maskz_permutevar_pd(0b00001111, a, b);
9897        let e = _mm512_set_pd(0., 0., 0., 0., 5., 5., 7., 7.);
9898        assert_eq_m512d(r, e);
9899    }
9900
9901    #[simd_test(enable = "avx512f,avx512vl")]
9902    fn test_mm256_mask_permutevar_pd() {
9903        let a = _mm256_set_pd(0., 1., 2., 3.);
9904        let b = _mm256_set1_epi64x(0b1);
9905        let r = _mm256_mask_permutevar_pd(a, 0, a, b);
9906        assert_eq_m256d(r, a);
9907        let r = _mm256_mask_permutevar_pd(a, 0b00001111, a, b);
9908        let e = _mm256_set_pd(1., 1., 3., 3.);
9909        assert_eq_m256d(r, e);
9910    }
9911
9912    #[simd_test(enable = "avx512f,avx512vl")]
9913    fn test_mm256_maskz_permutevar_pd() {
9914        let a = _mm256_set_pd(0., 1., 2., 3.);
9915        let b = _mm256_set1_epi64x(0b1);
9916        let r = _mm256_maskz_permutevar_pd(0, a, b);
9917        assert_eq_m256d(r, _mm256_setzero_pd());
9918        let r = _mm256_maskz_permutevar_pd(0b00001111, a, b);
9919        let e = _mm256_set_pd(1., 1., 3., 3.);
9920        assert_eq_m256d(r, e);
9921    }
9922
9923    #[simd_test(enable = "avx512f,avx512vl")]
9924    fn test_mm_mask_permutevar_pd() {
9925        let a = _mm_set_pd(0., 1.);
9926        let b = _mm_set1_epi64x(0b1);
9927        let r = _mm_mask_permutevar_pd(a, 0, a, b);
9928        assert_eq_m128d(r, a);
9929        let r = _mm_mask_permutevar_pd(a, 0b00000011, a, b);
9930        let e = _mm_set_pd(1., 1.);
9931        assert_eq_m128d(r, e);
9932    }
9933
9934    #[simd_test(enable = "avx512f,avx512vl")]
9935    fn test_mm_maskz_permutevar_pd() {
9936        let a = _mm_set_pd(0., 1.);
9937        let b = _mm_set1_epi64x(0b1);
9938        let r = _mm_maskz_permutevar_pd(0, a, b);
9939        assert_eq_m128d(r, _mm_setzero_pd());
9940        let r = _mm_maskz_permutevar_pd(0b00000011, a, b);
9941        let e = _mm_set_pd(1., 1.);
9942        assert_eq_m128d(r, e);
9943    }
9944
9945    #[simd_test(enable = "avx512f")]
9946    fn test_mm512_permutexvar_epi64() {
9947        let idx = _mm512_set1_epi64(1);
9948        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9949        let r = _mm512_permutexvar_epi64(idx, a);
9950        let e = _mm512_set1_epi64(6);
9951        assert_eq_m512i(r, e);
9952    }
9953
9954    #[simd_test(enable = "avx512f")]
9955    fn test_mm512_mask_permutexvar_epi64() {
9956        let idx = _mm512_set1_epi64(1);
9957        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9958        let r = _mm512_mask_permutexvar_epi64(a, 0, idx, a);
9959        assert_eq_m512i(r, a);
9960        let r = _mm512_mask_permutexvar_epi64(a, 0b11111111, idx, a);
9961        let e = _mm512_set1_epi64(6);
9962        assert_eq_m512i(r, e);
9963    }
9964
9965    #[simd_test(enable = "avx512f")]
9966    fn test_mm512_maskz_permutexvar_epi64() {
9967        let idx = _mm512_set1_epi64(1);
9968        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
9969        let r = _mm512_maskz_permutexvar_epi64(0, idx, a);
9970        assert_eq_m512i(r, _mm512_setzero_si512());
9971        let r = _mm512_maskz_permutexvar_epi64(0b00001111, idx, a);
9972        let e = _mm512_set_epi64(0, 0, 0, 0, 6, 6, 6, 6);
9973        assert_eq_m512i(r, e);
9974    }
9975
9976    #[simd_test(enable = "avx512f,avx512vl")]
9977    fn test_mm256_permutexvar_epi64() {
9978        let idx = _mm256_set1_epi64x(1);
9979        let a = _mm256_set_epi64x(0, 1, 2, 3);
9980        let r = _mm256_permutexvar_epi64(idx, a);
9981        let e = _mm256_set1_epi64x(2);
9982        assert_eq_m256i(r, e);
9983    }
9984
9985    #[simd_test(enable = "avx512f,avx512vl")]
9986    fn test_mm256_mask_permutexvar_epi64() {
9987        let idx = _mm256_set1_epi64x(1);
9988        let a = _mm256_set_epi64x(0, 1, 2, 3);
9989        let r = _mm256_mask_permutexvar_epi64(a, 0, idx, a);
9990        assert_eq_m256i(r, a);
9991        let r = _mm256_mask_permutexvar_epi64(a, 0b00001111, idx, a);
9992        let e = _mm256_set1_epi64x(2);
9993        assert_eq_m256i(r, e);
9994    }
9995
9996    #[simd_test(enable = "avx512f,avx512vl")]
9997    fn test_mm256_maskz_permutexvar_epi64() {
9998        let idx = _mm256_set1_epi64x(1);
9999        let a = _mm256_set_epi64x(0, 1, 2, 3);
10000        let r = _mm256_maskz_permutexvar_epi64(0, idx, a);
10001        assert_eq_m256i(r, _mm256_setzero_si256());
10002        let r = _mm256_maskz_permutexvar_epi64(0b00001111, idx, a);
10003        let e = _mm256_set1_epi64x(2);
10004        assert_eq_m256i(r, e);
10005    }
10006
10007    #[simd_test(enable = "avx512f")]
10008    fn test_mm512_permutexvar_pd() {
10009        let idx = _mm512_set1_epi64(1);
10010        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10011        let r = _mm512_permutexvar_pd(idx, a);
10012        let e = _mm512_set1_pd(6.);
10013        assert_eq_m512d(r, e);
10014    }
10015
10016    #[simd_test(enable = "avx512f")]
10017    fn test_mm512_mask_permutexvar_pd() {
10018        let idx = _mm512_set1_epi64(1);
10019        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10020        let r = _mm512_mask_permutexvar_pd(a, 0, idx, a);
10021        assert_eq_m512d(r, a);
10022        let r = _mm512_mask_permutexvar_pd(a, 0b11111111, idx, a);
10023        let e = _mm512_set1_pd(6.);
10024        assert_eq_m512d(r, e);
10025    }
10026
10027    #[simd_test(enable = "avx512f")]
10028    fn test_mm512_maskz_permutexvar_pd() {
10029        let idx = _mm512_set1_epi64(1);
10030        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10031        let r = _mm512_maskz_permutexvar_pd(0, idx, a);
10032        assert_eq_m512d(r, _mm512_setzero_pd());
10033        let r = _mm512_maskz_permutexvar_pd(0b00001111, idx, a);
10034        let e = _mm512_set_pd(0., 0., 0., 0., 6., 6., 6., 6.);
10035        assert_eq_m512d(r, e);
10036    }
10037
10038    #[simd_test(enable = "avx512f,avx512vl")]
10039    fn test_mm256_permutexvar_pd() {
10040        let idx = _mm256_set1_epi64x(1);
10041        let a = _mm256_set_pd(0., 1., 2., 3.);
10042        let r = _mm256_permutexvar_pd(idx, a);
10043        let e = _mm256_set1_pd(2.);
10044        assert_eq_m256d(r, e);
10045    }
10046
10047    #[simd_test(enable = "avx512f,avx512vl")]
10048    fn test_mm256_mask_permutexvar_pd() {
10049        let idx = _mm256_set1_epi64x(1);
10050        let a = _mm256_set_pd(0., 1., 2., 3.);
10051        let r = _mm256_mask_permutexvar_pd(a, 0, idx, a);
10052        assert_eq_m256d(r, a);
10053        let r = _mm256_mask_permutexvar_pd(a, 0b00001111, idx, a);
10054        let e = _mm256_set1_pd(2.);
10055        assert_eq_m256d(r, e);
10056    }
10057
10058    #[simd_test(enable = "avx512f,avx512vl")]
10059    fn test_mm256_maskz_permutexvar_pd() {
10060        let idx = _mm256_set1_epi64x(1);
10061        let a = _mm256_set_pd(0., 1., 2., 3.);
10062        let r = _mm256_maskz_permutexvar_pd(0, idx, a);
10063        assert_eq_m256d(r, _mm256_setzero_pd());
10064        let r = _mm256_maskz_permutexvar_pd(0b00001111, idx, a);
10065        let e = _mm256_set1_pd(2.);
10066        assert_eq_m256d(r, e);
10067    }
10068
10069    #[simd_test(enable = "avx512f")]
10070    fn test_mm512_permutex2var_epi64() {
10071        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
10072        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10073        let b = _mm512_set1_epi64(100);
10074        let r = _mm512_permutex2var_epi64(a, idx, b);
10075        let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
10076        assert_eq_m512i(r, e);
10077    }
10078
10079    #[simd_test(enable = "avx512f")]
10080    fn test_mm512_mask_permutex2var_epi64() {
10081        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
10082        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10083        let b = _mm512_set1_epi64(100);
10084        let r = _mm512_mask_permutex2var_epi64(a, 0, idx, b);
10085        assert_eq_m512i(r, a);
10086        let r = _mm512_mask_permutex2var_epi64(a, 0b11111111, idx, b);
10087        let e = _mm512_set_epi64(6, 100, 5, 100, 4, 100, 3, 100);
10088        assert_eq_m512i(r, e);
10089    }
10090
10091    #[simd_test(enable = "avx512f")]
10092    fn test_mm512_maskz_permutex2var_epi64() {
10093        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
10094        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10095        let b = _mm512_set1_epi64(100);
10096        let r = _mm512_maskz_permutex2var_epi64(0, a, idx, b);
10097        assert_eq_m512i(r, _mm512_setzero_si512());
10098        let r = _mm512_maskz_permutex2var_epi64(0b00001111, a, idx, b);
10099        let e = _mm512_set_epi64(0, 0, 0, 0, 4, 100, 3, 100);
10100        assert_eq_m512i(r, e);
10101    }
10102
10103    #[simd_test(enable = "avx512f")]
10104    fn test_mm512_mask2_permutex2var_epi64() {
10105        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
10106        let idx = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10107        let b = _mm512_set1_epi64(100);
10108        let r = _mm512_mask2_permutex2var_epi64(a, idx, 0, b);
10109        assert_eq_m512i(r, idx);
10110        let r = _mm512_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
10111        let e = _mm512_set_epi64(1000, 1 << 3, 2000, 1 << 3, 4, 100, 3, 100);
10112        assert_eq_m512i(r, e);
10113    }
10114
10115    #[simd_test(enable = "avx512f,avx512vl")]
10116    fn test_mm256_permutex2var_epi64() {
10117        let a = _mm256_set_epi64x(0, 1, 2, 3);
10118        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10119        let b = _mm256_set1_epi64x(100);
10120        let r = _mm256_permutex2var_epi64(a, idx, b);
10121        let e = _mm256_set_epi64x(2, 100, 1, 100);
10122        assert_eq_m256i(r, e);
10123    }
10124
10125    #[simd_test(enable = "avx512f,avx512vl")]
10126    fn test_mm256_mask_permutex2var_epi64() {
10127        let a = _mm256_set_epi64x(0, 1, 2, 3);
10128        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10129        let b = _mm256_set1_epi64x(100);
10130        let r = _mm256_mask_permutex2var_epi64(a, 0, idx, b);
10131        assert_eq_m256i(r, a);
10132        let r = _mm256_mask_permutex2var_epi64(a, 0b00001111, idx, b);
10133        let e = _mm256_set_epi64x(2, 100, 1, 100);
10134        assert_eq_m256i(r, e);
10135    }
10136
10137    #[simd_test(enable = "avx512f,avx512vl")]
10138    fn test_mm256_maskz_permutex2var_epi64() {
10139        let a = _mm256_set_epi64x(0, 1, 2, 3);
10140        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10141        let b = _mm256_set1_epi64x(100);
10142        let r = _mm256_maskz_permutex2var_epi64(0, a, idx, b);
10143        assert_eq_m256i(r, _mm256_setzero_si256());
10144        let r = _mm256_maskz_permutex2var_epi64(0b00001111, a, idx, b);
10145        let e = _mm256_set_epi64x(2, 100, 1, 100);
10146        assert_eq_m256i(r, e);
10147    }
10148
10149    #[simd_test(enable = "avx512f,avx512vl")]
10150    fn test_mm256_mask2_permutex2var_epi64() {
10151        let a = _mm256_set_epi64x(0, 1, 2, 3);
10152        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10153        let b = _mm256_set1_epi64x(100);
10154        let r = _mm256_mask2_permutex2var_epi64(a, idx, 0, b);
10155        assert_eq_m256i(r, idx);
10156        let r = _mm256_mask2_permutex2var_epi64(a, idx, 0b00001111, b);
10157        let e = _mm256_set_epi64x(2, 100, 1, 100);
10158        assert_eq_m256i(r, e);
10159    }
10160
10161    #[simd_test(enable = "avx512f,avx512vl")]
10162    fn test_mm_permutex2var_epi64() {
10163        let a = _mm_set_epi64x(0, 1);
10164        let idx = _mm_set_epi64x(1, 1 << 1);
10165        let b = _mm_set1_epi64x(100);
10166        let r = _mm_permutex2var_epi64(a, idx, b);
10167        let e = _mm_set_epi64x(0, 100);
10168        assert_eq_m128i(r, e);
10169    }
10170
10171    #[simd_test(enable = "avx512f,avx512vl")]
10172    fn test_mm_mask_permutex2var_epi64() {
10173        let a = _mm_set_epi64x(0, 1);
10174        let idx = _mm_set_epi64x(1, 1 << 1);
10175        let b = _mm_set1_epi64x(100);
10176        let r = _mm_mask_permutex2var_epi64(a, 0, idx, b);
10177        assert_eq_m128i(r, a);
10178        let r = _mm_mask_permutex2var_epi64(a, 0b00000011, idx, b);
10179        let e = _mm_set_epi64x(0, 100);
10180        assert_eq_m128i(r, e);
10181    }
10182
10183    #[simd_test(enable = "avx512f,avx512vl")]
10184    fn test_mm_maskz_permutex2var_epi64() {
10185        let a = _mm_set_epi64x(0, 1);
10186        let idx = _mm_set_epi64x(1, 1 << 1);
10187        let b = _mm_set1_epi64x(100);
10188        let r = _mm_maskz_permutex2var_epi64(0, a, idx, b);
10189        assert_eq_m128i(r, _mm_setzero_si128());
10190        let r = _mm_maskz_permutex2var_epi64(0b00000011, a, idx, b);
10191        let e = _mm_set_epi64x(0, 100);
10192        assert_eq_m128i(r, e);
10193    }
10194
10195    #[simd_test(enable = "avx512f,avx512vl")]
10196    fn test_mm_mask2_permutex2var_epi64() {
10197        let a = _mm_set_epi64x(0, 1);
10198        let idx = _mm_set_epi64x(1, 1 << 1);
10199        let b = _mm_set1_epi64x(100);
10200        let r = _mm_mask2_permutex2var_epi64(a, idx, 0, b);
10201        assert_eq_m128i(r, idx);
10202        let r = _mm_mask2_permutex2var_epi64(a, idx, 0b00000011, b);
10203        let e = _mm_set_epi64x(0, 100);
10204        assert_eq_m128i(r, e);
10205    }
10206
10207    #[simd_test(enable = "avx512f")]
10208    fn test_mm512_permutex2var_pd() {
10209        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10210        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10211        let b = _mm512_set1_pd(100.);
10212        let r = _mm512_permutex2var_pd(a, idx, b);
10213        let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10214        assert_eq_m512d(r, e);
10215    }
10216
10217    #[simd_test(enable = "avx512f")]
10218    fn test_mm512_mask_permutex2var_pd() {
10219        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10220        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10221        let b = _mm512_set1_pd(100.);
10222        let r = _mm512_mask_permutex2var_pd(a, 0, idx, b);
10223        assert_eq_m512d(r, a);
10224        let r = _mm512_mask_permutex2var_pd(a, 0b11111111, idx, b);
10225        let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10226        assert_eq_m512d(r, e);
10227    }
10228
10229    #[simd_test(enable = "avx512f")]
10230    fn test_mm512_maskz_permutex2var_pd() {
10231        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10232        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10233        let b = _mm512_set1_pd(100.);
10234        let r = _mm512_maskz_permutex2var_pd(0, a, idx, b);
10235        assert_eq_m512d(r, _mm512_setzero_pd());
10236        let r = _mm512_maskz_permutex2var_pd(0b00001111, a, idx, b);
10237        let e = _mm512_set_pd(0., 0., 0., 0., 4., 100., 3., 100.);
10238        assert_eq_m512d(r, e);
10239    }
10240
10241    #[simd_test(enable = "avx512f")]
10242    fn test_mm512_mask2_permutex2var_pd() {
10243        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
10244        let idx = _mm512_set_epi64(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
10245        let b = _mm512_set1_pd(100.);
10246        let r = _mm512_mask2_permutex2var_pd(a, idx, 0, b);
10247        assert_eq_m512d(r, _mm512_castsi512_pd(idx));
10248        let r = _mm512_mask2_permutex2var_pd(a, idx, 0b11111111, b);
10249        let e = _mm512_set_pd(6., 100., 5., 100., 4., 100., 3., 100.);
10250        assert_eq_m512d(r, e);
10251    }
10252
10253    #[simd_test(enable = "avx512f,avx512vl")]
10254    fn test_mm256_permutex2var_pd() {
10255        let a = _mm256_set_pd(0., 1., 2., 3.);
10256        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10257        let b = _mm256_set1_pd(100.);
10258        let r = _mm256_permutex2var_pd(a, idx, b);
10259        let e = _mm256_set_pd(2., 100., 1., 100.);
10260        assert_eq_m256d(r, e);
10261    }
10262
10263    #[simd_test(enable = "avx512f,avx512vl")]
10264    fn test_mm256_mask_permutex2var_pd() {
10265        let a = _mm256_set_pd(0., 1., 2., 3.);
10266        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10267        let b = _mm256_set1_pd(100.);
10268        let r = _mm256_mask_permutex2var_pd(a, 0, idx, b);
10269        assert_eq_m256d(r, a);
10270        let r = _mm256_mask_permutex2var_pd(a, 0b00001111, idx, b);
10271        let e = _mm256_set_pd(2., 100., 1., 100.);
10272        assert_eq_m256d(r, e);
10273    }
10274
10275    #[simd_test(enable = "avx512f,avx512vl")]
10276    fn test_mm256_maskz_permutex2var_pd() {
10277        let a = _mm256_set_pd(0., 1., 2., 3.);
10278        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10279        let b = _mm256_set1_pd(100.);
10280        let r = _mm256_maskz_permutex2var_pd(0, a, idx, b);
10281        assert_eq_m256d(r, _mm256_setzero_pd());
10282        let r = _mm256_maskz_permutex2var_pd(0b00001111, a, idx, b);
10283        let e = _mm256_set_pd(2., 100., 1., 100.);
10284        assert_eq_m256d(r, e);
10285    }
10286
10287    #[simd_test(enable = "avx512f,avx512vl")]
10288    fn test_mm256_mask2_permutex2var_pd() {
10289        let a = _mm256_set_pd(0., 1., 2., 3.);
10290        let idx = _mm256_set_epi64x(1, 1 << 2, 2, 1 << 2);
10291        let b = _mm256_set1_pd(100.);
10292        let r = _mm256_mask2_permutex2var_pd(a, idx, 0, b);
10293        assert_eq_m256d(r, _mm256_castsi256_pd(idx));
10294        let r = _mm256_mask2_permutex2var_pd(a, idx, 0b00001111, b);
10295        let e = _mm256_set_pd(2., 100., 1., 100.);
10296        assert_eq_m256d(r, e);
10297    }
10298
10299    #[simd_test(enable = "avx512f,avx512vl")]
10300    fn test_mm_permutex2var_pd() {
10301        let a = _mm_set_pd(0., 1.);
10302        let idx = _mm_set_epi64x(1, 1 << 1);
10303        let b = _mm_set1_pd(100.);
10304        let r = _mm_permutex2var_pd(a, idx, b);
10305        let e = _mm_set_pd(0., 100.);
10306        assert_eq_m128d(r, e);
10307    }
10308
10309    #[simd_test(enable = "avx512f,avx512vl")]
10310    fn test_mm_mask_permutex2var_pd() {
10311        let a = _mm_set_pd(0., 1.);
10312        let idx = _mm_set_epi64x(1, 1 << 1);
10313        let b = _mm_set1_pd(100.);
10314        let r = _mm_mask_permutex2var_pd(a, 0, idx, b);
10315        assert_eq_m128d(r, a);
10316        let r = _mm_mask_permutex2var_pd(a, 0b00000011, idx, b);
10317        let e = _mm_set_pd(0., 100.);
10318        assert_eq_m128d(r, e);
10319    }
10320
10321    #[simd_test(enable = "avx512f,avx512vl")]
10322    fn test_mm_maskz_permutex2var_pd() {
10323        let a = _mm_set_pd(0., 1.);
10324        let idx = _mm_set_epi64x(1, 1 << 1);
10325        let b = _mm_set1_pd(100.);
10326        let r = _mm_maskz_permutex2var_pd(0, a, idx, b);
10327        assert_eq_m128d(r, _mm_setzero_pd());
10328        let r = _mm_maskz_permutex2var_pd(0b00000011, a, idx, b);
10329        let e = _mm_set_pd(0., 100.);
10330        assert_eq_m128d(r, e);
10331    }
10332
10333    #[simd_test(enable = "avx512f,avx512vl")]
10334    fn test_mm_mask2_permutex2var_pd() {
10335        let a = _mm_set_pd(0., 1.);
10336        let idx = _mm_set_epi64x(1, 1 << 1);
10337        let b = _mm_set1_pd(100.);
10338        let r = _mm_mask2_permutex2var_pd(a, idx, 0, b);
10339        assert_eq_m128d(r, _mm_castsi128_pd(idx));
10340        let r = _mm_mask2_permutex2var_pd(a, idx, 0b00000011, b);
10341        let e = _mm_set_pd(0., 100.);
10342        assert_eq_m128d(r, e);
10343    }
10344
10345    #[simd_test(enable = "avx512f,avx512vl")]
10346    const fn test_mm256_mask_shuffle_pd() {
10347        let a = _mm256_set_pd(1., 4., 5., 8.);
10348        let b = _mm256_set_pd(2., 3., 6., 7.);
10349        let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10350        assert_eq_m256d(r, a);
10351        let r = _mm256_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00001111, a, b);
10352        let e = _mm256_set_pd(2., 1., 6., 5.);
10353        assert_eq_m256d(r, e);
10354    }
10355
10356    #[simd_test(enable = "avx512f,avx512vl")]
10357    const fn test_mm256_maskz_shuffle_pd() {
10358        let a = _mm256_set_pd(1., 4., 5., 8.);
10359        let b = _mm256_set_pd(2., 3., 6., 7.);
10360        let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10361        assert_eq_m256d(r, _mm256_setzero_pd());
10362        let r = _mm256_maskz_shuffle_pd::<0b11_11_11_11>(0b00001111, a, b);
10363        let e = _mm256_set_pd(2., 1., 6., 5.);
10364        assert_eq_m256d(r, e);
10365    }
10366
10367    #[simd_test(enable = "avx512f,avx512vl")]
10368    const fn test_mm_mask_shuffle_pd() {
10369        let a = _mm_set_pd(1., 4.);
10370        let b = _mm_set_pd(2., 3.);
10371        let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0, a, b);
10372        assert_eq_m128d(r, a);
10373        let r = _mm_mask_shuffle_pd::<0b11_11_11_11>(a, 0b00000011, a, b);
10374        let e = _mm_set_pd(2., 1.);
10375        assert_eq_m128d(r, e);
10376    }
10377
10378    #[simd_test(enable = "avx512f,avx512vl")]
10379    const fn test_mm_maskz_shuffle_pd() {
10380        let a = _mm_set_pd(1., 4.);
10381        let b = _mm_set_pd(2., 3.);
10382        let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0, a, b);
10383        assert_eq_m128d(r, _mm_setzero_pd());
10384        let r = _mm_maskz_shuffle_pd::<0b11_11_11_11>(0b00000011, a, b);
10385        let e = _mm_set_pd(2., 1.);
10386        assert_eq_m128d(r, e);
10387    }
10388
10389    #[simd_test(enable = "avx512f")]
10390    const fn test_mm512_shuffle_i64x2() {
10391        let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10392        let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10393        let r = _mm512_shuffle_i64x2::<0b00_00_00_00>(a, b);
10394        let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10395        assert_eq_m512i(r, e);
10396    }
10397
10398    #[simd_test(enable = "avx512f")]
10399    const fn test_mm512_mask_shuffle_i64x2() {
10400        let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10401        let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10402        let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0, a, b);
10403        assert_eq_m512i(r, a);
10404        let r = _mm512_mask_shuffle_i64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10405        let e = _mm512_setr_epi64(1, 4, 1, 4, 2, 3, 2, 3);
10406        assert_eq_m512i(r, e);
10407    }
10408
10409    #[simd_test(enable = "avx512f")]
10410    const fn test_mm512_maskz_shuffle_i64x2() {
10411        let a = _mm512_setr_epi64(1, 4, 5, 8, 9, 12, 13, 16);
10412        let b = _mm512_setr_epi64(2, 3, 6, 7, 10, 11, 14, 15);
10413        let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0, a, b);
10414        assert_eq_m512i(r, _mm512_setzero_si512());
10415        let r = _mm512_maskz_shuffle_i64x2::<0b00_00_00_00>(0b00001111, a, b);
10416        let e = _mm512_setr_epi64(1, 4, 1, 4, 0, 0, 0, 0);
10417        assert_eq_m512i(r, e);
10418    }
10419
10420    #[simd_test(enable = "avx512f,avx512vl")]
10421    const fn test_mm256_shuffle_i64x2() {
10422        let a = _mm256_set_epi64x(1, 4, 5, 8);
10423        let b = _mm256_set_epi64x(2, 3, 6, 7);
10424        let r = _mm256_shuffle_i64x2::<0b00>(a, b);
10425        let e = _mm256_set_epi64x(6, 7, 5, 8);
10426        assert_eq_m256i(r, e);
10427    }
10428
10429    #[simd_test(enable = "avx512f,avx512vl")]
10430    const fn test_mm256_mask_shuffle_i64x2() {
10431        let a = _mm256_set_epi64x(1, 4, 5, 8);
10432        let b = _mm256_set_epi64x(2, 3, 6, 7);
10433        let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0, a, b);
10434        assert_eq_m256i(r, a);
10435        let r = _mm256_mask_shuffle_i64x2::<0b00>(a, 0b00001111, a, b);
10436        let e = _mm256_set_epi64x(6, 7, 5, 8);
10437        assert_eq_m256i(r, e);
10438    }
10439
10440    #[simd_test(enable = "avx512f,avx512vl")]
10441    const fn test_mm256_maskz_shuffle_i64x2() {
10442        let a = _mm256_set_epi64x(1, 4, 5, 8);
10443        let b = _mm256_set_epi64x(2, 3, 6, 7);
10444        let r = _mm256_maskz_shuffle_i64x2::<0b00>(0, a, b);
10445        assert_eq_m256i(r, _mm256_setzero_si256());
10446        let r = _mm256_maskz_shuffle_i64x2::<0b00>(0b00001111, a, b);
10447        let e = _mm256_set_epi64x(6, 7, 5, 8);
10448        assert_eq_m256i(r, e);
10449    }
10450
10451    #[simd_test(enable = "avx512f")]
10452    const fn test_mm512_shuffle_f64x2() {
10453        let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10454        let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10455        let r = _mm512_shuffle_f64x2::<0b00_00_00_00>(a, b);
10456        let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10457        assert_eq_m512d(r, e);
10458    }
10459
10460    #[simd_test(enable = "avx512f")]
10461    const fn test_mm512_mask_shuffle_f64x2() {
10462        let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10463        let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10464        let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0, a, b);
10465        assert_eq_m512d(r, a);
10466        let r = _mm512_mask_shuffle_f64x2::<0b00_00_00_00>(a, 0b11111111, a, b);
10467        let e = _mm512_setr_pd(1., 4., 1., 4., 2., 3., 2., 3.);
10468        assert_eq_m512d(r, e);
10469    }
10470
10471    #[simd_test(enable = "avx512f")]
10472    const fn test_mm512_maskz_shuffle_f64x2() {
10473        let a = _mm512_setr_pd(1., 4., 5., 8., 9., 12., 13., 16.);
10474        let b = _mm512_setr_pd(2., 3., 6., 7., 10., 11., 14., 15.);
10475        let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0, a, b);
10476        assert_eq_m512d(r, _mm512_setzero_pd());
10477        let r = _mm512_maskz_shuffle_f64x2::<0b00_00_00_00>(0b00001111, a, b);
10478        let e = _mm512_setr_pd(1., 4., 1., 4., 0., 0., 0., 0.);
10479        assert_eq_m512d(r, e);
10480    }
10481
10482    #[simd_test(enable = "avx512f,avx512vl")]
10483    const fn test_mm256_shuffle_f64x2() {
10484        let a = _mm256_set_pd(1., 4., 5., 8.);
10485        let b = _mm256_set_pd(2., 3., 6., 7.);
10486        let r = _mm256_shuffle_f64x2::<0b00>(a, b);
10487        let e = _mm256_set_pd(6., 7., 5., 8.);
10488        assert_eq_m256d(r, e);
10489    }
10490
10491    #[simd_test(enable = "avx512f,avx512vl")]
10492    const fn test_mm256_mask_shuffle_f64x2() {
10493        let a = _mm256_set_pd(1., 4., 5., 8.);
10494        let b = _mm256_set_pd(2., 3., 6., 7.);
10495        let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0, a, b);
10496        assert_eq_m256d(r, a);
10497        let r = _mm256_mask_shuffle_f64x2::<0b00>(a, 0b00001111, a, b);
10498        let e = _mm256_set_pd(6., 7., 5., 8.);
10499        assert_eq_m256d(r, e);
10500    }
10501
10502    #[simd_test(enable = "avx512f,avx512vl")]
10503    const fn test_mm256_maskz_shuffle_f64x2() {
10504        let a = _mm256_set_pd(1., 4., 5., 8.);
10505        let b = _mm256_set_pd(2., 3., 6., 7.);
10506        let r = _mm256_maskz_shuffle_f64x2::<0b00>(0, a, b);
10507        assert_eq_m256d(r, _mm256_setzero_pd());
10508        let r = _mm256_maskz_shuffle_f64x2::<0b00>(0b00001111, a, b);
10509        let e = _mm256_set_pd(6., 7., 5., 8.);
10510        assert_eq_m256d(r, e);
10511    }
10512
10513    #[simd_test(enable = "avx512f")]
10514    const fn test_mm512_movedup_pd() {
10515        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10516        let r = _mm512_movedup_pd(a);
10517        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10518        assert_eq_m512d(r, e);
10519    }
10520
10521    #[simd_test(enable = "avx512f")]
10522    const fn test_mm512_mask_movedup_pd() {
10523        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10524        let r = _mm512_mask_movedup_pd(a, 0, a);
10525        assert_eq_m512d(r, a);
10526        let r = _mm512_mask_movedup_pd(a, 0b11111111, a);
10527        let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.);
10528        assert_eq_m512d(r, e);
10529    }
10530
10531    #[simd_test(enable = "avx512f")]
10532    const fn test_mm512_maskz_movedup_pd() {
10533        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10534        let r = _mm512_maskz_movedup_pd(0, a);
10535        assert_eq_m512d(r, _mm512_setzero_pd());
10536        let r = _mm512_maskz_movedup_pd(0b00001111, a);
10537        let e = _mm512_setr_pd(1., 1., 3., 3., 0., 0., 0., 0.);
10538        assert_eq_m512d(r, e);
10539    }
10540
10541    #[simd_test(enable = "avx512f,avx512vl")]
10542    const fn test_mm256_mask_movedup_pd() {
10543        let a = _mm256_set_pd(1., 2., 3., 4.);
10544        let r = _mm256_mask_movedup_pd(a, 0, a);
10545        assert_eq_m256d(r, a);
10546        let r = _mm256_mask_movedup_pd(a, 0b00001111, a);
10547        let e = _mm256_set_pd(2., 2., 4., 4.);
10548        assert_eq_m256d(r, e);
10549    }
10550
10551    #[simd_test(enable = "avx512f,avx512vl")]
10552    const fn test_mm256_maskz_movedup_pd() {
10553        let a = _mm256_set_pd(1., 2., 3., 4.);
10554        let r = _mm256_maskz_movedup_pd(0, a);
10555        assert_eq_m256d(r, _mm256_setzero_pd());
10556        let r = _mm256_maskz_movedup_pd(0b00001111, a);
10557        let e = _mm256_set_pd(2., 2., 4., 4.);
10558        assert_eq_m256d(r, e);
10559    }
10560
10561    #[simd_test(enable = "avx512f,avx512vl")]
10562    const fn test_mm_mask_movedup_pd() {
10563        let a = _mm_set_pd(1., 2.);
10564        let r = _mm_mask_movedup_pd(a, 0, a);
10565        assert_eq_m128d(r, a);
10566        let r = _mm_mask_movedup_pd(a, 0b00000011, a);
10567        let e = _mm_set_pd(2., 2.);
10568        assert_eq_m128d(r, e);
10569    }
10570
10571    #[simd_test(enable = "avx512f,avx512vl")]
10572    const fn test_mm_maskz_movedup_pd() {
10573        let a = _mm_set_pd(1., 2.);
10574        let r = _mm_maskz_movedup_pd(0, a);
10575        assert_eq_m128d(r, _mm_setzero_pd());
10576        let r = _mm_maskz_movedup_pd(0b00000011, a);
10577        let e = _mm_set_pd(2., 2.);
10578        assert_eq_m128d(r, e);
10579    }
10580
10581    #[simd_test(enable = "avx512f")]
10582    const fn test_mm512_inserti64x4() {
10583        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10584        let b = _mm256_setr_epi64x(17, 18, 19, 20);
10585        let r = _mm512_inserti64x4::<1>(a, b);
10586        let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10587        assert_eq_m512i(r, e);
10588    }
10589
10590    #[simd_test(enable = "avx512f")]
10591    const fn test_mm512_mask_inserti64x4() {
10592        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10593        let b = _mm256_setr_epi64x(17, 18, 19, 20);
10594        let r = _mm512_mask_inserti64x4::<1>(a, 0, a, b);
10595        assert_eq_m512i(r, a);
10596        let r = _mm512_mask_inserti64x4::<1>(a, 0b11111111, a, b);
10597        let e = _mm512_setr_epi64(1, 2, 3, 4, 17, 18, 19, 20);
10598        assert_eq_m512i(r, e);
10599    }
10600
10601    #[simd_test(enable = "avx512f")]
10602    const fn test_mm512_maskz_inserti64x4() {
10603        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
10604        let b = _mm256_setr_epi64x(17, 18, 19, 20);
10605        let r = _mm512_maskz_inserti64x4::<1>(0, a, b);
10606        assert_eq_m512i(r, _mm512_setzero_si512());
10607        let r = _mm512_maskz_inserti64x4::<1>(0b00001111, a, b);
10608        let e = _mm512_setr_epi64(1, 2, 3, 4, 0, 0, 0, 0);
10609        assert_eq_m512i(r, e);
10610    }
10611
10612    #[simd_test(enable = "avx512f")]
10613    const fn test_mm512_insertf64x4() {
10614        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10615        let b = _mm256_setr_pd(17., 18., 19., 20.);
10616        let r = _mm512_insertf64x4::<1>(a, b);
10617        let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10618        assert_eq_m512d(r, e);
10619    }
10620
10621    #[simd_test(enable = "avx512f")]
10622    const fn test_mm512_mask_insertf64x4() {
10623        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10624        let b = _mm256_setr_pd(17., 18., 19., 20.);
10625        let r = _mm512_mask_insertf64x4::<1>(a, 0, a, b);
10626        assert_eq_m512d(r, a);
10627        let r = _mm512_mask_insertf64x4::<1>(a, 0b11111111, a, b);
10628        let e = _mm512_setr_pd(1., 2., 3., 4., 17., 18., 19., 20.);
10629        assert_eq_m512d(r, e);
10630    }
10631
10632    #[simd_test(enable = "avx512f")]
10633    const fn test_mm512_maskz_insertf64x4() {
10634        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
10635        let b = _mm256_setr_pd(17., 18., 19., 20.);
10636        let r = _mm512_maskz_insertf64x4::<1>(0, a, b);
10637        assert_eq_m512d(r, _mm512_setzero_pd());
10638        let r = _mm512_maskz_insertf64x4::<1>(0b00001111, a, b);
10639        let e = _mm512_setr_pd(1., 2., 3., 4., 0., 0., 0., 0.);
10640        assert_eq_m512d(r, e);
10641    }
10642
10643    #[simd_test(enable = "avx512f")]
10644    const fn test_mm512_castpd128_pd512() {
10645        let a = _mm_setr_pd(17., 18.);
10646        let r = _mm512_castpd128_pd512(a);
10647        assert_eq_m128d(_mm512_castpd512_pd128(r), a);
10648    }
10649
10650    #[simd_test(enable = "avx512f")]
10651    const fn test_mm512_castpd256_pd512() {
10652        let a = _mm256_setr_pd(17., 18., 19., 20.);
10653        let r = _mm512_castpd256_pd512(a);
10654        assert_eq_m256d(_mm512_castpd512_pd256(r), a);
10655    }
10656
10657    #[simd_test(enable = "avx512f")]
10658    const fn test_mm512_zextpd128_pd512() {
10659        let a = _mm_setr_pd(17., 18.);
10660        let r = _mm512_zextpd128_pd512(a);
10661        let e = _mm512_setr_pd(17., 18., 0., 0., 0., 0., 0., 0.);
10662        assert_eq_m512d(r, e);
10663    }
10664
10665    #[simd_test(enable = "avx512f")]
10666    const fn test_mm512_zextpd256_pd512() {
10667        let a = _mm256_setr_pd(17., 18., 19., 20.);
10668        let r = _mm512_zextpd256_pd512(a);
10669        let e = _mm512_setr_pd(17., 18., 19., 20., 0., 0., 0., 0.);
10670        assert_eq_m512d(r, e);
10671    }
10672
10673    #[simd_test(enable = "avx512f")]
10674    const fn test_mm512_castpd512_pd128() {
10675        let a = _mm512_setr_pd(17., 18., -1., -1., -1., -1., -1., -1.);
10676        let r = _mm512_castpd512_pd128(a);
10677        let e = _mm_setr_pd(17., 18.);
10678        assert_eq_m128d(r, e);
10679    }
10680
10681    #[simd_test(enable = "avx512f")]
10682    const fn test_mm512_castpd512_pd256() {
10683        let a = _mm512_setr_pd(17., 18., 19., 20., -1., -1., -1., -1.);
10684        let r = _mm512_castpd512_pd256(a);
10685        let e = _mm256_setr_pd(17., 18., 19., 20.);
10686        assert_eq_m256d(r, e);
10687    }
10688
10689    #[simd_test(enable = "avx512f")]
10690    const fn test_mm512_castpd_ps() {
10691        let a = _mm512_set1_pd(1.);
10692        let r = _mm512_castpd_ps(a);
10693        let e = _mm512_set_ps(
10694            1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0, 1.875, 0.0,
10695            1.875, 0.0,
10696        );
10697        assert_eq_m512(r, e);
10698    }
10699
10700    #[simd_test(enable = "avx512f")]
10701    const fn test_mm512_castpd_si512() {
10702        let a = _mm512_set1_pd(1.);
10703        let r = _mm512_castpd_si512(a);
10704        let e = _mm512_set_epi32(
10705            1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248, 0, 1072693248,
10706            0, 1072693248, 0, 1072693248, 0,
10707        );
10708        assert_eq_m512i(r, e);
10709    }
10710
10711    #[simd_test(enable = "avx512f")]
10712    const fn test_mm512_castsi128_si512() {
10713        let a = _mm_setr_epi64x(17, 18);
10714        let r = _mm512_castsi128_si512(a);
10715        assert_eq_m128i(_mm512_castsi512_si128(r), a);
10716    }
10717
10718    #[simd_test(enable = "avx512f")]
10719    const fn test_mm512_castsi256_si512() {
10720        let a = _mm256_setr_epi64x(17, 18, 19, 20);
10721        let r = _mm512_castsi256_si512(a);
10722        assert_eq_m256i(_mm512_castsi512_si256(r), a);
10723    }
10724
10725    #[simd_test(enable = "avx512f")]
10726    const fn test_mm512_zextsi128_si512() {
10727        let a = _mm_setr_epi64x(17, 18);
10728        let r = _mm512_zextsi128_si512(a);
10729        let e = _mm512_setr_epi64(17, 18, 0, 0, 0, 0, 0, 0);
10730        assert_eq_m512i(r, e);
10731    }
10732
10733    #[simd_test(enable = "avx512f")]
10734    const fn test_mm512_zextsi256_si512() {
10735        let a = _mm256_setr_epi64x(17, 18, 19, 20);
10736        let r = _mm512_zextsi256_si512(a);
10737        let e = _mm512_setr_epi64(17, 18, 19, 20, 0, 0, 0, 0);
10738        assert_eq_m512i(r, e);
10739    }
10740
10741    #[simd_test(enable = "avx512f")]
10742    const fn test_mm512_castsi512_si128() {
10743        let a = _mm512_setr_epi64(17, 18, -1, -1, -1, -1, -1, -1);
10744        let r = _mm512_castsi512_si128(a);
10745        let e = _mm_setr_epi64x(17, 18);
10746        assert_eq_m128i(r, e);
10747    }
10748
10749    #[simd_test(enable = "avx512f")]
10750    const fn test_mm512_castsi512_si256() {
10751        let a = _mm512_setr_epi64(17, 18, 19, 20, -1, -1, -1, -1);
10752        let r = _mm512_castsi512_si256(a);
10753        let e = _mm256_setr_epi64x(17, 18, 19, 20);
10754        assert_eq_m256i(r, e);
10755    }
10756
10757    #[simd_test(enable = "avx512f")]
10758    const fn test_mm512_castsi512_ps() {
10759        let a = _mm512_set1_epi64(1 << 62);
10760        let r = _mm512_castsi512_ps(a);
10761        let e = _mm512_set_ps(
10762            2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0., 2., 0.,
10763        );
10764        assert_eq_m512(r, e);
10765    }
10766
10767    #[simd_test(enable = "avx512f")]
10768    const fn test_mm512_castsi512_pd() {
10769        let a = _mm512_set1_epi64(1 << 62);
10770        let r = _mm512_castsi512_pd(a);
10771        let e = _mm512_set_pd(2., 2., 2., 2., 2., 2., 2., 2.);
10772        assert_eq_m512d(r, e);
10773    }
10774
10775    #[simd_test(enable = "avx512f")]
10776    const fn test_mm512_broadcastq_epi64() {
10777        let a = _mm_setr_epi64x(17, 18);
10778        let r = _mm512_broadcastq_epi64(a);
10779        let e = _mm512_set1_epi64(17);
10780        assert_eq_m512i(r, e);
10781    }
10782
10783    #[simd_test(enable = "avx512f")]
10784    const fn test_mm512_mask_broadcastq_epi64() {
10785        let src = _mm512_set1_epi64(18);
10786        let a = _mm_setr_epi64x(17, 18);
10787        let r = _mm512_mask_broadcastq_epi64(src, 0, a);
10788        assert_eq_m512i(r, src);
10789        let r = _mm512_mask_broadcastq_epi64(src, 0b11111111, a);
10790        let e = _mm512_set1_epi64(17);
10791        assert_eq_m512i(r, e);
10792    }
10793
10794    #[simd_test(enable = "avx512f")]
10795    const fn test_mm512_maskz_broadcastq_epi64() {
10796        let a = _mm_setr_epi64x(17, 18);
10797        let r = _mm512_maskz_broadcastq_epi64(0, a);
10798        assert_eq_m512i(r, _mm512_setzero_si512());
10799        let r = _mm512_maskz_broadcastq_epi64(0b00001111, a);
10800        let e = _mm512_set_epi64(0, 0, 0, 0, 17, 17, 17, 17);
10801        assert_eq_m512i(r, e);
10802    }
10803
10804    #[simd_test(enable = "avx512f,avx512vl")]
10805    const fn test_mm256_mask_broadcastq_epi64() {
10806        let src = _mm256_set1_epi64x(18);
10807        let a = _mm_set_epi64x(17, 18);
10808        let r = _mm256_mask_broadcastq_epi64(src, 0, a);
10809        assert_eq_m256i(r, src);
10810        let r = _mm256_mask_broadcastq_epi64(src, 0b00001111, a);
10811        let e = _mm256_set1_epi64x(18);
10812        assert_eq_m256i(r, e);
10813    }
10814
10815    #[simd_test(enable = "avx512f,avx512vl")]
10816    const fn test_mm256_maskz_broadcastq_epi64() {
10817        let a = _mm_set_epi64x(17, 18);
10818        let r = _mm256_maskz_broadcastq_epi64(0, a);
10819        assert_eq_m256i(r, _mm256_setzero_si256());
10820        let r = _mm256_maskz_broadcastq_epi64(0b00001111, a);
10821        let e = _mm256_set1_epi64x(18);
10822        assert_eq_m256i(r, e);
10823    }
10824
10825    #[simd_test(enable = "avx512f,avx512vl")]
10826    const fn test_mm_mask_broadcastq_epi64() {
10827        let src = _mm_set1_epi64x(18);
10828        let a = _mm_set_epi64x(17, 18);
10829        let r = _mm_mask_broadcastq_epi64(src, 0, a);
10830        assert_eq_m128i(r, src);
10831        let r = _mm_mask_broadcastq_epi64(src, 0b00000011, a);
10832        let e = _mm_set1_epi64x(18);
10833        assert_eq_m128i(r, e);
10834    }
10835
10836    #[simd_test(enable = "avx512f,avx512vl")]
10837    const fn test_mm_maskz_broadcastq_epi64() {
10838        let a = _mm_set_epi64x(17, 18);
10839        let r = _mm_maskz_broadcastq_epi64(0, a);
10840        assert_eq_m128i(r, _mm_setzero_si128());
10841        let r = _mm_maskz_broadcastq_epi64(0b00000011, a);
10842        let e = _mm_set1_epi64x(18);
10843        assert_eq_m128i(r, e);
10844    }
10845
10846    #[simd_test(enable = "avx512f")]
10847    const fn test_mm512_broadcastsd_pd() {
10848        let a = _mm_set_pd(17., 18.);
10849        let r = _mm512_broadcastsd_pd(a);
10850        let e = _mm512_set1_pd(18.);
10851        assert_eq_m512d(r, e);
10852    }
10853
10854    #[simd_test(enable = "avx512f")]
10855    const fn test_mm512_mask_broadcastsd_pd() {
10856        let src = _mm512_set1_pd(18.);
10857        let a = _mm_set_pd(17., 18.);
10858        let r = _mm512_mask_broadcastsd_pd(src, 0, a);
10859        assert_eq_m512d(r, src);
10860        let r = _mm512_mask_broadcastsd_pd(src, 0b11111111, a);
10861        let e = _mm512_set1_pd(18.);
10862        assert_eq_m512d(r, e);
10863    }
10864
10865    #[simd_test(enable = "avx512f")]
10866    const fn test_mm512_maskz_broadcastsd_pd() {
10867        let a = _mm_set_pd(17., 18.);
10868        let r = _mm512_maskz_broadcastsd_pd(0, a);
10869        assert_eq_m512d(r, _mm512_setzero_pd());
10870        let r = _mm512_maskz_broadcastsd_pd(0b00001111, a);
10871        let e = _mm512_set_pd(0., 0., 0., 0., 18., 18., 18., 18.);
10872        assert_eq_m512d(r, e);
10873    }
10874
10875    #[simd_test(enable = "avx512f,avx512vl")]
10876    const fn test_mm256_mask_broadcastsd_pd() {
10877        let src = _mm256_set1_pd(18.);
10878        let a = _mm_set_pd(17., 18.);
10879        let r = _mm256_mask_broadcastsd_pd(src, 0, a);
10880        assert_eq_m256d(r, src);
10881        let r = _mm256_mask_broadcastsd_pd(src, 0b00001111, a);
10882        let e = _mm256_set1_pd(18.);
10883        assert_eq_m256d(r, e);
10884    }
10885
10886    #[simd_test(enable = "avx512f,avx512vl")]
10887    const fn test_mm256_maskz_broadcastsd_pd() {
10888        let a = _mm_set_pd(17., 18.);
10889        let r = _mm256_maskz_broadcastsd_pd(0, a);
10890        assert_eq_m256d(r, _mm256_setzero_pd());
10891        let r = _mm256_maskz_broadcastsd_pd(0b00001111, a);
10892        let e = _mm256_set1_pd(18.);
10893        assert_eq_m256d(r, e);
10894    }
10895
10896    #[simd_test(enable = "avx512f")]
10897    const fn test_mm512_broadcast_i64x4() {
10898        let a = _mm256_set_epi64x(17, 18, 19, 20);
10899        let r = _mm512_broadcast_i64x4(a);
10900        let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10901        assert_eq_m512i(r, e);
10902    }
10903
10904    #[simd_test(enable = "avx512f")]
10905    const fn test_mm512_mask_broadcast_i64x4() {
10906        let src = _mm512_set1_epi64(18);
10907        let a = _mm256_set_epi64x(17, 18, 19, 20);
10908        let r = _mm512_mask_broadcast_i64x4(src, 0, a);
10909        assert_eq_m512i(r, src);
10910        let r = _mm512_mask_broadcast_i64x4(src, 0b11111111, a);
10911        let e = _mm512_set_epi64(17, 18, 19, 20, 17, 18, 19, 20);
10912        assert_eq_m512i(r, e);
10913    }
10914
10915    #[simd_test(enable = "avx512f")]
10916    const fn test_mm512_maskz_broadcast_i64x4() {
10917        let a = _mm256_set_epi64x(17, 18, 19, 20);
10918        let r = _mm512_maskz_broadcast_i64x4(0, a);
10919        assert_eq_m512i(r, _mm512_setzero_si512());
10920        let r = _mm512_maskz_broadcast_i64x4(0b00001111, a);
10921        let e = _mm512_set_epi64(0, 0, 0, 0, 17, 18, 19, 20);
10922        assert_eq_m512i(r, e);
10923    }
10924
10925    #[simd_test(enable = "avx512f")]
10926    const fn test_mm512_broadcast_f64x4() {
10927        let a = _mm256_set_pd(17., 18., 19., 20.);
10928        let r = _mm512_broadcast_f64x4(a);
10929        let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10930        assert_eq_m512d(r, e);
10931    }
10932
10933    #[simd_test(enable = "avx512f")]
10934    const fn test_mm512_mask_broadcast_f64x4() {
10935        let src = _mm512_set1_pd(18.);
10936        let a = _mm256_set_pd(17., 18., 19., 20.);
10937        let r = _mm512_mask_broadcast_f64x4(src, 0, a);
10938        assert_eq_m512d(r, src);
10939        let r = _mm512_mask_broadcast_f64x4(src, 0b11111111, a);
10940        let e = _mm512_set_pd(17., 18., 19., 20., 17., 18., 19., 20.);
10941        assert_eq_m512d(r, e);
10942    }
10943
10944    #[simd_test(enable = "avx512f")]
10945    const fn test_mm512_maskz_broadcast_f64x4() {
10946        let a = _mm256_set_pd(17., 18., 19., 20.);
10947        let r = _mm512_maskz_broadcast_f64x4(0, a);
10948        assert_eq_m512d(r, _mm512_setzero_pd());
10949        let r = _mm512_maskz_broadcast_f64x4(0b00001111, a);
10950        let e = _mm512_set_pd(0., 0., 0., 0., 17., 18., 19., 20.);
10951        assert_eq_m512d(r, e);
10952    }
10953
10954    #[simd_test(enable = "avx512f")]
10955    const fn test_mm512_mask_blend_epi64() {
10956        let a = _mm512_set1_epi64(1);
10957        let b = _mm512_set1_epi64(2);
10958        let r = _mm512_mask_blend_epi64(0b11110000, a, b);
10959        let e = _mm512_set_epi64(2, 2, 2, 2, 1, 1, 1, 1);
10960        assert_eq_m512i(r, e);
10961    }
10962
10963    #[simd_test(enable = "avx512f,avx512vl")]
10964    const fn test_mm256_mask_blend_epi64() {
10965        let a = _mm256_set1_epi64x(1);
10966        let b = _mm256_set1_epi64x(2);
10967        let r = _mm256_mask_blend_epi64(0b00001111, a, b);
10968        let e = _mm256_set1_epi64x(2);
10969        assert_eq_m256i(r, e);
10970    }
10971
10972    #[simd_test(enable = "avx512f,avx512vl")]
10973    const fn test_mm_mask_blend_epi64() {
10974        let a = _mm_set1_epi64x(1);
10975        let b = _mm_set1_epi64x(2);
10976        let r = _mm_mask_blend_epi64(0b00000011, a, b);
10977        let e = _mm_set1_epi64x(2);
10978        assert_eq_m128i(r, e);
10979    }
10980
10981    #[simd_test(enable = "avx512f")]
10982    const fn test_mm512_mask_blend_pd() {
10983        let a = _mm512_set1_pd(1.);
10984        let b = _mm512_set1_pd(2.);
10985        let r = _mm512_mask_blend_pd(0b11110000, a, b);
10986        let e = _mm512_set_pd(2., 2., 2., 2., 1., 1., 1., 1.);
10987        assert_eq_m512d(r, e);
10988    }
10989
10990    #[simd_test(enable = "avx512f,avx512vl")]
10991    const fn test_mm256_mask_blend_pd() {
10992        let a = _mm256_set1_pd(1.);
10993        let b = _mm256_set1_pd(2.);
10994        let r = _mm256_mask_blend_pd(0b00001111, a, b);
10995        let e = _mm256_set1_pd(2.);
10996        assert_eq_m256d(r, e);
10997    }
10998
10999    #[simd_test(enable = "avx512f,avx512vl")]
11000    const fn test_mm_mask_blend_pd() {
11001        let a = _mm_set1_pd(1.);
11002        let b = _mm_set1_pd(2.);
11003        let r = _mm_mask_blend_pd(0b00000011, a, b);
11004        let e = _mm_set1_pd(2.);
11005        assert_eq_m128d(r, e);
11006    }
11007
11008    #[simd_test(enable = "avx512f")]
11009    const fn test_mm512_unpackhi_epi64() {
11010        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11011        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11012        let r = _mm512_unpackhi_epi64(a, b);
11013        let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
11014        assert_eq_m512i(r, e);
11015    }
11016
11017    #[simd_test(enable = "avx512f")]
11018    const fn test_mm512_mask_unpackhi_epi64() {
11019        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11020        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11021        let r = _mm512_mask_unpackhi_epi64(a, 0, a, b);
11022        assert_eq_m512i(r, a);
11023        let r = _mm512_mask_unpackhi_epi64(a, 0b11111111, a, b);
11024        let e = _mm512_set_epi64(17, 1, 19, 3, 21, 5, 23, 7);
11025        assert_eq_m512i(r, e);
11026    }
11027
11028    #[simd_test(enable = "avx512f")]
11029    const fn test_mm512_maskz_unpackhi_epi64() {
11030        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11031        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11032        let r = _mm512_maskz_unpackhi_epi64(0, a, b);
11033        assert_eq_m512i(r, _mm512_setzero_si512());
11034        let r = _mm512_maskz_unpackhi_epi64(0b00001111, a, b);
11035        let e = _mm512_set_epi64(0, 0, 0, 0, 21, 5, 23, 7);
11036        assert_eq_m512i(r, e);
11037    }
11038
11039    #[simd_test(enable = "avx512f,avx512vl")]
11040    const fn test_mm256_mask_unpackhi_epi64() {
11041        let a = _mm256_set_epi64x(1, 2, 3, 4);
11042        let b = _mm256_set_epi64x(17, 18, 19, 20);
11043        let r = _mm256_mask_unpackhi_epi64(a, 0, a, b);
11044        assert_eq_m256i(r, a);
11045        let r = _mm256_mask_unpackhi_epi64(a, 0b00001111, a, b);
11046        let e = _mm256_set_epi64x(17, 1, 19, 3);
11047        assert_eq_m256i(r, e);
11048    }
11049
11050    #[simd_test(enable = "avx512f,avx512vl")]
11051    const fn test_mm256_maskz_unpackhi_epi64() {
11052        let a = _mm256_set_epi64x(1, 2, 3, 4);
11053        let b = _mm256_set_epi64x(17, 18, 19, 20);
11054        let r = _mm256_maskz_unpackhi_epi64(0, a, b);
11055        assert_eq_m256i(r, _mm256_setzero_si256());
11056        let r = _mm256_maskz_unpackhi_epi64(0b00001111, a, b);
11057        let e = _mm256_set_epi64x(17, 1, 19, 3);
11058        assert_eq_m256i(r, e);
11059    }
11060
11061    #[simd_test(enable = "avx512f,avx512vl")]
11062    const fn test_mm_mask_unpackhi_epi64() {
11063        let a = _mm_set_epi64x(1, 2);
11064        let b = _mm_set_epi64x(17, 18);
11065        let r = _mm_mask_unpackhi_epi64(a, 0, a, b);
11066        assert_eq_m128i(r, a);
11067        let r = _mm_mask_unpackhi_epi64(a, 0b00000011, a, b);
11068        let e = _mm_set_epi64x(17, 1);
11069        assert_eq_m128i(r, e);
11070    }
11071
11072    #[simd_test(enable = "avx512f,avx512vl")]
11073    const fn test_mm_maskz_unpackhi_epi64() {
11074        let a = _mm_set_epi64x(1, 2);
11075        let b = _mm_set_epi64x(17, 18);
11076        let r = _mm_maskz_unpackhi_epi64(0, a, b);
11077        assert_eq_m128i(r, _mm_setzero_si128());
11078        let r = _mm_maskz_unpackhi_epi64(0b00000011, a, b);
11079        let e = _mm_set_epi64x(17, 1);
11080        assert_eq_m128i(r, e);
11081    }
11082
11083    #[simd_test(enable = "avx512f")]
11084    const fn test_mm512_unpackhi_pd() {
11085        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11086        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11087        let r = _mm512_unpackhi_pd(a, b);
11088        let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
11089        assert_eq_m512d(r, e);
11090    }
11091
11092    #[simd_test(enable = "avx512f")]
11093    const fn test_mm512_mask_unpackhi_pd() {
11094        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11095        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11096        let r = _mm512_mask_unpackhi_pd(a, 0, a, b);
11097        assert_eq_m512d(r, a);
11098        let r = _mm512_mask_unpackhi_pd(a, 0b11111111, a, b);
11099        let e = _mm512_set_pd(17., 1., 19., 3., 21., 5., 23., 7.);
11100        assert_eq_m512d(r, e);
11101    }
11102
11103    #[simd_test(enable = "avx512f")]
11104    const fn test_mm512_maskz_unpackhi_pd() {
11105        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11106        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11107        let r = _mm512_maskz_unpackhi_pd(0, a, b);
11108        assert_eq_m512d(r, _mm512_setzero_pd());
11109        let r = _mm512_maskz_unpackhi_pd(0b00001111, a, b);
11110        let e = _mm512_set_pd(0., 0., 0., 0., 21., 5., 23., 7.);
11111        assert_eq_m512d(r, e);
11112    }
11113
11114    #[simd_test(enable = "avx512f,avx512vl")]
11115    const fn test_mm256_mask_unpackhi_pd() {
11116        let a = _mm256_set_pd(1., 2., 3., 4.);
11117        let b = _mm256_set_pd(17., 18., 19., 20.);
11118        let r = _mm256_mask_unpackhi_pd(a, 0, a, b);
11119        assert_eq_m256d(r, a);
11120        let r = _mm256_mask_unpackhi_pd(a, 0b00001111, a, b);
11121        let e = _mm256_set_pd(17., 1., 19., 3.);
11122        assert_eq_m256d(r, e);
11123    }
11124
11125    #[simd_test(enable = "avx512f,avx512vl")]
11126    const fn test_mm256_maskz_unpackhi_pd() {
11127        let a = _mm256_set_pd(1., 2., 3., 4.);
11128        let b = _mm256_set_pd(17., 18., 19., 20.);
11129        let r = _mm256_maskz_unpackhi_pd(0, a, b);
11130        assert_eq_m256d(r, _mm256_setzero_pd());
11131        let r = _mm256_maskz_unpackhi_pd(0b00001111, a, b);
11132        let e = _mm256_set_pd(17., 1., 19., 3.);
11133        assert_eq_m256d(r, e);
11134    }
11135
11136    #[simd_test(enable = "avx512f,avx512vl")]
11137    const fn test_mm_mask_unpackhi_pd() {
11138        let a = _mm_set_pd(1., 2.);
11139        let b = _mm_set_pd(17., 18.);
11140        let r = _mm_mask_unpackhi_pd(a, 0, a, b);
11141        assert_eq_m128d(r, a);
11142        let r = _mm_mask_unpackhi_pd(a, 0b00000011, a, b);
11143        let e = _mm_set_pd(17., 1.);
11144        assert_eq_m128d(r, e);
11145    }
11146
11147    #[simd_test(enable = "avx512f,avx512vl")]
11148    const fn test_mm_maskz_unpackhi_pd() {
11149        let a = _mm_set_pd(1., 2.);
11150        let b = _mm_set_pd(17., 18.);
11151        let r = _mm_maskz_unpackhi_pd(0, a, b);
11152        assert_eq_m128d(r, _mm_setzero_pd());
11153        let r = _mm_maskz_unpackhi_pd(0b00000011, a, b);
11154        let e = _mm_set_pd(17., 1.);
11155        assert_eq_m128d(r, e);
11156    }
11157
11158    #[simd_test(enable = "avx512f")]
11159    const fn test_mm512_unpacklo_epi64() {
11160        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11161        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11162        let r = _mm512_unpacklo_epi64(a, b);
11163        let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11164        assert_eq_m512i(r, e);
11165    }
11166
11167    #[simd_test(enable = "avx512f")]
11168    const fn test_mm512_mask_unpacklo_epi64() {
11169        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11170        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11171        let r = _mm512_mask_unpacklo_epi64(a, 0, a, b);
11172        assert_eq_m512i(r, a);
11173        let r = _mm512_mask_unpacklo_epi64(a, 0b11111111, a, b);
11174        let e = _mm512_set_epi64(18, 2, 20, 4, 22, 6, 24, 8);
11175        assert_eq_m512i(r, e);
11176    }
11177
11178    #[simd_test(enable = "avx512f")]
11179    const fn test_mm512_maskz_unpacklo_epi64() {
11180        let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11181        let b = _mm512_set_epi64(17, 18, 19, 20, 21, 22, 23, 24);
11182        let r = _mm512_maskz_unpacklo_epi64(0, a, b);
11183        assert_eq_m512i(r, _mm512_setzero_si512());
11184        let r = _mm512_maskz_unpacklo_epi64(0b00001111, a, b);
11185        let e = _mm512_set_epi64(0, 0, 0, 0, 22, 6, 24, 8);
11186        assert_eq_m512i(r, e);
11187    }
11188
11189    #[simd_test(enable = "avx512f,avx512vl")]
11190    const fn test_mm256_mask_unpacklo_epi64() {
11191        let a = _mm256_set_epi64x(1, 2, 3, 4);
11192        let b = _mm256_set_epi64x(17, 18, 19, 20);
11193        let r = _mm256_mask_unpacklo_epi64(a, 0, a, b);
11194        assert_eq_m256i(r, a);
11195        let r = _mm256_mask_unpacklo_epi64(a, 0b00001111, a, b);
11196        let e = _mm256_set_epi64x(18, 2, 20, 4);
11197        assert_eq_m256i(r, e);
11198    }
11199
11200    #[simd_test(enable = "avx512f,avx512vl")]
11201    const fn test_mm256_maskz_unpacklo_epi64() {
11202        let a = _mm256_set_epi64x(1, 2, 3, 4);
11203        let b = _mm256_set_epi64x(17, 18, 19, 20);
11204        let r = _mm256_maskz_unpacklo_epi64(0, a, b);
11205        assert_eq_m256i(r, _mm256_setzero_si256());
11206        let r = _mm256_maskz_unpacklo_epi64(0b00001111, a, b);
11207        let e = _mm256_set_epi64x(18, 2, 20, 4);
11208        assert_eq_m256i(r, e);
11209    }
11210
11211    #[simd_test(enable = "avx512f,avx512vl")]
11212    const fn test_mm_mask_unpacklo_epi64() {
11213        let a = _mm_set_epi64x(1, 2);
11214        let b = _mm_set_epi64x(17, 18);
11215        let r = _mm_mask_unpacklo_epi64(a, 0, a, b);
11216        assert_eq_m128i(r, a);
11217        let r = _mm_mask_unpacklo_epi64(a, 0b00000011, a, b);
11218        let e = _mm_set_epi64x(18, 2);
11219        assert_eq_m128i(r, e);
11220    }
11221
11222    #[simd_test(enable = "avx512f,avx512vl")]
11223    const fn test_mm_maskz_unpacklo_epi64() {
11224        let a = _mm_set_epi64x(1, 2);
11225        let b = _mm_set_epi64x(17, 18);
11226        let r = _mm_maskz_unpacklo_epi64(0, a, b);
11227        assert_eq_m128i(r, _mm_setzero_si128());
11228        let r = _mm_maskz_unpacklo_epi64(0b00000011, a, b);
11229        let e = _mm_set_epi64x(18, 2);
11230        assert_eq_m128i(r, e);
11231    }
11232
11233    #[simd_test(enable = "avx512f")]
11234    const fn test_mm512_unpacklo_pd() {
11235        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11236        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11237        let r = _mm512_unpacklo_pd(a, b);
11238        let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11239        assert_eq_m512d(r, e);
11240    }
11241
11242    #[simd_test(enable = "avx512f")]
11243    const fn test_mm512_mask_unpacklo_pd() {
11244        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11245        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11246        let r = _mm512_mask_unpacklo_pd(a, 0, a, b);
11247        assert_eq_m512d(r, a);
11248        let r = _mm512_mask_unpacklo_pd(a, 0b11111111, a, b);
11249        let e = _mm512_set_pd(18., 2., 20., 4., 22., 6., 24., 8.);
11250        assert_eq_m512d(r, e);
11251    }
11252
11253    #[simd_test(enable = "avx512f")]
11254    const fn test_mm512_maskz_unpacklo_pd() {
11255        let a = _mm512_set_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11256        let b = _mm512_set_pd(17., 18., 19., 20., 21., 22., 23., 24.);
11257        let r = _mm512_maskz_unpacklo_pd(0, a, b);
11258        assert_eq_m512d(r, _mm512_setzero_pd());
11259        let r = _mm512_maskz_unpacklo_pd(0b00001111, a, b);
11260        let e = _mm512_set_pd(0., 0., 0., 0., 22., 6., 24., 8.);
11261        assert_eq_m512d(r, e);
11262    }
11263
11264    #[simd_test(enable = "avx512f,avx512vl")]
11265    const fn test_mm256_mask_unpacklo_pd() {
11266        let a = _mm256_set_pd(1., 2., 3., 4.);
11267        let b = _mm256_set_pd(17., 18., 19., 20.);
11268        let r = _mm256_mask_unpacklo_pd(a, 0, a, b);
11269        assert_eq_m256d(r, a);
11270        let r = _mm256_mask_unpacklo_pd(a, 0b00001111, a, b);
11271        let e = _mm256_set_pd(18., 2., 20., 4.);
11272        assert_eq_m256d(r, e);
11273    }
11274
11275    #[simd_test(enable = "avx512f,avx512vl")]
11276    const fn test_mm256_maskz_unpacklo_pd() {
11277        let a = _mm256_set_pd(1., 2., 3., 4.);
11278        let b = _mm256_set_pd(17., 18., 19., 20.);
11279        let r = _mm256_maskz_unpacklo_pd(0, a, b);
11280        assert_eq_m256d(r, _mm256_setzero_pd());
11281        let r = _mm256_maskz_unpacklo_pd(0b00001111, a, b);
11282        let e = _mm256_set_pd(18., 2., 20., 4.);
11283        assert_eq_m256d(r, e);
11284    }
11285
11286    #[simd_test(enable = "avx512f,avx512vl")]
11287    const fn test_mm_mask_unpacklo_pd() {
11288        let a = _mm_set_pd(1., 2.);
11289        let b = _mm_set_pd(17., 18.);
11290        let r = _mm_mask_unpacklo_pd(a, 0, a, b);
11291        assert_eq_m128d(r, a);
11292        let r = _mm_mask_unpacklo_pd(a, 0b00000011, a, b);
11293        let e = _mm_set_pd(18., 2.);
11294        assert_eq_m128d(r, e);
11295    }
11296
11297    #[simd_test(enable = "avx512f,avx512vl")]
11298    const fn test_mm_maskz_unpacklo_pd() {
11299        let a = _mm_set_pd(1., 2.);
11300        let b = _mm_set_pd(17., 18.);
11301        let r = _mm_maskz_unpacklo_pd(0, a, b);
11302        assert_eq_m128d(r, _mm_setzero_pd());
11303        let r = _mm_maskz_unpacklo_pd(0b00000011, a, b);
11304        let e = _mm_set_pd(18., 2.);
11305        assert_eq_m128d(r, e);
11306    }
11307
11308    #[simd_test(enable = "avx512f")]
11309    const fn test_mm512_alignr_epi64() {
11310        let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11311        let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11312        let r = _mm512_alignr_epi64::<0>(a, b);
11313        assert_eq_m512i(r, b);
11314        let r = _mm512_alignr_epi64::<8>(a, b);
11315        assert_eq_m512i(r, b);
11316        let r = _mm512_alignr_epi64::<1>(a, b);
11317        let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11318        assert_eq_m512i(r, e);
11319    }
11320
11321    #[simd_test(enable = "avx512f")]
11322    const fn test_mm512_mask_alignr_epi64() {
11323        let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11324        let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11325        let r = _mm512_mask_alignr_epi64::<1>(a, 0, a, b);
11326        assert_eq_m512i(r, a);
11327        let r = _mm512_mask_alignr_epi64::<1>(a, 0b11111111, a, b);
11328        let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10);
11329        assert_eq_m512i(r, e);
11330    }
11331
11332    #[simd_test(enable = "avx512f")]
11333    const fn test_mm512_maskz_alignr_epi64() {
11334        let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1);
11335        let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9);
11336        let r = _mm512_maskz_alignr_epi64::<1>(0, a, b);
11337        assert_eq_m512i(r, _mm512_setzero_si512());
11338        let r = _mm512_maskz_alignr_epi64::<1>(0b00001111, a, b);
11339        let e = _mm512_set_epi64(0, 0, 0, 0, 13, 12, 11, 10);
11340        assert_eq_m512i(r, e);
11341    }
11342
11343    #[simd_test(enable = "avx512f,avx512vl")]
11344    const fn test_mm256_alignr_epi64() {
11345        let a = _mm256_set_epi64x(4, 3, 2, 1);
11346        let b = _mm256_set_epi64x(8, 7, 6, 5);
11347        let r = _mm256_alignr_epi64::<0>(a, b);
11348        let e = _mm256_set_epi64x(8, 7, 6, 5);
11349        assert_eq_m256i(r, e);
11350        let r = _mm256_alignr_epi64::<1>(a, b);
11351        let e = _mm256_set_epi64x(1, 8, 7, 6);
11352        assert_eq_m256i(r, e);
11353        let r = _mm256_alignr_epi64::<6>(a, b);
11354        let e = _mm256_set_epi64x(2, 1, 8, 7);
11355        assert_eq_m256i(r, e);
11356    }
11357
11358    #[simd_test(enable = "avx512f,avx512vl")]
11359    const fn test_mm256_mask_alignr_epi64() {
11360        let a = _mm256_set_epi64x(4, 3, 2, 1);
11361        let b = _mm256_set_epi64x(8, 7, 6, 5);
11362        let r = _mm256_mask_alignr_epi64::<1>(a, 0, a, b);
11363        assert_eq_m256i(r, a);
11364        let r = _mm256_mask_alignr_epi64::<0>(a, 0b00001111, a, b);
11365        let e = _mm256_set_epi64x(8, 7, 6, 5);
11366        assert_eq_m256i(r, e);
11367    }
11368
11369    #[simd_test(enable = "avx512f,avx512vl")]
11370    const fn test_mm256_maskz_alignr_epi64() {
11371        let a = _mm256_set_epi64x(4, 3, 2, 1);
11372        let b = _mm256_set_epi64x(8, 7, 6, 5);
11373        let r = _mm256_maskz_alignr_epi64::<1>(0, a, b);
11374        assert_eq_m256i(r, _mm256_setzero_si256());
11375        let r = _mm256_maskz_alignr_epi64::<0>(0b00001111, a, b);
11376        let e = _mm256_set_epi64x(8, 7, 6, 5);
11377        assert_eq_m256i(r, e);
11378    }
11379
11380    #[simd_test(enable = "avx512f,avx512vl")]
11381    const fn test_mm_alignr_epi64() {
11382        let a = _mm_set_epi64x(2, 1);
11383        let b = _mm_set_epi64x(4, 3);
11384        let r = _mm_alignr_epi64::<0>(a, b);
11385        let e = _mm_set_epi64x(4, 3);
11386        assert_eq_m128i(r, e);
11387    }
11388
11389    #[simd_test(enable = "avx512f,avx512vl")]
11390    const fn test_mm_mask_alignr_epi64() {
11391        let a = _mm_set_epi64x(2, 1);
11392        let b = _mm_set_epi64x(4, 3);
11393        let r = _mm_mask_alignr_epi64::<1>(a, 0, a, b);
11394        assert_eq_m128i(r, a);
11395        let r = _mm_mask_alignr_epi64::<0>(a, 0b00000011, a, b);
11396        let e = _mm_set_epi64x(4, 3);
11397        assert_eq_m128i(r, e);
11398    }
11399
11400    #[simd_test(enable = "avx512f,avx512vl")]
11401    const fn test_mm_maskz_alignr_epi64() {
11402        let a = _mm_set_epi64x(2, 1);
11403        let b = _mm_set_epi64x(4, 3);
11404        let r = _mm_maskz_alignr_epi64::<1>(0, a, b);
11405        assert_eq_m128i(r, _mm_setzero_si128());
11406        let r = _mm_maskz_alignr_epi64::<0>(0b00000011, a, b);
11407        let e = _mm_set_epi64x(4, 3);
11408        assert_eq_m128i(r, e);
11409    }
11410
11411    #[simd_test(enable = "avx512f")]
11412    const fn test_mm512_and_epi64() {
11413        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11414        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11415        let r = _mm512_and_epi64(a, b);
11416        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11417        assert_eq_m512i(r, e);
11418    }
11419
11420    #[simd_test(enable = "avx512f")]
11421    const fn test_mm512_mask_and_epi64() {
11422        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11423        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11424        let r = _mm512_mask_and_epi64(a, 0, a, b);
11425        assert_eq_m512i(r, a);
11426        let r = _mm512_mask_and_epi64(a, 0b01111111, a, b);
11427        let e = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11428        assert_eq_m512i(r, e);
11429    }
11430
11431    #[simd_test(enable = "avx512f")]
11432    const fn test_mm512_maskz_and_epi64() {
11433        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11434        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11435        let r = _mm512_maskz_and_epi64(0, a, b);
11436        assert_eq_m512i(r, _mm512_setzero_si512());
11437        let r = _mm512_maskz_and_epi64(0b00001111, a, b);
11438        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11439        assert_eq_m512i(r, e);
11440    }
11441
11442    #[simd_test(enable = "avx512f,avx512vl")]
11443    const fn test_mm256_mask_and_epi64() {
11444        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11445        let b = _mm256_set1_epi64x(1 << 0);
11446        let r = _mm256_mask_and_epi64(a, 0, a, b);
11447        assert_eq_m256i(r, a);
11448        let r = _mm256_mask_and_epi64(a, 0b00001111, a, b);
11449        let e = _mm256_set1_epi64x(1 << 0);
11450        assert_eq_m256i(r, e);
11451    }
11452
11453    #[simd_test(enable = "avx512f,avx512vl")]
11454    const fn test_mm256_maskz_and_epi64() {
11455        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11456        let b = _mm256_set1_epi64x(1 << 0);
11457        let r = _mm256_maskz_and_epi64(0, a, b);
11458        assert_eq_m256i(r, _mm256_setzero_si256());
11459        let r = _mm256_maskz_and_epi64(0b00001111, a, b);
11460        let e = _mm256_set1_epi64x(1 << 0);
11461        assert_eq_m256i(r, e);
11462    }
11463
11464    #[simd_test(enable = "avx512f,avx512vl")]
11465    const fn test_mm_mask_and_epi64() {
11466        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11467        let b = _mm_set1_epi64x(1 << 0);
11468        let r = _mm_mask_and_epi64(a, 0, a, b);
11469        assert_eq_m128i(r, a);
11470        let r = _mm_mask_and_epi64(a, 0b00000011, a, b);
11471        let e = _mm_set1_epi64x(1 << 0);
11472        assert_eq_m128i(r, e);
11473    }
11474
11475    #[simd_test(enable = "avx512f,avx512vl")]
11476    const fn test_mm_maskz_and_epi64() {
11477        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11478        let b = _mm_set1_epi64x(1 << 0);
11479        let r = _mm_maskz_and_epi64(0, a, b);
11480        assert_eq_m128i(r, _mm_setzero_si128());
11481        let r = _mm_maskz_and_epi64(0b00000011, a, b);
11482        let e = _mm_set1_epi64x(1 << 0);
11483        assert_eq_m128i(r, e);
11484    }
11485
11486    #[simd_test(enable = "avx512f")]
11487    const fn test_mm512_and_si512() {
11488        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11489        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11490        let r = _mm512_and_epi64(a, b);
11491        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11492        assert_eq_m512i(r, e);
11493    }
11494
11495    #[simd_test(enable = "avx512f")]
11496    const fn test_mm512_or_epi64() {
11497        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11498        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11499        let r = _mm512_or_epi64(a, b);
11500        #[rustfmt::skip]
11501        let e = _mm512_set_epi64(
11502            1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11503            0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11504        );
11505        assert_eq_m512i(r, e);
11506    }
11507
11508    #[simd_test(enable = "avx512f")]
11509    const fn test_mm512_mask_or_epi64() {
11510        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11511        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11512        let r = _mm512_mask_or_epi64(a, 0, a, b);
11513        assert_eq_m512i(r, a);
11514        let r = _mm512_mask_or_epi64(a, 0b11111111, a, b);
11515        #[rustfmt::skip]
11516        let e = _mm512_set_epi64(
11517            1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11518            0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11519        );
11520        assert_eq_m512i(r, e);
11521    }
11522
11523    #[simd_test(enable = "avx512f")]
11524    const fn test_mm512_maskz_or_epi64() {
11525        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11526        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11527        let r = _mm512_maskz_or_epi64(0, a, b);
11528        assert_eq_m512i(r, _mm512_setzero_si512());
11529        let r = _mm512_maskz_or_epi64(0b00001111, a, b);
11530        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11531        assert_eq_m512i(r, e);
11532    }
11533
11534    #[simd_test(enable = "avx512f,avx512vl")]
11535    const fn test_mm256_or_epi64() {
11536        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11537        let b = _mm256_set1_epi64x(1 << 13);
11538        let r = _mm256_or_epi64(a, b);
11539        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11540        assert_eq_m256i(r, e);
11541    }
11542
11543    #[simd_test(enable = "avx512f,avx512vl")]
11544    const fn test_mm256_mask_or_epi64() {
11545        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11546        let b = _mm256_set1_epi64x(1 << 13);
11547        let r = _mm256_mask_or_epi64(a, 0, a, b);
11548        assert_eq_m256i(r, a);
11549        let r = _mm256_mask_or_epi64(a, 0b00001111, a, b);
11550        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11551        assert_eq_m256i(r, e);
11552    }
11553
11554    #[simd_test(enable = "avx512f,avx512vl")]
11555    const fn test_mm256_maskz_or_epi64() {
11556        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11557        let b = _mm256_set1_epi64x(1 << 13);
11558        let r = _mm256_maskz_or_epi64(0, a, b);
11559        assert_eq_m256i(r, _mm256_setzero_si256());
11560        let r = _mm256_maskz_or_epi64(0b00001111, a, b);
11561        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11562        assert_eq_m256i(r, e);
11563    }
11564
11565    #[simd_test(enable = "avx512f,avx512vl")]
11566    const fn test_mm_or_epi64() {
11567        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11568        let b = _mm_set1_epi64x(1 << 13);
11569        let r = _mm_or_epi64(a, b);
11570        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11571        assert_eq_m128i(r, e);
11572    }
11573
11574    #[simd_test(enable = "avx512f,avx512vl")]
11575    const fn test_mm_mask_or_epi64() {
11576        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11577        let b = _mm_set1_epi64x(1 << 13);
11578        let r = _mm_mask_or_epi64(a, 0, a, b);
11579        assert_eq_m128i(r, a);
11580        let r = _mm_mask_or_epi64(a, 0b00000011, a, b);
11581        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11582        assert_eq_m128i(r, e);
11583    }
11584
11585    #[simd_test(enable = "avx512f,avx512vl")]
11586    const fn test_mm_maskz_or_epi64() {
11587        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11588        let b = _mm_set1_epi64x(1 << 13);
11589        let r = _mm_maskz_or_epi64(0, a, b);
11590        assert_eq_m128i(r, _mm_setzero_si128());
11591        let r = _mm_maskz_or_epi64(0b00000011, a, b);
11592        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11593        assert_eq_m128i(r, e);
11594    }
11595
11596    #[simd_test(enable = "avx512f")]
11597    const fn test_mm512_or_si512() {
11598        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11599        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11600        let r = _mm512_or_epi64(a, b);
11601        #[rustfmt::skip]
11602        let e = _mm512_set_epi64(
11603            1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0,
11604            0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3,
11605        );
11606        assert_eq_m512i(r, e);
11607    }
11608
11609    #[simd_test(enable = "avx512f")]
11610    const fn test_mm512_xor_epi64() {
11611        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11612        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11613        let r = _mm512_xor_epi64(a, b);
11614        let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11615        assert_eq_m512i(r, e);
11616    }
11617
11618    #[simd_test(enable = "avx512f")]
11619    const fn test_mm512_mask_xor_epi64() {
11620        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11621        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11622        let r = _mm512_mask_xor_epi64(a, 0, a, b);
11623        assert_eq_m512i(r, a);
11624        let r = _mm512_mask_xor_epi64(a, 0b11111111, a, b);
11625        let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11626        assert_eq_m512i(r, e);
11627    }
11628
11629    #[simd_test(enable = "avx512f")]
11630    const fn test_mm512_maskz_xor_epi64() {
11631        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11632        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11633        let r = _mm512_maskz_xor_epi64(0, a, b);
11634        assert_eq_m512i(r, _mm512_setzero_si512());
11635        let r = _mm512_maskz_xor_epi64(0b00001111, a, b);
11636        let e = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
11637        assert_eq_m512i(r, e);
11638    }
11639
11640    #[simd_test(enable = "avx512f,avx512vl")]
11641    const fn test_mm256_xor_epi64() {
11642        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11643        let b = _mm256_set1_epi64x(1 << 13);
11644        let r = _mm256_xor_epi64(a, b);
11645        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11646        assert_eq_m256i(r, e);
11647    }
11648
11649    #[simd_test(enable = "avx512f,avx512vl")]
11650    const fn test_mm256_mask_xor_epi64() {
11651        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11652        let b = _mm256_set1_epi64x(1 << 13);
11653        let r = _mm256_mask_xor_epi64(a, 0, a, b);
11654        assert_eq_m256i(r, a);
11655        let r = _mm256_mask_xor_epi64(a, 0b00001111, a, b);
11656        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11657        assert_eq_m256i(r, e);
11658    }
11659
11660    #[simd_test(enable = "avx512f,avx512vl")]
11661    const fn test_mm256_maskz_xor_epi64() {
11662        let a = _mm256_set1_epi64x(1 << 0 | 1 << 15);
11663        let b = _mm256_set1_epi64x(1 << 13);
11664        let r = _mm256_maskz_xor_epi64(0, a, b);
11665        assert_eq_m256i(r, _mm256_setzero_si256());
11666        let r = _mm256_maskz_xor_epi64(0b00001111, a, b);
11667        let e = _mm256_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11668        assert_eq_m256i(r, e);
11669    }
11670
11671    #[simd_test(enable = "avx512f,avx512vl")]
11672    const fn test_mm_xor_epi64() {
11673        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11674        let b = _mm_set1_epi64x(1 << 13);
11675        let r = _mm_xor_epi64(a, b);
11676        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11677        assert_eq_m128i(r, e);
11678    }
11679
11680    #[simd_test(enable = "avx512f,avx512vl")]
11681    const fn test_mm_mask_xor_epi64() {
11682        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11683        let b = _mm_set1_epi64x(1 << 13);
11684        let r = _mm_mask_xor_epi64(a, 0, a, b);
11685        assert_eq_m128i(r, a);
11686        let r = _mm_mask_xor_epi64(a, 0b00000011, a, b);
11687        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11688        assert_eq_m128i(r, e);
11689    }
11690
11691    #[simd_test(enable = "avx512f,avx512vl")]
11692    const fn test_mm_maskz_xor_epi64() {
11693        let a = _mm_set1_epi64x(1 << 0 | 1 << 15);
11694        let b = _mm_set1_epi64x(1 << 13);
11695        let r = _mm_maskz_xor_epi64(0, a, b);
11696        assert_eq_m128i(r, _mm_setzero_si128());
11697        let r = _mm_maskz_xor_epi64(0b00000011, a, b);
11698        let e = _mm_set1_epi64x(1 << 0 | 1 << 13 | 1 << 15);
11699        assert_eq_m128i(r, e);
11700    }
11701
11702    #[simd_test(enable = "avx512f")]
11703    const fn test_mm512_xor_si512() {
11704        let a = _mm512_set_epi64(1 << 0 | 1 << 15, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11705        let b = _mm512_set_epi64(1 << 13, 0, 0, 0, 0, 0, 0, 1 << 1 | 1 << 2 | 1 << 3);
11706        let r = _mm512_xor_epi64(a, b);
11707        let e = _mm512_set_epi64(1 << 0 | 1 << 13 | 1 << 15, 0, 0, 0, 0, 0, 0, 0);
11708        assert_eq_m512i(r, e);
11709    }
11710
11711    #[simd_test(enable = "avx512f")]
11712    const fn test_mm512_andnot_epi64() {
11713        let a = _mm512_set1_epi64(0);
11714        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11715        let r = _mm512_andnot_epi64(a, b);
11716        let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11717        assert_eq_m512i(r, e);
11718    }
11719
11720    #[simd_test(enable = "avx512f")]
11721    const fn test_mm512_mask_andnot_epi64() {
11722        let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11723        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11724        let r = _mm512_mask_andnot_epi64(a, 0, a, b);
11725        assert_eq_m512i(r, a);
11726        let r = _mm512_mask_andnot_epi64(a, 0b11111111, a, b);
11727        let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11728        assert_eq_m512i(r, e);
11729    }
11730
11731    #[simd_test(enable = "avx512f")]
11732    const fn test_mm512_maskz_andnot_epi64() {
11733        let a = _mm512_set1_epi64(1 << 1 | 1 << 2);
11734        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11735        let r = _mm512_maskz_andnot_epi64(0, a, b);
11736        assert_eq_m512i(r, _mm512_setzero_si512());
11737        let r = _mm512_maskz_andnot_epi64(0b00001111, a, b);
11738        #[rustfmt::skip]
11739        let e = _mm512_set_epi64(
11740            0, 0, 0, 0,
11741            1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4, 1 << 3 | 1 << 4,
11742        );
11743        assert_eq_m512i(r, e);
11744    }
11745
11746    #[simd_test(enable = "avx512f,avx512vl")]
11747    const fn test_mm256_mask_andnot_epi64() {
11748        let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11749        let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11750        let r = _mm256_mask_andnot_epi64(a, 0, a, b);
11751        assert_eq_m256i(r, a);
11752        let r = _mm256_mask_andnot_epi64(a, 0b00001111, a, b);
11753        let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11754        assert_eq_m256i(r, e);
11755    }
11756
11757    #[simd_test(enable = "avx512f,avx512vl")]
11758    const fn test_mm256_maskz_andnot_epi64() {
11759        let a = _mm256_set1_epi64x(1 << 1 | 1 << 2);
11760        let b = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11761        let r = _mm256_maskz_andnot_epi64(0, a, b);
11762        assert_eq_m256i(r, _mm256_setzero_si256());
11763        let r = _mm256_maskz_andnot_epi64(0b00001111, a, b);
11764        let e = _mm256_set1_epi64x(1 << 3 | 1 << 4);
11765        assert_eq_m256i(r, e);
11766    }
11767
11768    #[simd_test(enable = "avx512f,avx512vl")]
11769    const fn test_mm_mask_andnot_epi64() {
11770        let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11771        let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11772        let r = _mm_mask_andnot_epi64(a, 0, a, b);
11773        assert_eq_m128i(r, a);
11774        let r = _mm_mask_andnot_epi64(a, 0b00000011, a, b);
11775        let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11776        assert_eq_m128i(r, e);
11777    }
11778
11779    #[simd_test(enable = "avx512f,avx512vl")]
11780    const fn test_mm_maskz_andnot_epi64() {
11781        let a = _mm_set1_epi64x(1 << 1 | 1 << 2);
11782        let b = _mm_set1_epi64x(1 << 3 | 1 << 4);
11783        let r = _mm_maskz_andnot_epi64(0, a, b);
11784        assert_eq_m128i(r, _mm_setzero_si128());
11785        let r = _mm_maskz_andnot_epi64(0b00000011, a, b);
11786        let e = _mm_set1_epi64x(1 << 3 | 1 << 4);
11787        assert_eq_m128i(r, e);
11788    }
11789
11790    #[simd_test(enable = "avx512f")]
11791    const fn test_mm512_andnot_si512() {
11792        let a = _mm512_set1_epi64(0);
11793        let b = _mm512_set1_epi64(1 << 3 | 1 << 4);
11794        let r = _mm512_andnot_si512(a, b);
11795        let e = _mm512_set1_epi64(1 << 3 | 1 << 4);
11796        assert_eq_m512i(r, e);
11797    }
11798
11799    #[simd_test(enable = "avx512f")]
11800    const fn test_mm512_reduce_add_epi64() {
11801        let a = _mm512_set1_epi64(1);
11802        let e: i64 = _mm512_reduce_add_epi64(a);
11803        assert_eq!(8, e);
11804    }
11805
11806    #[simd_test(enable = "avx512f")]
11807    const fn test_mm512_mask_reduce_add_epi64() {
11808        let a = _mm512_set1_epi64(1);
11809        let e: i64 = _mm512_mask_reduce_add_epi64(0b11110000, a);
11810        assert_eq!(4, e);
11811    }
11812
11813    #[simd_test(enable = "avx512f")]
11814    const fn test_mm512_reduce_add_pd() {
11815        let a = _mm512_set1_pd(1.);
11816        let e: f64 = _mm512_reduce_add_pd(a);
11817        assert_eq!(8., e);
11818    }
11819
11820    #[simd_test(enable = "avx512f")]
11821    const fn test_mm512_mask_reduce_add_pd() {
11822        let a = _mm512_set1_pd(1.);
11823        let e: f64 = _mm512_mask_reduce_add_pd(0b11110000, a);
11824        assert_eq!(4., e);
11825    }
11826
11827    #[simd_test(enable = "avx512f")]
11828    const fn test_mm512_reduce_mul_epi64() {
11829        let a = _mm512_set1_epi64(2);
11830        let e: i64 = _mm512_reduce_mul_epi64(a);
11831        assert_eq!(256, e);
11832    }
11833
11834    #[simd_test(enable = "avx512f")]
11835    const fn test_mm512_mask_reduce_mul_epi64() {
11836        let a = _mm512_set1_epi64(2);
11837        let e: i64 = _mm512_mask_reduce_mul_epi64(0b11110000, a);
11838        assert_eq!(16, e);
11839    }
11840
11841    #[simd_test(enable = "avx512f")]
11842    const fn test_mm512_reduce_mul_pd() {
11843        let a = _mm512_set1_pd(2.);
11844        let e: f64 = _mm512_reduce_mul_pd(a);
11845        assert_eq!(256., e);
11846    }
11847
11848    #[simd_test(enable = "avx512f")]
11849    const fn test_mm512_mask_reduce_mul_pd() {
11850        let a = _mm512_set1_pd(2.);
11851        let e: f64 = _mm512_mask_reduce_mul_pd(0b11110000, a);
11852        assert_eq!(16., e);
11853    }
11854
11855    #[simd_test(enable = "avx512f")]
11856    const fn test_mm512_reduce_max_epi64() {
11857        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11858        let e: i64 = _mm512_reduce_max_epi64(a);
11859        assert_eq!(7, e);
11860    }
11861
11862    #[simd_test(enable = "avx512f")]
11863    const fn test_mm512_mask_reduce_max_epi64() {
11864        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11865        let e: i64 = _mm512_mask_reduce_max_epi64(0b11110000, a);
11866        assert_eq!(3, e);
11867    }
11868
11869    #[simd_test(enable = "avx512f")]
11870    const fn test_mm512_reduce_max_epu64() {
11871        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11872        let e: u64 = _mm512_reduce_max_epu64(a);
11873        assert_eq!(7, e);
11874    }
11875
11876    #[simd_test(enable = "avx512f")]
11877    const fn test_mm512_mask_reduce_max_epu64() {
11878        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11879        let e: u64 = _mm512_mask_reduce_max_epu64(0b11110000, a);
11880        assert_eq!(3, e);
11881    }
11882
11883    #[simd_test(enable = "avx512f")]
11884    fn test_mm512_reduce_max_pd() {
11885        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11886        let e: f64 = _mm512_reduce_max_pd(a);
11887        assert_eq!(7., e);
11888    }
11889
11890    #[simd_test(enable = "avx512f")]
11891    fn test_mm512_mask_reduce_max_pd() {
11892        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11893        let e: f64 = _mm512_mask_reduce_max_pd(0b11110000, a);
11894        assert_eq!(3., e);
11895    }
11896
11897    #[simd_test(enable = "avx512f")]
11898    const fn test_mm512_reduce_min_epi64() {
11899        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11900        let e: i64 = _mm512_reduce_min_epi64(a);
11901        assert_eq!(0, e);
11902    }
11903
11904    #[simd_test(enable = "avx512f")]
11905    const fn test_mm512_mask_reduce_min_epi64() {
11906        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11907        let e: i64 = _mm512_mask_reduce_min_epi64(0b11110000, a);
11908        assert_eq!(0, e);
11909    }
11910
11911    #[simd_test(enable = "avx512f")]
11912    const fn test_mm512_reduce_min_epu64() {
11913        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11914        let e: u64 = _mm512_reduce_min_epu64(a);
11915        assert_eq!(0, e);
11916    }
11917
11918    #[simd_test(enable = "avx512f")]
11919    const fn test_mm512_mask_reduce_min_epu64() {
11920        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
11921        let e: u64 = _mm512_mask_reduce_min_epu64(0b11110000, a);
11922        assert_eq!(0, e);
11923    }
11924
11925    #[simd_test(enable = "avx512f")]
11926    fn test_mm512_reduce_min_pd() {
11927        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11928        let e: f64 = _mm512_reduce_min_pd(a);
11929        assert_eq!(0., e);
11930    }
11931
11932    #[simd_test(enable = "avx512f")]
11933    fn test_mm512_mask_reduce_min_pd() {
11934        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
11935        let e: f64 = _mm512_mask_reduce_min_pd(0b11110000, a);
11936        assert_eq!(0., e);
11937    }
11938
11939    #[simd_test(enable = "avx512f")]
11940    const fn test_mm512_reduce_and_epi64() {
11941        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11942        let e: i64 = _mm512_reduce_and_epi64(a);
11943        assert_eq!(0, e);
11944    }
11945
11946    #[simd_test(enable = "avx512f")]
11947    const fn test_mm512_mask_reduce_and_epi64() {
11948        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11949        let e: i64 = _mm512_mask_reduce_and_epi64(0b11110000, a);
11950        assert_eq!(1, e);
11951    }
11952
11953    #[simd_test(enable = "avx512f")]
11954    const fn test_mm512_reduce_or_epi64() {
11955        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11956        let e: i64 = _mm512_reduce_or_epi64(a);
11957        assert_eq!(3, e);
11958    }
11959
11960    #[simd_test(enable = "avx512f")]
11961    const fn test_mm512_mask_reduce_or_epi64() {
11962        let a = _mm512_set_epi64(1, 1, 1, 1, 2, 2, 2, 2);
11963        let e: i64 = _mm512_mask_reduce_or_epi64(0b11110000, a);
11964        assert_eq!(1, e);
11965    }
11966
11967    #[simd_test(enable = "avx512f")]
11968    const fn test_mm512_extractf64x4_pd() {
11969        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11970        let r = _mm512_extractf64x4_pd::<1>(a);
11971        let e = _mm256_setr_pd(5., 6., 7., 8.);
11972        assert_eq_m256d(r, e);
11973    }
11974
11975    #[simd_test(enable = "avx512f")]
11976    const fn test_mm512_mask_extractf64x4_pd() {
11977        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11978        let src = _mm256_set1_pd(100.);
11979        let r = _mm512_mask_extractf64x4_pd::<1>(src, 0, a);
11980        assert_eq_m256d(r, src);
11981        let r = _mm512_mask_extractf64x4_pd::<1>(src, 0b11111111, a);
11982        let e = _mm256_setr_pd(5., 6., 7., 8.);
11983        assert_eq_m256d(r, e);
11984    }
11985
11986    #[simd_test(enable = "avx512f")]
11987    const fn test_mm512_maskz_extractf64x4_pd() {
11988        let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
11989        let r = _mm512_maskz_extractf64x4_pd::<1>(0, a);
11990        assert_eq_m256d(r, _mm256_setzero_pd());
11991        let r = _mm512_maskz_extractf64x4_pd::<1>(0b00000001, a);
11992        let e = _mm256_setr_pd(5., 0., 0., 0.);
11993        assert_eq_m256d(r, e);
11994    }
11995
11996    #[simd_test(enable = "avx512f")]
11997    const fn test_mm512_extracti64x4_epi64() {
11998        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
11999        let r = _mm512_extracti64x4_epi64::<0x1>(a);
12000        let e = _mm256_setr_epi64x(5, 6, 7, 8);
12001        assert_eq_m256i(r, e);
12002    }
12003
12004    #[simd_test(enable = "avx512f")]
12005    const fn test_mm512_mask_extracti64x4_epi64() {
12006        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
12007        let src = _mm256_set1_epi64x(100);
12008        let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0, a);
12009        assert_eq_m256i(r, src);
12010        let r = _mm512_mask_extracti64x4_epi64::<0x1>(src, 0b11111111, a);
12011        let e = _mm256_setr_epi64x(5, 6, 7, 8);
12012        assert_eq_m256i(r, e);
12013    }
12014
12015    #[simd_test(enable = "avx512f")]
12016    const fn test_mm512_maskz_extracti64x4_epi64() {
12017        let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
12018        let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0, a);
12019        assert_eq_m256i(r, _mm256_setzero_si256());
12020        let r = _mm512_maskz_extracti64x4_epi64::<0x1>(0b00000001, a);
12021        let e = _mm256_setr_epi64x(5, 0, 0, 0);
12022        assert_eq_m256i(r, e);
12023    }
12024
12025    #[simd_test(enable = "avx512f")]
12026    fn test_mm512_mask_compress_epi64() {
12027        let src = _mm512_set1_epi64(200);
12028        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12029        let r = _mm512_mask_compress_epi64(src, 0, a);
12030        assert_eq_m512i(r, src);
12031        let r = _mm512_mask_compress_epi64(src, 0b01010101, a);
12032        let e = _mm512_set_epi64(200, 200, 200, 200, 1, 3, 5, 7);
12033        assert_eq_m512i(r, e);
12034    }
12035
12036    #[simd_test(enable = "avx512f")]
12037    fn test_mm512_maskz_compress_epi64() {
12038        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12039        let r = _mm512_maskz_compress_epi64(0, a);
12040        assert_eq_m512i(r, _mm512_setzero_si512());
12041        let r = _mm512_maskz_compress_epi64(0b01010101, a);
12042        let e = _mm512_set_epi64(0, 0, 0, 0, 1, 3, 5, 7);
12043        assert_eq_m512i(r, e);
12044    }
12045
12046    #[simd_test(enable = "avx512f,avx512vl")]
12047    fn test_mm256_mask_compress_epi64() {
12048        let src = _mm256_set1_epi64x(200);
12049        let a = _mm256_set_epi64x(0, 1, 2, 3);
12050        let r = _mm256_mask_compress_epi64(src, 0, a);
12051        assert_eq_m256i(r, src);
12052        let r = _mm256_mask_compress_epi64(src, 0b00000101, a);
12053        let e = _mm256_set_epi64x(200, 200, 1, 3);
12054        assert_eq_m256i(r, e);
12055    }
12056
12057    #[simd_test(enable = "avx512f,avx512vl")]
12058    fn test_mm256_maskz_compress_epi64() {
12059        let a = _mm256_set_epi64x(0, 1, 2, 3);
12060        let r = _mm256_maskz_compress_epi64(0, a);
12061        assert_eq_m256i(r, _mm256_setzero_si256());
12062        let r = _mm256_maskz_compress_epi64(0b00000101, a);
12063        let e = _mm256_set_epi64x(0, 0, 1, 3);
12064        assert_eq_m256i(r, e);
12065    }
12066
12067    #[simd_test(enable = "avx512f,avx512vl")]
12068    fn test_mm_mask_compress_epi64() {
12069        let src = _mm_set1_epi64x(200);
12070        let a = _mm_set_epi64x(0, 1);
12071        let r = _mm_mask_compress_epi64(src, 0, a);
12072        assert_eq_m128i(r, src);
12073        let r = _mm_mask_compress_epi64(src, 0b00000001, a);
12074        let e = _mm_set_epi64x(200, 1);
12075        assert_eq_m128i(r, e);
12076    }
12077
12078    #[simd_test(enable = "avx512f,avx512vl")]
12079    fn test_mm_maskz_compress_epi64() {
12080        let a = _mm_set_epi64x(0, 1);
12081        let r = _mm_maskz_compress_epi64(0, a);
12082        assert_eq_m128i(r, _mm_setzero_si128());
12083        let r = _mm_maskz_compress_epi64(0b00000001, a);
12084        let e = _mm_set_epi64x(0, 1);
12085        assert_eq_m128i(r, e);
12086    }
12087
12088    #[simd_test(enable = "avx512f")]
12089    fn test_mm512_mask_compress_pd() {
12090        let src = _mm512_set1_pd(200.);
12091        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12092        let r = _mm512_mask_compress_pd(src, 0, a);
12093        assert_eq_m512d(r, src);
12094        let r = _mm512_mask_compress_pd(src, 0b01010101, a);
12095        let e = _mm512_set_pd(200., 200., 200., 200., 1., 3., 5., 7.);
12096        assert_eq_m512d(r, e);
12097    }
12098
12099    #[simd_test(enable = "avx512f")]
12100    fn test_mm512_maskz_compress_pd() {
12101        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12102        let r = _mm512_maskz_compress_pd(0, a);
12103        assert_eq_m512d(r, _mm512_setzero_pd());
12104        let r = _mm512_maskz_compress_pd(0b01010101, a);
12105        let e = _mm512_set_pd(0., 0., 0., 0., 1., 3., 5., 7.);
12106        assert_eq_m512d(r, e);
12107    }
12108
12109    #[simd_test(enable = "avx512f,avx512vl")]
12110    fn test_mm256_mask_compress_pd() {
12111        let src = _mm256_set1_pd(200.);
12112        let a = _mm256_set_pd(0., 1., 2., 3.);
12113        let r = _mm256_mask_compress_pd(src, 0, a);
12114        assert_eq_m256d(r, src);
12115        let r = _mm256_mask_compress_pd(src, 0b00000101, a);
12116        let e = _mm256_set_pd(200., 200., 1., 3.);
12117        assert_eq_m256d(r, e);
12118    }
12119
12120    #[simd_test(enable = "avx512f,avx512vl")]
12121    fn test_mm256_maskz_compress_pd() {
12122        let a = _mm256_set_pd(0., 1., 2., 3.);
12123        let r = _mm256_maskz_compress_pd(0, a);
12124        assert_eq_m256d(r, _mm256_setzero_pd());
12125        let r = _mm256_maskz_compress_pd(0b00000101, a);
12126        let e = _mm256_set_pd(0., 0., 1., 3.);
12127        assert_eq_m256d(r, e);
12128    }
12129
12130    #[simd_test(enable = "avx512f,avx512vl")]
12131    fn test_mm_mask_compress_pd() {
12132        let src = _mm_set1_pd(200.);
12133        let a = _mm_set_pd(0., 1.);
12134        let r = _mm_mask_compress_pd(src, 0, a);
12135        assert_eq_m128d(r, src);
12136        let r = _mm_mask_compress_pd(src, 0b00000001, a);
12137        let e = _mm_set_pd(200., 1.);
12138        assert_eq_m128d(r, e);
12139    }
12140
12141    #[simd_test(enable = "avx512f,avx512vl")]
12142    fn test_mm_maskz_compress_pd() {
12143        let a = _mm_set_pd(0., 1.);
12144        let r = _mm_maskz_compress_pd(0, a);
12145        assert_eq_m128d(r, _mm_setzero_pd());
12146        let r = _mm_maskz_compress_pd(0b00000001, a);
12147        let e = _mm_set_pd(0., 1.);
12148        assert_eq_m128d(r, e);
12149    }
12150
12151    #[simd_test(enable = "avx512f")]
12152    fn test_mm512_mask_expand_epi64() {
12153        let src = _mm512_set1_epi64(200);
12154        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12155        let r = _mm512_mask_expand_epi64(src, 0, a);
12156        assert_eq_m512i(r, src);
12157        let r = _mm512_mask_expand_epi64(src, 0b01010101, a);
12158        let e = _mm512_set_epi64(200, 4, 200, 5, 200, 6, 200, 7);
12159        assert_eq_m512i(r, e);
12160    }
12161
12162    #[simd_test(enable = "avx512f")]
12163    fn test_mm512_maskz_expand_epi64() {
12164        let a = _mm512_set_epi64(0, 1, 2, 3, 4, 5, 6, 7);
12165        let r = _mm512_maskz_expand_epi64(0, a);
12166        assert_eq_m512i(r, _mm512_setzero_si512());
12167        let r = _mm512_maskz_expand_epi64(0b01010101, a);
12168        let e = _mm512_set_epi64(0, 4, 0, 5, 0, 6, 0, 7);
12169        assert_eq_m512i(r, e);
12170    }
12171
12172    #[simd_test(enable = "avx512f,avx512vl")]
12173    fn test_mm256_mask_expand_epi64() {
12174        let src = _mm256_set1_epi64x(200);
12175        let a = _mm256_set_epi64x(0, 1, 2, 3);
12176        let r = _mm256_mask_expand_epi64(src, 0, a);
12177        assert_eq_m256i(r, src);
12178        let r = _mm256_mask_expand_epi64(src, 0b00000101, a);
12179        let e = _mm256_set_epi64x(200, 2, 200, 3);
12180        assert_eq_m256i(r, e);
12181    }
12182
12183    #[simd_test(enable = "avx512f,avx512vl")]
12184    fn test_mm256_maskz_expand_epi64() {
12185        let a = _mm256_set_epi64x(0, 1, 2, 3);
12186        let r = _mm256_maskz_expand_epi64(0, a);
12187        assert_eq_m256i(r, _mm256_setzero_si256());
12188        let r = _mm256_maskz_expand_epi64(0b00000101, a);
12189        let e = _mm256_set_epi64x(0, 2, 0, 3);
12190        assert_eq_m256i(r, e);
12191    }
12192
12193    #[simd_test(enable = "avx512f,avx512vl")]
12194    fn test_mm_mask_expand_epi64() {
12195        let src = _mm_set1_epi64x(200);
12196        let a = _mm_set_epi64x(0, 1);
12197        let r = _mm_mask_expand_epi64(src, 0, a);
12198        assert_eq_m128i(r, src);
12199        let r = _mm_mask_expand_epi64(src, 0b00000001, a);
12200        let e = _mm_set_epi64x(200, 1);
12201        assert_eq_m128i(r, e);
12202    }
12203
12204    #[simd_test(enable = "avx512f,avx512vl")]
12205    fn test_mm_maskz_expand_epi64() {
12206        let a = _mm_set_epi64x(0, 1);
12207        let r = _mm_maskz_expand_epi64(0, a);
12208        assert_eq_m128i(r, _mm_setzero_si128());
12209        let r = _mm_maskz_expand_epi64(0b00000001, a);
12210        let e = _mm_set_epi64x(0, 1);
12211        assert_eq_m128i(r, e);
12212    }
12213
12214    #[simd_test(enable = "avx512f")]
12215    fn test_mm512_mask_expand_pd() {
12216        let src = _mm512_set1_pd(200.);
12217        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12218        let r = _mm512_mask_expand_pd(src, 0, a);
12219        assert_eq_m512d(r, src);
12220        let r = _mm512_mask_expand_pd(src, 0b01010101, a);
12221        let e = _mm512_set_pd(200., 4., 200., 5., 200., 6., 200., 7.);
12222        assert_eq_m512d(r, e);
12223    }
12224
12225    #[simd_test(enable = "avx512f")]
12226    fn test_mm512_maskz_expand_pd() {
12227        let a = _mm512_set_pd(0., 1., 2., 3., 4., 5., 6., 7.);
12228        let r = _mm512_maskz_expand_pd(0, a);
12229        assert_eq_m512d(r, _mm512_setzero_pd());
12230        let r = _mm512_maskz_expand_pd(0b01010101, a);
12231        let e = _mm512_set_pd(0., 4., 0., 5., 0., 6., 0., 7.);
12232        assert_eq_m512d(r, e);
12233    }
12234
12235    #[simd_test(enable = "avx512f,avx512vl")]
12236    fn test_mm256_mask_expand_pd() {
12237        let src = _mm256_set1_pd(200.);
12238        let a = _mm256_set_pd(0., 1., 2., 3.);
12239        let r = _mm256_mask_expand_pd(src, 0, a);
12240        assert_eq_m256d(r, src);
12241        let r = _mm256_mask_expand_pd(src, 0b00000101, a);
12242        let e = _mm256_set_pd(200., 2., 200., 3.);
12243        assert_eq_m256d(r, e);
12244    }
12245
12246    #[simd_test(enable = "avx512f,avx512vl")]
12247    fn test_mm256_maskz_expand_pd() {
12248        let a = _mm256_set_pd(0., 1., 2., 3.);
12249        let r = _mm256_maskz_expand_pd(0, a);
12250        assert_eq_m256d(r, _mm256_setzero_pd());
12251        let r = _mm256_maskz_expand_pd(0b00000101, a);
12252        let e = _mm256_set_pd(0., 2., 0., 3.);
12253        assert_eq_m256d(r, e);
12254    }
12255
12256    #[simd_test(enable = "avx512f,avx512vl")]
12257    fn test_mm_mask_expand_pd() {
12258        let src = _mm_set1_pd(200.);
12259        let a = _mm_set_pd(0., 1.);
12260        let r = _mm_mask_expand_pd(src, 0, a);
12261        assert_eq_m128d(r, src);
12262        let r = _mm_mask_expand_pd(src, 0b00000001, a);
12263        let e = _mm_set_pd(200., 1.);
12264        assert_eq_m128d(r, e);
12265    }
12266
12267    #[simd_test(enable = "avx512f,avx512vl")]
12268    fn test_mm_maskz_expand_pd() {
12269        let a = _mm_set_pd(0., 1.);
12270        let r = _mm_maskz_expand_pd(0, a);
12271        assert_eq_m128d(r, _mm_setzero_pd());
12272        let r = _mm_maskz_expand_pd(0b00000001, a);
12273        let e = _mm_set_pd(0., 1.);
12274        assert_eq_m128d(r, e);
12275    }
12276
12277    #[simd_test(enable = "avx512f")]
12278    const fn test_mm512_loadu_epi64() {
12279        let a = &[4, 3, 2, 5, -8, -9, -64, -50];
12280        let p = a.as_ptr();
12281        let r = unsafe { _mm512_loadu_epi64(black_box(p)) };
12282        let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12283        assert_eq_m512i(r, e);
12284    }
12285
12286    #[simd_test(enable = "avx512f,avx512vl")]
12287    const fn test_mm256_loadu_epi64() {
12288        let a = &[4, 3, 2, 5];
12289        let p = a.as_ptr();
12290        let r = unsafe { _mm256_loadu_epi64(black_box(p)) };
12291        let e = _mm256_setr_epi64x(4, 3, 2, 5);
12292        assert_eq_m256i(r, e);
12293    }
12294
12295    #[simd_test(enable = "avx512f,avx512vl")]
12296    const fn test_mm_loadu_epi64() {
12297        let a = &[4, 3];
12298        let p = a.as_ptr();
12299        let r = unsafe { _mm_loadu_epi64(black_box(p)) };
12300        let e = _mm_setr_epi64x(4, 3);
12301        assert_eq_m128i(r, e);
12302    }
12303
12304    #[simd_test(enable = "avx512f")]
12305    fn test_mm512_mask_cvtepi64_storeu_epi16() {
12306        let a = _mm512_set1_epi64(9);
12307        let mut r = _mm_undefined_si128();
12308        unsafe {
12309            _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12310        }
12311        let e = _mm_set1_epi16(9);
12312        assert_eq_m128i(r, e);
12313    }
12314
12315    #[simd_test(enable = "avx512f,avx512vl")]
12316    fn test_mm256_mask_cvtepi64_storeu_epi16() {
12317        let a = _mm256_set1_epi64x(9);
12318        let mut r = _mm_set1_epi16(0);
12319        unsafe {
12320            _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12321        }
12322        let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
12323        assert_eq_m128i(r, e);
12324    }
12325
12326    #[simd_test(enable = "avx512f,avx512vl")]
12327    fn test_mm_mask_cvtepi64_storeu_epi16() {
12328        let a = _mm_set1_epi64x(9);
12329        let mut r = _mm_set1_epi16(0);
12330        unsafe {
12331            _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12332        }
12333        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9);
12334        assert_eq_m128i(r, e);
12335    }
12336
12337    #[simd_test(enable = "avx512f")]
12338    fn test_mm512_mask_cvtsepi64_storeu_epi16() {
12339        let a = _mm512_set1_epi64(i64::MAX);
12340        let mut r = _mm_undefined_si128();
12341        unsafe {
12342            _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12343        }
12344        let e = _mm_set1_epi16(i16::MAX);
12345        assert_eq_m128i(r, e);
12346    }
12347
12348    #[simd_test(enable = "avx512f,avx512vl")]
12349    fn test_mm256_mask_cvtsepi64_storeu_epi16() {
12350        let a = _mm256_set1_epi64x(i64::MAX);
12351        let mut r = _mm_set1_epi16(0);
12352        unsafe {
12353            _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12354        }
12355        let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
12356        assert_eq_m128i(r, e);
12357    }
12358
12359    #[simd_test(enable = "avx512f,avx512vl")]
12360    fn test_mm_mask_cvtsepi64_storeu_epi16() {
12361        let a = _mm_set1_epi64x(i64::MAX);
12362        let mut r = _mm_set1_epi16(0);
12363        unsafe {
12364            _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12365        }
12366        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX);
12367        assert_eq_m128i(r, e);
12368    }
12369
12370    #[simd_test(enable = "avx512f")]
12371    fn test_mm512_mask_cvtusepi64_storeu_epi16() {
12372        let a = _mm512_set1_epi64(i64::MAX);
12373        let mut r = _mm_undefined_si128();
12374        unsafe {
12375            _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12376        }
12377        let e = _mm_set1_epi16(u16::MAX as i16);
12378        assert_eq_m128i(r, e);
12379    }
12380
12381    #[simd_test(enable = "avx512f,avx512vl")]
12382    fn test_mm256_mask_cvtusepi64_storeu_epi16() {
12383        let a = _mm256_set1_epi64x(i64::MAX);
12384        let mut r = _mm_set1_epi16(0);
12385        unsafe {
12386            _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12387        }
12388        let e = _mm_set_epi16(
12389            0,
12390            0,
12391            0,
12392            0,
12393            u16::MAX as i16,
12394            u16::MAX as i16,
12395            u16::MAX as i16,
12396            u16::MAX as i16,
12397        );
12398        assert_eq_m128i(r, e);
12399    }
12400
12401    #[simd_test(enable = "avx512f,avx512vl")]
12402    fn test_mm_mask_cvtusepi64_storeu_epi16() {
12403        let a = _mm_set1_epi64x(i64::MAX);
12404        let mut r = _mm_set1_epi16(0);
12405        unsafe {
12406            _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
12407        }
12408        let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16);
12409        assert_eq_m128i(r, e);
12410    }
12411
12412    #[simd_test(enable = "avx512f")]
12413    fn test_mm512_mask_cvtepi64_storeu_epi8() {
12414        let a = _mm512_set1_epi64(9);
12415        let mut r = _mm_set1_epi8(0);
12416        unsafe {
12417            _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12418        }
12419        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
12420        assert_eq_m128i(r, e);
12421    }
12422
12423    #[simd_test(enable = "avx512f,avx512vl")]
12424    fn test_mm256_mask_cvtepi64_storeu_epi8() {
12425        let a = _mm256_set1_epi64x(9);
12426        let mut r = _mm_set1_epi8(0);
12427        unsafe {
12428            _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12429        }
12430        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
12431        assert_eq_m128i(r, e);
12432    }
12433
12434    #[simd_test(enable = "avx512f,avx512vl")]
12435    fn test_mm_mask_cvtepi64_storeu_epi8() {
12436        let a = _mm_set1_epi64x(9);
12437        let mut r = _mm_set1_epi8(0);
12438        unsafe {
12439            _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12440        }
12441        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9);
12442        assert_eq_m128i(r, e);
12443    }
12444
12445    #[simd_test(enable = "avx512f")]
12446    fn test_mm512_mask_cvtsepi64_storeu_epi8() {
12447        let a = _mm512_set1_epi64(i64::MAX);
12448        let mut r = _mm_set1_epi8(0);
12449        unsafe {
12450            _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12451        }
12452        #[rustfmt::skip]
12453        let e = _mm_set_epi8(
12454            0, 0, 0, 0,
12455            0, 0, 0, 0,
12456            i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12457            i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12458        );
12459        assert_eq_m128i(r, e);
12460    }
12461
12462    #[simd_test(enable = "avx512f,avx512vl")]
12463    fn test_mm256_mask_cvtsepi64_storeu_epi8() {
12464        let a = _mm256_set1_epi64x(i64::MAX);
12465        let mut r = _mm_set1_epi8(0);
12466        unsafe {
12467            _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12468        }
12469        #[rustfmt::skip]
12470        let e = _mm_set_epi8(
12471            0, 0, 0, 0,
12472            0, 0, 0, 0,
12473            0, 0, 0, 0,
12474            i8::MAX, i8::MAX, i8::MAX, i8::MAX,
12475        );
12476        assert_eq_m128i(r, e);
12477    }
12478
12479    #[simd_test(enable = "avx512f,avx512vl")]
12480    fn test_mm_mask_cvtsepi64_storeu_epi8() {
12481        let a = _mm_set1_epi64x(i64::MAX);
12482        let mut r = _mm_set1_epi8(0);
12483        unsafe {
12484            _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12485        }
12486        let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX);
12487        assert_eq_m128i(r, e);
12488    }
12489
12490    #[simd_test(enable = "avx512f")]
12491    fn test_mm512_mask_cvtusepi64_storeu_epi8() {
12492        let a = _mm512_set1_epi64(i64::MAX);
12493        let mut r = _mm_set1_epi8(0);
12494        unsafe {
12495            _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12496        }
12497        #[rustfmt::skip]
12498        let e = _mm_set_epi8(
12499            0, 0, 0, 0,
12500            0, 0, 0, 0,
12501            u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12502            u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12503        );
12504        assert_eq_m128i(r, e);
12505    }
12506
12507    #[simd_test(enable = "avx512f,avx512vl")]
12508    fn test_mm256_mask_cvtusepi64_storeu_epi8() {
12509        let a = _mm256_set1_epi64x(i64::MAX);
12510        let mut r = _mm_set1_epi8(0);
12511        unsafe {
12512            _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12513        }
12514        #[rustfmt::skip]
12515        let e = _mm_set_epi8(
12516            0, 0, 0, 0,
12517            0, 0, 0, 0,
12518            0, 0, 0, 0,
12519            u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
12520        );
12521        assert_eq_m128i(r, e);
12522    }
12523
12524    #[simd_test(enable = "avx512f,avx512vl")]
12525    fn test_mm_mask_cvtusepi64_storeu_epi8() {
12526        let a = _mm_set1_epi64x(i64::MAX);
12527        let mut r = _mm_set1_epi8(0);
12528        unsafe {
12529            _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
12530        }
12531        #[rustfmt::skip]
12532        let e = _mm_set_epi8(
12533            0, 0, 0, 0,
12534            0, 0, 0, 0,
12535            0, 0, 0, 0,
12536            0, 0, u8::MAX as i8, u8::MAX as i8,
12537        );
12538        assert_eq_m128i(r, e);
12539    }
12540
12541    #[simd_test(enable = "avx512f")]
12542    fn test_mm512_mask_cvtepi64_storeu_epi32() {
12543        let a = _mm512_set1_epi64(9);
12544        let mut r = _mm256_undefined_si256();
12545        unsafe {
12546            _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12547        }
12548        let e = _mm256_set1_epi32(9);
12549        assert_eq_m256i(r, e);
12550    }
12551
12552    #[simd_test(enable = "avx512f,avx512vl")]
12553    fn test_mm256_mask_cvtepi64_storeu_epi32() {
12554        let a = _mm256_set1_epi64x(9);
12555        let mut r = _mm_set1_epi32(0);
12556        unsafe {
12557            _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12558        }
12559        let e = _mm_set_epi32(9, 9, 9, 9);
12560        assert_eq_m128i(r, e);
12561    }
12562
12563    #[simd_test(enable = "avx512f,avx512vl")]
12564    fn test_mm_mask_cvtepi64_storeu_epi32() {
12565        let a = _mm_set1_epi64x(9);
12566        let mut r = _mm_set1_epi16(0);
12567        unsafe {
12568            _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12569        }
12570        let e = _mm_set_epi32(0, 0, 9, 9);
12571        assert_eq_m128i(r, e);
12572    }
12573
12574    #[simd_test(enable = "avx512f")]
12575    fn test_mm512_mask_cvtsepi64_storeu_epi32() {
12576        let a = _mm512_set1_epi64(i64::MAX);
12577        let mut r = _mm256_undefined_si256();
12578        unsafe {
12579            _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12580        }
12581        let e = _mm256_set1_epi32(i32::MAX);
12582        assert_eq_m256i(r, e);
12583    }
12584
12585    #[simd_test(enable = "avx512f,avx512vl")]
12586    fn test_mm256_mask_cvtsepi64_storeu_epi32() {
12587        let a = _mm256_set1_epi64x(i64::MAX);
12588        let mut r = _mm_set1_epi32(0);
12589        unsafe {
12590            _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
12591        }
12592        let e = _mm_set1_epi32(i32::MAX);
12593        assert_eq_m128i(r, e);
12594    }
12595
12596    #[simd_test(enable = "avx512f,avx512vl")]
12597    fn test_mm_mask_cvtsepi64_storeu_epi32() {
12598        let a = _mm_set1_epi64x(i64::MAX);
12599        let mut r = _mm_set1_epi16(0);
12600        unsafe {
12601            _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
12602        }
12603        let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX);
12604        assert_eq_m128i(r, e);
12605    }
12606
12607    #[simd_test(enable = "avx512f")]
12608    fn test_mm512_mask_cvtusepi64_storeu_epi32() {
12609        let a = _mm512_set1_epi64(i64::MAX);
12610        let mut r = _mm256_undefined_si256();
12611        unsafe {
12612            _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
12613        }
12614        let e = _mm256_set1_epi32(u32::MAX as i32);
12615        assert_eq_m256i(r, e);
12616    }
12617
12618    #[simd_test(enable = "avx512f,avx512vl")]
12619    fn test_mm256_mask_cvtusepi64_storeu_epi32() {
12620        let a = _mm256_set1_epi64x(i64::MAX);
12621        let mut r = _mm_set1_epi32(0);
12622        unsafe {
12623            _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
12624        }
12625        let e = _mm_set1_epi32(u32::MAX as i32);
12626        assert_eq_m128i(r, e);
12627    }
12628
12629    #[simd_test(enable = "avx512f,avx512vl")]
12630    fn test_mm_mask_cvtusepi64_storeu_epi32() {
12631        let a = _mm_set1_epi64x(i64::MAX);
12632        let mut r = _mm_set1_epi16(0);
12633        unsafe {
12634            _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
12635        }
12636        let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32);
12637        assert_eq_m128i(r, e);
12638    }
12639
12640    #[simd_test(enable = "avx512f")]
12641    const fn test_mm512_storeu_epi64() {
12642        let a = _mm512_set1_epi64(9);
12643        let mut r = _mm512_set1_epi64(0);
12644        unsafe {
12645            _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12646        }
12647        assert_eq_m512i(r, a);
12648    }
12649
12650    #[simd_test(enable = "avx512f,avx512vl")]
12651    const fn test_mm256_storeu_epi64() {
12652        let a = _mm256_set1_epi64x(9);
12653        let mut r = _mm256_set1_epi64x(0);
12654        unsafe {
12655            _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12656        }
12657        assert_eq_m256i(r, a);
12658    }
12659
12660    #[simd_test(enable = "avx512f,avx512vl")]
12661    const fn test_mm_storeu_epi64() {
12662        let a = _mm_set1_epi64x(9);
12663        let mut r = _mm_set1_epi64x(0);
12664        unsafe {
12665            _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
12666        }
12667        assert_eq_m128i(r, a);
12668    }
12669
12670    #[simd_test(enable = "avx512f")]
12671    const fn test_mm512_load_epi64() {
12672        #[repr(align(64))]
12673        struct Align {
12674            data: [i64; 8], // 64 bytes
12675        }
12676        let a = Align {
12677            data: [4, 3, 2, 5, -8, -9, -64, -50],
12678        };
12679        let p = (a.data).as_ptr();
12680        let r = unsafe { _mm512_load_epi64(black_box(p)) };
12681        let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
12682        assert_eq_m512i(r, e);
12683    }
12684
12685    #[simd_test(enable = "avx512f,avx512vl")]
12686    const fn test_mm256_load_epi64() {
12687        #[repr(align(64))]
12688        struct Align {
12689            data: [i64; 4],
12690        }
12691        let a = Align { data: [4, 3, 2, 5] };
12692        let p = (a.data).as_ptr();
12693        let r = unsafe { _mm256_load_epi64(black_box(p)) };
12694        let e = _mm256_set_epi64x(5, 2, 3, 4);
12695        assert_eq_m256i(r, e);
12696    }
12697
12698    #[simd_test(enable = "avx512f,avx512vl")]
12699    const fn test_mm_load_epi64() {
12700        #[repr(align(64))]
12701        struct Align {
12702            data: [i64; 2],
12703        }
12704        let a = Align { data: [4, 3] };
12705        let p = (a.data).as_ptr();
12706        let r = unsafe { _mm_load_epi64(black_box(p)) };
12707        let e = _mm_set_epi64x(3, 4);
12708        assert_eq_m128i(r, e);
12709    }
12710
12711    #[simd_test(enable = "avx512f")]
12712    const fn test_mm512_store_epi64() {
12713        let a = _mm512_set1_epi64(9);
12714        let mut r = _mm512_set1_epi64(0);
12715        unsafe {
12716            _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
12717        }
12718        assert_eq_m512i(r, a);
12719    }
12720
12721    #[simd_test(enable = "avx512f,avx512vl")]
12722    const fn test_mm256_store_epi64() {
12723        let a = _mm256_set1_epi64x(9);
12724        let mut r = _mm256_set1_epi64x(0);
12725        unsafe {
12726            _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
12727        }
12728        assert_eq_m256i(r, a);
12729    }
12730
12731    #[simd_test(enable = "avx512f,avx512vl")]
12732    const fn test_mm_store_epi64() {
12733        let a = _mm_set1_epi64x(9);
12734        let mut r = _mm_set1_epi64x(0);
12735        unsafe {
12736            _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
12737        }
12738        assert_eq_m128i(r, a);
12739    }
12740
12741    #[simd_test(enable = "avx512f")]
12742    const fn test_mm512_load_pd() {
12743        #[repr(align(64))]
12744        struct Align {
12745            data: [f64; 8], // 64 bytes
12746        }
12747        let a = Align {
12748            data: [4., 3., 2., 5., -8., -9., -64., -50.],
12749        };
12750        let p = (a.data).as_ptr();
12751        let r = unsafe { _mm512_load_pd(black_box(p)) };
12752        let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.);
12753        assert_eq_m512d(r, e);
12754    }
12755
12756    #[simd_test(enable = "avx512f")]
12757    const fn test_mm512_store_pd() {
12758        let a = _mm512_set1_pd(9.);
12759        let mut r = _mm512_undefined_pd();
12760        unsafe {
12761            _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
12762        }
12763        assert_eq_m512d(r, a);
12764    }
12765
12766    #[simd_test(enable = "avx512f")]
12767    const fn test_mm512_test_epi64_mask() {
12768        let a = _mm512_set1_epi64(1 << 0);
12769        let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12770        let r = _mm512_test_epi64_mask(a, b);
12771        let e: __mmask8 = 0b11111111;
12772        assert_eq!(r, e);
12773    }
12774
12775    #[simd_test(enable = "avx512f")]
12776    const fn test_mm512_mask_test_epi64_mask() {
12777        let a = _mm512_set1_epi64(1 << 0);
12778        let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12779        let r = _mm512_mask_test_epi64_mask(0, a, b);
12780        assert_eq!(r, 0);
12781        let r = _mm512_mask_test_epi64_mask(0b11111111, a, b);
12782        let e: __mmask8 = 0b11111111;
12783        assert_eq!(r, e);
12784    }
12785
12786    #[simd_test(enable = "avx512f,avx512vl")]
12787    const fn test_mm256_test_epi64_mask() {
12788        let a = _mm256_set1_epi64x(1 << 0);
12789        let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12790        let r = _mm256_test_epi64_mask(a, b);
12791        let e: __mmask8 = 0b00001111;
12792        assert_eq!(r, e);
12793    }
12794
12795    #[simd_test(enable = "avx512f,avx512vl")]
12796    const fn test_mm256_mask_test_epi64_mask() {
12797        let a = _mm256_set1_epi64x(1 << 0);
12798        let b = _mm256_set1_epi64x(1 << 0 | 1 << 1);
12799        let r = _mm256_mask_test_epi64_mask(0, a, b);
12800        assert_eq!(r, 0);
12801        let r = _mm256_mask_test_epi64_mask(0b00001111, a, b);
12802        let e: __mmask8 = 0b00001111;
12803        assert_eq!(r, e);
12804    }
12805
12806    #[simd_test(enable = "avx512f,avx512vl")]
12807    const fn test_mm_test_epi64_mask() {
12808        let a = _mm_set1_epi64x(1 << 0);
12809        let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12810        let r = _mm_test_epi64_mask(a, b);
12811        let e: __mmask8 = 0b00000011;
12812        assert_eq!(r, e);
12813    }
12814
12815    #[simd_test(enable = "avx512f,avx512vl")]
12816    const fn test_mm_mask_test_epi64_mask() {
12817        let a = _mm_set1_epi64x(1 << 0);
12818        let b = _mm_set1_epi64x(1 << 0 | 1 << 1);
12819        let r = _mm_mask_test_epi64_mask(0, a, b);
12820        assert_eq!(r, 0);
12821        let r = _mm_mask_test_epi64_mask(0b00000011, a, b);
12822        let e: __mmask8 = 0b00000011;
12823        assert_eq!(r, e);
12824    }
12825
12826    #[simd_test(enable = "avx512f")]
12827    const fn test_mm512_testn_epi64_mask() {
12828        let a = _mm512_set1_epi64(1 << 0);
12829        let b = _mm512_set1_epi64(1 << 0 | 1 << 1);
12830        let r = _mm512_testn_epi64_mask(a, b);
12831        let e: __mmask8 = 0b00000000;
12832        assert_eq!(r, e);
12833    }
12834
12835    #[simd_test(enable = "avx512f")]
12836    const fn test_mm512_mask_testn_epi64_mask() {
12837        let a = _mm512_set1_epi64(1 << 0);
12838        let b = _mm512_set1_epi64(1 << 1);
12839        let r = _mm512_mask_testn_epi64_mask(0, a, b);
12840        assert_eq!(r, 0);
12841        let r = _mm512_mask_testn_epi64_mask(0b11111111, a, b);
12842        let e: __mmask8 = 0b11111111;
12843        assert_eq!(r, e);
12844    }
12845
12846    #[simd_test(enable = "avx512f,avx512vl")]
12847    const fn test_mm256_testn_epi64_mask() {
12848        let a = _mm256_set1_epi64x(1 << 0);
12849        let b = _mm256_set1_epi64x(1 << 1);
12850        let r = _mm256_testn_epi64_mask(a, b);
12851        let e: __mmask8 = 0b00001111;
12852        assert_eq!(r, e);
12853    }
12854
12855    #[simd_test(enable = "avx512f,avx512vl")]
12856    const fn test_mm256_mask_testn_epi64_mask() {
12857        let a = _mm256_set1_epi64x(1 << 0);
12858        let b = _mm256_set1_epi64x(1 << 1);
12859        let r = _mm256_mask_testn_epi64_mask(0, a, b);
12860        assert_eq!(r, 0);
12861        let r = _mm256_mask_testn_epi64_mask(0b11111111, a, b);
12862        let e: __mmask8 = 0b00001111;
12863        assert_eq!(r, e);
12864    }
12865
12866    #[simd_test(enable = "avx512f,avx512vl")]
12867    const fn test_mm_testn_epi64_mask() {
12868        let a = _mm_set1_epi64x(1 << 0);
12869        let b = _mm_set1_epi64x(1 << 1);
12870        let r = _mm_testn_epi64_mask(a, b);
12871        let e: __mmask8 = 0b00000011;
12872        assert_eq!(r, e);
12873    }
12874
12875    #[simd_test(enable = "avx512f,avx512vl")]
12876    const fn test_mm_mask_testn_epi64_mask() {
12877        let a = _mm_set1_epi64x(1 << 0);
12878        let b = _mm_set1_epi64x(1 << 1);
12879        let r = _mm_mask_testn_epi64_mask(0, a, b);
12880        assert_eq!(r, 0);
12881        let r = _mm_mask_testn_epi64_mask(0b11111111, a, b);
12882        let e: __mmask8 = 0b00000011;
12883        assert_eq!(r, e);
12884    }
12885
12886    #[simd_test(enable = "avx512f")]
12887    const fn test_mm512_mask_set1_epi64() {
12888        let src = _mm512_set1_epi64(2);
12889        let a: i64 = 11;
12890        let r = _mm512_mask_set1_epi64(src, 0, a);
12891        assert_eq_m512i(r, src);
12892        let r = _mm512_mask_set1_epi64(src, 0b11111111, a);
12893        let e = _mm512_set1_epi64(11);
12894        assert_eq_m512i(r, e);
12895    }
12896
12897    #[simd_test(enable = "avx512f")]
12898    const fn test_mm512_maskz_set1_epi64() {
12899        let a: i64 = 11;
12900        let r = _mm512_maskz_set1_epi64(0, a);
12901        assert_eq_m512i(r, _mm512_setzero_si512());
12902        let r = _mm512_maskz_set1_epi64(0b11111111, a);
12903        let e = _mm512_set1_epi64(11);
12904        assert_eq_m512i(r, e);
12905    }
12906
12907    #[simd_test(enable = "avx512f,avx512vl")]
12908    const fn test_mm256_mask_set1_epi64() {
12909        let src = _mm256_set1_epi64x(2);
12910        let a: i64 = 11;
12911        let r = _mm256_mask_set1_epi64(src, 0, a);
12912        assert_eq_m256i(r, src);
12913        let r = _mm256_mask_set1_epi64(src, 0b00001111, a);
12914        let e = _mm256_set1_epi64x(11);
12915        assert_eq_m256i(r, e);
12916    }
12917
12918    #[simd_test(enable = "avx512f,avx512vl")]
12919    const fn test_mm256_maskz_set1_epi64() {
12920        let a: i64 = 11;
12921        let r = _mm256_maskz_set1_epi64(0, a);
12922        assert_eq_m256i(r, _mm256_setzero_si256());
12923        let r = _mm256_maskz_set1_epi64(0b00001111, a);
12924        let e = _mm256_set1_epi64x(11);
12925        assert_eq_m256i(r, e);
12926    }
12927
12928    #[simd_test(enable = "avx512f,avx512vl")]
12929    const fn test_mm_mask_set1_epi64() {
12930        let src = _mm_set1_epi64x(2);
12931        let a: i64 = 11;
12932        let r = _mm_mask_set1_epi64(src, 0, a);
12933        assert_eq_m128i(r, src);
12934        let r = _mm_mask_set1_epi64(src, 0b00000011, a);
12935        let e = _mm_set1_epi64x(11);
12936        assert_eq_m128i(r, e);
12937    }
12938
12939    #[simd_test(enable = "avx512f,avx512vl")]
12940    const fn test_mm_maskz_set1_epi64() {
12941        let a: i64 = 11;
12942        let r = _mm_maskz_set1_epi64(0, a);
12943        assert_eq_m128i(r, _mm_setzero_si128());
12944        let r = _mm_maskz_set1_epi64(0b00000011, a);
12945        let e = _mm_set1_epi64x(11);
12946        assert_eq_m128i(r, e);
12947    }
12948
12949    #[simd_test(enable = "avx512f")]
12950    fn test_mm_cvtsd_i64() {
12951        let a = _mm_set_pd(1., -1.5);
12952        let r = _mm_cvtsd_i64(a);
12953        let e: i64 = -2;
12954        assert_eq!(r, e);
12955    }
12956
12957    #[simd_test(enable = "avx512f")]
12958    fn test_mm_cvtss_i64() {
12959        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12960        let r = _mm_cvtss_i64(a);
12961        let e: i64 = -2;
12962        assert_eq!(r, e);
12963    }
12964
12965    #[simd_test(enable = "avx512f")]
12966    fn test_mm_cvt_roundi64_ss() {
12967        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12968        let b: i64 = 9;
12969        let r = _mm_cvt_roundi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12970        let e = _mm_set_ps(0., -0.5, 1., 9.);
12971        assert_eq_m128(r, e);
12972    }
12973
12974    #[simd_test(enable = "avx512f")]
12975    fn test_mm_cvt_roundsi64_ss() {
12976        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12977        let b: i64 = 9;
12978        let r = _mm_cvt_roundsi64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
12979        let e = _mm_set_ps(0., -0.5, 1., 9.);
12980        assert_eq_m128(r, e);
12981    }
12982
12983    #[simd_test(enable = "avx512f")]
12984    const fn test_mm_cvti64_ss() {
12985        let a = _mm_set_ps(0., -0.5, 1., -1.5);
12986        let b: i64 = 9;
12987        let r = _mm_cvti64_ss(a, b);
12988        let e = _mm_set_ps(0., -0.5, 1., 9.);
12989        assert_eq_m128(r, e);
12990    }
12991
12992    #[simd_test(enable = "avx512f")]
12993    const fn test_mm_cvti64_sd() {
12994        let a = _mm_set_pd(1., -1.5);
12995        let b: i64 = 9;
12996        let r = _mm_cvti64_sd(a, b);
12997        let e = _mm_set_pd(1., 9.);
12998        assert_eq_m128d(r, e);
12999    }
13000
13001    #[simd_test(enable = "avx512f")]
13002    fn test_mm_cvt_roundsd_si64() {
13003        let a = _mm_set_pd(1., -1.5);
13004        let r = _mm_cvt_roundsd_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
13005        let e: i64 = -1;
13006        assert_eq!(r, e);
13007    }
13008
13009    #[simd_test(enable = "avx512f")]
13010    fn test_mm_cvt_roundsd_i64() {
13011        let a = _mm_set_pd(1., -1.5);
13012        let r = _mm_cvt_roundsd_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
13013        let e: i64 = -1;
13014        assert_eq!(r, e);
13015    }
13016
13017    #[simd_test(enable = "avx512f")]
13018    fn test_mm_cvt_roundsd_u64() {
13019        let a = _mm_set_pd(1., f64::MAX);
13020        let r = _mm_cvt_roundsd_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
13021        let e: u64 = u64::MAX;
13022        assert_eq!(r, e);
13023    }
13024
13025    #[simd_test(enable = "avx512f")]
13026    fn test_mm_cvtsd_u64() {
13027        let a = _mm_set_pd(1., -1.5);
13028        let r = _mm_cvtsd_u64(a);
13029        let e: u64 = u64::MAX;
13030        assert_eq!(r, e);
13031    }
13032
13033    #[simd_test(enable = "avx512f")]
13034    fn test_mm_cvt_roundss_i64() {
13035        let a = _mm_set_ps(0., -0.5, 1., -1.5);
13036        let r = _mm_cvt_roundss_i64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
13037        let e: i64 = -1;
13038        assert_eq!(r, e);
13039    }
13040
13041    #[simd_test(enable = "avx512f")]
13042    fn test_mm_cvt_roundss_si64() {
13043        let a = _mm_set_ps(0., -0.5, 1., -1.5);
13044        let r = _mm_cvt_roundss_si64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
13045        let e: i64 = -1;
13046        assert_eq!(r, e);
13047    }
13048
13049    #[simd_test(enable = "avx512f")]
13050    fn test_mm_cvt_roundss_u64() {
13051        let a = _mm_set_ps(0., -0.5, 1., -1.5);
13052        let r = _mm_cvt_roundss_u64::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a);
13053        let e: u64 = u64::MAX;
13054        assert_eq!(r, e);
13055    }
13056
13057    #[simd_test(enable = "avx512f")]
13058    fn test_mm_cvtss_u64() {
13059        let a = _mm_set_ps(0., -0.5, 1., -1.5);
13060        let r = _mm_cvtss_u64(a);
13061        let e: u64 = u64::MAX;
13062        assert_eq!(r, e);
13063    }
13064
13065    #[simd_test(enable = "avx512f")]
13066    fn test_mm_cvttsd_i64() {
13067        let a = _mm_set_pd(1., -1.5);
13068        let r = _mm_cvttsd_i64(a);
13069        let e: i64 = -1;
13070        assert_eq!(r, e);
13071    }
13072
13073    #[simd_test(enable = "avx512f")]
13074    fn test_mm_cvtt_roundsd_i64() {
13075        let a = _mm_set_pd(1., -1.5);
13076        let r = _mm_cvtt_roundsd_i64::<_MM_FROUND_NO_EXC>(a);
13077        let e: i64 = -1;
13078        assert_eq!(r, e);
13079    }
13080
13081    #[simd_test(enable = "avx512f")]
13082    fn test_mm_cvtt_roundsd_si64() {
13083        let a = _mm_set_pd(1., -1.5);
13084        let r = _mm_cvtt_roundsd_si64::<_MM_FROUND_NO_EXC>(a);
13085        let e: i64 = -1;
13086        assert_eq!(r, e);
13087    }
13088
13089    #[simd_test(enable = "avx512f")]
13090    fn test_mm_cvtt_roundsd_u64() {
13091        let a = _mm_set_pd(1., -1.5);
13092        let r = _mm_cvtt_roundsd_u64::<_MM_FROUND_NO_EXC>(a);
13093        let e: u64 = u64::MAX;
13094        assert_eq!(r, e);
13095    }
13096
13097    #[simd_test(enable = "avx512f")]
13098    fn test_mm_cvttsd_u64() {
13099        let a = _mm_set_pd(1., -1.5);
13100        let r = _mm_cvttsd_u64(a);
13101        let e: u64 = u64::MAX;
13102        assert_eq!(r, e);
13103    }
13104
13105    #[simd_test(enable = "avx512f")]
13106    fn test_mm_cvttss_i64() {
13107        let a = _mm_set_ps(0., -0.5, 1., -1.5);
13108        let r = _mm_cvttss_i64(a);
13109        let e: i64 = -1;
13110        assert_eq!(r, e);
13111    }
13112
13113    #[simd_test(enable = "avx512f")]
13114    fn test_mm_cvtt_roundss_i64() {
13115        let a = _mm_set_ps(0., -0.5, 1., -1.5);
13116        let r = _mm_cvtt_roundss_i64::<_MM_FROUND_NO_EXC>(a);
13117        let e: i64 = -1;
13118        assert_eq!(r, e);
13119    }
13120
13121    #[simd_test(enable = "avx512f")]
13122    fn test_mm_cvtt_roundss_si64() {
13123        let a = _mm_set_ps(0., -0.5, 1., -1.5);
13124        let r = _mm_cvtt_roundss_si64::<_MM_FROUND_NO_EXC>(a);
13125        let e: i64 = -1;
13126        assert_eq!(r, e);
13127    }
13128
13129    #[simd_test(enable = "avx512f")]
13130    fn test_mm_cvtt_roundss_u64() {
13131        let a = _mm_set_ps(0., -0.5, 1., -1.5);
13132        let r = _mm_cvtt_roundss_u64::<_MM_FROUND_NO_EXC>(a);
13133        let e: u64 = u64::MAX;
13134        assert_eq!(r, e);
13135    }
13136
13137    #[simd_test(enable = "avx512f")]
13138    fn test_mm_cvttss_u64() {
13139        let a = _mm_set_ps(0., -0.5, 1., -1.5);
13140        let r = _mm_cvttss_u64(a);
13141        let e: u64 = u64::MAX;
13142        assert_eq!(r, e);
13143    }
13144
13145    #[simd_test(enable = "avx512f")]
13146    const fn test_mm_cvtu64_ss() {
13147        let a = _mm_set_ps(0., -0.5, 1., -1.5);
13148        let b: u64 = 9;
13149        let r = _mm_cvtu64_ss(a, b);
13150        let e = _mm_set_ps(0., -0.5, 1., 9.);
13151        assert_eq_m128(r, e);
13152    }
13153
13154    #[simd_test(enable = "avx512f")]
13155    const fn test_mm_cvtu64_sd() {
13156        let a = _mm_set_pd(1., -1.5);
13157        let b: u64 = 9;
13158        let r = _mm_cvtu64_sd(a, b);
13159        let e = _mm_set_pd(1., 9.);
13160        assert_eq_m128d(r, e);
13161    }
13162
13163    #[simd_test(enable = "avx512f")]
13164    fn test_mm_cvt_roundu64_ss() {
13165        let a = _mm_set_ps(0., -0.5, 1., -1.5);
13166        let b: u64 = 9;
13167        let r = _mm_cvt_roundu64_ss::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13168        let e = _mm_set_ps(0., -0.5, 1., 9.);
13169        assert_eq_m128(r, e);
13170    }
13171
13172    #[simd_test(enable = "avx512f")]
13173    fn test_mm_cvt_roundu64_sd() {
13174        let a = _mm_set_pd(1., -1.5);
13175        let b: u64 = 9;
13176        let r = _mm_cvt_roundu64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13177        let e = _mm_set_pd(1., 9.);
13178        assert_eq_m128d(r, e);
13179    }
13180
13181    #[simd_test(enable = "avx512f")]
13182    fn test_mm_cvt_roundi64_sd() {
13183        let a = _mm_set_pd(1., -1.5);
13184        let b: i64 = 9;
13185        let r = _mm_cvt_roundi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13186        let e = _mm_set_pd(1., 9.);
13187        assert_eq_m128d(r, e);
13188    }
13189
13190    #[simd_test(enable = "avx512f")]
13191    fn test_mm_cvt_roundsi64_sd() {
13192        let a = _mm_set_pd(1., -1.5);
13193        let b: i64 = 9;
13194        let r = _mm_cvt_roundsi64_sd::<{ _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC }>(a, b);
13195        let e = _mm_set_pd(1., 9.);
13196        assert_eq_m128d(r, e);
13197    }
13198}