aes64dsm in core::arch::riscv64 - Rust
Description: AES middle round decryption instruction for RV64.

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## aes64dsm

# Function aes64dsm

Source

    pub fn aes64dsm(rs1: u64, rs2: u64) -> u64

🔬This is a nightly-only experimental API. (`riscv_ext_intrinsics` #114544)
Available on (RISC-V RV64) and target feature `zknd` only.
Expand description

AES middle round decryption instruction for RV64.

Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps. This instruction must always be implemented such that its execution latency does not depend on the data being operated on.

Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions

Version: v1.0.1

Section: 3.6